A multi-phase clocking circuit for SerDes clock data recovery

Abstract

The application discloses a kind of multi-phase clock circuits for SerDes clock data recovery, it is related to integrated circuit design technical field, including: phase control unit, delay chain, delay calibration circuit and MUX switch array;Delay chain is connected phase control unit, delay calibration circuit and MUX switch array respectively;Phase control unit adjusts the input reference clock signal, and outputs clock signal CK_0 to delay chain;Delay calibration circuit is used to calibrate the delay time of delay chain;Delay chain inputs clock signal CK_0, CK_1, CK_1n..., CK_N into MUX switch array, carries out phase sorting and selects output, generates multi-phase clock signal CK0, CK1, CK2,..., CKN, is input to the data sampler and edge sampler in SerDes receiving circuit and carries out sampling.The application realizes the phase continuous adjustment of multi-phase output clock signal, meets the demand of SerDes CDR circuit to clock signal phase control, can effectively reduce the overall chip area and power consumption of SerDes multi-phase clock CDR circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design, and in particular to a multi-phase clock circuit for SerDes clock data recovery. BACKGROUND

[0002] With the development of information technology, the transmission rate of signals is continuously increasing, however, the limited bandwidth of the channel will cause serious loss of high frequency signals, resulting in serious intersymbol interference (ISI), which affects the signal quality at the receiving end and brings challenges to large bandwidth data transmission. The application of serializer / deserializer (SerDes) link technology to realize high-speed data transmission has been very widespread. SerDes link can effectively eliminate the influence of high frequency attenuation of the channel by adopting various channel equalization technologies, and at the same time, advanced data coding technology is adopted to make the SerDes link not need to transmit a clock signal, and the clock signal can be recovered through the received data stream, so the performance of the clock and data recovery (CDR) circuit in the SerDes transmission link is very critical.

[0003] In order to reduce the frequency of the SerDes clock signal, thereby reducing the difficulty, complexity and power consumption of the system, a half-rate or quarter-rate clock signal is usually used in the SerDes receiver, or even a lower rate clock signal may be used. Since the clock and data recovery circuit (CDR) in the SerDes receiver needs to sample the results at the center of the data and the edge of the data at the same time, the clock signal needs to generate multiple phases, for example, a quarter-rate structure needs a quadrature 4-phase clock signal, and a quarter-rate structure needs an 8-phase clock signal.

[0004] The multi-phase clock signal in the clock and data recovery circuit (CDR) of the SerDes is usually implemented by a phase interpolator (PI). The existing 8-phase clock CDR structure based on a phase interpolator is shown in Figure 1 An 8-phase clock CDR structure is implemented by using multiple phase interpolators. A plurality of phase control signals are generated by a digital feedback control loop to control the phase of the clock signal output by each phase interpolator (PI). Since each phase interpolator (PI) can only output a differential 2-phase signal, four phase interpolators (PI) are needed for an 8-phase clock.

[0005] The existing 4-phase clock CDR structure based on a phase interpolator is shown in Figure 2As shown, the disclosure number CN108880537A discloses a wide frequency clock generation circuit based on a phase interpolator in high-speed serial communication, and a circuit structure of a 4-phase clock CDR function is realized by using a phase interpolator (PI). The circuit generates 4 groups of phase control signals through a phase control word generation circuit and a decoding circuit, and generates 4-phase clock signals in quadrature through 2 phase interpolators (PI).

[0006] The multi-phase clock CDR structure realized by the phase interpolator (PI) circuit has the following disadvantages: first, the phase interpolator (PI) circuit needs to input 4-phase quadrature reference clock signals, such as the input clock signals CLK0, CLK90, CLK180 and CLK270 in Figure 1 and Figure 2 The generation circuit of the additional high-speed quadrature clock signal increases the system complexity, increases the chip area and increases the power consumption; secondly, the generation of the multi-phase clock signal needs multiple phase interpolators (PI) circuits, which increases the chip area and increases the power consumption. SUMMARY

[0007] The purpose of the present application is to overcome the shortcomings of the prior art and provide a multi-phase clock circuit for SerDes clock data recovery.

[0008] The purpose of the present application is achieved by the following technical solutions:

[0009] The present application discloses a multi-phase clock circuit for SerDes clock data recovery, comprising:

[0010] A phase control unit, a delay chain, a delay calibration circuit and a MUX switch array; the delay chain is connected to the phase control unit, the delay calibration circuit and the MUX switch array respectively; the phase control unit is used for delaying and phase controlling the input reference clock signal, and then outputting the clock signal CK_0 to the delay chain; the delay calibration circuit is used for calibrating the delay time of the delay chain; the delay chain comprises N variable delay units connected in series, each variable delay unit outputs a phase clock signal, and then the delay chain inputs the clock signals CK_0, CK_1, CK_1n…, CK_N into the MUX switch array, sorts and selects the clock signals CK_0, CK_1, CK_1n…, CK_N through the MUX switch array, and finally generates the multi-phase clock signals CK0, CK1, CK2, …, CKN, which are input into the data sampler and the edge sampler in the SerDes receiving circuit to drive the sampling circuit to perform data sampling and edge sampling.

[0011] Further, the SerDes clock data recovery circuit comprises a phase detector, a voter, a digital filter, an integrator and a decoder connected in series; the phase detector is further connected with a data sampler and an edge sampler respectively, for receiving the Data[n:0] signal output by the data sampler and the Edge[n:0] signal output by the edge sampler, and performing phase detection to obtain phase lead or lag information of the sampling clock, and then the phase detector inputs the phase lead or lag information into the voter; the voter makes a voting decision on the phase lead or lag information, and outputs a 1-bit decision result to the digital filter, and the digital filter performs accumulation and filtering processing on the decision result, and outputs the filtering result to the integrator; the integrator performs phase integration on the filtering result to obtain a phase control signal and output the phase control signal to the decoder; finally, the decoder decodes the phase control signal to obtain a first control signal quad[k:0] and a second control signal phase[m:0], and the decoder is further connected with a phase control unit and a MUX switch array respectively, and the decoder inputs the first control signal quad[k:0] into the MUX switch array, and the decoder inputs the second control signal phase[m:0] into the phase control unit.

[0012] Preferably, after the reference clock signal CK_REF is input into the phase control unit, the delay time and phase of the reference clock signal CK_REF are adjusted by the second control signal phase[m:0], and finally the phase control unit outputs a clock signal CK_0 to the delay chain, so as to change the phases of all clock signals CK_0, CK_1, CK_1n…, CK_N; wherein the phase adjustment range of the phase control unit is greater than the delay time generated by one variable delay unit, so as to realize continuous 360-degree phase adjustment through the clock cycle shift switching of the MUX switch array.

[0013] Further, the delay calibration circuit compares the phase difference between the clock signals CK_0 and CK_N to generate an error signal, and then integrates and filters the error signal to generate a fifth control signal VCTL, and then inputs the fifth control signal VCTL into each variable delay unit clock to control the variable delay unit to generate a delay time, and the delay chain forms a delay time with a total phase of 180 degrees or 360 degrees, i.e. the total delay time of the clock signals CK_0, CK_1, CK_1n…, CK_N is 180 degrees or 360 degrees.

[0014] Preferably, if the delay time is set to 180 degrees, the clock signals CK_1, CK_i, …, CK_N in the 0-degree to 180-degree phase range output by the delay chain are phase-inverted by the inverter to obtain complementary phase clock signals in the 180-degree to 360-degree phase range.

[0015] Preferably, after the delay chain inputs the clock signals CK_0, CK_1, CK_1n…, CK_N to the MUX switch array, the MUX switch array reorders and selects the output of the clock signals through the first control signal quad[k:0], that is, the MUX switch array cyclically shifts the clock signals CK_0, CK_1, CK_1n, CK_i, CK_in, …, CK_N according to the first control signal quad[k:0], selects the correct mapping clock signal, and finally obtains the multi-phase clock signals CK0, CK1, CK2, …, CKN; then the multi-phase clock signals CK0, CK1, CK2, …, CKN are input to the data sampler and the edge sampler in the SerDes receiving circuit.

[0016] The beneficial effects of the present application are:

[0017] 1) The present application only needs to input a reference clock signal, and then generates a multi-phase clock signal through a variable delay chain and a delay calibration circuit, controls the delay and phase of the input reference clock signal, realizes the phase continuous adjustment of the multi-phase output clock signal, and meets the demand of the SerDes CDR circuit for clock signal phase control.

[0018] 2) The technical scheme provided by the present application does not need to input a quadrature reference clock signal, nor a plurality of phase interpolators (PI) circuits, and can effectively reduce the overall chip area and power consumption of the SerDes multi-phase clock CDR circuit. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 It is an existing 8-phase clock CDR structure diagram based on a phase interpolator;

[0020] Figure 2 It is an existing 4-phase clock CDR structure diagram based on a phase interpolator;

[0021] Figure 3 It is a CDR structure diagram of a multi-phase clock circuit for SerDes clock data recovery according to an embodiment of the present application;

[0022] Figure 4 It is a phase control unit circuit schematic diagram according to an embodiment of the present application;

[0023] Figure 5 It is a variable delay unit circuit schematic diagram according to an embodiment of the present application;

[0024] Figure 6 It is a delay calibration circuit schematic diagram according to an embodiment of the present application, wherein Figure 6 (a) in the above is a 180-degree delay chain calibration circuit, Figure 6 (b) in the above is a 360-degree delay chain DLL calibration circuit;

[0025] Figure 7 A schematic diagram of a MUX switch array circuit for an embodiment of the present application;

[0026] Figure 8 A timing waveform diagram in 4 phases of a multi-phase clock circuit for SerDes clock data recovery for an embodiment of the present application. DETAILED DESCRIPTION

[0027] The technical solutions of the present application will be described clearly and completely below in conjunction with embodiments. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort fall within the scope of the present application.

[0028] Based on the deficiencies of the multi-phase clock generation circuit technical solution in the existing SerDes CDR, the present application provides a multi-phase clock circuit for SerDes clock data recovery, which has the characteristics of small area and low power consumption. The CDR structure diagram is as shown in Figure 3 and specifically comprises:

[0029] a phase control unit, a delay chain, a delay calibration circuit and a MUX switch array; the delay chain is connected to the phase control unit, the delay calibration circuit and the MUX switch array respectively; the phase control unit is used for delaying and phase controlling the input reference clock signal, and then outputs the clock signal CK_0 to the delay chain; the delay calibration circuit is used for calibrating the delay time of the delay chain; the delay chain comprises N variable delay units connected in series, each variable delay unit outputs a phase clock signal, and then the delay chain inputs the clock signals CK_0, CK_1, CK_1n…, CK_N into the MUX switch array, sorts and selects the clock signals CK_0, CK_1, CK_1n…, CK_N through the MUX switch array, and finally generates multi-phase clock signals CK0, CK1, CK2, …, CKN, which are input into the Data Sampler and the Edge Sampler in the SerDes receiving circuit to drive the sampling circuit to perform data sampling and edge sampling.

[0030] Specifically, the SerDes clock data recovery circuit comprises, in series, a phase detector (BBPD), a voter, a digital filter, an integrator and a decoder; the phase detector is further connected to a data sampler and an edge sampler respectively, for receiving a Data[n:0] signal output by the data sampler and an Edge[n:0] signal output by the edge sampler, and performing phase detection to obtain phase advance (Early) or phase lag (Late) information of a sampling clock, and then inputting the phase advance or phase lag information into the voter; the voter performs voting decision on the phase advance or phase lag information, and outputs a 1-bit decision result to the digital filter; the digital filter performs accumulation and filtering processing on the decision result, and outputs a filtering result to the integrator; the integrator performs phase integration on the filtering result to obtain a phase control signal and output the phase control signal to the decoder; finally, the decoder decodes the phase control signal to obtain a first control signal quad[k:0] and a second control signal phase[m:0], and the decoder is further connected to a phase control unit and a MUX switch array respectively, and the decoder inputs the first control signal quad[k:0] into the MUX switch array, and inputs the second control signal phase[m:0] into the phase control unit.

[0031] Specifically, after the reference clock signal CK_REF is input into the phase control unit, the second control signal phase[m:0] is used to adjust the delay and phase of the reference clock signal CK_REF, and finally the phase control unit outputs a clock signal CK_0 to a delay chain, so as to change the phases of all clock signals CK_0, CK_1, CK_1n…, CK_N; wherein the phase adjustment range of the phase control unit needs to be greater than the delay time generated by one variable delay unit, so that the clock can be circularly shifted and switched through the MUX switch array, and the phase adjustment in a continuous 360-degree range can be realized.

[0032] For example, the input reference clock signal CK_REF is connected to the phase control unit for phase adjustment, and the circuit schematic diagram of the phase control unit in the embodiment is as shown in Figure 4As shown, the input reference clock passes through an inverter to obtain a signal with opposite phase, and the reference clock and the inverted signal are simultaneously sent to a MUX multi-way switch for phase selection. When the second control signal phase[m:0] is 0, the reference clock signal is selected, and when the second control signal phase[m:0] is 1, the inverted clock signal is selected, thereby realizing 180-degree phase control. The output signal of the MUX multi-way switch is connected to the variable delay circuit, and the fourth control signal V_phase of the variable delay circuit is an analog voltage signal output after the third control signal phase[m-1:0] passes through a digital-to-analog converter (DAC), and the fourth control signal V_phase controls the delay time generated by the variable delay circuit, thereby realizing continuous control of the phase. The schematic diagram of the variable delay unit circuit in the embodiment is as shown in Figure 5 As shown, the required controllable delay time range ΔT is greater than the delay time of one variable delay unit in the delay chain. Figure 4 The phase control unit shown can realize 180-degree phase flip and continuous delay time adjustment of ΔT, and the clock of the MUX switch array is sequentially and circularly shifted to realize continuous phase adjustment in a range of 360 degrees.

[0033] Specifically, the delay calibration circuit compares the phase difference of the clock signals CK_0 and CK_N to generate an error signal, integrates and filters the error signal to generate a fifth control signal VCTL, and then inputs the fifth control signal VCTL into each variable delay unit clock for controlling the variable delay unit to generate a delay time. Each variable delay unit is a completely identical circuit, i.e., each variable delay unit is connected to the same fifth control signal VCTL, the delay time of each variable delay unit is the same, and each variable delay unit sequentially outputs a clock signal with the same phase difference, thereby obtaining a plurality of phase clock signals with the same phase difference; the delay chain forms a total delay time of 180-degree phase or 360-degree phase, i.e., the total delay time of the clock signals CK_0, CK_1, CK_1n…, CK_N is 180-degree phase or 360-degree phase. By flexibly adjusting the number N of the series-connected variable delay units, a different number of multi-phase clock signals can be obtained, and the clock signal output by each variable delay unit can be inverted by an inverter to expand to more clock phases.

[0034] Exemplarily, the clock signal CK_0 output by the phase control unit is input into a delay chain composed of variable delay units 1 to N connected in series, each variable delay unit is a completely identical circuit, the input fifth control signal VCTL connected thereto controls the variable delay unit to generate a specific delay time, and the delay chain forms a total delay time of 180-degree phase or 360-degree phase. The schematic diagram of the variable delay unit circuit is as shown in Figure 5As shown, the structure is a two-stage inverter series circuit, the output of each inverter is connected to a variable capacitor to realize delay adjustment, the capacitance of the variable capacitor is controlled by the fifth control signal VCTL connected thereto. The delay time of each delay unit is the same, so each variable delay unit outputs a clock signal with the same phase difference in turn, thereby obtaining multi-phase clock signals with the same phase difference.

[0035] Specifically, the total delay time of the delay chain is precisely controlled and calibrated by the delay calibration circuit, so as to ensure that the total delay time generated by the delay chain is 180 degrees or 360 degrees, and the accuracy of the phase difference between the multi-phase clock signals is ensured. According to the structure of the phase difference detection circuit in the delay calibration circuit, the total delay time of the delay chain can be set to 180 degrees or 360 degrees. If the delay time is set to 180 degrees, the clock signals CK_1, CK_i, …, CK_N in the phase range of 0 degrees to 180 degrees output by the delay chain are inverted in phase by the inverter, and the complementary phase clock signals in the phase range of 180 degrees to 360 degrees are obtained.

[0036] Specifically, the total delay time of the delay chain is precisely controlled and calibrated by the delay calibration circuit, so as to ensure that the total delay time generated by the delay chain is 180 degrees or 360 degrees, and the accuracy of the phase difference between the multi-phase clock signals is ensured. According to the structure of the phase difference detection circuit in the delay calibration circuit, the total delay time of the delay chain can be set to 180 degrees or 360 degrees. If the delay time is set to 180 degrees, the clock signals CK_1, CK_i, …, CK_N in the phase range of 0 degrees to 180 degrees output by the delay chain are inverted in phase by the inverter, and the complementary phase clock signals in the phase range of 180 degrees to 360 degrees are obtained. Figure 6 As shown, the structure is a two-stage inverter series circuit, the output of each inverter is connected to a variable capacitor to realize delay adjustment, the capacitance of the variable capacitor is controlled by the fifth control signal VCTL connected thereto. The delay time of each delay unit is the same, so each variable delay unit outputs a clock signal with the same phase difference in turn, thereby obtaining multi-phase clock signals with the same phase difference. Figure 6 (a) is a 180-degree delay chain calibration circuit, Figure 6 (b) is a 360-degree delay chain DLL calibration circuit. Figure 6The (a) in the figure includes phase detection circuit based on SR latch, RC low-pass filter circuit, error amplifier circuit (EA) and integral filter capacitor C connected in series. The phase detection circuit adopts SR latch structure, one input port is connected with clock signal CK_0, the other input port is connected with clock signal CK_N, and the SR latch outputs phase detection results Q1 and Q2 signals. Q1 signal and Q2 signal are respectively subjected to signal shaping and filtering by RC low-pass filter circuit to obtain average output voltage V1 and V2, wherein the RC low-pass filter circuit is composed of series resistance R and parallel capacitor C1 connected to ground. When the phase delay time of CK_0 and CK_N clock is less than 180 degrees phase, V1 is less than V2; when the phase delay time of CK_0 and CK_N clock is greater than 180 degrees phase, V1 is greater than V2; when the phase delay time of CK_0 and CK_N clock is just equal to 180 degrees phase, V1 is equal to V2. V1 and V2 signals are respectively connected to the positive and negative terminals of error amplifier circuit (EA), and the error amplifier circuit (EA) outputs error signal by comparing the size of input signals V1 and V2. The error signal is subjected to integration and filtering by capacitor C to obtain VCTL control voltage, which is used for feedback to the variable delay unit for delay control. Through the negative feedback control effect of 180 degree delay calibration circuit, the delay time generated by 180 degree phase delay chain can gradually approach 180 degrees, and finally equal to 180 degree phase delay, so as to ensure that the clock signals generated by multi-phase clock generation circuit have equal and accurate phase difference. In order to obtain all equal phase difference clock signals in 0 degree to 360 degree phase range, the clock signals CK_1, CK_i, …, CK_N in 0 degree to 180 degree phase range output by delay chain need to be subjected to phase inversion operation by inverter, so as to obtain complementary phase clock signals in 180 degree to 360 degree phase range.

[0037] Figure 6 The (b) in the figure is delay-locked loop (DLL) calibration structure, including frequency discriminator (PFD), charge pump (CP) and low-pass filter (LPF). The frequency discriminator (PFD) detects the phase difference of input clock signals CK_0 and CK_N, and outputs UP and DN signals connected to the input terminal of charge pump (CP). The charge pump (CP) outputs current according to UP and DN signals to charge and discharge the low-pass filter (LPF) connected outside, and the output signal VCTL of the low-pass filter is feedback connected to the delay time of the control clock signal in the 360 degree phase delay chain, forming a complete delay-locked loop (DLL) structure. When the delay-locked loop is locked, the phase difference of CK_0 and CK_N signals is 360 degrees, thereby completing the delay time calibration of the delay chain.

[0038] Specifically, the delay chain inputs the clock signals CK_0, CK_1, CK_1n…, CK_N to the MUX switch array, and the MUX switch array reorders and selects the output of the clock signals through the first control signal quad[k:0], that is, the MUX switch array cyclically shifts the clock signals CK_0, CK_1, CK_1n, CK_i, CK_in, …, CK_N according to the first control signal quad[k:0] to select the correctly mapped clock signals, and finally obtains the multi-phase clock signals CK0, CK1, CK2, …, CKN, which are then input to the data sampler and the edge sampler in the SerDes receiving circuit. The role of the MUX switch array is to cooperate with the phase control unit to realize the continuous adjustment of the phase of the multi-phase clock signals from 0 degrees to 360 degrees. In order to reduce the power consumption and area of the circuit, the continuous phase adjustment range of the phase control unit is usually just greater than the delay time generated by one variable delay unit, rather than the adjustment range from 0 degrees to 360 degrees, so the MUX switch array is needed to cyclically shift and switch the multi-phase clock signals output by the delay chain, so as to expand the clock phase adjustment range to 360 degrees.

[0039] Exemplarily, the multi-phase clock signals CK_0, CK_1, CK_1n, CK_i, CK_in, …, CK_N output by the delay chain are connected to the MUX switch array, the clock signals are reordered and selected through the first control signal quad[k:0], and the role of the MUX switch array is to cooperate with the phase control unit to realize the continuous adjustment of the phase of the multi-phase clock signals from 0 degrees to 360 degrees. The circuit schematic diagram of the MUX switch array is as shown in Figure 7 The switch array cyclically shifts and selects the input clock signals CK_0, CK_1, CK_2, …, CK_N according to the input first control signal quad[k:0] to output the correctly mapped clock signals to CK0, CK1, CK2, …, CKN. For example, when the first control signal quad[k:0] is equal to 0, CK0 is connected to CK_0, CK1 is connected to CK_1, …, and CKN is connected to CK_N; when the first control signal quad[k:0] is equal to 1, CK0 is connected to CK_1, CK1 is connected to CK_2, …, and CKN is connected to CK_0; when the first control signal quad[k:0] is equal to 2, CK0 is connected to CK_2, CK1 is connected to CK_3, …, and CKN is connected to CK_1; and so on for all control words. Through the cyclic shift selection mode of the MUX switch, the output multi-phase clock signals can be adjusted in steps with a phase difference of 360 / (N+1) degrees, and the phase control unit cooperating with the reference clock signal CK_REF can realize the continuous phase adjustment range from 0 to 360 degrees.

[0040] The timing waveform diagram of the multi-phase clock circuit in 4 phases is as follows: Figure 8 As shown, a 180-degree delay chain and Figure 6 The calibration circuit structure corresponding to (a) in the figure uses a reference clock signal CK_REF that generates a delay time as shown in the figure after passing through a phase control unit. The series-connected variable delay units sequentially generate clock signals CK_0, CK_1, CK_2, and CK_1n, with phases of 0 degrees, 90 degrees, 180 degrees, and 270 degrees, respectively. Figure 8 The unit delay shown is the delay time generated by a single variable delay unit, corresponding to a 90-degree phase. Figure 8 The diagram shows the case where the first control signal quad[k:0] of the MUX switch array is equal to 1. Therefore, CK0 is connected to CK_1, CK1 is connected to CK_2, CK2 is connected to CK_1n, and CK3 is connected to CK_0. In this case, the total delay time of the clock signal generated by the multiphase clock generation circuit is equal to delay + 1 * unit delay. If the first control signal quad[k:0] is equal to 2, then the total delay time is equal to delay + 2 * unit delay.

[0041] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A multi-phase clock circuit for SerDes clock data recovery, characterized in that, include: Phase control unit, delay chain, delay calibration circuit and MUX switch array; The delay chain is connected to the phase control unit, the delay calibration circuit and the MUX switch array respectively; the phase control unit is used to delay and control the phase of the input reference clock signal, and then outputs the clock signal CK_0 to the delay chain; The delay calibration circuit is used to calibrate the delay time of the delay chain. The delay chain includes N variable delay units connected in series. Each variable delay unit outputs a clock signal of one phase. Then, the delay chain inputs the clock signals CK_0, CK_1, CK_1n, ..., CK_N into the MUX switch array. The MUX switch array sorts and selects the phases of the clock signals CK_0, CK_1, CK_1n, ..., CK_N, and finally generates multi-phase clock signals CK0, CK1, CK2, ..., CKN, which are input into the data sampler and edge sampler in the SerDes receiving circuit to drive the sampling circuit to perform data sampling and edge sampling. The SerDes clock data recovery circuit includes a phase detector, a voter, a digital filter, an integrator, and a decoder connected in series. The phase detector is also connected to a data sampler and an edge sampler, respectively, to receive the Data[n:0] signal output from the data sampler and the Edge[n:0] signal output from the edge sampler, and performs phase detection to obtain the phase lead or lag information of the sampled clock. The phase detector then inputs this phase lead or lag information into the voter. The voter makes a decision based on the phase lead or lag information and outputs a 1-bit decision result to the digital filter. The decision results are accumulated and filtered, and the filtered result is output to the integrator. The integrator performs phase integration on the filtered result to obtain the phase control signal and outputs it to the decoder. Finally, the decoder decodes the phase control signal to obtain the first control signal quad[k:0] and the second control signal phase[m:0]. The decoder is also connected to the phase control unit and the MUX switch array. The decoder inputs the first control signal quad[k:0] into the MUX switch array and the decoder inputs the second control signal phase[m:0] into the phase control unit. After the reference clock signal CK_REF is input to the phase control unit, its delay and phase are adjusted by the second control signal phase[m:0]. Finally, the phase control unit outputs the clock signal CK_0 to the delay chain, thereby changing the phase of all clock signals CK_0, CK_1, CK_1n, ..., CK_N. The phase adjustment range of the phase control unit is greater than the delay time generated by one variable delay unit, thereby achieving continuous 360-degree phase adjustment by sequentially switching the clock cycle of the MUX switch array.

2. The multi-phase clock circuit for SerDes clock data recovery according to claim 1, characterized in that: The delay calibration circuit generates an error signal by comparing the phase difference between clock signals CK_0 and CK_N. After integrating and filtering the error signal, a fifth control signal VCTL is generated. The fifth control signal VCTL is then input into each variable delay unit clock to control the variable delay unit to generate a delay time. The delay chain forms a delay time with a total phase of 180 degrees or 360 degrees, that is, the total delay time of clock signals CK_0, CK_1, CK_1n, ..., CK_N is 180 degrees or 360 degrees.

3. A multi-phase clock circuit for SerDes clock data recovery according to claim 2, characterized in that: If the delay time is set to 180 degrees phase, the clock signals CK_1, CK_i, ..., CK_N in the phase range of 0 to 180 degrees output by the delay chain are inverted by an inverter to obtain complementary phase clock signals in the phase range of 180 to 360 degrees.

4. A multi-phase clock circuit for SerDes clock data recovery according to claim 1, characterized in that: The delay chain inputs clock signals CK_0, CK_1, CK_1n, ..., CK_N into the MUX switch array. The MUX switch array then reorders and selects the output clock signals using the first control signal quad[k:0]. Specifically, the MUX switch array performs cyclic shifting of the clock signals CK_0, CK_1, CK_1n, CK_i, CK_in, ..., CK_N according to the first control signal quad[k:0], selecting the correctly mapped clock signals. Finally, it obtains multi-phase clock signals CK0, CK1, CK2, ..., CKN, which are then input into the data sampler and edge sampler in the SerDes receiving circuit.

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