Second-order feed-forward noise shaping successive approximation analog-to-digital converter

Abstract

A second-order feed-forward noise shaping successive approximation analog-to-digital converter comprises a differential capacitor array DAC1, a differential capacitor array DAC2, a first-stage passive integrator INT1, a second-stage passive integrator INT2, a low-gain amplifier G, a negative feedback FB, a four-input comparator COMP, a digital logic module SAR Logic and an asynchronous clock module CLK. Through the circuit structure, the loop filter in the circuit is composed of the INT1, the G, the INT2 and the FB, and the low-gain amplifier is realized by adopting a differential common-source amplifier loaded by a diode. The integrator in the loop filter is composed of a passive switched capacitor, the power consumption is low, and good process portability is achieved. The circuit can effectively suppress in-band noise, achieves high precision, and is also suitable for low-power-consumption application occasions.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, and specifically relates to a second-order feedforward noise-shaping successive approximation analog-to-digital converter. Background Technology

[0002] Noise-shaping successive approximation analog-to-digital converters (ADCs) are implemented by applying a Σ-Δ modulator to the SAR ADC circuit. Traditional SAR ADCs are simple in structure, have low power consumption, and are readily adaptable to technological advancements. However, as SAR ADC accuracy improves and quantization step sizes decrease, the impact of non-ideal factors such as noise, offset, and quantization error on the quantization process gradually increases, becoming a bottleneck for further accuracy improvements. Σ-Δ modulators, which trade bandwidth for accuracy, are widely used in high-precision applications; however, continuously increasing accuracy requires an exponential increase in bandwidth, gradually reducing the efficiency of accuracy improvement. SAR ADCs inherently possess moderate accuracy, and the addition of a Σ-Δ modulator allows for accuracy improvement with only a small bandwidth sacrifice, enabling NS SAR ADCs to exhibit high accuracy and low power consumption.

[0003] Traditional active NS SAR ADCs offer good shaping performance, but the internal operational amplifiers increase power consumption and area overhead, and reduce circuit portability. Traditional passive NS SAR ADCs, on the other hand, have limited shaping capabilities, and the presence of passive integrators results in a larger overall circuit capacitance. Furthermore, traditional NS SAR ADCs are often implemented on synchronous SAR ADCs, and an external clock can limit the overall conversion speed of the ADC. Summary of the Invention

[0004] To address the aforementioned problems in existing technologies, this invention proposes a second-order feedforward noise-shaping successive approximation analog-to-digital converter. The aim is to achieve better shaping results with less hardware resource overhead, thereby significantly improving the accuracy of SAR ADCs under conditions of low oversampling. This invention is suitable for high-speed and high-precision signal processing applications.

[0005] To achieve the above objectives, the technical solution adopted by this invention is as follows: a second-order feedforward noise-shaping successive approximation analog-to-digital converter, including differential capacitor arrays DAC1 and DAC2, a first-stage passive integrator INT1, a second-stage passive integrator INT2, a low-gain amplifier G, negative feedback FB, a four-input comparator COMP, a digital logic module SAR Logic, and an asynchronous clock module CLK.

[0006] The output of the external sampling switch circuit is connected to the input of capacitor arrays DAC1 and DAC2. The outputs of capacitor arrays DAC1 and DAC2 are connected to the first positive and first negative inputs of the four-input comparator COMP, respectively. The outputs of capacitor arrays DAC1 and DAC2 are connected to the input of the first-stage integrator INT1. The differential output of the first-stage integrator INT1 is connected to the input of the low-gain amplifier G. The output of the low-gain amplifier G is connected to the input of the second-stage integrator INT2. The differential output of the second-stage integrator INT2 is connected to the other input of the four-input comparator COMP. The output of the second-stage integrator INT2 is also connected to the input of the negative feedback FB. The output of the negative feedback FB is connected to the first-stage integrator INT1. The output signal of the four-input comparator COMP is connected to the asynchronous clock module CLK. The output signal of the four-input comparator COMP is connected to the digital logic module SARLogic. The output signal of the digital logic module SARLogic returns to capacitor arrays DAC1 and DAC2.

[0007] The capacitor arrays DAC1 and DAC2 are used to hold the sampled analog signal and the residual voltage of the conversion. The loop filter, consisting of the first-stage passive integrator INT1, the second-stage passive integrator INT2, the low-gain amplifier G, and the negative feedback FB, is used to process the residual signal of a single conversion cycle and send it to the next quantization cycle for quantization.

[0008] The first-stage integrator INT1 includes capacitors C1, C2, C3, C4, C9, and C10, and switches S3, S4, S5, S6, S11, S12, S13, and S14. The first plate of capacitor C1 is connected to capacitor array DAC1 via switch S3, and is also connected to the first plate of capacitor C3 and the positive input terminal of low-gain amplifier G via switch S5. The first plate of capacitor C2 is connected to capacitor array DAC2 via switch S4, and is also connected to the first plate of capacitor C4 and the negative input terminal of low-gain amplifier G via switch S6. The second plates of C1, C2, C3, and C4 are connected to the common-mode level VCM. The first plate of capacitor C9 is connected to the negative input terminal of low-gain amplifier G via switch S13, and is also connected to the first plate of capacitor C5 in the second-stage integrator INT2 via switch S11. The second plate of C9 is connected to the common-mode level VC. On M; the first plate of C9 is connected to the second plate of C9 through switch S15; the first plate of capacitor C10 is connected to the non-inverting input of low-gain amplifier G through switch S14, and is also connected to the first plate of capacitor C6 in the second-stage integrator INT2 through switch S12; the second plate of C10 is connected to the common-mode level VCM; the first plate of C10 is connected to the second plate of C10 through switch S16; the operation of integrator INT1 includes two processes: sampling and integration. During the sampling stage: switches S3, S4, S11, and S12 are turned on, while S5, S6, S13, and S14 are turned off, and capacitors C1, C2, C9, and C10 receive the integrator input signal; during the integration stage: switches S5, S6, S13, and S14 are turned on, while S3, S4, S11, and S12 are closed, and capacitors C1, C2, C9, and C10 share charge with capacitors C3 and C4, completing the integration process.

[0009] The second-stage integrator INT2 consists of switches S7, S8, S9, and S10, and capacitors C5, C6, C7, and C8. The first plate of capacitor C5 is connected to the positive output of the low-gain amplifier G via switch S7, and to the first plate of capacitor C7 and the second positive input of the multi-input comparator COMP via switch S9. The first plate of capacitor C6 is connected to the negative output of the low-gain amplifier G via switch S8, and to the first plate of capacitor C8 and the second negative input of the multi-input comparator COMP via switch S10. The second plates of C5, C6, C7, and C8 are connected to the common-mode level VCM. The operation of integrator INT2 includes two processes: sampling and integration. During the sampling stage, S7 and S8 are turned on while S9 and S10 are turned off, and capacitors C5 and C6 receive the sampled signal. During the integration stage, S9 and S10 are turned on while S7 and S8 are turned off, and capacitors C5 and C6 share charge with capacitors C7 and C8 to complete the integration process.

[0010] The switches S3, S4, S11, and S12 are controlled by the same signal. The control simultaneously turns the circuit on and off; switches S5, S6, S13, S14, S7, and S8 are controlled by the same signal. The control is simultaneously turned on and off; the integration of the first-stage integrator INT1 and the sampling of the second-stage integrator INT2 occur at the same time; switches S9, S10, S15, and S16 are controlled by the same signal. Controls both on and off simultaneously.

[0011] The low-gain amplifier G is a continuous-time amplifier.

[0012] The beneficial effects of this invention are as follows: Through the configuration of differential capacitor arrays DAC1 and DAC2, a first-stage passive integrator INT1, a second-stage passive integrator INT2, a low-gain amplifier G, negative feedback FB, a four-input comparator COMP, a digital logic module SAR Logic, and an asynchronous clock module CLK, this invention consumes less power and has good process portability. The circuit can effectively suppress in-band noise, achieving high accuracy, and is also suitable for low-power applications. Attached Figure Description

[0013] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the specific embodiments or the prior art are briefly introduced below.

[0014] Figure 1 This is a schematic diagram of the overall circuit structure of the present invention;

[0015] Figure 2 This is a signal flow diagram of the overall circuit of the present invention;

[0016] Figure 3 This is a timing diagram of the overall circuit in an embodiment of the present invention;

[0017] Figure 4 Output the reconstructed spectral characteristics of the NS SAR ADC. Detailed Implementation

[0018] A second-order feedforward noise-shaping successive approximation analog-to-digital converter includes: sampling capacitor arrays DAC1 and DAC2, used to store externally sampled analog signals, provide input signals for a four-input comparator COMP, and retain the residual voltage signal after a single-cycle conversion; Figure 1The integrators INT1 and INT2, the low-gain amplifier G, and the feedback section FB together constitute the noise shaping module, which is used to process the residual voltage to achieve noise shaping. Its input comes from the sampling capacitor, and the output signal goes to the comparator input. The four-input comparator COMP's main function is to obtain the comparison result of the analog signal to form a digital output. It includes two pairs of differential signal inputs, a clock signal input, and two signal outputs. The input signals come from the capacitor array output and the noise shaping module output. The clock signal input comes from the asynchronous clock module CLK. The three output signals include a pair of digital comparison results (opposite numbers) outputs and a comparison end indicator signal output. The clock module CLK is used to provide an asynchronous clock for the circuit system. Its inputs include the comparator's comparison end indicator signal and an external clock signal. The digital logic module SAR Logic is used to convert the comparator's serial output to parallel output. The conversion is facilitated by the feedback signal from the comparison structure to the capacitor array.

[0019] like Figure 1 As shown, the noise shaping module in the structure consists of a first-stage integrator INT1, a second-stage integrator INT2, an amplification stage G, and a feedback section FB.

[0020] The first-stage integrator INT1 in the loop filter includes capacitors C1, C2, C3, C4, C9, and C10, and switches S3, S4, S5, S6, S13, and S14. C1, C2, C9, and C10 are sampling capacitors, and C3 and C4 are integration capacitors. The first-stage integrator INT1 contains two pairs of differential inputs and one pair of differential outputs. One pair of differential inputs is connected to the capacitor array to receive the residual signal; the second pair of differential inputs is connected to the output of the feedback section FB to receive the feedback signal; and the differential output is connected to the differential input port of the amplification stage G to pass the integrated signal down. The first-stage integrator INT1 operates in two phases: sampling and integration. During sampling: switches S3, S4, S11, and S12 are on, while S5, S6, S13, and S14 are off. Capacitors C1 and C2 receive the residual voltage from the capacitor array after the current quantization cycle, and capacitors C9 and C10 receive the integration result from the second-stage integrator. During integration: switches S5, S6, S13, and S14 are on, while S3, S4, S11, and S12 are off. Capacitors C1, C2, C9, and C10 share charge with capacitors C3 and C4, accumulating charge on C3 and C4 to achieve integration.

[0021] The second-stage integrator INT2 in the loop filter includes capacitors C5, C6, C7, and C8, and switches S7, S8, S9, and S10. INT2 has one pair of differential inputs and two pairs of differential outputs. The differential inputs are connected to the differential output ports of the amplifier stage G, receiving the sampled signal from the second stage. One pair of differential outputs outputs a signal to a comparator to participate in the quantization of the input signal; the other pair of differential outputs is connected to the input of the feedback section FB. The operation of INT2 includes two stages: sampling and integration. During the sampling stage, S7 and S8 are on, and S9 and S10 are off, allowing capacitors C5 and C6 to receive the output signal from the amplifier stage G. During the integration stage, S9 and S10 are on, and S7 and S8 are off, allowing capacitors C5 and C6 to share charge with capacitors C7 and C8, accumulating charge on C7 and C8 to achieve integration.

[0022] The gain stage G in the loop filter is a low-gain amplifier containing a pair of differential inputs and a pair of differential outputs. The differential inputs are connected to the differential output of the first-stage integrator INT1; the differential outputs are connected to the pair of differential outputs of the second-stage integrator INT2. The output signal of the first-stage integrator INT1 is amplified and used as the input signal of the second-stage integrator INT2.

[0023] The negative feedback FB in the loop filter is used to achieve zero-point optimization. Figure 2 for Figure 1 The signal flow graph corresponding to the overall circuit structure shown defines the signal transfer function (STF) in the system as the ratio of output Vout(Z) to input Vin(Z), and the noise transfer function (NTF) as the ratio of output Vout(Z) to noise Q(Z), where noise Q(Z) includes quantization noise and noise introduced by non-ideal factors. The addition of the negative feedback module FB transforms the real zeros into conjugate zeros to address the low noise suppression capability at the end of the bandwidth. This module consists of a pair of differential inputs and a pair of differential outputs. The differential inputs are connected to the pair of differential outputs of the second-stage integrator INT2; the differential outputs are fed back to the pair of differential inputs of the first-stage integrator.

[0024] Based on the above, draw the signal flow diagram of the overall structure as follows: Figure 2 As shown, the following parameters are defined: α1=C1 / (C1+C3+C9)=C2 / (C2+C4+C10), α2=C5 / (C5+C7)=C6 / (C6+C8), g1=C9 / (C9+C5)=C10 / (C10+C12), g2=C9 / (C1+C3+C9)=C10 / (C2+C4+C10), g=g1×g2. The transfer function of the noise shaping module in the structure can be derived as follows:

[0025]

[0026] Example 1:

[0027] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. The embodiments described herein are only some, not all, embodiments of this invention, and are merely illustrative and not intended to limit the scope of this application.

[0028] The present invention proposes a second-order feedforward noise shaping successive approximation analog-to-digital converter structure as follows: Figure 1 As shown, the structure consists of capacitor arrays DAC1 and DAC2, a loop filter, a four-input dynamic comparator COMP, a digital logic module SAR Logic, and an asynchronous clock module CLK. The capacitor arrays DAC1 and DAC2 store externally sampled analog signals, provide input signals to the comparator, and retain the residual voltage signal after a single-cycle conversion. The noise shaping module, acting as a loop filter for the overall circuit, filters the residual voltage and sends the output to the comparator for quantization in the next cycle. The comparator COMP compares the output of the shaping module with the analog input on the capacitor array and a corresponding threshold, using the comparison result to form the digital output. The clock module CLK provides the asynchronous SARADC timing. The SAR Logic module converts the serial output of the comparator into a parallel output and outputs control signals to the capacitor array during the SARADC conversion process to facilitate the conversion.

[0029] The loop filter in the described structure consists of four parts: a first-stage integrator INT1, a low-gain amplifier G, a second-stage integrator INT2, and a feedback section FB. Both the first-stage integrator INT1 and the second-stage integrator INT2 employ passive switching integrators to achieve integration. The low-gain amplifier G uses a common-source amplifier with a diode-connected MOSFET as the load, providing a certain gain while offering good linearity and a large bandwidth. The addition of the feedback section FB transforms the real zeros in the system's NTF into conjugate zeros, further suppressing noise at the end of the signal band and achieving a better shaping effect. The loop filter in this structure has a simple circuit structure, low area and power consumption, effectively suppresses in-band noise, achieves high accuracy, and has good process portability. This structure is also suitable for some applications with large bandwidth.

[0030] The working cycle of the structure is divided into three stages: sampling stage, SAR ADC conversion stage, and noise shaping stage. For example... Figure 3As shown, at the beginning of a conversion cycle, the circuit first enters the sampling stage. The circuit samples the external analog signal and saves the collected information to the capacitor array. At the same time, the second-stage integrator in the loop filter completes the integration operation, and the integration result is directly sent to the input of the comparator. Next, the circuit enters the asynchronous SAR ADC conversion stage. Under the control of the asynchronous clock, the circuit completes the bit-by-bit quantization of the input signal. After the comparison is completed, the SAR Logic module outputs the parallel quantization result. Finally, the circuit enters the noise shaping stage. The clock module CLK controls the comparator to perform two additional comparison signals. Under the control of these two signals, the loop filter completes the processing of the residual voltage signal.

[0031] The clock signal of the overall circuit is as follows Figure 3 As shown, The external clock signal for the circuit controls switches S1 and S2. When the signal is high, switches S1 and S2 are turned on, sampling external analog signals; when... When the signal changes to a low level, switches S1 and S2 close, and the circuit enters the SAR ADC conversion stage. Additionally, in the circuit... The signal will control The signal undergoes the same change. The comp_clk signal is the comparator's clock signal, outp(outn) is the comparator's comparison result output, and valid is the comparator's comparison end flag. Under the control of the digital module CLK, the SAR ADC conversion begins. After the SAR ADC stage is completed, the comparator performs two additional comparisons. The first comparison generates a clock signal. The second comparison generates a clock signal. After the two comparisons are completed, the rdy signal jumps to a high level, forcibly disconnecting the comparator's clock signal. Clock signal When the transition to a high level, switches S3, S4, S11, and S12 are turned on while S5, S6, S13, and S14 are turned off. Integrator INT1 samples the residual voltage on the capacitor array after the quantization of this cycle through capacitors C1 and C2, and feeds back the integration result of the second-stage integrator through capacitors C9 and C10 in FB. Integrator INT1 completes the sampling action. The transition to low level When the signal transitions to a high level, switches S5, S6, S13, and S14 in integrator INT1 are turned on, while S3, S4, S11, and S12 are closed. Capacitors C1, C2, C9, and C10 share charge with capacitors C3 and C4, achieving integration on C3 and C4. In integrator INT2, switches S7 and S8 are turned on, while S9 and S10 are turned off. Capacitors C5 and C6 sample the output signal of the amplification stage G. When the signal transitions to a high level, switches S9 and S10 in integrator INT2 are turned on while S7 and S8 are turned off. Capacitors C5 and C6 share the charge with capacitors C7 and C8, and integration is achieved on C7 and C8. At the same time, switches S15 and S16 in feedback FB are turned on, and the charge on capacitors C9 and C10 is cleared.

[0032] The sampling phase circuit samples the external analog input signal, and the signal is quantized during the conversion phase. After the last bit of the SAR ADC conversion is complete, the sampling capacitor needs to perform an additional toggle operation based on the last bit to obtain the residual voltage VRES(z) for this cycle. Its relationship with the input and output signals is as follows:

[0033] V RES (z)=D OUT (z)-V IN (z)

[0034] During the residual voltage sampling stage, VRES(z) is shaped by the loop filter HLF(z) and accumulated into the comparator to participate in the SAR ADC quantization process of the next cycle. Its relationship can be written as follows:

[0035] D OUT (z)=V IN (z)-V RES (z)×H LF (z)

[0036] The output DOUT(z) contains the input signal, the quantization error Q(z), and the noise N(z) inside the comparator, i.e.

[0037] D OUT (z)=V IN (z)+Q(z)+N(z)

[0038] Substituting the above equation and simplifying, we get...

[0039]

[0040] Then STF and NTF are respectively

[0041]

[0042] The above situation is derived from the structure of the CIFF-type NS SAR ADC. From the above relationships, it can be seen that the signal is directly output without being affected by the loop filter; quantization noise and comparator noise are filtered by the loop filter. In this structure, the loop filter is composed of an integrator, and the corresponding NTF exhibits high-pass characteristics, pushing noise within the signal band to higher frequencies, improving the signal-to-noise ratio, and consequently increasing the effective number of bits.

[0043] The transfer function of the loop filter in the structure is represented by HLF(z), and the overall signal flow graph of the circuit is as follows. Figure 2 As shown, based on the overall signal flow graph of the circuit, the transfer function of the noise shaping module in the structure can be derived as follows:

[0044]

[0045] In this specific embodiment, the capacitance relationships are as follows: C1 = C2 = 0.15Cu, C3 = C4 = 0.05Cu, C9 = C10 = 0.8Cu, where Cu is defined as unit capacitance; C5 = C6 = 0.075Cu, C7 = C8 = 0.3Cu, and G = 8. Based on the above capacitance relationships, the signal flow diagram of the overall circuit can be obtained as follows. Figure 4 As shown, the corresponding α1 = 0.15, α2 = 0.25, g1 = 0.4, g2 = 0.05, and g = g1 × g2 = 0.02. From the above relationships, the transfer function of the structured loop filter is obtained as follows:

[0046]

[0047] Further, the NTF of the system is obtained as follows:

[0048]

[0049] In the example circuit, the capacitor arrays DAC1 and DAC2 are selected with a quantization bit depth of 10 bits and a signal bandwidth of 500kHz. With 8x oversampling, a 391kHz sinusoidal signal is converted, and FFT analysis of the output yields the converted signal spectrum curve, as shown below. Figure 4 As shown in the figure, the noise shaping effect is significant, with an in-band signal-to-noise ratio of 89.8 dB and an effective bit depth of 14.63 bits.

Claims

1. A second-order feedforward noise-shaping successive approximation analog-to-digital converter, characterized in that: It includes differential capacitor arrays DAC1 and DAC2, first-stage passive integrator INT1, second-stage passive integrator INT2, low-gain amplifier G, negative feedback FB, four-input comparator COMP, digital logic module SAR Logic, and asynchronous clock module CLK; The output of the external sampling switch circuit is connected to the input of capacitor arrays DAC1 and DAC2. The outputs of capacitor arrays DAC1 and DAC2 are connected to the first positive and first negative inputs of the four-input comparator COMP, respectively. The outputs of capacitor arrays DAC1 and DAC2 are connected to the input of the first-stage integrator INT1. The differential output of the first-stage integrator INT1 is connected to the input of the low-gain amplifier G. The output of the low-gain amplifier G is connected to the input of the second-stage integrator INT2. The differential output of the second-stage integrator INT2 is connected to the other input of the four-input comparator COMP. The output of the second-stage integrator INT2 is also connected to the input of the negative feedback FB. The output of the negative feedback FB is connected to the first-stage integrator INT1. The output signal of the four-input comparator COMP is connected to the asynchronous clock module CLK. The output signal of the four-input comparator COMP is connected to the digital logic module SARLogic. The output signal of the digital logic module SARLogic returns to capacitor arrays DAC1 and DAC2.

2. The second-order feedforward noise-shaping successive approximation analog-to-digital converter according to claim 1, characterized in that: The capacitor arrays DAC1 and DAC2 are used to hold the sampled analog signal and the residual voltage of the conversion. The loop filter, consisting of the first-stage passive integrator INT1, the second-stage passive integrator INT2, the low-gain amplifier G, and the negative feedback FB, is used to process the residual signal of a single conversion cycle and send it to the next quantization cycle for quantization.

3. The second-order feedforward noise-shaping successive approximation analog-to-digital converter according to claim 1, characterized in that: The first-stage integrator INT1 includes capacitors C1, C2, C3, C4, C9, and C10, and switches S3, S4, S5, S6, S11, S12, S13, and S14. The first plate of capacitor C1 is connected to capacitor array DAC1 via switch S3, and is also connected to the first plate of capacitor C3 and the positive input terminal of low-gain amplifier G via switch S5. The first plate of capacitor C2 is connected to capacitor array DAC2 via switch S4, and is also connected to the first plate of capacitor C4 and the negative input terminal of low-gain amplifier G via switch S6. The second plates of C1, C2, C3, and C4 are connected to the common-mode level VCM. The first plate of capacitor C9 is connected to the negative input terminal of low-gain amplifier G via switch S13, and is also connected to the first plate of capacitor C5 in the second-stage integrator INT2 via switch S11. The second plate of C9 is connected to the common-mode level VC. On M; the first plate of C9 is connected to the second plate of C9 through switch S15; the first plate of capacitor C10 is connected to the non-inverting input of low-gain amplifier G through switch S14, and is also connected to the first plate of capacitor C6 in the second-stage integrator INT2 through switch S12; the second plate of C10 is connected to the common-mode level VCM; the first plate of C10 is connected to the second plate of C10 through switch S16; the operation of integrator INT1 includes two processes: sampling and integration. During the sampling stage: switches S3, S4, S11, and S12 are turned on, while S5, S6, S13, and S14 are turned off, and capacitors C1, C2, C9, and C10 receive the integrator input signal; during the integration stage: switches S5, S6, S13, and S14 are turned on, while S3, S4, S11, and S12 are closed, and capacitors C1, C2, C9, and C10 share charge with capacitors C3 and C4, completing the integration process.

4. A second-order feedforward noise-shaping successive approximation analog-to-digital converter according to claim 3, characterized in that: The second-stage integrator INT2 consists of switches S7, S8, S9, and S10, and capacitors C5, C6, C7, and C8. The first plate of capacitor C5 is connected to the positive output of the low-gain amplifier G via switch S7, and is also connected to the first plate of capacitor C7 and the second positive input of the multi-input comparator COMP via switch S9. The first plate of capacitor C6 is connected to the negative output of the low-gain amplifier G via switch S8, and is also connected to the first plate of capacitor C8 and the second negative input of the multi-input comparator COMP via switch S10. The second plates of C5, C6, C7, and C8 are connected to the common-mode level VCM. The operation of integrator INT2 includes two processes: sampling and integration. During the sampling stage, S7 and S8 are turned on, and S9 and S10 are turned off, and the sampling signal is received on capacitors C5 and C6. Integration phase: S9 and S10 are turned on, S7 and S8 are turned off, capacitors C5 and C6 share charge with capacitors C7 and C8, and the integration process is completed.

5. A second-order feedforward noise-shaping successive approximation analog-to-digital converter according to claim 4, characterized in that: The switches S3, S4, S11, and S12 are controlled by the same signal. The control simultaneously turns the circuit on and off; switches S5, S6, S13, S14, S7, and S8 are controlled by the same signal. The control is simultaneously turned on and off; the integration of the first-stage integrator INT1 and the sampling of the second-stage integrator INT2 occur at the same time; switches S9, S10, S15, and S16 are controlled by the same signal. Controls both on and off simultaneously.

6. A second-order feedforward noise-shaping successive approximation analog-to-digital converter according to claim 1, characterized in that: The low-gain amplifier G is a continuous-time amplifier.

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