Interleaving sampling circuit and infrared detector reading circuit
By employing an independently powered interleaved sampling circuit structure and noise initialization processing in the infrared detector readout circuit, the noise crosstalk problem was solved, and a low-power, high dynamic range infrared detector readout circuit was achieved.
Patent Information
- Application Number
- CN202510893650.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-30
- Publication Date
- 2025-10-28
AI Technical Summary
In existing infrared detector readout circuits, the interleaved sampling circuit suffers from noise crosstalk due to sharing the same power supply during the acquisition and transmission of sensing signals from adjacent rows of pixels, which affects the output quality.
An interleaved sampling circuit structure with independent power supply is adopted. The storage circuit is powered by the alternating operation of the first and second branches. Noise initialization processing is performed at the beginning of each frame. The output precharge circuit and buffer are combined to reduce noise interference.
This effectively avoids noise crosstalk, improves the uniformity and stability of the output signal, reduces power consumption, and realizes a low-power, high dynamic range infrared detector readout circuit.
Smart Images
Figure CN120856145A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of infrared detection technology, and in particular to an interleaved sampling circuit and an infrared detector readout circuit. Background Technology
[0002] As infrared detectors develop towards large scale, high dynamic range, and low power consumption, the readout circuits of infrared detectors are gradually becoming digital. On-chip integrated analog-to-digital converters (ADCs) avoid noise interference introduced when analog signals are transmitted between chips, enabling the chip to achieve multi-functionality and high dynamic range. The sampling circuit directly connected to the on-chip ADC becomes an important bridge between pixel array data and ADC quantization readout.
[0003] To meet the requirements of large-area arrays, high frame rates, and low power consumption, existing infrared detector readout circuits employ an interleaved sampling circuit structure. This interleaved sampling circuit allows for simultaneous signal acquisition and data transmission, reducing data readout time and increasing the chip's frame rate. Simultaneously, at the same frame rate, the interleaved sampling circuit effectively increases the ADC quantization time, reducing constraints on ADC speed and lowering chip power consumption. Summary of the Invention
[0004] In a first aspect, this disclosure provides an interleaved sampling circuit capable of operating in alternating first and second operating phases, comprising: a first branch and a second branch connected in parallel;
[0005] The first branch road includes:
[0006] The first storage circuit is used to receive and store the electrical signal input to the sampling input terminal during the first working stage, and to output the stored electrical signal to the sampling output terminal during the second working stage.
[0007] The first switching circuit is connected to the first storage circuit, the independent first power supply terminal and the second power supply terminal, and is used to realize the first power supply terminal and the first storage circuit forming a circuit and the second power supply terminal and the first storage circuit forming a circuit in the first working stage, and to realize the second power supply terminal and the first storage circuit forming a circuit and the first power supply terminal and the first storage circuit forming a circuit in the second working stage.
[0008] The second branch road includes:
[0009] The second storage circuit is used to receive and store the electrical signal input to the sampling input terminal during the second working stage, and to output the stored electrical signal to the sampling output terminal during the first working stage.
[0010] The second switching circuit is connected to the second storage circuit, the first power supply terminal, and the second power supply terminal. It is used to achieve a circuit between the second power supply terminal and the second storage circuit and an open circuit between the first power supply terminal and the second storage circuit during the first operating phase, and to achieve a circuit between the first power supply terminal and the second storage circuit and an open circuit between the second power supply terminal and the second storage circuit during the second operating phase.
[0011] In some embodiments, the first switching circuit includes: a first switching transistor and a second switching transistor;
[0012] The control electrode of the first switching transistor is connected to the first control line, the first electrode of the first switching transistor is connected to the first storage circuit, and the second electrode of the first switching transistor is connected to the first power supply terminal.
[0013] The control electrode of the second switching transistor is connected to the second control line, the first electrode of the second switching transistor is connected to the first storage circuit, and the second electrode of the second switching transistor is connected to the second power supply terminal.
[0014] In some embodiments, the second switching circuit includes a third switch and a fourth switch;
[0015] The second switching circuit includes: a third switching transistor and a fourth switching transistor;
[0016] The control electrode of the third switch is connected to the third control line, the first electrode of the third switch is connected to the first storage circuit, and the second electrode of the third switch is connected to the first power supply terminal.
[0017] The control electrode of the fourth switch is connected to the fourth control line, the first electrode of the fourth switch is connected to the second storage circuit, and the second electrode of the fourth switch is connected to the second power supply terminal.
[0018] In some embodiments, an output pre-charge phase is further included between the first working phase and the second working phase;
[0019] The interleaved sampling circuit also includes:
[0020] The output pre-charge circuit is connected to the pre-charge voltage power supply terminal and the sampling output terminal, and is used to form a path between the pre-charge voltage power supply terminal and the sampling output terminal during the pre-charge stage.
[0021] In some embodiments, the output precharge circuit includes: a first transmission gate circuit, wherein the two transmission terminals of the first transmission gate circuit are respectively connected to the precharge voltage power supply terminal and the sampling output terminal.
[0022] In some embodiments, the first branch further includes:
[0023] The first switching circuit is connected to the sampling input terminal and the first intermediate node, and is used to realize the sampling input terminal and the first intermediate node to form a path in the first stage, and to realize the sampling input terminal and the first intermediate node to form an open circuit in the second stage.
[0024] The second switching circuit is connected to the sampling output terminal and the first intermediate node. It is used to achieve a circuit break between the sampling output terminal and the first intermediate node in the first stage, and to achieve a circuit between the sampling output terminal and the first intermediate node in the second stage.
[0025] The second branch road also includes:
[0026] The third switching circuit is connected to the sampling input terminal and the second intermediate node. It is used to achieve a circuit break between the sampling input terminal and the first intermediate node in the first stage and to achieve a circuit between the sampling input terminal and the first intermediate node in the second stage.
[0027] The fourth switching circuit is connected to the sampling output terminal and the second intermediate node. It is used to establish a path between the sampling output terminal and the second intermediate node in the first stage and to establish an open circuit between the sampling output terminal and the second intermediate node in the second stage.
[0028] In some embodiments, the first branch further includes:
[0029] The first noise initialization circuit is connected to the first intermediate node and the corresponding first preset initialization terminal, and is used to establish a path between the first intermediate node and the first preset initialization terminal at the beginning of each frame so as to perform noise initialization processing on the first intermediate node.
[0030] The second branch road also includes:
[0031] The second noise initialization circuit is connected to the second intermediate node and the second preset initialization terminal. It is used to establish a path between the second storage circuit and the second preset initialization terminal at the beginning of each frame so as to perform noise initialization processing on the second intermediate node.
[0032] In some embodiments, the first branch further includes: a first buffer, the first buffer being disposed between the first intermediate node and the second switching circuit, the input terminal of the first buffer being connected to the first intermediate node, the output terminal of the first buffer being connected to the second switching circuit, and the first buffer being used to implement isolation buffering between the first intermediate node and the sampling output terminal.
[0033] The second branch also includes a second buffer, which is located between the second intermediate node and the fourth switching circuit. The input of the second buffer is connected to the second intermediate node, and the output of the second buffer is connected to the fourth switching circuit. The second buffer is used to achieve isolation buffering between the second intermediate node and the sampling output.
[0034] In a second aspect, embodiments of this disclosure provide an infrared detector readout circuit, including: multiple signal readout lines and multiple interleaved sampling circuits corresponding one-to-one with the signal readout lines. The sampling input terminal of the interleaved sampling circuit is connected to the corresponding signal readout line, and the interleaved sampling circuit adopts the interleaved sampling circuit provided in the first aspect.
[0035] In some embodiments, the number of interleaved sampling circuits is M, wherein the first to the (M-1)th interleaved sampling circuits are provided with a first noise initialization circuit and a second noise initialization circuit;
[0036] The first preset initialization terminal connected to the first noise initialization circuit in the m-th interleaved sampling circuit is the first intermediate node in the (m+1)-th interleaved sampling circuit, and the second preset initialization terminal connected to the second noise initialization circuit in the m-th interleaved sampling circuit is the second intermediate node in the (m+1)-th interleaved sampling circuit, where m∈[1,M-1] and is an integer.
[0037] The technical solution disclosed herein, by setting up a first switching circuit and a second switching circuit, enables the acquisition and transmission of sensing signals of adjacent row pixel structures by alternating between the first branch and the second branch. Although the signal acquisition process of the current row and the data transmission process of the previous row overlap in the time domain, the two storage circuits are powered by two independent power supply terminals in these two processes. Therefore, the problem of noise crosstalk caused by coupling between the two branches can be avoided without affecting the normal operation of the two branches. Attached Figure Description
[0038] Figure 1 This is a schematic diagram of a structure of the infrared detector readout circuit involved in this disclosure;
[0039] Figure 2 This is a schematic diagram of the circuit structure of an interleaved sampling circuit involved in related technologies;
[0040] Figure 3 A schematic diagram of the circuit structure of an interleaved sampling circuit provided in an embodiment of this disclosure;
[0041] Figure 4 A schematic diagram of another interleaved sampling circuit provided in an embodiment of this disclosure;
[0042] Figure 5 A schematic diagram of the circuit structure of another interleaved sampling circuit provided in an embodiment of this disclosure;
[0043] Figure 6 This is a schematic diagram of a circuit structure of a buffer in an embodiment of this disclosure;
[0044] Figure 7A schematic diagram comparing the transient output waveforms of the interleaved sampling circuit provided in this disclosure with those of a conventional interleaved sampling circuit;
[0045] Figure 8 A schematic diagram of a plurality of interleaved sampling circuits in an infrared detector readout circuit provided in an embodiment of this disclosure;
[0046] Figure 9 This is a schematic diagram of the working timing of the infrared detector readout circuit in this disclosure.
[0047] Figure 10 This is a schematic diagram comparing the output noise of the interleaved sampling circuit in this disclosure with that of a conventional interleaved sampling circuit. Detailed Implementation
[0048] To enable those skilled in the art to better understand the technical solutions of this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0049] The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as "comprising" or "including" mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.
[0050] The switching device used in this embodiment is a transistor, specifically a thin-film transistor, a field-effect transistor (e.g., a MOSFET), or other devices with switching characteristics. In this embodiment, to distinguish the two terminals of the transistor other than the control electrode (i.e., the gate), one terminal is called the first terminal, and the other is called the second terminal. One of the first and second terminals is the source, and the other is the drain. Generally, the source and drain of a transistor can be interchanged; for example, the first terminal can be used as the source and the second terminal as the drain, or vice versa. Furthermore, according to their conduction performance, transistors can be divided into N-type transistors and P-type transistors. An N-type transistor conducts when the control electrode voltage is high and is cut off when the control electrode voltage is low; a P-type transistor conducts when the control electrode voltage is low and is cut off when the control electrode voltage is high.
[0051] In the various figures, the same elements are represented by similar reference numerals. For clarity, not all parts in the figures are drawn to scale. Furthermore, some well-known parts may not be shown in the figures.
[0052] Many specific details of this disclosure, such as the structure, materials, dimensions, and models of components, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.
[0053] Figure 1 This is a schematic diagram of one structure of the infrared detector readout circuit involved in this disclosure. Figure 1 As shown, the infrared detector readout circuit includes multiple pixel structures (PIX) arranged in an array. Pixel structures in the same column are connected to a corresponding interleaved sampling circuit through the same signal readout lines R_1 to R_M, while pixel structures in different columns are connected to different interleaved sampling circuits through different signal readout lines R_1 to R_M.
[0054] Figure 2 This is a schematic diagram of the circuit structure of an interleaved sampling circuit involved in related technologies. For example... Figure 2 As shown, the interleaved sampling circuit includes: a first branch and a second branch connected in parallel; the first branch includes: a first switching circuit 1, a second switching circuit 2, and a first storage circuit 5, all three connected to a first intermediate node N1; the second branch includes a third switching circuit 3, a fourth switching circuit 4, and a second storage circuit 6, all three connected to a second intermediate node N2. The first storage circuit 5 and the second storage circuit 6 are connected to the same preset power supply terminal and operate under the power supply of the same preset power supply terminal.
[0055] As an example, the first storage circuit 5 includes a first capacitor C1, the first end of which is connected to a first intermediate node N1, and the second end of which is connected to a preset power supply terminal; the second storage circuit 6 includes a second capacitor C2, the first end of which is connected to a second intermediate node N2, and the second end of which is connected to a preset power supply terminal.
[0056] Specifically, the interleaved sampling circuit can operate in alternating first and second operating phases.
[0057] In the first operating phase, the first switching circuit 1 is in the ON state (also known as the "circuit" state), the second switching circuit 2 is in the OFF state (also known as the "open circuit" state), the third switching circuit 3 is in the OFF state, and the fourth switching circuit 4 is in the ON state. At this time, the first storage circuit 5 receives and stores the electrical signal input at the sampling input terminal IN, and the second storage circuit 6 outputs the pre-stored electrical signal to the sampling output terminal OUT. That is, the first branch is in the "signal acquisition" phase, and the second branch is in the "data transmission" phase.
[0058] In the second operating phase, the first switching circuit 1 is in the off state, the second switching circuit 2 is in the on state, the third switching circuit 3 is in the on state, and the fourth switching circuit 4 is in the off state. At this time, the first storage circuit 5 outputs the pre-stored electrical signal to the sampling output terminal OUT, and the second storage circuit 6 receives and stores the electrical signal input to the sampling input terminal IN. The first branch is in the "data transmission" phase, and the second branch is in the "signal acquisition" phase.
[0059] During the actual reading process, each row of pixel structure PIX outputs data line by line. As an example, in the first stage, the pixel structure PIX in the first row inputs the sensed electrical signal to the first branch of the corresponding interleaved sampling circuit through the corresponding signal readout line and stores it; in the first stage, the pixel structure PIX in the second row inputs the sensed electrical signal to the second branch of the corresponding interleaved sampling circuit through the corresponding signal readout line, and the first branch of the corresponding interleaved sampling circuit outputs the sensed electrical signal of the previously stored pixel structure PIX in the first row to the ADC; in the second stage, the pixel structure PIX in the third row inputs the sensed electrical signal to the first branch of the corresponding interleaved sampling circuit through the corresponding signal readout line, and the second branch of the corresponding interleaved sampling circuit outputs the sensed electrical signal of the previously stored pixel structure PIX in the second row to the ADC; in the second stage, the pixel structure PIX in the fourth row inputs the sensed electrical signal to the second branch of the corresponding interleaved sampling circuit through the corresponding signal readout line, and the first branch of the corresponding interleaved sampling circuit outputs the sensed electrical signal of the previously stored pixel structure PIX in the third row to the ADC. That is, the first branch and the second branch alternately output the sensing electrical signal of the corresponding row pixel structure PIX to the ADC.
[0060] However, in practical applications, it was found that when the sensing signals of adjacent row pixel structures PIX are collected and transmitted alternately using two branches, the signal acquisition process of the current row and the data transmission process of the previous row overlap in the time domain. These two processes will be coupled to each other by sharing the same preset power supply terminal, resulting in noise crosstalk between the upper and lower branches, which affects the output of the interleaved sampling circuit.
[0061] Figure 3 This is a schematic diagram of the circuit structure of an interleaved sampling circuit provided in an embodiment of this disclosure. Figure 3 As shown, the interleaved sampling circuit includes: a first branch and a second branch connected in parallel between the sampling input terminal IN and the sampling output terminal OUT; the first branch includes: a first storage circuit 5 and a first switching circuit 7, and the second branch includes: a second storage circuit 6 and a second switching circuit 8.
[0062] The first storage circuit 5 is used to receive and store the electrical signal input at the sampling input terminal IN during the first working stage, and to output the stored electrical signal to the sampling output terminal OUT during the second working stage.
[0063] The first switching circuit 7 is connected to the first storage circuit 5, and to the independent first power supply terminal and second power supply terminal. The first switching circuit 7 is used to achieve a circuit between the first power supply terminal and the first storage circuit 5 and an open circuit between the second power supply terminal and the first storage circuit 5 during the first working stage, and to achieve a circuit between the second power supply terminal and the first storage circuit 5 and an open circuit between the first power supply terminal and the first storage circuit 5 during the second working stage.
[0064] The second storage circuit 6 is used to receive and store the electrical signal input at the sampling input terminal IN during the second working stage, and to output the stored electrical signal to the sampling output terminal OUT during the first working stage.
[0065] The second switching circuit 8 is connected to the second storage circuit 6, the first power supply terminal, and the second power supply terminal. The second switching circuit 8 is used to achieve a circuit between the second power supply terminal and the second storage circuit 6 and an open circuit between the first power supply terminal and the second storage circuit 6 during the first working stage, and to achieve a circuit between the first power supply terminal and the second storage circuit 6 and an open circuit between the second power supply terminal and the second storage circuit 6 during the second working stage.
[0066] It should be noted that in this disclosure, the first power supply terminal and the second power supply terminal are independent of each other, and the voltage values provided by the two are equal. For example, the first power supply terminal provides a first analog ground voltage AVSS1, and the second power supply terminal provides a second analog ground voltage AVSS2, where AVSS1 = AVSS2.
[0067] In the first stage, the first storage circuit 5 in the first branch performs the "signal acquisition" process, and the first power supply terminal supplies power to the first storage circuit 5 through the first switching circuit 7; the second storage circuit 6 in the second branch performs the "data transmission" process, and the second power supply terminal supplies power to the second storage circuit 6 through the second switching circuit 8.
[0068] In the second stage, the first storage circuit 5 in the first branch performs the "data transmission" process, and the second power supply terminal supplies power to the first storage circuit 5 through the first switching circuit 7; the second storage circuit 6 in the second branch performs the "signal acquisition" process, and the second power supply terminal supplies power to the second storage circuit 6 through the second switching circuit 8.
[0069] As can be seen from the above, in the process of acquiring and transmitting the sensing signals of adjacent row pixel structures PIX by alternating between the first and second branches, although the signal acquisition process of the current row and the data transmission process of the previous row overlap in the time domain, the two storage circuits are powered by two independent power supply terminals in these two processes. Therefore, the problem of noise crosstalk caused by coupling between the two branches can be avoided without affecting the normal operation of the two branches.
[0070] In addition, in this disclosure, whether it is the first branch or the second branch, the first power supply terminal will be used to supply power as long as the corresponding branch is in the "signal acquisition" process, and the second power supply terminal will be used to supply power as long as the corresponding branch is in the "data transmission" process.
[0071] It should be noted that the first branch of the interleaved sampling circuit provided in this disclosure also includes the first switching circuit 1 and the second switching circuit 2 involved in the related art, and the second branch also includes the third switching circuit 3 and the fourth switching circuit 4 involved in the related art.
[0072] The first switching circuit 1 is connected to the sampling input terminal IN and the first intermediate node N1. The first switching circuit 1 is used to realize the sampling input terminal IN and the first intermediate node N1 to form a path in the first stage, and to realize the sampling input terminal IN and the first intermediate node N1 to form an open circuit in the second stage.
[0073] The second switching circuit 2 is connected to the sampling output terminal OUT and the first intermediate node N1. The second switching circuit 2 is used to realize the sampling output terminal OUT and the first intermediate node N1 as an open circuit in the first stage, and to realize the sampling output terminal OUT and the first intermediate node N1 as a closed circuit in the second stage.
[0074] The third switching circuit 3 is connected to the sampling input terminal IN and the second intermediate node N2. The third switching circuit 3 is used to realize the sampling input terminal IN and the first intermediate node N1 as an open circuit in the first stage, and to realize the sampling input terminal IN and the first intermediate node N1 as a closed circuit in the second stage.
[0075] The fourth switching circuit 4 is connected to the sampling output terminal OUT and the second intermediate node N2. The fourth switching circuit 4 is used to realize the sampling output terminal OUT and the second intermediate node N2 to form a path in the first stage, and to realize the sampling output terminal OUT and the second intermediate node N2 to form an open circuit in the second stage.
[0076] Figure 4 A schematic diagram of another interleaved sampling circuit provided in an embodiment of this disclosure. (See attached diagram.) Figure 4 As shown, Figure 4 The circuit structure of the interleaved sampling circuit shown is as follows: Figure 3A specific alternative implementation of the circuit structure shown.
[0077] In some embodiments, the first storage circuit 5 includes a first capacitor C1, and the second storage circuit 6 includes a second capacitor C2.
[0078] In some embodiments, the first switching circuit 1, the second switching circuit 2, the third switching circuit 3, and the fourth switching circuit 4 are all transmission gate circuits TG1 to TG4, which can support a large transmission voltage swing. Transmission gate circuits TG1 to TG4 are generally composed of an N-type transistor and a P-type transistor connected in parallel. The operating state of the transmission gate circuit is controlled by controlling the on / off states of the N-type and P-type transistors. As an example, transmission gate circuits TG1 to TG4 use CMOS transmission gates, i.e., an NMOS transistor and a PMOS transistor connected in parallel.
[0079] See Figure 4 As shown, four transmission gate circuits TG1 to TG4, respectively used as the first switching circuit 1, the second switching circuit 2, the third switching circuit 3, and the fourth switching circuit 4, are controlled by the first group of clock control signal lines (CKP1 and CKN2), the second group of clock control signal lines (CKP2 and CKN2), the third group of clock control signal lines (CKP3 and CKN2), and the fourth group of clock control signal lines (CKP4 and CKN4). Two clock control signal lines in each group provide opposite timing to control the N-type transistors and P-type transistors in the corresponding transmission gate circuits TG1 to TG4 to be simultaneously turned on or off.
[0080] In some embodiments, the first switching circuit 7 includes: a first switching transistor S1 and a second switching transistor S2; the control electrode of the first switching transistor S1 is connected to the first control line NG1, the first electrode of the first switching transistor S1 is connected to the first storage circuit 5, and the second electrode of the first switching transistor S1 is connected to the first power supply terminal; the control electrode of the second switching transistor S2 is connected to the second control line NG2, the first electrode of the second switching transistor S2 is connected to the first storage circuit 5, and the second electrode of the second switching transistor S2 is connected to the second power supply terminal.
[0081] The second switching circuit 8 includes: a third switch S3 and a fourth switch S4; the control electrode of the third switch S3 is connected to the third control line NG3, the first electrode of the third switch S3 is connected to the first storage circuit 5, and the second electrode of the third switch S3 is connected to the first power supply terminal; the control electrode of the fourth switch S4 is connected to the fourth control line NG4, the first electrode of the fourth switch S4 is connected to the second storage circuit 6, and the second electrode of the fourth switch S2 is connected to the second power supply terminal.
[0082] In some embodiments, considering that the first switch S1 and the fourth switch S4 are both turned on in the first stage and turned off in the second stage, and the second switch S2 and the third switch S3 are both turned off in the first stage and turned on in the second stage, when the first switch S1 and the fourth switch S4 are both N-type transistors or P-type transistors, the first control line NG1 and the fourth control line NG4 can be the same control signal; when the second switch S2 and the third switch S3 are both N-type transistors or P-type transistors, the second control line NG2 and the third control line NG3 can be the same control signal, thus effectively reducing the types and number of control line wiring.
[0083] It should be noted that the attached figures only illustrate the case where all switching transistors are N-type switching transistors, and this case is only shown as an example.
[0084] Figure 5 This is a schematic diagram of the circuit structure of another interleaved sampling circuit provided in an embodiment of this disclosure. (See attached diagram.) Figure 5 As shown, the interleaved sampling circuit in this embodiment includes not only the first branch and the second branch in the previous embodiment, but also the output pre-charge circuit 9.
[0085] In some embodiments, between the first operating phase and the second operating phase, there is also an output pre-charge phase; the interleaved sampling circuit further includes an output pre-charge circuit 9, which is connected to the pre-charge voltage power supply terminal and the sampling output terminal OUT, and the output pre-charge circuit 9 is used to realize the pre-charge voltage power supply terminal and the sampling output terminal OUT forming a path during the pre-charge phase.
[0086] The output pre-charging circuit 9 can pre-charge the sampling output terminal OUT before the start of each working stage, so that the second branch can complete the charging / discharging quickly when transmitting data to the sampling output terminal OUT in the first stage, and the first branch can complete the charging / discharging quickly when transmitting data to the sampling output terminal OUT in the first stage.
[0087] As an example, the precharge voltage provided by the precharge voltage power supply is AVDD / 2; where AVDD is the maximum operating voltage (preset) that the first / second branch can output to the sampling output terminal OUT. In contrast, when the output precharge circuit is not set, in the first / second stage, the voltage jump variable (the absolute value of the difference between the target voltage value and the initial voltage value) ΔV at the sampling output terminal OUT ranges from 0V to AVDD; when the output precharge circuit is set (the initial voltage value at the sampling output terminal OUT is constant at AVDD / 2), in the first / second stage, the voltage jump variable ΔV at the sampling output terminal OUT ranges from 0V to AVDD / 2, meaning the maximum value of the voltage jump variable is halved.
[0088] In some embodiments, the output precharge circuit 9 includes a first transmission gate circuit TG5, the two transmission terminals of which are respectively connected to the precharge voltage power supply terminal and the sampling output terminal OUT. The on / off state between the precharge voltage power supply terminal and the sampling output terminal OUT can be controlled by a corresponding set of control lines NG5 / NG6 (providing opposite timing).
[0089] The first transmission gate circuit TG5 includes: a first N-type transistor and a first P-type transistor; the control electrode of the first N-type transistor is connected to the fifth control line, the first electrode of the first N-type transistor is connected to the sampling output terminal OUT, and the second electrode of the first N-type transistor is connected to the pre-charge voltage power supply terminal; the control electrode of the first P-type transistor is connected to the sixth control line, the first electrode of the first P-type transistor is connected to the sampling output terminal OUT, and the second electrode of the first P-type transistor is connected to the pre-charge voltage power supply terminal.
[0090] In practical applications, it has been found that parasitic capacitance mismatch between different channel columns and non-ideal switching effects lead to non-uniformity of noise interference at the first / second intermediate nodes in different interleaved sampling circuits within the infrared detector readout circuit. This non-uniformity of noise and interference causes different interleaved sampling circuits to ultimately output different electrical signals when receiving the same sensing electrical signal. To effectively improve the above-mentioned technical problems, this disclosure provides a corresponding solution.
[0091] In some embodiments, the first branch further includes a first noise initialization circuit 10, and the second branch further includes a second noise initialization circuit 11.
[0092] The first noise initialization circuit 10 is connected to the first intermediate node N1 and the corresponding first preset initialization terminal. The first noise initialization circuit 10 is used to establish a path between the first intermediate node N1 and the first preset initialization terminal at the beginning of each frame so as to perform noise initialization processing on the first intermediate node N1.
[0093] The second noise initialization circuit 11 is connected to the second intermediate node N2 and the second preset initialization terminal. The second noise initialization circuit 11 is used to establish a path between the second storage circuit 6 and the second preset initialization terminal at the beginning of each frame so as to perform noise initialization processing on the second intermediate node N2.
[0094] In this disclosure, noise initialization processing of the first / second intermediate nodes is performed using the first / second noise initialization circuit at the beginning of each frame, thereby ensuring that the initial noise of the first / second intermediate nodes in each interleaving sampling circuit is consistent at the beginning of each frame, so as to ensure the consistency of the output performance of each subsequent interleaving sampling circuit.
[0095] It should be noted that the first / second preset initialization terminal of the first noise initialization circuit used in this disclosure can be a voltage supply terminal that provides a constant voltage, a ground terminal, or a first / second intermediate node in other interleaved sampling circuits (the noise consistency of all first / second intermediate nodes can be achieved by electrically connecting the first / second intermediate nodes in multiple interleaved sampling circuits, as described later).
[0096] In some embodiments, the first noise initialization circuit includes a second transmission gate circuit TG6. The two transmission terminals of the second transmission gate circuit TG6 are respectively connected to the first intermediate node N1 and the first preset initialization terminal P1. The on / off state between the first intermediate node N1 and the first preset initialization terminal P1 can be controlled by a corresponding set of control lines NG7 / NG8 (providing opposite timing).
[0097] The second noise initialization circuit includes a third transmission gate circuit TG7. The two transmission terminals of the third transmission gate circuit TG7 are connected to the second intermediate node N2 and the second preset initialization terminal P2, respectively. The on / off state between the second intermediate node N2 and the second preset initialization terminal P2 can be controlled through a corresponding set of control lines NG9 / NG10 (providing opposite timing).
[0098] In practical applications, considering that the first noise initialization circuit 10 and the second noise initialization circuit 11 work simultaneously at the beginning of each frame, the set of control lines NG7 / NG8 used to control the second transmission gate circuit TG6 and the set of control lines NG9 / NG10 used to control the third transmission gate circuit TG7 are the same set of control lines.
[0099] See you again Figure 2 As shown, in related technologies, because the ADC input terminal has parasitic capacitance and is directly connected to the interleaved sampling circuit, when the second switching circuit 2 or the fourth switching circuit 4 is in the conducting state, the voltage value held on the first capacitor C1 or the second capacitor C2 will deviate from the voltage value held on the first capacitor C1 or the second capacitor C2 due to charge redistribution. Furthermore, the same sensing electrical signal data input will cause the output data result to deviate due to the different sensing electrical signal data in the previous row, which deteriorates the uniformity of the array data output.
[0100] Specifically, in a certain first working stage, the first switch circuit 1 in the first branch is in the on state and the second switch circuit 2 is in the off state, while the third switch circuit 3 in the second branch is in the off state and the second switch circuit 2 is in the on state. At this time, the first branch writes the sensing signal of the corresponding pixel structure PIX in the a-th row to the first intermediate node N1 through the "signal acquisition" process, with a voltage magnitude of VIN_a. The second branch outputs the sensing signal of the corresponding pixel structure PIX in the a-1-th row (the row above the a-th row) to the input terminal of the ADC through the "data transmission" process, with a voltage magnitude of VOUT_a-1.
[0101] In the second operating stage following the first operating stage, the first switching circuit 1 in the first branch is in an open state, and the second switching circuit 2 is in a conducting state; the third switching circuit 3 in the second branch is in a conducting state, and the second switching circuit 2 is in an open state. According to charge conservation, after the second switching circuit 2 is in a conducting state, it outputs voltage VOUT_a to the sampling output terminal OUT (i.e., the input terminal of the ADC).
[0102]
[0103] in, The capacitance value of the first capacitor C1. This is the parasitic capacitance value at the OUT end of the sampling output terminal (which can be regarded as the parasitic capacitance at the ADC input terminal).
[0104] Based on the above, it can be seen that due to the charge redistribution effect, the final output voltage VOUT_a of the first branch to the sampling output terminal OUT changes relative to the voltage VIN_a written to the first capacitor C1 during the "signal acquisition" process. .in, The smaller the ratio, the more significant the change in output voltage. Even with the same VIN_a, if the output data VOUT_a-1 in the previous row is different, the output result VOUT_a will also be different.
[0105] To effectively address this technical problem, the technical solution disclosed herein provides a corresponding solution. (See also: [link to related document]) Figure 5As shown, in some embodiments, the first branch further includes: a first buffer BUF1, which is disposed between the first intermediate node N1 and the second switching circuit 2. The input terminal of the first buffer BUF1 is connected to the first intermediate node N1, and the output terminal of the first buffer BUF1 is connected to the second switching circuit 2. The first buffer BUF1 is used to achieve isolation buffering between the first intermediate node N1 and the sampling output terminal OUT. The second branch further includes: a second buffer BUF2, which is disposed between the second intermediate node N2 and the fourth switching circuit 4. The input terminal of the second buffer BUF2 is connected to the second intermediate node N2, and the output terminal of the second buffer BUF2 is connected to the fourth switching circuit 4. The second buffer BUF2 is used to achieve isolation buffering between the second intermediate node N2 and the sampling output terminal OUT.
[0106] In this disclosure, by setting a first / second buffer in the first / second branch, isolation buffering between the first / second intermediate node and the sampling output terminal OUT can be achieved, so that the "data transmission" is not affected by the back-end parasitic capacitance, and the voltage of the first / second intermediate node is stably output.
[0107] Figure 6 This is a schematic diagram of a circuit structure for a buffer in an embodiment of this disclosure. Figure 6 As shown, in this disclosure, both the first buffer and the second buffer can be adopted. Figure 6 The buffer circuit structure shown is a differential input-current mirror load buffer, specifically including: a current source, a differential pair, and a current mirror structure. The buffer uses the differential pair (transistors M1, M2) to suppress common-mode noise, and the current mirror (transistors M3, M4) to provide active load gain boost.
[0108] Considering that the first and second branches alternate in the "data transmission" process, it is only necessary to ensure that the first buffer is in normal working condition during the second working phase and the second buffer is in normal working condition during the first working phase. Optionally, this disclosure makes corresponding improvements to the buffer circuit, namely, adding a control circuit part that can control whether the buffer is operating normally; specifically, a working control switch MT is connected in parallel across the current source; when the working control switch MT is in the on state, the current source is short-circuited and the buffer is in a non-working state; when the working control switch MT is in the off state, the current source supplies power normally and the buffer is in a normal working state. Specifically, in the first stage, the working control switch in the first buffer (controlled by BUF_EN1) is in the on state and the working control switch in the second buffer (controlled by BUF_EN2) is in the off state; in the second stage, the working control switch in the first buffer is in the off state and the working control switch in the second buffer is in the on state. This design can effectively reduce the overall power consumption of the two buffers.
[0109] It should be noted that when the first / second branch is equipped with the first / second buffer, the aforementioned output precharge circuit 9 is also added, which can effectively reduce the average fluctuation of the buffer output voltage. For example, when the precharge voltage provided by the precharge voltage power supply terminal is AVDD / 2, the average fluctuation of the buffer output voltage is reduced by half, and the static power consumption is reduced by half.
[0110] In some embodiments, a third capacitor C3 for low-pass filtering is added at the sampling output terminal OUT. By setting the third capacitor C3, the glitch signal generated by the high-frequency coupling interference of the ADC can be suppressed, so that the peak value of the glitch noise at the output terminal of the analog column channel is less than 1 / 2 LSB, and the high-frequency noise interference can prevent the ADC quantization process from having bit errors.
[0111] Figure 7 This diagram illustrates a comparison of the transient output waveforms of the interleaved sampling circuit provided in this disclosure and a traditional interleaved sampling circuit. Figure 7 As shown, under the same high-level input, the output of a conventional interleaved sampling circuit is non-uniform due to charge redistribution, and the output deviates from the input value. The interleaved sampling circuit provided in this disclosure has low noise, stable output that follows the input value, ensuring good uniformity, and also features low power consumption.
[0112] Based on the same inventive concept, this disclosure also provides an infrared detector readout circuit. Figure 8 This is a schematic diagram of a structure of multiple interleaved sampling circuits in the readout circuit of an infrared detector provided in an embodiment of this disclosure. Figure 9 This is a schematic diagram of the working timing of the infrared detector readout circuit in this disclosure. Figure 10 This is a schematic diagram comparing the output noise of the interleaved sampling circuit in this disclosure with that of a conventional interleaved sampling circuit. Figure 1 as well as Figures 8 to 10 As shown, the infrared detector readout circuit includes: multiple pixel structures (PIX) arranged in an array, multiple signal readout lines R_1 to R_M, and multiple interleaved sampling circuits. Pixel structures (PIX) located in the same column are connected to a corresponding interleaved sampling circuit through the same signal readout line R_1 to R_M, and pixel structures (PIX) located in different columns are connected to different interleaved sampling circuits through different signal readout lines. The interleaved sampling circuit can be the interleaved sampling circuit provided in any of the previous embodiments.
[0113] In some embodiments, the number of interleaved sampling circuits is M, wherein the first to the (M-1)th interleaved sampling circuits are each provided with a first noise initialization circuit 10 and a second noise initialization circuit 11; at this time, the first preset initialization terminal P1 connected to the first noise initialization circuit 10 in the m-th interleaved sampling circuit is the first intermediate node N1 in the (m+1)-th interleaved sampling circuit, and the second preset initialization terminal P2 connected to the second noise initialization circuit 11 in the m-th interleaved sampling circuit is the second intermediate node N2 in the (m+1)-th interleaved sampling circuit, where m∈[1,M-1] and is an integer.
[0114] At the beginning of each frame, the first noise initialization circuit 10 and the second noise initialization circuit 11 in all interleaved sampling circuits are in the on state. At this time, all first intermediate nodes N1 are electrically connected to achieve noise unification, and all second intermediate nodes N2 are electrically connected to achieve noise unification.
[0115] See also Figure 1 As shown, the infrared detector readout circuit also includes multiple row scan lines SEL_1 to SEL_N. Pixel structures PIX located in the same row are connected to the same row scan lines SEL_1 to SEL_N. Through these multiple row scan lines SEL_1 to SEL_N, the pixel structures PIX in each row can be controlled to output sensing signals to the corresponding interleaved sampling circuit row by row.
[0116] See Figure 9 As shown, at the beginning of a frame, the first noise initialization circuit 10 and the second noise initialization circuit 11 can be controlled to operate via control lines NG7, NG8, NG9, and NG10. Thereafter, the first and second operating phases alternate, with an output pre-charge phase existing between them. Furthermore, during the alternation of the first and second operating phases, the first and second buffers also alternate in a low-power mode.
[0117] In addition, by Figure 10 It is evident that the technical solution disclosed herein can effectively eliminate internal noise coupling in the interleaved sampling circuit and suppress non-uniform noise from different interleaved sampling circuits in the infrared detector readout circuit.
[0118] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.
Claims
1. An interleaved sampling circuit, characterized in that, It can operate in alternating first and second working phases, including: the first branch and the second branch in parallel; The first branch road includes: The first storage circuit is used to receive and store the electrical signal input to the sampling input terminal during the first working stage, and to output the stored electrical signal to the sampling output terminal during the second working stage. The first switching circuit is connected to the first storage circuit, the independent first power supply terminal and the second power supply terminal, and is used to realize the first power supply terminal and the first storage circuit forming a circuit and the second power supply terminal and the first storage circuit forming a circuit in the first working stage, and to realize the second power supply terminal and the first storage circuit forming a circuit and the first power supply terminal and the first storage circuit forming a circuit in the second working stage. The second branch road includes: The second storage circuit is used to receive and store the electrical signal input to the sampling input terminal during the second working stage, and to output the stored electrical signal to the sampling output terminal during the first working stage. The second switching circuit is connected to the second storage circuit, the first power supply terminal, and the second power supply terminal. It is used to achieve a circuit between the second power supply terminal and the second storage circuit and an open circuit between the first power supply terminal and the second storage circuit during the first operating phase, and to achieve a circuit between the first power supply terminal and the second storage circuit and an open circuit between the second power supply terminal and the second storage circuit during the second operating phase.
2. The interleaved sampling circuit according to claim 1, characterized in that, The first switching circuit includes: a first switching transistor and a second switching transistor; The control electrode of the first switching transistor is connected to the first control line, the first electrode of the first switching transistor is connected to the first storage circuit, and the second electrode of the first switching transistor is connected to the first power supply terminal. The control electrode of the second switching transistor is connected to the second control line, the first electrode of the second switching transistor is connected to the first storage circuit, and the second electrode of the second switching transistor is connected to the second power supply terminal.
3. The interleaved sampling circuit according to claim 1, characterized in that, The second switching circuit includes: a third switching transistor and a fourth switching transistor; The second switching circuit includes: a third switching transistor and a fourth switching transistor; The control electrode of the third switch is connected to the third control line, the first electrode of the third switch is connected to the first storage circuit, and the second electrode of the third switch is connected to the first power supply terminal. The control electrode of the fourth switch is connected to the fourth control line, the first electrode of the fourth switch is connected to the second storage circuit, and the second electrode of the fourth switch is connected to the second power supply terminal.
4. The interleaved sampling circuit according to claim 1, characterized in that, Between the first and second working phases, there is also an output pre-charge phase. The interleaved sampling circuit also includes: The output pre-charge circuit is connected to the pre-charge voltage power supply terminal and the sampling output terminal, and is used to form a path between the pre-charge voltage power supply terminal and the sampling output terminal during the pre-charge stage.
5. The interleaved sampling circuit according to claim 1, characterized in that, The output precharge circuit includes: a first transmission gate circuit, the two transmission terminals of which are respectively connected to the precharge voltage power supply terminal and the sampling output terminal.
6. The interleaved sampling circuit according to any one of claims 1 to 5, characterized in that, The first branch road also includes: The first switching circuit is connected to the sampling input terminal and the first intermediate node, and is used to realize the sampling input terminal and the first intermediate node to form a path in the first stage, and to realize the sampling input terminal and the first intermediate node to form an open circuit in the second stage. The second switching circuit is connected to the sampling output terminal and the first intermediate node. It is used to achieve a circuit break between the sampling output terminal and the first intermediate node in the first stage, and to achieve a circuit between the sampling output terminal and the first intermediate node in the second stage. The second branch road also includes: The third switching circuit is connected to the sampling input terminal and the second intermediate node. It is used to achieve a circuit break between the sampling input terminal and the first intermediate node in the first stage and to achieve a circuit between the sampling input terminal and the first intermediate node in the second stage. The fourth switching circuit is connected to the sampling output terminal and the second intermediate node. It is used to establish a path between the sampling output terminal and the second intermediate node in the first stage and to establish an open circuit between the sampling output terminal and the second intermediate node in the second stage.
7. The interleaved sampling circuit according to claim 6, characterized in that, The first branch road also includes: The first noise initialization circuit is connected to the first intermediate node and the corresponding first preset initialization terminal, and is used to establish a path between the first intermediate node and the first preset initialization terminal at the beginning of each frame so as to perform noise initialization processing on the first intermediate node. The second branch road also includes: The second noise initialization circuit is connected to the second intermediate node and the second preset initialization terminal. It is used to establish a path between the second storage circuit and the second preset initialization terminal at the beginning of each frame so as to perform noise initialization processing on the second intermediate node.
8. The interleaved sampling circuit according to claim 6, characterized in that, The first branch also includes: a first buffer, which is disposed between the first intermediate node and the second switching circuit. The input terminal of the first buffer is connected to the first intermediate node, and the output terminal of the first buffer is connected to the second switching circuit. The first buffer is used to achieve isolation buffering between the first intermediate node and the sampling output terminal. The second branch also includes a second buffer, which is located between the second intermediate node and the fourth switching circuit. The input of the second buffer is connected to the second intermediate node, and the output of the second buffer is connected to the fourth switching circuit. The second buffer is used to achieve isolation buffering between the second intermediate node and the sampling output.
9. An infrared detector readout circuit, characterized in that, include: Multiple signal readout lines and multiple interleaved sampling circuits corresponding one-to-one with the signal readout lines, wherein the sampling input terminal of the interleaved sampling circuit is connected to the corresponding signal readout line, and the interleaved sampling circuit adopts any one of the interleaved sampling circuits in claims 1 to 8.
10. The infrared detector readout circuit according to claim 9, characterized in that, The number of interleaved sampling circuits is M, wherein the first to the (M-1)th interleaved sampling circuits all adopt the interleaved sampling circuit of claim 7; The first preset initialization terminal connected to the first noise initialization circuit in the m-th interleaved sampling circuit is the first intermediate node in the (m+1)-th interleaved sampling circuit, and the second preset initialization terminal connected to the second noise initialization circuit in the m-th interleaved sampling circuit is the second intermediate node in the (m+1)-th interleaved sampling circuit, where m∈[1,M-1] and is an integer.