Crimping type IGBT current self-balancing emitter signal loop structure and circuit

Abstract

The invention provides a crimping type IGBT current self-balancing emitter signal loop structure and circuit, and relates to the crimping type IGBT chip technology field, the loop structure comprises an IGBT chip, a driving signal PCB provided with a first position, a second position and two wiring holes, and an emitter pedestal, the grid electrode is electrically connected with one wiring hole through the first position, and the second position is electrically connected with the other wiring hole through the second position. The emitting electrode is electrically connected with the other wiring hole through a third position and a second position on the emitting electrode base, and an external driving circuit is electrically connected between the two wiring holes. According to the loop structure, through a new grid-emitting electrode signal loop construction mode, the influence of stray inductance of an emitting electrode base on parallel chip grid signals is eliminated, and consistent emitting electrode boss inductance in the emitting electrode base is creatively introduced into a negative feedback mechanism for chip current sharing; the parallel chips are endowed with the capability of automatically adjusting the grid voltage according to the magnitude of the through-flow, so that the crimping type IGBT has a better current sharing effect.

Description

Technical Field

[0001] This invention relates to the field of press-fit IGBT chip technology, specifically to a press-fit IGBT current self-balancing emitter signal loop structure and circuit. Background Technology

[0002] As a core component of high-voltage, high-capacity power electronic equipment, press-fit IGBTs have become one of the core devices in flexible DC transmission systems due to their double-sided heat dissipation and ease of series connection. However, with the increase in the number of parallel IGBTs, the problem of uneven current distribution within the press-fit IGBTs has become increasingly serious. Due to differences in the dynamic and static characteristics of the chips and the stray parameters of the packaging structure, the current carried by each chip will vary significantly, leading to reliability risks such as local overload and shortened lifespan, thus limiting the number of chips that can be connected in parallel. Summary of the Invention

[0003] This invention addresses the problems existing in the prior art by providing an emitter signal loop structure and circuit for press-fit IGBTs that eliminates the influence of stray inductance from the emitter base on the gate voltage, reduces the current change rate, and achieves good current sharing. Through a novel gate-emitter signal loop construction method, the influence of stray inductance from the emitter base on the gate signal of parallel chips is eliminated. Furthermore, the invention creatively introduces the emitter bump inductance in the consistent emitter base into a negative feedback mechanism for chip current sharing, giving parallel chips the ability to autonomously adjust the gate voltage according to the current magnitude, thus enabling press-fit IGBTs to achieve better current sharing.

[0004] To achieve the above objectives, the present invention adopts the following technical solution: a press-fit type IGBT current self-balancing emitter signal loop structure, comprising at least two IGBT chips, a drive signal PCB board, and an emitter base. The emitter of the IGBT chip is electrically connected to the emitter base. The drive signal PCB board includes two wiring holes, at least two first positions, and at least two second positions. The at least two first positions and the at least two second positions correspond one-to-one with the at least two IGBT chips. The at least two first positions are electrically connected to one of the wiring holes, and the at least two second positions are electrically connected to the other wiring hole. The gate of each IGBT chip is electrically connected to the corresponding first position. The emitter base includes at least two third positions, which correspond one-to-one with the at least two second positions. The third positions are electrically connected to the corresponding second positions. An external drive circuit is electrically connected between the two wiring holes.

[0005] In some embodiments, the at least two IGBT chips and the drive signal PCB board are respectively mounted on the emitter base.

[0006] In some embodiments, at least two emitter protrusions are provided on the emitter base, and the at least two emitter protrusions correspond one-to-one with the at least two IGBT chips. At least two through holes are provided on the drive signal PCB board, and the at least two through holes correspond one-to-one with the at least two emitter protrusions. The emitter protrusions pass through the corresponding through holes, and the emitter of the IGBT chip is electrically connected to the corresponding emitter protrusion.

[0007] In some embodiments, the emitter of the IGBT chip is electrically connected to the end of the corresponding emitter bump, and the third position is close to the root of the emitter bump.

[0008] In some embodiments, the end face of the emitter boss is located on the same side of the drive signal PCB board as the third position.

[0009] In some embodiments, each of the second positions is electrically connected to a spring pin, which is electrically connected to the third position.

[0010] In some embodiments, the drive signal PCB board further includes at least two first surface mount resistors, with each second position having a first surface mount resistor on one side, and the spring pin connected in series with the corresponding first surface mount resistor.

[0011] In some embodiments, the IGBT chip further includes a gate pin, one end of which is electrically connected to the gate of the IGBT chip, and each of the first positions is electrically connected to a gate pin, with the gate pin being electrically connected to the corresponding gate pin.

[0012] In some embodiments, the drive signal PCB board further includes at least two first surface mount resistors, with a second surface mount resistor disposed on one side of each of the first positions, and the gate pin is connected in series with the corresponding second surface mount resistor.

[0013] A self-balancing emitter signal circuit for press-fit IGBTs is provided, applied to the self-balancing emitter signal loop structure of the press-fit IGBT. The circuit includes at least two IGBT chips, a drive signal PCB board, and an emitter base. The emitter is electrically connected to the emitter base. The drive signal PCB board includes two wiring holes, at least two first positions, and at least two second positions. Each of the at least two first positions and at least two second positions corresponds one-to-one with one of the at least two IGBT chips. Each of the at least two first positions is electrically connected to one of the wiring holes, and each of the at least two second positions is electrically connected to the other wiring hole. The gate of each IGBT chip is electrically connected to its corresponding first position. The emitter base includes at least two third positions, each corresponding one-to-one with one of the at least two second positions. Each third position is electrically connected to its corresponding second position. An external drive circuit is electrically connected between the two wiring holes.

[0014] Compared with the prior art, this disclosure has the following beneficial effects:

[0015] 1. This disclosure constructs a feedback emitter circuit, which bypasses the large amount of stray inductance brought by the emitter base of the original press-fit IGBT signal circuit with a new structural layout, eliminates the influence of stray inductance brought by the emitter base on the gate voltage, and creatively introduces the emitter bump inductance of the consistent emitter base into the negative feedback mechanism for chip current sharing, giving the parallel chip the ability to adjust the gate voltage autonomously according to the current magnitude. Compared with the existing typical press-fit IGBT, the parallel IGBT chip has a better current sharing effect.

[0016] 2. The feedback emitter circuit of this disclosure reduces the rate of current change and reduces the impact of stray inductance on the turn-on / turn-off of press-fit IGBTs.

[0017] 3. This disclosure effectively prevents the effects of gate oscillation by connecting a second surface mount resistor in series with the gate pin and a first surface mount resistor in series with the spring pin. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the emitter signal circuit structure of the current self-balancing press-fit IGBT disclosed in this paper.

[0019] Figure 2 Exploded view of the self-balancing emitter signal circuit structure of the press-fit type IGBT. Figure I ;

[0020] Figure 3 This is an exploded front view of the emitter signal circuit structure of the current self-balancing press-fit IGBT disclosed in this paper.

[0021] Figure 4 Exploded view of the self-balancing emitter signal circuit structure of the press-fit type IGBT. Figure II ;

[0022] Figure 5 Exploded view of the self-balancing emitter signal circuit structure of the press-fit type IGBT. Figure III ;

[0023] Figure 6 The circuit diagram shows the emitter signal loop structure of the current self-balancing press-fit IGBT disclosed in this paper.

[0024] Figure 7 This is a circuit diagram of a multi-chip parallel structure of a typical press-fit IGBT in the prior art.

[0025] The reference numerals in the attached drawings are as follows: 1. Collector top cover; 11. First groove; 2. Drive signal PCB board; 21. Wiring hole; 22. Through hole; 3. Emitter base; 31. Emitter boss; 4. IGBT chip; 41. Second groove; 5. Gate pin; 6. Spring pin; 7. Gate pin; 8. First surface mount resistor; 9. Second surface mount resistor. Detailed Implementation

[0026] To address the problems in the background technology, the following analysis is provided on a typical press-fit IGBT in the prior art: See Figure 7 The figure shows a typical multi-chip parallel structure circuit diagram of a press-fit type IGBT.

[0027] Figure 7 In the middle, v GE The voltage across the GE terminals of the signal circuit is the voltage of the external drive circuit when a typical press-fit IGBT is used. GEi Let L be the actual gate-emitter voltage of the i-th IGBT chip, where i is the IGBT chip number (i = 1 to n), and n is the total number of IGBT chips. Ei Let L be the stray inductance of the emitter bump of the i-th IGBT chip. EPi L is the distributed stray inductance associated with the i-th IGBT chip due to the emitter base. CPi Let i be the distributed stray inductance of the collector copper plate above the i-th IGBT chip. CEi The actual current of the i-th IGBT chip is shown in the figure. The stray inductance of the drive signal PCB board is simplified and omitted because it is decoupled from the power circuit and the gate current is much smaller than the main circuit current.

[0028] According to Kirchhoff's voltage law, the actual gate-emitter voltage of each IGBT chip can be described by equation (1):

[0029]

[0030] For different chips, the parasitic inductance of the emitter bump is the stray inductance L of the i-th IGBT chip. Ei Their values ​​are basically the same, because they have the same structure, so the first term on the right side of the equation (1) is equal to the second term. In the multi-chip parallel structure of press-fit IGBT, since the gate-emitter (GE) signal circuit and the collector-emitter (CE) power circuit share the common path of the conductor where the emitter base is located, the position of the IGBT chip is related to the current path. Different positions will cause the parasitic inductance in the third term, that is, the distributed stray inductance L brought by the emitter base related to the i-th IGBT chip. EPi Different. The transient current change rate of a press-fit IGBT during turn-on / off can exceed 10⁸ A / s. At this time, the gate voltage of the drive circuit, i.e., the voltage v of the external drive circuit, is... GE It is also in a rapidly changing phase, which means that the induced voltage on the parasitic inductance will significantly affect the actual gate voltage of each IGBT chip, i.e., the actual gate-emitter voltage v of the i-th IGBT chip. GEi This ultimately leads to differences in the switching speed and current distribution of the parallel IGBT chips.

[0031] Existing technologies primarily mitigate this problem by optimizing the power circuit layout. However, regardless of whether it's a circular layout or other layout methods, it's difficult to completely eliminate the issue of varying stray inductances in each emitter power circuit.

[0032] Existing methods cannot solve the problem of stray inductance from the emitter base causing differences in the gate voltage (i.e., the actual gate-emitter voltage) of each IGBT chip, leading to uneven current distribution among the chips and significantly impacting chip reliability. Therefore, this invention proposes a feedback emitter loop to eliminate the influence of stray inductance from the emitter base on the gate voltage, thereby achieving better current sharing for multiple parallel-connected chips.

[0033] To clearly illustrate the technical features of this solution, the implementation methods of this application will be described in detail below with reference to the accompanying drawings and embodiments. This will allow for a full understanding and implementation of how this application uses technical means to solve technical problems and achieve corresponding technical effects. The embodiments of this application and the various features within them can be combined with each other without conflict, and the resulting technical solutions are all within the protection scope of this application.

[0034] See Figure 1-5This disclosure provides a self-balancing emitter signal loop structure for press-fit IGBTs, including at least two IGBT chips 4, a drive signal PCB board 2, and an emitter base 3. The emitter of the IGBT chip 4 is electrically connected to the emitter base 3. The drive signal PCB board 2 includes two wiring holes 21, at least two first positions, and at least two second positions. The at least two first positions and at least two second positions correspond one-to-one with the at least two IGBT chips 4. The at least two first positions are electrically connected to one of the wiring holes 21, and the at least two second positions are electrically connected to the other wiring hole 21. The gate of each IGBT chip 4 is electrically connected to the corresponding first position. The emitter base 3 includes at least two third positions, which correspond one-to-one with the at least two second positions. The third positions are electrically connected to the corresponding second positions. An external drive circuit is electrically connected between the two wiring holes 21.

[0035] The advantage is that the drive signal PCB board 2 has two electrical connection holes 21. The gate of the IGBT chip is electrically connected to one of the connection holes 21 via a first position on the drive signal PCB board 2. The emitter of the IGBT chip is electrically connected to the other connection hole 21 via a third position on the emitter base 3 and a second position on the drive signal PCB board 2. The two connection holes 21 are electrically connected to an external drive circuit. This allows the emitter of the IGBT chip used to connect to the external drive circuit to be led out through the emitter base 3, which is originally the emitter plate, instead of through the emitter base 3, but through the drive signal PCB board 2 and the gate of the IGBT chip. This eliminates the problem caused by the emitter base 3. The stray inductance, which varies in value due to the different positions of the IGBT chips, is used to avoid differences in the gate voltage (i.e., the actual gate-emitter voltage) of each IGBT chip 4. At the same time, the inductance with the same value as the emitter base 3 corresponding to the IGBT chip 4 is retained. The inductance with the same value as the emitter base 3 corresponding to the IGBT chip 4 refers to the inductance between the emitter of the IGBT chip 4 and the electrical connection point of the emitter base 3, and the corresponding third position. This serves as a negative feedback mechanism for current sharing among the press-fit IGBTs or IGBT chips 4, thereby avoiding the problem of uneven current among the IGBT chips 4 and ensuring the reliability of the IGBT chips 4 and the press-fit IGBTs.

[0036] In some embodiments, at least two IGBT chips 4 and the drive signal PCB board 2 are respectively mounted on the emitter base 3, which meets the packaging requirements and ensures closed integration. The press-fit type IGBT current self-balancing emitter signal loop structure without integrated top cover 1 is applied to: integrated packaging design where the collector is connected to the module pin through the internal copper substrate without the need for an external top cover, packaging design for low power or low voltage applications, and closed design for special application scenarios such as flexibility or lightweight.

[0037] When the press-fit IGBT current self-balancing emitter signal loop structure is applied to high-voltage, high-current power devices, harsh environment applications, or high-reliability scenarios such as medical devices and industrial motor drives, the press-fit IGBT current self-balancing emitter signal loop structure also includes a collector top cover 1. The collectors of at least two IGBT chips 4 are electrically connected to the collector top cover 1, respectively. See [link to relevant documentation]. Figure 4 The drive signal PCB board 2 is installed between the collector top cover 1 and the emitter base 3. At least two first grooves 11 are opened on the inner side of the collector top cover 1. The two first grooves 11 correspond one-to-one with at least two IGBT chips 4. The collector of the IGBT chip 4 is electrically connected to the corresponding first groove 11.

[0038] In some embodiments, at least two emitter protrusions 31 are provided on the emitter base 3, and the at least two emitter protrusions 31 correspond one-to-one with at least two IGBT chips 4. At least two through holes 22 are opened on the drive signal PCB board 2, and the at least two through holes 22 correspond one-to-one with at least two emitter protrusions 31. The emitter protrusions 31 pass through the corresponding through holes 22. The emitter of the IGBT chip 4 is electrically connected to the corresponding emitter protrusion 31. Advantageously, the basic connection is the same as the traditional basic connection, which facilitates improvement on the original basis.

[0039] In some embodiments, the emitter of the IGBT chip 4 is electrically connected to the end face of the corresponding emitter protrusion 31, and the third position is close to the root of the emitter protrusion 31. By controlling the position of the electrical connection between the emitter of the IGBT chip 4 and the emitter protrusion 31, and the distance between the third position and the position, the inductance with the same value as that on the emitter base 3 corresponding to the IGBT chip 4 is retained, that is, the same inductance is the inductance of the emitter protrusion 31.

[0040] See Figure 6 By integrating the gate and emitter of IGBT chip 4 onto the drive signal PCB board 2 and leading them out together, an independent signal loop GE' is obtained. A complete signal transmission path, i.e., a feedback emitter loop, is constructed through the signal loop GE', thus making the signal loop GE' a bypass for the stray inductance of the emitter base 3. When the gate drive signal is applied, the drive signal is switched by the independent control device through the signal loop GE'. Therefore, the actual gate-emitter voltage of each improved IGBT chip can be described by equation (2):

[0041]

[0042] In the formula, v GE' The voltage across the signal loop GE' is the voltage of the external drive circuit in this disclosure;

[0043] In the gate-emitter circuit, the stray inductance of the emitter bump of each IGBT chip will generate a voltage drop when the current changes, as shown in equation (3):

[0044]

[0045] In the formula, Δv Ei The voltage drop generated by the stray inductance of the emitter bump of the i-th IGBT chip when the current changes;

[0046] In the gate-emitter circuit of the press-fit IGBT with parallel chip current self-balancing characteristics disclosed in this disclosure, this voltage drop Δv Ei The feedback is sent to the gate-emitter voltage input terminal of the corresponding IGBT chip, which is equivalent to a negative feedback loop;

[0047] Under the small-signal approximation, IGBT chip 4 can be considered as a gain that varies with the actual gate-emitter voltage v of each IGBT chip. GEi For a linearly varying amplifier, see equation (4):

[0048] i CEi (s)=K P v GEi (s) (4)

[0049] In the formula, K P s represents the transconductance of the IGBT chip, and s represents the Laplace operator;

[0050] The emitter convex inductance feedback can be expressed as equation (5):

[0051] V FB (s)=H(s)i CEi (s),H(s)=sL Ei (5)

[0052] In the formula, V FB For emitter convexity inductance feedback, H is the transfer function of the feedback loop;

[0053] Combining equations (2), (4), and (5), we can obtain equation (6) as follows:

[0054]

[0055] That is, the closed-loop transfer function T(s) of the IGBT chip current in this disclosure can be expressed as equation (7):

[0056]

[0057] As can be seen from equation (7), this is a typical first-order low-pass negative feedback mechanism, which has inherent stability and will not cause feedback oscillation. When the system frequency is low, that is, when the press-fit IGBT with parallel chip current self-balancing characteristics is working in steady state, this first-order low-pass negative feedback mechanism is basically ineffective; when the system frequency is high, that is, when the press-fit IGBT with parallel chip current self-balancing characteristics is working in switching transient state, the current change rate increases significantly, and the feedback voltage rises accordingly, so the first-order low-pass negative feedback mechanism begins to appear and promotes current sharing. With the help of this first-order low-pass negative feedback mechanism, when the press-fit IGBT is turned on, the voltage drop Δv of the IGBT chip 4 with a fast current rise rate is reduced. Ei Increase, suppress the actual gate-emitter voltage v of the IGBT chip 4 GEi This slows down the conduction process; the voltage drop Δv of the IGBT chip 4, which has a slower current rise, is due to the slower conduction. Ei The smaller the voltage, the larger the actual gate-emitter voltage v of the IGBT chip 4. GEi The current can catch up, thus achieving dynamic current sharing of the press-fit IGBT, which possesses the current self-balancing characteristic of parallel chips. The same principle applies when the press-fit IGBT is turned off; that is, when the press-fit IGBT is turned off, the IGBT chip 4 with the fastest current decrease rate has a voltage drop Δv. Ei Increase, suppress the actual gate-emitter voltage v of the IGBT chip 4 GEi Slower shutdown; IGBT chips with slower current drop have a voltage drop Δv Ei The smaller the voltage, the larger the actual gate-emitter voltage v of the IGBT chip 4. GEi The current can catch up, thus achieving dynamic current sharing of the press-fit IGBT with the current self-balancing characteristics of parallel chips.

[0058] In some embodiments, the end face of the emitter protrusion 31 is located on the same side of the drive signal PCB board 2 as the third position, which facilitates the arrangement of at least two first positions and at least two second positions on the same side of the drive signal PCB board 2. Preferably, the first position and the second position are both located on the side of the drive signal PCB board 2 close to the IGBT chip 4.

[0059] In some embodiments, each second position is electrically connected to a spring pin 6, and the spring pin 6 is electrically connected to a third position. The IGBT chip 4 also includes a gate pin 5, one end of which is electrically connected to the gate of the IGBT chip 4, and each first position is electrically connected to a gate pin 7, with the gate pin 5 electrically connected to the corresponding gate pin 7.

[0060] The advantage is that the gate and emitter of the IGBT chip 4 are integrated on the drive signal PCB board 2 and brought out together through the drive signal PCB board 2 by means of the spring pin 6 and the gate pin 7. Since the spring pin 6 and the gate pin 7 are very small, they will not affect the layout of other devices of the press-fit type IGBT.

[0061] In some embodiments, a second groove 41 is formed on the end face of the IGBT chip 4. The second groove 41 is sleeved on the emitter protrusion 31. A gate pin 5 is provided on one side of the second groove 41. A spring pin 6 abuts against the outer side of the root of the emitter protrusion 31. The emitter of the IGBT chip 4 is arranged at least at the junction of the end face of the second groove 41 and the emitter protrusion 31.

[0062] Preferably, one corner of the second groove 41 is recessed inward, and a gate pin 5 is provided in the side wall of the recessed second groove 41. Correspondingly, one corner of the emitter protrusion 31 is recessed inward and matches the second groove 41, and one corner of the through hole 22 is recessed inward and matches the emitter protrusion 31. The gate pin 7 is provided on the edge of the recessed part of the through hole 22, so that the gate pin 7 is close to the corresponding IGBT chip 4 in the layout, reducing the extra area occupied by the gate pin 7 on the drive signal PCB board 2. The layout is reasonable and further reduces the impact on the layout of other pressure-fit IGBT devices.

[0063] In some embodiments, the drive signal PCB board 2 further includes at least two first surface mount resistors 8, with each second position having a first surface mount resistor 8 on one side. The spring pin 6 is connected in series with the corresponding first surface mount resistor 8. The series connection of the first surface mount resistors 8 can prevent the gate oscillation from affecting the spring pin 6.

[0064] In some embodiments, the drive signal PCB board 2 further includes at least two second surface mount resistors 9, with a second surface mount resistor 9 provided on one side of each first position. The gate pin 7 is connected in series with the corresponding second surface mount resistor 9. Similarly, the series connection of the second surface mount resistors 9 can prevent the gate oscillation from affecting the gate pin 7.

[0065] In some embodiments, two wiring holes 21 are opened at the same end of the longitudinal direction of the drive signal PCB board 2, which facilitates wiring of external drive circuits.

[0066] A self-balancing emitter signal circuit for press-fit IGBTs is provided, applied to a self-balancing emitter signal loop structure for press-fit IGBTs. It includes at least two IGBT chips 4, a drive signal PCB board 2, and an emitter base 3. The emitter of the IGBT chip 4 is electrically connected to the emitter base 3. The drive signal PCB board 2 includes two wiring holes 21, at least two first positions, and at least two second positions. Each of the at least two first positions corresponds one-to-one with one of the at least two IGBT chips 4. Each of the at least two first positions is electrically connected to one of the wiring holes 21, and each of the at least two second positions is electrically connected to the other wiring hole 21. The gate of each IGBT chip 4 is electrically connected to its corresponding first position. The emitter base 3 includes at least two third positions, each corresponding one-to-one with one of the at least two second positions. The third positions are electrically connected to their corresponding second positions. An external drive circuit is electrically connected between the two wiring holes 21.

[0067] Finally, it should be noted that the above content is only used to illustrate the technical solution of the present invention, and is not intended to limit the scope of protection of the present invention. Simple modifications or equivalent substitutions made by those skilled in the art to the technical solution of the present invention do not depart from the essence and scope of the technical solution of the present invention.

Claims

1. A self-balancing emitter signal loop structure for press-fit IGBTs, comprising at least two IGBT chips, a drive signal PCB board, and an emitter base, wherein the emitter of the IGBT chip is electrically connected to the emitter base, characterized in that: The drive signal PCB board includes two wiring holes, at least two first positions, and at least two second positions. The at least two first positions and the at least two second positions correspond one-to-one with the at least two IGBT chips. The at least two first positions are electrically connected to one of the wiring holes, and the at least two second positions are electrically connected to the other wiring hole. The gate of each IGBT chip is electrically connected to the corresponding first position. The emitter base includes at least two third positions, which correspond one-to-one with the at least two second positions. The third positions are electrically connected to the corresponding second positions, and an external drive circuit is electrically connected between the two wiring holes.

2. The self-balancing emitter signal circuit structure for press-fit IGBT current as described in claim 1, characterized in that: The at least two IGBT chips and the drive signal PCB board are respectively mounted on the emitter base.

3. The self-balancing emitter signal circuit structure for press-fit IGBT current as described in claim 2, characterized in that: At least two emitter protrusions are provided on the emitter base, and the at least two emitter protrusions correspond one-to-one with the at least two IGBT chips. At least two through holes are provided on the drive signal PCB board, and the at least two through holes correspond one-to-one with the at least two emitter protrusions. The emitter protrusions pass through the corresponding through holes, and the emitter of the IGBT chip is electrically connected to the corresponding emitter protrusion.

4. The self-balancing emitter signal circuit structure for press-fit IGBT current as described in claim 3, characterized in that: The emitter of the IGBT chip is electrically connected to the end face of the corresponding emitter protrusion, and the third position is close to the root of the emitter protrusion.

5. The self-balancing emitter signal circuit structure for press-fit IGBT current as described in claim 4, characterized in that: The end face of the emitter boss and the third position are located on the same side of the drive signal PCB board.

6. The self-balancing emitter signal circuit structure for press-fit IGBT current according to any one of claims 1-5, characterized in that: Each of the second positions is electrically connected to a spring pin, and the spring pin is electrically connected to the third position.

7. The self-balancing emitter signal circuit structure for press-fit IGBT current as described in claim 6, characterized in that: The drive signal PCB board also includes at least two first surface mount resistors, with each second position having a first surface mount resistor on one side, and the spring pin connected in series with the corresponding first surface mount resistor.

8. The self-balancing emitter signal circuit structure of the press-fit type IGBT according to claim 1, characterized in that: The IGBT chip also includes a gate pin, one end of which is electrically connected to the gate of the IGBT chip. Each of the first positions is electrically connected to a gate pin, and the gate pin is electrically connected to the corresponding gate pin.

9. The self-balancing emitter signal circuit structure for press-fit IGBT current as described in claim 8, characterized in that: The drive signal PCB board also includes at least two first surface mount resistors, and a second surface mount resistor is provided on one side of each of the first positions. The gate pin is connected in series with the corresponding second surface mount resistor.

10. A self-balancing emitter signal circuit for a press-fit IGBT, applied to the self-balancing emitter signal loop structure of a press-fit IGBT as described in any one of claims 1-9, comprising at least two IGBT chips, a drive signal PCB board, and an emitter base, wherein the emitter is electrically connected to the emitter base, characterized in that: The drive signal PCB board includes two wiring holes, at least two first positions, and at least two second positions. The at least two first positions and the at least two second positions correspond one-to-one with the at least two IGBT chips. The at least two first positions are electrically connected to one of the wiring holes, and the at least two second positions are electrically connected to the other wiring hole. The gate of each IGBT chip is electrically connected to the corresponding first position. The emitter base includes at least two third positions, which correspond one-to-one with the at least two second positions. The third positions are electrically connected to the corresponding second positions, and an external drive circuit is electrically connected between the two wiring holes.

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