A high-density integrated design method for a medium-high voltage large-capacity four-level converter

Abstract

The application discloses a high-density integrated design method of a medium-high voltage large-capacity four-level converter, relates to the fields of power electronics and new energy, and comprises compact module layout, low-stray inductance busbar design, distributed capacitor design, a small-size radiator and high-density integrated design of the whole converter. Through the design method, the internal space of the four-level converter is optimally utilized, the stray inductance of the power circuit is inhibited, and the heat dissipation efficiency is optimized, so that the four-level converter with high reliability and high density is finally realized. The method is suitable for medium-high voltage converters based on high-voltage SiC or Si devices, and can be applied to the fields of high-power motor driving, energy storage / new energy grid connection and AC / DC interconnection.

Description

Technical Field

[0001] This invention relates to the fields of power electronics and new energy technology, and in particular to a high-density integrated design method for a medium- and high-voltage (2-10 kV) large-capacity four-level converter. Background Technology

[0002] Multilevel converters are core equipment for medium- and high-voltage high-power applications (such as megawatt-level motor drives, photovoltaic / energy storage power station grid connection, and transportation electrification). Compared with traditional two-level and three-level converters, four-level and above converters have advantages such as lower output harmonics, lower voltage stress on switching devices, and weaker electromagnetic interference. Among them, the four-level hybrid clamp converter (4L-HCC) has attracted much attention due to its moderate number of switching devices, flexible control, and superior performance.

[0003] However, with the increase in the number of voltage levels, the internal structure of the converter becomes increasingly complex, with more commutation loops and longer paths, leading to a significant increase in stray inductance. Especially when using SiC MOSFETs, their extremely high switching speed can induce severe switching overvoltages on the stray inductance, threatening device safety and limiting the full potential of device performance. At the same time, the complex structure also presents a significant challenge to improving power density. The power density of existing medium-voltage converters is typically below 0.5 MW / m². 3 Their large size makes them unsuitable for applications in space-constrained environments such as ship propulsion and mining equipment.

[0004] While existing technologies have researched low-inductance designs for two-level or three-level converters, these methods are typically designed for scenarios with a small number of circuits and simple structures. They cannot be directly applied to the complex situation of multiple "long commutation circuits" coexisting and coupling in four-level converters. Furthermore, traditional designs often consider layout, busbars, capacitors, and heat dissipation in isolation, lacking a system-level, collaboratively optimized, high-density integrated design method, making it difficult to overcome performance bottlenecks.

[0005] Therefore, this invention provides a high-density integrated design method for medium- and high-voltage large-capacity four-level converters to solve the above problems. Summary of the Invention

[0006] To address the aforementioned challenges, this invention provides a high-density integrated design method for medium- and high-voltage large-capacity four-level converters. Through a clear design process and guidelines, it achieves optimal utilization of the converter's internal space, minimizes stray inductance in the converter circuit, and maximizes heat dissipation efficiency. Ultimately, this guides the manufacture of medium- and high-voltage large-capacity four-level converters with significantly higher power density and reliable performance than traditional solutions.

[0007] To achieve the above objectives, this invention provides a high-density integrated design method for a medium- and high-voltage, large-capacity four-level converter, comprising the following steps:

[0008] S1: Based on the working principle and loss distribution characteristics of the four-level converter topology, the length of the current commutation distance and heat dissipation, determine the symmetrical arrangement of the four power modules of each phase on the heat dissipation substrate.

[0009] S2: Design different segmented stacked busbar structures to connect power modules, DC support capacitors, and load terminals. Design the busbar connecting the bus capacitor side and the busbar connecting the power module as a stacked busbar, and optimize the conductor layer spacing, width, shape, and relative position through simulation. Minimize the stray inductance of the busbar by utilizing the negative mutual inductance effect.

[0010] S3: Based on the DC bus capacitor voltage fluctuation, select the capacitor value and rated capacitor voltage, and use multiple capacitors in series and parallel to form a thin film capacitor array with low equivalent series inductance. The capacitor layout adopts an interleaved layout to reduce parasitic parameters; and copper plating on the printed circuit board is used to connect all capacitors to reduce parasitic parameters.

[0011] S4: Based on the optimized layout structure, a finite element thermal simulation model is established, and based on the thermal simulation results under actual losses, an appropriate heat sink structure is constructed, including length, width, height, heat sink thickness, spacing, and heat dissipation method, to establish a centralized heat sink structure with 4 modules per phase on a single heat sink.

[0012] S5: Through a three-dimensional structure with the heat sink at the bottom, the device in the middle, and the drive unit at the top, and a symmetrical structure with the bus capacitor and flying capacitor array on both sides, the connection between the bus capacitor and the device and the connection between the device adopts a stacked busbar structure, a single-phase integrated power unit is constructed, and the overall design of the single-phase converter is completed.

[0013] Preferably, the four-level converter is a hybrid clamped four-level topology, with three series-connected bus capacitors on the DC side, and each phase includes eight switching devices and one flying capacitor; wherein the rated voltages of the bus capacitors and the flying capacitors are equal, and each device bears 1 / 3 of the bus voltage.

[0014] Preferably, S1 specifically includes:

[0015] S1 specifically includes: For each phase four-level converter, based on the working principle and loss distribution characteristics of the four-level converter topology, the length of the current commutation distance, and heat dissipation, four power modules are arranged with the heat sink centerline as the axis of symmetry. Two modules are located on one side of the centerline, and the other two modules are symmetrically distributed on the other side. The upper and lower transistor modules of the same half-bridge are placed adjacent to each other.

[0016] Preferably, in step S2, the segmented stacked busbar adopts a double-layer structure. The busbar between the capacitor and the device adopts an L-shaped stacked structure, and the L-shaped chamfer adopts an arc-shaped structure to disperse the electric field stress. The size is determined by the actual voltage level and does not exceed 20kV / cm. The busbar between the devices adopts a planar stacked structure. The insulation between the busbars is designed with polyethylene terephthalate, with a withstand voltage of 28 kV / mm and a thickness determined by the actual voltage level with a certain margin. The conductor uses thin copper sheets, and the current density is controlled at 5-8 A / mm². 2 Within this range, the specific details are determined by the actual system, ultimately ensuring that the busbar shape precisely matches the module terminals, using a shorter path for connection.

[0017] Preferably, the capacitor in step S3 is determined by the following formula. Since the voltage fluctuation of the upper and lower capacitors on the bus side is the largest, the capacitor voltage fluctuation is expressed as:

[0018] ;

[0019] in C Here are the capacitance values ​​for all capacitors. i N1 and i N2 Representing neutral points N 1 and N The current of 2, τ This is the time integral.

[0020] Preferably, in step S3, both the DC bus capacitor and the flying capacitor adopt an m×n series-parallel architecture, where m≥1 and n≥2. All capacitors are electrically connected through copper plating in an N-layer printed circuit board, where N≥4. Any series-parallel structure on the printed circuit board adopts a wiring layout with alternating positive and negative polarities.

[0021] Preferably, S4 specifically includes: establishing a finite element thermal simulation model based on the optimized layout structure, obtaining thermal simulation results according to the loss distribution under rated operating conditions, and obtaining the optimal aluminum-based heat sink structure by using a simulation iteration method, specifically as follows: determining the basic shape of the single-phase heat sink based on the layout, determining the thickness, spacing and heat dissipation method of the heat sink, and obtaining the system junction temperature does not exceed the limit value under low wind speed through continuous simulation optimization, and finally forming a centralized heat sink structure with 4 modules per phase on a single heat sink.

[0022] Preferably, S5 specifically includes: a centralized heat dissipation structure as the base, the device above the heat sink, two modules with higher losses on one side and two modules with lower losses on the other side, wherein the connection with the heat sink is uniformly connected using thin heat dissipation silicon, the drive device is above the device, realizing a high and low voltage isolation partition structure, the bus capacitor and the flying capacitor array on both sides of the heat sink, forming a sequential structure with separate input and output, constructing a single-phase integrated power unit, and completing the single-phase overall design of the converter.

[0023] Preferably, when designing the insulation between module layout intervals, busbar layer thicknesses, printed circuit board layer thicknesses, and heat sinks in each step, the design specifications under insulation standards and manufacturing tolerances are met, and a certain margin is reserved.

[0024] Preferably, it also includes an iterative optimization step, specifically:

[0025] Mechanical integration and simulation checks are performed in a 3D environment. Parasitic parameters are extracted for switching overvoltage simulation. Fluid-thermal coupling simulation is performed to verify heat dissipation performance. Based on the simulation results, the layout, busbar, capacitor or heat dissipation design is iteratively optimized.

[0026] Therefore, the high-density integrated design method of the above-mentioned medium-high voltage large-capacity four-level converter has the following beneficial effects:

[0027] (1) The present invention can achieve ultra-high power density: through integrated design, the power density can be increased to 1.6 MVA / m 3 The above far exceeds the level of existing medium-voltage converters.

[0028] (2) The present invention can achieve low voltage overshoot: through the above-mentioned optimized design of low parasitic parameters, the voltage overshoot caused by the longest commutation circuit is less than 40%.

[0029] (3) The method of the present invention has universality: the design method is not only applicable to the 4L-HCC topology, but its core ideas (such as loop analysis, hardware design, and collaborative integration) can also guide the high-density design of other complex multilevel converters.

[0030] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0031] Figure 1 This is a flowchart illustrating a high-density integrated design method for a medium-voltage, high-capacity four-level converter according to the present invention.

[0032] Figure 2 This is a schematic diagram of the four-level hybrid converter topology in an embodiment of the present invention;

[0033] Figure 3This is a schematic diagram of a common layout of a four-level converter in an embodiment of the present invention, wherein (a) is a schematic diagram of the layout with the largest surface area and volume, (b) is a schematic diagram of the layout of four power modules arranged with the center line of the heat sink as the axis of symmetry, and (c) is a schematic diagram of the layout of all capacitors arranged on the same side.

[0034] Figure 4 This is a schematic diagram of the segmented busbar design in an embodiment of the present invention;

[0035] Figure 5 This is a schematic diagram of the capacitor layout circuit in an embodiment of the present invention;

[0036] Figure 6 This is a schematic diagram of the capacitor layout design in an embodiment of the present invention;

[0037] Figure 7 This is a schematic diagram of a single-phase hybrid converter prototype in an embodiment of the present invention. Detailed Implementation

[0038] The following detailed description of embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0039] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains.

[0040] The terms "comprising" or "including" as used in this invention mean that the element preceding the term encompasses the element listed after the term, and do not exclude the possibility of encompassing other elements. Terms such as "inner," "outer," "upper," and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. In this invention, unless otherwise explicitly specified and limited, the term "attached" and similar terms should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral part; it can refer to a direct connection or an indirect connection through an intermediate medium; it can refer to the internal communication of two elements or the interaction relationship between two elements. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0041] Example

[0042] A high-density integrated design method for medium- and high-voltage, large-capacity four-level converters, such as... Figure 1 As shown, it includes the following steps:

[0043] S1: Based on the working principle and loss distribution characteristics of the four-level converter topology, as well as the length of the current commutation distance, the symmetrical arrangement of the four power modules in each phase on the heat dissipation substrate is determined; the four-level converter is a hybrid clamped four-level topology, with three series-connected bus capacitors on the DC side, and each phase contains eight switching devices and one flying capacitor; the rated voltages of the bus capacitors and the flying capacitors are equal, and each device bears 1 / 3 of the bus voltage.

[0044] Specifically, the four-level converter is a hybrid clamped four-level topology. The DC side includes three series-connected bus capacitors: upper, middle, and lower DC bus capacitors. Each phase includes eight switching devices S1, S'1, S2, S'2, S3, S'3, S4, and S'4, and one flying capacitor. The rated voltages of the bus capacitors and the flying capacitor are equal, and each device carries 1 / 3 of the bus voltage. Taking a MOSFET as an example, the positive terminal of the upper DC bus capacitor is connected to the drain of S1, and the source of S1 is connected to the drain of S'1 and S2. The drains of S2 and S3 are connected. The negative terminal of the upper DC bus capacitor is connected to the source of S'1 and the positive terminal of the middle DC bus. The source of S2 is connected to the positive terminal of the flying capacitor and the drain of S3. The source of S3 is connected to the drain of S'3 and the output point. The negative terminal of the middle DC bus is connected to the positive terminal of the lower DC bus capacitor and the drain of S4. The source of S4 and the drain of S'4 are connected to the source of S'2. The negative terminal of the lower DC bus capacitor is connected to the source of S'4. The drain of S'2 is connected to the negative terminal of the flying capacitor and the source of S'3. The losses of S2 and S'3 are much greater than the loss distribution characteristics of the four devices on the bus side. Considering the topology characteristics of the long physical distance of the current commutation loop of S2 and S'2, the symmetrical arrangement of the four power modules of each phase on the heat sink is determined by comprehensively considering heat dissipation and current commutation distance.

[0045] For each phase four-level converter, four power modules are arranged with the center line of the heat sink as the axis of symmetry. Two modules are located on one side of the center line, and the other two modules are symmetrically distributed on the other side. The upper and lower tube modules of the same half bridge are placed adjacent to each other. This layout ensures that the converter circuit is small and symmetrical, while distributing the power modules with higher losses to the edge of the heat sink, thus achieving the shortest heat dissipation path and the minimum installation area.

[0046] S2: Design different segmented stacked busbar structures to connect power modules, DC support capacitors, and load terminals. By optimizing the conductor layer spacing, width, shape, and relative position, the stray inductance of the busbar is minimized using the negative mutual inductance effect.

[0047] The segmented stacked busbars adopt a double-layer structure. The busbars between capacitors and devices use an L-shaped stacked structure, with the L-shaped chamfer used to disperse electric field stress. The size of the chamfer is determined by the actual voltage level and does not exceed 20kV / cm. The busbars between devices use a planar stacked structure. The insulation between the busbars is made of polyethylene terephthalate with a withstand voltage of 28 kV / mm. The thickness is determined by the actual voltage level and a certain margin is reserved. The conductors use thin copper sheets, and the current density is controlled at 5-8 A / mm². 2 Within this range, the specific details are determined by the actual system, ultimately ensuring that the busbar shape precisely matches the module terminals, using a shorter path for connection.

[0048] S3: Select the capacitor value and rated capacitor voltage based on the fluctuation of DC bus voltage and capacitor voltage, and use multiple capacitors in series and parallel to form a capacitor array with low equivalent series inductance, and adopt an interleaved layout in the printed circuit board.

[0049] The DC bus capacitor and the flying capacitor adopt an m×n series-parallel architecture, where m≥1 and n≥2. All capacitors are electrically connected through multi-layer (≥4) printed circuit boards (PCBs). The capacitors on the PCB adopt a layout with alternating positive and negative polarities to maximize the use of the current reverse cancellation effect and reduce the overall equivalent series inductance of the capacitor bank to one of m / n.

[0050] The capacitance is determined by the following formula. Since the voltage fluctuations of the upper and lower capacitors on the bus side are the largest, the capacitor voltage fluctuation is expressed as:

[0051] ;

[0052] in C Here are the capacitance values ​​for all capacitors. i N1 and i N2 Representing neutral points N 1 and N The current of 2, τ This is the time integral.

[0053] S4: Establish a thermal simulation model based on the actual loss distribution, and customize the heat sink structure based on the simulation results under the actual loss.

[0054] An accurate thermal simulation model is established based on the actual loss distribution. By simulating the junction temperature of the system under different cooling methods, heat sink structures and material properties, the maximum junction temperature of the power device is ensured to be within the preset safety margin. Based on this, the topology and cooling scheme of the heat sink are customized. The heat sink structure includes length, width and height, heat sink thickness, spacing, etc.

[0055] A finite element thermal simulation model was established based on the optimized layout structure. The thermal simulation results were obtained based on the loss distribution under rated operating conditions. The optimal aluminum-based heat sink structure was obtained by simulation iteration method, as follows: the basic shape of the single-phase heat sink was determined based on the layout, and the thickness, spacing and heat dissipation method of the heat sink were determined. Through continuous simulation optimization, it was found that the junction temperature of the system does not exceed the limit value at low wind speed. Finally, a centralized heat sink structure with 4 modules per phase on a single heat sink was formed.

[0056] S5: By using three-dimensional spatial layering and partitioning layout, an integrated power unit is constructed to complete the overall design of the converter.

[0057] Based on a centralized heat dissipation structure as the base, the device is located above the heat sink. The two modules with higher losses are on one side, and the two modules with lower losses are on the other side. The connection with the heat sink is uniformly connected using thin heat-dissipating silicon. The drive device is located above the device, realizing a high- and low-voltage isolation partition structure. The bus capacitor and flying capacitor array are on both sides of the heat sink, forming a sequential structure with separate input and output, thus constructing a single-phase integrated power unit and completing the overall single-phase converter design.

[0058] Each step includes insulation design, specifically:

[0059] When designing the insulation between module layout spacing, busbar layer thickness, printed circuit board layer thickness and heat sink, the design specifications should meet the insulation standards and manufacturing tolerances and a certain margin should be reserved.

[0060] It also includes iterative optimization steps, specifically:

[0061] Mechanical integration and simulation checks are performed in a 3D environment. Parasitic parameters are extracted for switching overvoltage simulation. Fluid-thermal coupling simulation is performed to verify heat dissipation performance. Based on the simulation results, the layout, busbar, capacitor or heat dissipation design is iteratively optimized.

[0062] The method in this embodiment is applicable to four-level converters with device voltage ratings of 1.2–10 kV, system voltages of tens of kilovolts, and power ranges from hundreds of kilovolt-amperes to megavolt-amperes.

[0063] Example 1

[0064] This embodiment takes the development of a four-level hybrid clamp converter (4L-HCC) with a DC bus voltage of 3.3 kV and an output capacity of 500 kVA as an example. Figures 2-5 As shown, the target power density is greater than 1.5 MW / m². 3 It uses a Rohm SiC MOSFET half-bridge module, model BSM250D17P12E004.

[0065] The 4L-HCC topology used in this embodiment is as follows. Figure 2 As shown, the DC side is supported by a voltage source Vdc and three series-connected DC bus capacitors (Cu, Cm, Cl), forming four voltage levels. Each phase arm contains eight switching devices (S1-S4 and complementary switches S'1-S'4) and one flying capacitor (Cf). This topology can output four phase voltage levels (0, E, 2E, 3E, where E = Vdc / 3).

[0066] For the aforementioned four-level converter, each phase contains four power modules. Several common layouts are preferred, such as... Figure 3 As shown, (a) has the largest surface area and volume, so it is not considered. (b) and (c) have the same surface area. The physical lengths of the commutation circuits of devices S2 and S'2 are basically the same. However, in layout (c), the two half-bridge power modules corresponding to devices S2, S'2, S3, and S'3 are in the middle, which is not conducive to heat dissipation. At the same time, all capacitors are on the same side, with 6 potential points, making the stacked busbar design difficult. Therefore, the power module layout shown in (b) was finally selected. The four power modules are arranged with the heat sink centerline as the axis of symmetry. Two modules are located on one side of the centerline, and the other two modules are symmetrically distributed on the other side. The upper and lower transistor modules of the same half-bridge are placed adjacent to each other.

[0067] Based on the optimized layout determined above, without reducing integration and simplifying the design complexity of the busbar, a wide and thin segmented stacked busbar is used to connect the main circuit, such as... Figure 4 As shown. First, the busbars between the bus capacitors and devices adopt an L-shaped stacked structure. The L-shaped chamfer is designed with an arc shape to disperse the electric field stress. Through finite element electric field simulation of the busbars, the chamfer radius is optimized to 0.5 mm. At this point, the electric field strength does not exceed 20 kV / cm. The outer layer lengths are 61 mm and 42 mm, and the inner layer lengths are 38 mm and 18.5 mm. The busbars between devices adopt a planar stacked structure, with each layer having a length of 82 mm. This length is determined by the spacing between devices and the creepage distance. The insulation between the busbars uses polyethylene terephthalate (PET) (insulation strength 28 kV / mm) for insulation design. Considering a certain margin, 0.25 mm thick PET is used as the insulation material, the copper thickness is 0.5 mm, and the conductor width is 11 mm. Finite element simulation shows that its current density is less than 4 A / mm. 2 This will ultimately ensure a precise match between the busbar shape and the module terminals, enabling a shorter connection path. The proposed segmented busbar structure avoids the complexity of traditional single integrated busbar designs, reducing design complexity while maintaining integration.

[0068] Based on the DC bus voltage rating of 3.3 kV, the rated operating voltage of the capacitor can be determined to be 1100 V, with a certain margin required. Simultaneously, considering the voltage fluctuation of the bus capacitor (… ΔV c The tolerance value can be determined; in this embodiment, 15% is used as the maximum fluctuation value. It can be expressed by the following formula:

[0069] ;

[0070] in C This represents the capacitance value of all capacitors. i N1 and i N2 Representing neutral points N 1 and N The current of 2, τ For time integration. Based on this, this embodiment selects a capacitance value of 0.18 mF, and to retain a certain margin, the rated voltage of the capacitor needs to be greater than 1500 V.

[0071] To further reduce the length of the commutation circuit and parasitic parameters, this embodiment abandons the single large capacitor and adopts a distributed, series-parallel capacitor network architecture, as shown in the figure. Figure 5 and 6 As shown, V1 represents the positive potential in series, V2 represents the intermediate potential, and V3 represents the negative potential in series. Considering the advantages of film capacitors, such as low equivalent series inductance, low loss, excellent high-frequency performance, and high capacitance, this embodiment uses 60 uF / 800 V film capacitors connected in series and parallel, with the DC bus shared by all three phases and the flying capacitors arranged independently.

[0072] The DC bus capacitor bank uses multiple thin-film capacitors connected in series and parallel in a 2×2 configuration for each phase, such as... Figure 5 As shown, each capacitor carries 550V and is shared across all three phases, ultimately forming 2... The three-phase common DC bus capacitor architecture consists of 6 capacitors; each phase of the flying capacitor bank is independently configured, and each phase adopts a 2-series × 6-parallel structure, ultimately resulting in parasitic parameters that are only 1 / 3 of those of a single small capacitor. Figure 6 As shown.

[0073] The capacitor layout described abandons the traditional copper busbar connection design used in medium and high voltage applications, extending the original printed circuit board (PCB) used for low voltage to the application range of medium and high voltage, that is, using PCB to connect all capacitors. In this embodiment, a 6-layer PCB with copper plating is used to connect all capacitors, and a design of alternating and overlapping copper plating with opposite polarities is adopted to maximize the use of the current reverse cancellation effect, reducing the overall equivalent series inductance of the capacitor bank to an extremely low level, which is less than 10 nH as shown by finite element analysis. At the same time, two aspects need to be considered: current balance and insulation design. Simulation analysis shows that the current imbalance of the proposed staggered layout is less than 10%, which meets the capacitor current tolerance level, and a 0.2mm thick prepreg is used between the insulating layers to meet the relevant insulation design standards.

[0074] Based on the optimized layout described above, a perfectly matched custom heatsink is designed at the bottom, made of high thermal conductivity aluminum, and manufactured using extrusion or toothing processes. Taking 3.3kV, 500kVA as an example, each device (S1, S'1, S4, S'4) is approximately 90W, and each device (S2, S'2, S3, S'3) is approximately 175W. Based on the actual loss distribution in the solid and fluid fields of the COMSOL, a precise... Figure 7 The finite element thermal simulation model shown simulates the system thermal behavior under different cooling methods, heat sink structures and material properties. It sets appropriate length, width and height of the heat sink and the spacing of the heat sink to ensure that the maximum junction temperature of the power device is within the preset safety margin. Finally, a centralized heat sink structure with 4 modules per phase on a single heat sink is established.

[0075] Based on the proposed centralized heat dissipation structure as the base, the device is located above the heat sink. The two modules with higher losses are on one side, and the two with lower losses are on the other side. The connection with the heat sink is uniformly connected using thin heat-dissipating silicon. The drive device is located above the device, realizing a high-low voltage isolation partition structure. The bus capacitor and flying capacitor array are located on both sides of the heat sink, forming a sequential structure with separate input and output, thus constructing a single-phase integrated power unit and completing the overall single-phase converter design.

[0076] The integrated prototype model was mechanically integrated and simulated in a 3D environment; parasitic parameters under this layout were extracted for switching overvoltage simulation; fluid-thermal coupling simulation was performed to verify heat dissipation performance; and the layout, busbars, capacitors, or heat dissipation design were iteratively optimized based on the simulation results. Finally, the integrated prototype was... Figure 7 The prototype shown. Power density: Single-phase unit dimensions are 23 cm × 17 cm × 32 cm, with a calculated volume of approximately 12.5 liters, and a single-phase power of approximately 167 kVA (three-phase is 500 kVA), resulting in a power density as high as 13.3 kVA / L (i.e., 13.3 MVA / m³). 3Considering the space required for a three-phase system and auxiliary power supply, the overall power density easily exceeds 1.6 MVA / m². 3 .

[0077] Therefore, this invention adopts the high-density integrated design method of a medium-high voltage large-capacity four-level converter mentioned above. Through five key steps, namely, optimized power module layout, segmented stacked busbar design, staggered arrangement of distributed capacitors, efficient thermal management, and system-level multi-physics field collaborative integration and iterative optimization, system-level collaborative design is achieved. Through clear design process and criteria, the internal space utilization of the converter is optimized, the stray inductance of the converter circuit is minimized, and the heat dissipation efficiency is maximized. Ultimately, this guides the manufacture of a medium-high voltage large-capacity four-level converter with a power density significantly higher than that of traditional solutions and reliable performance.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the technical solutions of the present invention, and these modifications or equivalent substitutions cannot cause the modified technical solutions to deviate from the spirit and scope of the technical solutions of the present invention.

Claims

1. A high-density integrated design method for a medium-voltage, high-capacity four-level converter, characterized in that, Includes the following steps: S1: Based on the working principle and loss distribution characteristics of the four-level converter topology, the length of the current commutation distance and heat dissipation, determine the symmetrical arrangement of the four power modules of each phase on the heat dissipation substrate. S2: Design different segmented stacked busbar structures to connect power modules, DC support capacitors and load terminals. Design the busbar connecting the bus capacitor side and the busbar connecting the power module as a stacked busbar. Optimize the conductor layer spacing, width, shape and relative position through simulation. Utilize the negative mutual inductance effect to significantly reduce the stray inductance of the busbar. S3: The selected capacitor value and rated capacitor voltage are determined based on the bus capacitor voltage fluctuation; a thin-film capacitor array with low equivalent series inductance is formed by connecting multiple capacitors in series and parallel, and the capacitor layout adopts an interleaved layout to reduce parasitic parameters; and copper plating on the printed circuit board is used to connect all capacitors to reduce parasitic parameters. S4: Based on the optimized layout structure, a finite element thermal simulation model is established, and based on the thermal simulation results under actual losses, an appropriate heat sink structure is constructed, including length, width, height, heat sink thickness, spacing, and heat dissipation method, to establish a centralized heat sink structure with 4 modules per phase on a single heat sink. S5: Through a three-dimensional structure with the heat sink at the bottom, the device in the middle, and the drive unit at the top, and a symmetrical structure with the bus capacitor and flying capacitor array on both sides, the connection between the bus capacitor and the device and the connection between the device adopts a stacked busbar structure, a single-phase integrated power unit is constructed, and the overall design of the single-phase converter is completed.

2. The high-density integrated design method for a medium-voltage, high-capacity four-level converter according to claim 1, characterized in that, The four-level converter is a hybrid clamped four-level topology. The DC side includes three bus capacitors connected in series, and each phase includes eight switching devices and one flying capacitor. The rated voltages of the bus capacitors and the flying capacitors are equal, and each device carries 1 / 3 of the bus voltage.

3. The high-density integrated design method for a medium-voltage, high-capacity four-level converter according to claim 2, characterized in that, S1 specifically includes: For each phase four-level converter, based on the working principle and loss distribution characteristics of the four-level converter topology, the length of the current commutation distance and heat dissipation, four power modules are arranged with the heat sink centerline as the axis of symmetry, two of which are located on one side of the centerline, and the other two are symmetrically distributed on the other side, and the upper and lower tube modules of the same half-bridge are placed adjacent to each other.

4. The high-density integrated design method for a medium-voltage, high-capacity four-level converter according to claim 3, characterized in that, In step S2, the segmented stacked busbars adopt a double-layer structure. The busbars between capacitors and devices use an L-shaped stacked structure, with the L-shaped chamfer used to disperse electric field stress. The size of the chamfer is determined by the actual voltage level and does not exceed 20kV / cm. The busbars between devices use a planar stacked structure. The insulation between the busbars is designed using polyethylene terephthalate, with a withstand voltage of 28 kV / mm. The thickness is determined by the actual voltage level and a certain margin is reserved. The conductors use thin copper sheets, and the current density is controlled at 5-8 A / mm². 2 Within this range, the specific details are determined by the actual system, ultimately ensuring that the busbar shape precisely matches the module terminals, using a shorter path for connection.

5. The high-density integrated design method for a medium-voltage, high-capacity four-level converter according to claim 4, characterized in that, In step S3, the capacitor is determined by the following formula. Since the voltage fluctuations of the upper and lower capacitors on the bus side are the largest, the capacitor voltage fluctuation is expressed as: ； in C Here are the capacitance values ​​for all capacitors. i N1 and i N2 Representing neutral points N 1 and N The current of 2, τ This is the time integral.

6. The high-density integrated design method for a medium-high voltage, large-capacity four-level converter according to claim 5, characterized in that, In step S3, both the DC bus capacitor and the flying capacitor adopt an m×n series-parallel architecture, where m≥1 and n≥2. All capacitors are electrically connected through copper plating on an N-layer printed circuit board, where N≥4. Any series-parallel structure on the printed circuit board adopts a routing layout with alternating positive and negative polarities.

7. The high-density integrated design method for a medium-high voltage, large-capacity four-level converter according to claim 6, characterized in that, S4 specifically includes: establishing a finite element thermal simulation model based on the optimized layout structure, obtaining thermal simulation results based on the loss distribution under rated operating conditions, and obtaining the optimal aluminum-based heat sink structure using the simulation iteration method, as follows: determining the basic shape of the single-phase heat sink based on the layout, determining the thickness, spacing and heat dissipation method of the heat sink, and obtaining the system junction temperature does not exceed the limit value under low wind speed through continuous simulation optimization, and finally forming a centralized heat sink structure with 4 modules per phase on a single heat sink.

8. The high-density integrated design method for a medium-voltage, high-capacity four-level converter according to claim 7, characterized in that, S5 specifically includes: a centralized heat dissipation structure as the base, with the device above the heat sink, two modules with higher losses on one side and two modules with lower losses on the other side, where the connection to the heat sink is uniformly connected using thin heat-dissipating silicon, the drive device is above the device, realizing a high and low voltage isolation partition structure, bus capacitors and flying capacitor arrays on both sides of the heat sink, forming a sequential structure with separate input and output, constructing a single-phase integrated power unit, and completing the single-phase overall design of the converter.

9. The high-density integrated design method for a medium-voltage, high-capacity four-level converter according to claim 8, characterized in that, When designing the insulation between module layout spacing, busbar layer thickness, printed circuit board layer thickness and heat sink for each step, the design specifications must meet the insulation standards and manufacturing tolerances, and a certain margin must be reserved.

10. A high-density integrated design method for a medium-voltage, high-capacity four-level converter according to any one of claims 1-9, characterized in that, It also includes iterative optimization steps, specifically: Mechanical integration and simulation checks are performed in a 3D environment. Parasitic parameters are extracted for switching overvoltage simulation. Fluid-thermal coupling simulation is performed to verify heat dissipation performance and current balance. Based on the simulation results, the layout, busbar, capacitor or heat dissipation design is iteratively optimized.

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