Method for manufacturing metal oxide layer and method for manufacturing semiconductor device

Abstract

Provided are a metal oxide layer having high carrier mobility, a method for manufacturing the metal oxide layer, and a method for manufacturing a semiconductor device. The method for manufacturing the metal oxide layer includes a first step of forming a crystal portion and a second step of forming a crystalline metal oxide layer with the crystal portion as a core. The metal oxide layer contains indium. The metal oxide layer is formed by atomic layer deposition, and the substrate heating temperature is set to 150 DEG C or more and 250 DEG C or less. In addition, the crystal orientation of crystal grains included in the metal oxide layer is lt; 111gt, 111gt; the crystal orientation of the crystal part is lt; 001gt, 001gt; .

Description

Technical Field

[0001] One aspect of the present invention relates to a metal oxide layer, a semiconductor device, a memory device, a display device, and an electronic device. Furthermore, another aspect of the present invention relates to a method for manufacturing a metal oxide layer and a method for manufacturing a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the technical fields described above. Examples of technical fields for one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), methods for driving them, or methods for manufacturing them.

[0003] In this specification, a semiconductor device refers to a device that utilizes the properties of semiconductors, as well as circuits that include semiconductor elements (transistors, diodes, photodiodes, etc.) and devices that include such circuits. Furthermore, a semiconductor device refers to all devices capable of functioning by utilizing the properties of semiconductors. Examples of semiconductor devices include integrated circuits, chips containing integrated circuits, and electronic components that house chips in packages. In addition, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and sometimes include semiconductor devices in their design. Background Technology

[0004] The technique of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. These transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. Silicon-based semiconductor materials are widely known as suitable for use in transistors. Among other materials, oxide semiconductors have also garnered interest.

[0005] Furthermore, it is known that transistors using oxide semiconductors have extremely low leakage current in the off state. For example, Patent Document 1 discloses a low-power CPU (Central Processing Unit) that utilizes the low leakage current characteristic of transistors using oxide semiconductors. Additionally, for example, Patent Document 2 discloses a storage device that utilizes the low leakage current characteristic of transistors using oxide semiconductors to achieve long-term retention of stored content.

[0006] Furthermore, examples of oxide semiconductors that can be used as active layers in transistors include indium oxide and indium gallium zinc oxide. Non-Patent Document 1 discloses a thin-film transistor using hydrogenated polycrystalline indium oxide, formed by low-temperature solid-state crystallization, as the active layer.

[0007] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187 [Patent Document 2] Japanese Patent Application Publication No. 2011-151383

[0008] [Non-Patent Literature 1] Y. Magari et al., “High-mobility hydrogenated polycrystalline In2O3(In2O3:H)thin-film transistors”, Nature COMMUNICATIONS, 13, 1078 (2022). [Non-Patent Literature 2] N. Preissler et al., “Electrical transport, electronothermal transport, and effective electron mass in single-crystalline In2O3 films”, Phys. Rev. B, 88, 085305 (2013). [Non-Patent Literature 3] Takashi Koida, “High Mobility Transparent Conductive Film”, National Institute of Advanced Industrial Science and Technology (AIST), Japan, AIST Solar Power Research Results Presentation 2019, website:<URL:https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf> Summary of the Invention

[0009] One objective of this invention is to provide a metal oxide layer with high carrier mobility. Another objective of this invention is to provide a novel metal oxide layer. Finally, one objective of this invention is to provide a transistor, semiconductor device, memory device, or display device using a metal oxide layer.

[0010] One objective of this invention is to provide a transistor with good electrical characteristics. Another objective of this invention is to provide a transistor with a large on-state current. Another objective of this invention is to provide a transistor with low parasitic capacitance. Another objective of this invention is to provide a transistor, semiconductor device, memory device, or display device with high reliability. Another objective of this invention is to provide a transistor, semiconductor device, or memory device capable of miniaturization or high integration. Another objective of this invention is to provide a semiconductor device, memory device, or display device with low power consumption. Another objective of this invention is to provide a memory device with high operating speed. Finally, another objective of this invention is to provide a method for manufacturing the aforementioned transistor, semiconductor device, memory device, or display device.

[0011] Note that the description of these objectives does not preclude the existence of other objectives. One aspect of the invention does not necessarily require achieving all of the above objectives. Objectives other than those described above can be extracted from the description, drawings, and claims.

[0012] One aspect of the present invention is a method for manufacturing a metal oxide layer, the method comprising a first step of forming crystalline portions and a second step of forming a crystalline metal oxide layer using the crystalline portions as nuclei. The metal oxide layer comprises indium.

[0013] In the above-described method for manufacturing the metal oxide layer, it is preferable to form a crystalline portion from one grain of the polycrystalline film in the first step described above.

[0014] Furthermore, in the above-described method for manufacturing a metal oxide layer, it is preferable to include a third step of forming an amorphous metal oxide film before the first step. In this case, it is preferable to form crystalline portions on the amorphous metal oxide film in the first step. Moreover, it is preferable to form a metal oxide layer in a second step by crystallizing the amorphous metal oxide film.

[0015] In the above-mentioned method for manufacturing metal oxide layers, it is preferable to use atomic layer deposition (ALD) to form the metal oxide layer, and set the substrate heating temperature to 100°C or higher and 300°C or lower.

[0016] In the above-mentioned method for manufacturing metal oxide layers, it is preferable to use atomic layer deposition to form the metal oxide layer, and to set the substrate heating temperature to 150°C or higher and 250°C or lower.

[0017] One aspect of the present invention is a method for manufacturing a metal oxide layer, the method comprising a first step of forming a crystalline portion on an insulating layer and a second step of forming a crystalline metal oxide layer on the crystalline portion. The metal oxide layer comprises indium. Prior to the second step, the top surface of the insulating layer is planarized using a chemical mechanical polishing method, and the average surface roughness of the top surface of the insulating layer is set to be greater than 0 nm and less than 3 nm.

[0018] In the above-described method for manufacturing a metal oxide layer, it is preferable to allow the metal oxide layer to undergo lateral crystal growth after the second step.

[0019] In the above-mentioned method for manufacturing metal oxide layers, it is preferable to form a film that becomes a crystalline portion in the first step, and then process the film using a wet etching method to form the crystalline portion.

[0020] In the above-described method for manufacturing a metal oxide layer, the crystal orientation of the grains contained in the metal oxide layer is preferably... <111> .

[0021] In the above-described method for manufacturing the metal oxide layer, the crystal orientation of the crystalline portion is preferably... <001> .

[0022] In the above-mentioned method for manufacturing metal oxide layers, the crystalline portion preferably contains indium, gallium, and zinc, and the composition of the crystalline portion is preferably In:Ga:Zn = 1:1:1 [atomic ratio] or close to it, or In:Ga:Zn = 1:3:2 [atomic ratio] or close to it.

[0023] In the above-described method for manufacturing a metal oxide layer, the crystal orientation of the grains contained in the metal oxide layer is preferably consistent with or substantially consistent with the crystal orientation of the crystalline portion.

[0024] In the above-mentioned method for manufacturing metal oxide layers, the crystalline portion preferably contains indium.

[0025] One aspect of the present invention is a method for manufacturing a semiconductor device, the method comprising: a first step of forming a crystalline portion on a first insulating layer; a second step of forming a crystalline metal oxide layer using the crystalline portion as a nucleus; a third step of processing the metal oxide layer into an island shape; a fourth step of forming a second insulating layer covering the metal oxide layer; a fifth step of forming an opening in the second insulating layer overlapping the metal oxide layer; a sixth step of forming a third insulating layer in the opening; and a seventh step of forming a conductive layer on the third insulating layer. The metal oxide layer comprises indium.

[0026] In the above-described method for manufacturing a semiconductor device, it is preferable to form a crystalline portion using one grain of a polycrystalline film in the first step described above.

[0027] In the above-mentioned semiconductor device manufacturing method, it is preferable to use atomic layer deposition to form a metal oxide layer, and set the substrate heating temperature to 100°C or higher and 300°C or lower.

[0028] In the above-mentioned semiconductor device manufacturing method, it is preferable to use atomic layer deposition to form a metal oxide layer, and set the substrate heating temperature to 150°C or higher and 250°C or lower.

[0029] One aspect of the present invention is a method for manufacturing a semiconductor device, the method comprising: a first step of forming a crystalline portion on a first insulating layer; a second step of forming a crystalline metal oxide layer on the crystalline portion; a third step of processing the metal oxide layer into an island shape; a fourth step of forming a second insulating layer covering the metal oxide layer; a fifth step of forming an opening in the second insulating layer overlapping the metal oxide layer; a sixth step of forming a third insulating layer in the opening; and a seventh step of forming a conductive layer on the third insulating layer. The metal oxide layer comprises indium. Prior to the second step, the top surface of the first insulating layer is planarized using a chemical mechanical polishing method, and the average surface roughness of the top surface of the first insulating layer is set to be 0 nm or more and less than 3 nm.

[0030] In the above-described method for manufacturing a semiconductor device, it is preferable to perform lateral crystal growth on the metal oxide layer after the second step.

[0031] In the above-described semiconductor device manufacturing method, it is preferable to form a film that becomes a crystallized portion in the first step, and to process the film using a wet etching method to form the crystallized portion.

[0032] In the above-described method for manufacturing a semiconductor device, the crystal orientation of the grains contained in the metal oxide layer is preferably... <111> .

[0033] In the above-described method for manufacturing a semiconductor device, the crystal orientation of the crystallized portion is preferably... <001> .

[0034] In the above-described method for manufacturing a semiconductor device, the crystallization portion preferably contains indium, gallium, and zinc, and the composition of the crystallization portion is preferably In:Ga:Zn = 1:1:1 [atomic ratio] or close to it, or In:Ga:Zn = 1:3:2 [atomic ratio] or close to it.

[0035] In the above-described semiconductor device manufacturing method, the crystal orientation of the grains contained in the metal oxide layer is preferably the same as or substantially the same as the crystal orientation of the crystalline portion.

[0036] In the above-described method for manufacturing a semiconductor device, the crystallization section preferably contains indium.

[0037] One aspect of the present invention is a metal oxide layer on an insulating layer, the metal oxide layer comprising indium, wherein the concentrations of gallium and zinc in the metal oxide layer are both below 0.1 atomic%, and the metal oxide layer comprises crystals having a cubic crystal structure, the crystal orientation of which is relative to the top surface of the insulating layer. <111> The average surface roughness of the top surface of the insulating layer is greater than 0 nm and less than 3 nm.

[0038] According to one aspect of the present invention, a metal oxide layer with high carrier mobility can be provided. According to one aspect of the present invention, a novel metal oxide layer can be provided. According to one aspect of the present invention, a semiconductor device, a memory device, or a display device using a metal oxide layer can be provided.

[0039] According to one aspect of the present invention, a transistor with good electrical characteristics can be provided. According to one aspect of the present invention, a transistor with a large on-state current can be provided. According to one aspect of the present invention, a transistor with small parasitic capacitance can be provided. According to one aspect of the present invention, a transistor, semiconductor device, memory device, or display device with high reliability can be provided. According to one aspect of the present invention, a transistor, semiconductor device, or memory device capable of miniaturization or high integration can be provided. According to one aspect of the present invention, a semiconductor device, memory device, or display device with low power consumption can be provided. According to one aspect of the present invention, a memory device with high operating speed can be provided. According to one aspect of the present invention, a method for manufacturing the above-mentioned transistor, semiconductor device, memory device, or display device can be provided.

[0040] Note that the description of these effects does not preclude the existence of other effects. One aspect of the invention does not necessarily require all of the aforementioned effects. Effects other than those described above can be extracted from the specification, drawings, and claims. Attached Figure Description

[0041] Figures 1A to 1E This is a three-dimensional schematic diagram illustrating an example of a semiconductor device. Figure 1F This is a schematic cross-sectional view showing an example of a semiconductor device; Figure 2A This is a cross-sectional diagram illustrating the indium oxide film. Figure 2B and Figure 2C This is a graph illustrating the carrier concentration dependence of Hall mobility; Figure 3 This is a graph illustrating the carrier concentration dependence of the indium oxide mobility disclosed in Non-Patent Document 2; Figures 4A to 4E It is a diagram illustrating the crystal structure of metal oxides; Figure 5 It is a diagram illustrating the crystallinity of metal oxides; Figure 6A , Figure 6C , Figure 6D and Figure 6F This is a three-dimensional schematic diagram illustrating an example of a semiconductor device. Figure 6B and Figure 6E This is a schematic cross-sectional view showing an example of a semiconductor device; Figure 7It is a diagram illustrating the shape of the top surface of the layer; Figures 8A to 8C This is a schematic cross-sectional view showing an example of a semiconductor device; Figure 9A , Figure 9C , Figure 9E and Figure 9G This is a three-dimensional schematic diagram illustrating an example of a semiconductor device manufacturing method. Figure 9B , Figure 9D , Figure 9F and Figure 9H This is a cross-sectional schematic diagram illustrating an example of a semiconductor device manufacturing method; Figure 10A and Figure 10C This is a three-dimensional schematic diagram illustrating an example of a semiconductor device manufacturing method. Figure 10B and Figure 10D This is a cross-sectional schematic diagram illustrating an example of a semiconductor device manufacturing method; Figure 11A , Figure 11C , Figure 11E and Figure 11G This is a three-dimensional schematic diagram illustrating an example of a semiconductor device manufacturing method. Figure 11B , Figure 11D , Figure 11F and Figure 11H This is a cross-sectional schematic diagram illustrating an example of a semiconductor device manufacturing method; Figures 12A to 12E and Figure 12G This is a three-dimensional schematic diagram illustrating an example of a semiconductor device manufacturing method. Figure 12F This is a cross-sectional schematic diagram illustrating an example of a semiconductor device manufacturing method; Figures 13A to 13D This is a three-dimensional schematic diagram illustrating an example of a semiconductor device manufacturing method; Figure 14A , Figure 14B and Figure 14D This is a three-dimensional schematic diagram illustrating an example of a semiconductor device manufacturing method. Figure 14C This is a schematic cross-sectional view showing an example of a semiconductor device; Figure 15A This is a plan view showing an example of a semiconductor device. Figures 15B to 15D This is a cross-sectional view showing an example of a semiconductor device; Figure 16A This is a plan view showing an example of a semiconductor device. Figures 16B to 16D This is a cross-sectional view showing an example of a semiconductor device; Figure 17A This is a plan view showing an example of a semiconductor device. Figures 17B to 17D This is a cross-sectional view showing an example of a semiconductor device; Figure 18 This is a cross-sectional view showing an example of a semiconductor device; Figures 19A to 19C This is a cross-sectional view showing an example of a semiconductor device; Figure 20A This is a plan view showing an example of a semiconductor device. Figures 20B to 20D This is a cross-sectional view showing an example of a semiconductor device; Figure 21A This is a plan view showing an example of a semiconductor device. Figures 21B to 21D This is a cross-sectional view showing an example of a semiconductor device; Figures 22A to 22C This is a cross-sectional view showing an example of a semiconductor device; Figure 23A This is a plan view showing an example of a semiconductor device. Figures 23B to 23D This is a cross-sectional view showing an example of a semiconductor device; Figure 24 This is a cross-sectional view showing an example of a semiconductor device; Figure 25A This is a plan view showing an example of a semiconductor device. Figures 25B to 25D This is a cross-sectional view showing an example of a semiconductor device; Figure 26A This is a plan view showing an example of a semiconductor device. Figures 26B to 26D This is a cross-sectional view showing an example of a semiconductor device; Figure 27 This is a block diagram illustrating an example of the structure of a semiconductor device; Figures 28A to 28G This is a diagram illustrating an example of the circuit structure of a memory cell; Figure 29 This is a cross-sectional view showing an example of a semiconductor device; Figure 30A and Figure 30B It is a three-dimensional diagram illustrating an example of the structure of a semiconductor device; Figure 31 This is a cross-sectional view showing an example of a semiconductor device; Figure 32 It is a block diagram illustrating the CPU; Figure 33A and Figure 33B It is a 3D diagram of a semiconductor device; Figure 34A and Figure 34B It is a 3D diagram of a semiconductor device; Figure 35 This is a schematic diagram illustrating the hierarchy of storage devices; Figure 36A and Figure 36BThis is a perspective view showing an example of a display device; Figure 37 This is a cross-sectional view showing an example of a display device; Figure 38 This is a cross-sectional view showing an example of a display device; Figure 39A and Figure 39B This is a diagram showing an example of an electronic component; Figures 40A to 40C This is a diagram illustrating an example of a mainframe computer. Figure 40D This is a diagram illustrating an example of a space device. Figure 40E This is a diagram illustrating an example of a storage system that can be used in a data center; Figures 41A to 41F This is a diagram illustrating an example of an electronic device; Figures 42A to 42G This is a diagram illustrating an example of an electronic device; Figures 43A to 43F This is a diagram illustrating an example of an electronic device; Figure 44 The results are AFM measurement results according to the embodiment. Detailed Implementation

[0042] The embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the present invention should not be construed as being limited only to the contents described in the embodiments shown below.

[0043] Note that in the structure of the invention described below, the same symbols are used in different figures to represent the same parts or parts with the same function, and repeated descriptions are omitted. Furthermore, when representing parts with the same function, the same shading lines are sometimes used without additional symbols.

[0044] Furthermore, for ease of understanding, the positions, sizes, and extents of the constituent elements shown in the accompanying drawings may not represent their actual positions, sizes, and extents. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and extents disclosed in the accompanying drawings.

[0045] In this specification and the like, ordinal numbers such as "first" and "second" are used for convenience, but these ordinal numbers do not limit the number of constituent elements or the order of the constituent elements (e.g., process sequence or stacking sequence). Furthermore, sometimes the ordinal numbers used for constituent elements in one part of this specification differ from those used for the same constituent element in another part of this specification or in the claims.

[0046] A transistor is a type of semiconductor device that can amplify current or voltage, control switching operations (turning the device on or off), etc. The transistors discussed in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0047] In this specification and the like, transistors that use oxide semiconductors or metal oxides as semiconductor layers, and transistors that contain oxide semiconductors or metal oxides in the channel formation region, are sometimes referred to as OS (Oxide Semiconductor) transistors. Furthermore, transistors that contain silicon in the channel formation region are sometimes referred to as Si transistors.

[0048] Furthermore, in cases where transistors of different polarities are used or the current direction changes during circuit operation, the functions of the source and drain may sometimes be interchanged. Therefore, in this specification, the source and drain may be interchanged.

[0049] Note that in this specification, etc., oxynitrides refer to materials in which the oxygen content is greater than the nitrogen content in their composition. Nitrogen oxides refer to materials in which the nitrogen content is greater than the oxygen content in their composition. For example, when described as "silicon oxynitride," it refers to a material in which the oxygen content is greater than the nitrogen content in its composition, while when described as "silicon oxynitride," it refers to a material in which the nitrogen content is greater than the oxygen content in its composition.

[0050] Note that the content percentage in this specification refers to the proportion of the components contained in the film. For example, an oxide semiconductor layer contains metal elements X, Y, and Z, and the number of atoms of each metal element X, Y, and Z contained in the oxide semiconductor layer is A. X 、A Y 、A Z When the content of metallic element X is such that it can be expressed as A, the percentage of X in the composition of metal can be expressed as A. X / (A X +A Y +A Z Furthermore, when the ratio of the number of atoms of metal elements X, Y, and Z in the oxide semiconductor layer (atomic number ratio) is expressed as B... X B Y B Z When the content of metallic element X is such that B is used, the percentage of X can be expressed as B. X / (B X +B Y +B Z ).

[0051] Furthermore, depending on the situation or state, the "film" and "layer" can be interchanged. For example, a "conductive layer" can be replaced with a "conductive film." Similarly, an "insulating film" can be replaced with an "insulating layer."

[0052] In this specification, "parallel" refers to a state where the angle formed by two straight lines is -10° or more and less than 10°. Therefore, it also includes states where the angle is -5° or more and less than 5°. "Approximately parallel" refers to a state where the angle formed by two straight lines is -20° or more and less than 20°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is 80° or more and less than 100°. Therefore, it also includes states where the angle is 85° or more and less than 95°. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is 70° or more and less than 110°.

[0053] Furthermore, in this specification, "electrical connection" includes connections made via "elements that have a certain electrical function." Here, "elements that have a certain electrical function" are not particularly limited as long as they can transmit and receive electrical signals between the connected objects. For example, "elements that have a certain electrical function" include, in addition to electrodes or wiring, switching elements such as transistors, resistors, coils, and other elements with various functions.

[0054] Note that in this specification, the connection between two nodes via insulators such as the dielectric of a capacitor, the gate insulating film of a transistor, or the interlayer insulating film is not included in the "electrical connection" section.

[0055] Note that, in this specification, a conical shape refers to a shape in which at least a portion of the side surface of a constituent element is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region where the angle (also referred to as the cone angle) formed by the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Here, the side surface of the constituent element, the substrate surface, and the surface to be formed do not necessarily have to be completely flat; they may also be approximately planar with slight curvature or approximately planar with slight irregularities.

[0056] Note that arrows indicating the X, Y, and Z directions are sometimes included in the accompanying drawings and other materials of this specification. Note that in this specification, "X direction" refers to the direction along the X-axis, and unless explicitly stated otherwise, its direction (clockwise or counterclockwise) is not always distinguished. The same applies to "Y direction" and "Z direction." Furthermore, the X, Y, and Z directions are intersecting directions. For example, the X, Y, and Z directions are orthogonal to each other.

[0057] In this specification and other materials, the cubic crystal system is sometimes referred to as cubic crystal, cubic crystal structure, etc. The same applies to other crystal systems (hexagonal, trigonal, tetragonal, orthorhombic, monoclinic, triclinic).

[0058] Implementation Method 1 In this embodiment, refer to Figures 1A to 14D This invention describes a semiconductor device according to one aspect of the present invention and a method for manufacturing the semiconductor device. One aspect of the semiconductor device includes a transistor having a semiconductor layer.

[0059] <Structure of Semiconductor Devices> Figures 1A to 1E This is a three-dimensional schematic diagram of a semiconductor device. About Figure 1A Some of the constituent elements (such as insulating layers) are shown only in outlines represented by dashed lines. Figure 1B It cuts along the YZ plane, including the dotted line. Figure 1A A three-dimensional diagram of a portion of it. Figure 1C It is a cut along the XZ plane including the double-dotted line. Figure 1A A three-dimensional diagram of a portion of it. Figures 1A to 1C Arrows indicate the X, Y, and Z directions. Note that... Figures 1A to 1C The same symbols for X, Y, and Z are used throughout, but their directions do not necessarily need to be consistent across these figures. In later figures, the X, Y, and Z directions may also differ between figures.

[0060] Figures 1A to 1C The illustrated semiconductor device includes a substrate 10, an insulating layer 20 on the substrate 10, a semiconductor layer 30 on the insulating layer 20, an insulating layer 50 on the semiconductor layer 30, and a conductive layer 60 on the insulating layer 50. Furthermore, the semiconductor device includes an insulating layer 80. Note that, in one embodiment of the present invention, the semiconductor device sometimes includes layer 29.

[0061] Figure 1D The substrate 10, insulating layer 20, layer 29 and semiconductor layer 30 are shown as components of a semiconductor device. Figure 1E The substrate 10, insulating layer 20, and layer 29 are shown as components of a semiconductor device. Figure 1F It cuts along the YZ plane, including the dotted line. Figure 1A A partial cross-sectional view. For example... Figure 1F As shown, the insulating layer 80 includes an opening 89.

[0062] In a transistor according to one embodiment of the invention, a conductive layer 60 is used as a gate electrode, and an insulating layer 50 is used as a gate insulating layer. Furthermore, the semiconductor layer 30 has a channel forming region. At least a portion of the region of the semiconductor layer that overlaps with the conductive layer 60 across the insulating layer 50 is used as the channel forming region.

[0063] According to one aspect of the present invention, a transistor contains a metal oxide (also referred to as an oxide semiconductor) serving as a semiconductor in a semiconductor layer 30 including a channel formation region. That is, the transistor can be described as an OS transistor. Note that in this specification, etc., the semiconductor layer containing the oxide semiconductor can be referred to as an oxide semiconductor layer. Furthermore, since the semiconductor layer 30 contains a metal oxide, the semiconductor layer 30 can be referred to as a metal oxide layer.

[0064] In an OS transistor, when oxygen vacancies (V0) exist in the channel formation region of the oxide semiconductor... O When oxygen vacancies and impurities are present, the electrical properties can easily change, potentially leading to a decrease in reliability. Therefore, in the channel formation region of an oxide semiconductor, it is preferable to minimize oxygen vacancies and impurities. In other words, it is preferable that the carrier concentration in the channel formation region of the oxide semiconductor is reduced and intrinsically or substantially eigentyped.

[0065] Furthermore, when excessive oxygen is supplied to the semiconductor layer 30, electron traps caused by the excess oxygen form in the insulating layer 50. Consequently, in the OS transistor, positive drift degradation during +GBT (Positive Gate Bias-Temperature) stress testing is more likely to occur. In other words, the amount of positive drift degradation increases under +GBT stress testing.

[0066] Therefore, in one aspect of the semiconductor device of the present invention, the impurity concentration in the semiconductor layer 30 is preferably low. Furthermore, it is preferable to supply an appropriate amount of oxygen to the semiconductor layer 30. Additionally, it is preferable to reduce the amount of excess oxygen in the semiconductor layer 30.

[0067] Semiconductor layer 30 is preferably made of indium oxide. In this case, semiconductor layer 30 contains indium and oxygen. In metal oxides, the higher the proportion of indium atoms in the total number of atoms of all metal elements, the higher the field-effect mobility of the transistor. Therefore, by using indium oxide in semiconductor layer 30, the transistor can achieve high on-state current and high frequency characteristics.

[0068] Furthermore, the indium oxide film preferably has crystallinity. For example, the indium oxide film preferably contains grains. Examples of films containing grains include monocrystalline films, polycrystalline films, or amorphous films containing grains. It can be considered that polycrystalline films are composed of two or more grains, while monocrystalline films are composed of one grain. Grain boundaries (also called grain boundaries) are observed in polycrystalline films, but not in monocrystalline films.

[0069] Note that, unlike polycrystalline films, grain boundaries are not observed in the channel formation region of monocrystalline films. Impurities that impede carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at grain boundaries. Therefore, the presence of grain boundaries in the channel formation region increases the inhomogeneity of transistor characteristics. On the other hand, in a monocrystalline film according to one embodiment of the present invention, grain boundaries are not observed in the channel formation region, thus exhibiting the excellent effect of suppressing inhomogeneities in transistor characteristics caused by these grain boundaries.

[0070] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel formation region, a semiconductor layer in which the channel formation region is included in a single grain, or a semiconductor layer in which the crystal axis orientation is the same in at least two regions of the channel formation region, may be referred to as a single crystal film. Alternatively, a semiconductor layer in which at least one crystal orientation is oriented in the same direction in the channel formation region may be referred to as a single crystal film.

[0071] Note that the channel formation region refers to the region in the semiconductor layer that overlaps (or is opposite) to the gate electrode across the gate insulating layer, and specifically refers to the region located between the region contacting the source electrode and the region contacting the drain electrode. Note that the following semiconductor layers can also be referred to as single-crystal films: semiconductor layers in which no grains are observed in the region between the region contacting the source electrode and the region contacting the drain electrode; semiconductor layers in which the region between the region contacting the source electrode and the region contacting the drain electrode is contained within a single grain; or semiconductor layers in which at least two regions in the region between the region contacting the source electrode and the region contacting the drain electrode have the same crystal axis orientation. Alternatively, a semiconductor layer in which at least one crystal orientation in the region between the region contacting the source electrode and the region contacting the drain electrode is oriented in the same direction can be referred to as a single-crystal film.

[0072] Note that the current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, by observing the cross-section including the semiconductor layer, the source electrode, and the drain electrode, the grains, grain boundaries, grain axes, crystal orientations, etc., in the aforementioned channel formation region or the region between the source electrode and the drain electrode can be identified.

[0073] The crystallinity of the semiconductor layer 30 can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of the above methods can be used for analysis.

[0074] For example, grains can be observed in high-resolution transmission electron microscopy (TEM) images. Furthermore, grain boundaries can sometimes be observed in high-resolution TEM images, for example. That is, grains and grain boundaries can sometimes be observed in high-resolution TEM images of crystalline films. Note that the total magnification when obtaining the TEM image is preferably 2 million times or more, more preferably 4 million times or more.

[0075] Indium oxide films are more preferably single-crystal. Since single crystals lack grain boundaries, carrier scattering at grain boundaries can be suppressed, thereby enabling transistors with high field-effect mobility. Furthermore, transistors with high reliability can be achieved.

[0076] The indium oxide film can also be polycrystalline or amorphous, containing grains. In this case, it is preferable that no grain boundaries are observed or that the grain boundary content is low in the channel formation region. For example, by placing a single grain in the channel formation region, a structure in which no grain boundaries are observed in the channel formation region can be achieved. This structure can also perform the same function as a single-crystal indium oxide film.

[0077] Furthermore, two or more grains can be located in the channel forming region. For example, when the first grain and the second grain are located in the channel forming region, the crystal orientation of the first grain is preferably the same as or substantially the same as the crystal orientation of the second grain. When the crystal orientation of the first grain is the same as or substantially the same as the crystal orientation of the second grain, sometimes no grain boundary is observed at the boundary between the first grain and the second grain. By making the crystal orientation of the first grain the same as or substantially the same as the crystal orientation of the second grain, the formation of grain boundaries between the first grain and the second grain can be suppressed. Therefore, the same effect as the structure where the indium oxide film is a single crystal can be achieved in this structure. For example, sometimes the crystal orientation of the first grain is the same as or substantially the same as the crystal orientation of the second grain can be observed in high-resolution TEM images. Specifically, in high-resolution TEM images, the lattice fringes of the first grain and the second grain are continuously connected at the boundary between the first grain and the second grain.

[0078] Note that in this specification, a grain boundary refers, for example, to the boundary between adjacent grains with different crystal orientations. Therefore, in this specification, the boundary between adjacent grains with the same crystal orientation is not included in the term grain boundary. For example, even if the boundary between two grains is observed in a high-resolution TEM image, it is sometimes not referred to as a grain boundary when the crystal orientations of the two grains are consistent or substantially consistent.

[0079] Furthermore, crystal orientation can be evaluated using diffraction patterns observed by nanobeam electron diffraction (NBED). Alternatively, crystal orientation can also be evaluated using patterns obtained by performing a Fast Fourier Transform (FFT) on a TEM image (also known as FFT patterns). FFT patterns reflect the same reciprocal space information as the diffraction patterns described above.

[0080] For example, in each FFT pattern of the first and second grains, when the angle difference between their FFT patterns is -5 degrees or more and 5 degrees or less, preferably -3 degrees or more and 3 degrees or less, and more preferably -2 degrees or more and 2 degrees or less, it can be said that the crystal orientation of the first grain and the crystal orientation of the second grain are consistent or approximately consistent. Note, for example, the angle of the FFT pattern in the orientation

[111] refers to the acute angle formed by the approximate straight line between the spot originating from the (222) plane and the spot originating from the (-2-2-2) plane and the center spot and the reference line (e.g., a straight line extending in the vertical direction).

[0081] The polycrystalline degree of indium oxide films can be evaluated based on the grain size. The grain size can be calculated, for example, by calculating the grain area, assuming a circle corresponding to that area, and using the diameter of that circle as the grain size. This diameter is sometimes referred to as the equivalent circular area diameter, etc.

[0082] Furthermore, the polycrystalline nature of indium oxide films can be evaluated based on the elongation length of grain boundaries. The elongation length of grain boundaries can be calculated, for example, by extracting a specific area of ​​field of view from a TEM image of the film obtained at a total magnification sufficient to observe the grain boundaries, and using the sum of the lengths of the grain boundaries observed in that field of view as the elongation length. An indium oxide film with an elongation length of 0 nm can be considered a single crystal. This also implies that the longer the elongation length of the grain boundaries, the greater the grain boundary composition.

[0083] The elongation length of grain boundaries in the indium oxide film is preferably 0 nm or more and 1500 nm or less, more preferably 0 nm or more and 1000 nm or less, and even more preferably 0 nm or more and 800 nm or less. By having an indium oxide film with an elongation length of grain boundaries within the aforementioned range in the semiconductor layer 30, a structure in which no grain boundaries are observed or where the grain boundary composition is low can be achieved. Note that, unless otherwise specified in this specification, the field of view used for calculating the elongation length of grain boundaries is 90 nm squared.

[0084] The thickness of the semiconductor layer 30 is preferably 2 nm or more and 50 nm or less, more preferably 2.5 nm or more and 30 nm or less, even more preferably 2.5 nm or more and 20 nm or less, even more preferably 5 nm or more and 20 nm or less, and still more preferably 5 nm or more and 10 nm or less. Furthermore, at least a portion of the semiconductor layer 30 may have the aforementioned thickness. For example, a region in the channel formation region of the semiconductor layer 30 may have the aforementioned thickness. Increasing the thickness of the semiconductor layer 30 increases the on-state current of the transistor. On the other hand, when the semiconductor layer 30 is too thick, the grain boundary elongation length increases, and the on-state current of the transistor may decrease due to the scattering of carriers at the grain boundaries. Furthermore, reducing the thickness of the semiconductor layer 30 suppresses the decrease in threshold voltage, thereby enabling normally-off transistors. On the other hand, when the semiconductor layer 30 is too thin, the non-uniform crystallinity of the semiconductor layer 30 within the substrate surface may lead to non-uniform electrical characteristics of the transistor. Therefore, by setting the thickness of the semiconductor layer 30 within the aforementioned range, the crystallinity of the semiconductor layer 30 can be improved. By increasing the crystallinity of the semiconductor layer 30, the semiconductor layer 30 can contain grains.

[0085] Furthermore, when metal oxides contain indium and zinc, they sometimes exhibit a CAAC (c-axis aligned crystalline) structure. CAAC structures have fewer grain boundaries on the ab plane than polycrystalline structures. Examples of metal oxides containing indium and zinc include indium zinc oxide (also known as In-Zn oxide, IZO (registered trademark)) and indium gallium zinc oxide (also known as In-Ga-Zn oxide, IGZO).

[0086] In a crystalline oxide semiconductor layer, an indium oxide film, for example, is a film in which hydrogen and oxygen migrate more readily than an IGZO film. Therefore, an indium oxide film can be considered, for example, a film in which hydrogen and oxygen are more readily supplied and discharged than an IGZO film. Furthermore, an indium oxide film can be considered, for example, a film with higher permeability to hydrogen and oxygen than an IGZO film. In other words, an indium oxide film can be considered, for example, a film with lower barrier properties to hydrogen and oxygen than an IGZO film.

[0087] The indium oxide film preferably has the following properties: in a heat treatment at a heating temperature of 400°C and a treatment time of 8 hours, for example, 1×10 20 atoms / cm 3 Above and 2×10 21 atoms / cm 3 Oxygen permeability within the following range is preferably 2×10 20 atoms / cm 3Above and 1×10 21 atoms / cm 3 Oxygen permeability within the following range. Furthermore, the indium oxide film preferably possesses the following properties: [e.g., 1×10⁻⁶] [This refers to a specific heat treatment process, e.g., heat treatment at 400°C for 8 hours, resulting in a film with a permeability of 1×10⁻⁶]. 20 atoms / cm 3 Above and 2×10 21 atoms / cm 3 The following is preferred: 2×10 20 atoms / cm 3 Above and 1×10 21 atoms / cm 3 Oxygen diffuses within the grains within the following range.

[0088] By allowing oxygen in the indium oxide film to diffuse through grains and grain boundaries, the amount of V present in grains or grain boundaries can be reduced. O Therefore, the electrical characteristics and reliability of transistors can be improved.

[0089] Furthermore, the permeability of the membrane to oxygen and hydrogen can be evaluated, for example, using calculations based on the NEB (Nudged elastic band) method. Specifically, this can be evaluated by calculating the migration barriers of oxygen and hydrogen atoms using the NEB method. In other words, the smaller the migration barrier value, the easier it is for the atom to migrate (the easier it is to permeate).

[0090] Table 1 shows an example of the calculation results. The In₂O₃ shown in Table 1 is the crystal model of indium oxide, and the IGZO shown is the crystal model of In-Ga-Zn oxide. Note that the excess oxygen shown in Table 1 refers to oxygen not located at lattice positions or oxygen located between lattice points.

[0091] [Table 1] <![CDATA[In2O3]]> IGZO oxygen migration barrier 0.85eV 1.88eV Hydrogen migration barrier 0.34eV 1.39eV Migration barrier of excess oxygen 1.25eV 1.43eV

[0092] Table 1 shows that the migration barriers for oxygen, hydrogen, and excess oxygen are large in the In-Ga-Zn oxide crystal model but small in the indium oxide crystal model. This indicates that oxygen and hydrogen migrate more easily (permeate more readily) in indium oxide compared to In-Ga-Zn oxide. Furthermore, the permeability of indium oxide films to oxygen and hydrogen atoms is higher than that of In-Ga-Zn oxide films. Therefore, it can be inferred that indium oxide films are films where hydrogen and oxygen are easily supplied and expelled. Additionally, it is expected that oxygen can be used to fill the V generated during +GBT testing. O Based on its function, it can be inferred that it can achieve highly reliable transistors.

[0093] Thus, as Figure 2A As shown, diffusion occurs into the indium oxide film (referred to as InO). XOxygen (O) permeates through the indium oxide membrane and is released as oxygen molecules (O2). Additionally, it is sometimes released as water molecules (H2O) by reacting with hydrogen contained in the membrane. Furthermore, when oxygen vacancies (V) are present in the membrane... O When oxygen diffuses, it fills the oxygen vacancies. Because oxygen diffuses easily, indium oxide (IO) films can fill oxygen vacancies more readily than IGZO films. Therefore, IO films can more easily reduce oxygen vacancies compared to IGZO films. Thus, by using IO films in transistors, transistors with extremely high reliability can be realized.

[0094] In addition, such as Figure 2A As shown, hydrogen diffuses through the indium oxide membrane. Hydrogen diffuses from the outside into the indium oxide membrane and is released as hydrogen molecules (H2) through the membrane. Alternatively, as described above, the hydrogen reacts with oxygen contained in the membrane and is released as water molecules.

[0095] The content of the first element in the semiconductor layer 30 is preferably low. Furthermore, the concentration of the first element in the semiconductor layer 30 is preferably low. In particular, the concentration of the first element in the channel forming region is preferably low. Here, the first element is at least one of boron, carbon, aluminum, silicon, zinc, and gallium. That is, in the semiconductor layer 30, it is preferable that the concentration of any one of boron, carbon, aluminum, silicon, zinc, and gallium is low; more preferably, the concentration of two selected from boron, carbon, aluminum, silicon, zinc, and gallium is low; and even more preferably, the concentrations of each of boron, carbon, aluminum, silicon, zinc, and gallium are low. The concentration of the first element in the semiconductor layer 30 is preferably, for example, 1 atomic% or less, more preferably 0.1 atomic% or less, and even more preferably 0.01 atomic% (100 ppm) or less. Furthermore, the preferred concentration of the first element in the semiconductor layer 30 can also be considered the preferred concentration of the first element in the channel forming region.

[0096] Furthermore, as described below, by using a precursor that has undergone more than one distillation, the concentration of the first element in the semiconductor layer 30 can be set to 0.01 atomic% (100 ppm) or less, 0.0001% (1 ppm) or less, 0.00001% (0.1 ppm or 100 ppb) or less, or 0.0000001% (0.001 ppm or 1 ppb) or less. In other words, the content (purity) of indium other than oxygen in the semiconductor layer 30 can be set to 99.99 atomic% or more (4N), 99.9999 atomic% or more (6N), 99.99999 atomic% or more (7N), or 99.9999999 atomic% or more (9N), making it possible to form a semiconductor layer 30 with a purity equivalent to that of silicon used in the semiconductor layer (10N).

[0097] The crystallinity of semiconductor layer 30 can be improved by reducing the concentration of boron, carbon, aluminum and silicon in semiconductor layer 30.

[0098] When the semiconductor layer 30 contains gallium atoms, these gallium atoms bond with excess oxygen atoms to form a Ga-O structure. The Ga-O structure acts as an acceptor for trapped electrons. Therefore, in transistors including a semiconductor layer 30 containing both gallium atoms and excess oxygen atoms, the threshold voltage variation in the PBTS (Positive Bias Temperature Stress) test increases. Therefore, by reducing the gallium concentration in the semiconductor layer 30, the threshold voltage variation in the PBTS test can be reduced. Thus, a transistor with high reliability for applying a positive bias voltage can be realized. Furthermore, when the semiconductor layer 30 contains zinc atoms, the same situation may occur as when it contains gallium atoms.

[0099] Furthermore, aluminum, gallium, and zinc atoms have stronger bonding forces with oxygen atoms compared to indium atoms. Therefore, by reducing the concentration of aluminum, gallium, and zinc in the indium oxide film, the decrease in oxygen permeability can be suppressed.

[0100] Furthermore, impurities such as the first element contained in the indium oxide film can act as crystal nuclei. By minimizing impurities in the indium oxide film, the number of crystal nuclei can be reduced, which can promote larger crystal sizes as described below.

[0101] Furthermore, when the indium oxide film is a polycrystalline film, the first element segregates at the grain boundaries, forming an oxide containing the first element. Because this oxide has insulating properties, it can potentially cause a decrease in the transistor's on-state current or field-effect mobility. By minimizing the amount of the first element in the indium oxide film, the transistor's on-state current or field-effect mobility can be improved.

[0102] Furthermore, by reducing impurities in the indium oxide film, impurity scattering can be suppressed. This allows for the realization of transistors with high field-effect mobility. For example, by setting the concentration of the first element in the semiconductor layer 30 within the aforementioned preferred range, the field-effect mobility of the transistor can be set to 100 cm⁻¹. 2 / (V·s) or more, preferably 150cm 2 / (V·s) or more, more preferably 200cm 2 / (V·s) or higher, more preferably 250cm 2 / (V·s) and above.

[0103] Furthermore, Non-Patent Literature 2 reports the fact that, assuming the primary cause of scattering in indium oxide is ionized impurities and polar optical phonons, the Hall mobility is calculated to have an upper limit of 270 cm⁻¹. 2 / (V·s)(refer to) Figure 3 ).

[0104] Here, the carrier concentration dependence of Hall mobility for indium oxide, silicon, and IGZO is explained. Figure 2B It concerns silicon (Si) and indium oxide (InO). X A schematic diagram illustrating the carrier concentration dependence of Hall mobility. Figure 2C This is a schematic diagram showing the carrier concentration dependence of Hall mobility in IGZO.

[0105] First, such as Figure 2C As indicated by the arrows, IGZO tends to exhibit higher Hall mobility with higher carrier concentrations. On the other hand, as... Figure 2B As indicated by the arrows, indium oxide (INO) tends to exhibit higher Hall mobility with lower carrier concentrations (see Non-Patent Literature 3). This tendency is similar to that of silicon; the lower the concentration of dopants (impurities) in the material, the less impurity scattering occurs, and the higher the Hall mobility. In other words, in INO, higher purity and more intrinsic properties result in higher Hall mobility. From this result, it can be concluded that, unlike IGZO, INO possesses properties close to those of silicon. Note that... Figure 2B The properties of indium oxide shown are those assuming a single crystal. Therefore, when indium oxide is not a single crystal (e.g., polycrystalline), its properties may differ. Figure 2B The characteristics shown are different.

[0106] exist Figure 2B In this context, the range R1, characterized by low carrier concentration, corresponds to a range with extremely high Hall mobility. Therefore, it can be considered, for example, a suitable range of carrier concentrations for use in the channel formation region of a transistor. For instance, in indium oxide, the range R1 includes carrier concentrations of 1 × 10⁻⁶. 15 cm -3 The range, for example, is 1×10 14 cm -3 Above and 1×10 18 cm -3 The following range. By sufficiently reducing the carrier concentration, it is expected that the Hall mobility value can be increased to 270 cm⁻¹. 2 Approximately / (V·s).

[0107] Furthermore, in indium oxide, the region with a carrier concentration in the range R1 can contain elements that reduce the carrier concentration. Examples of elements that reduce carrier concentration include magnesium, calcium, zinc, cadmium, and copper. Replacing indium with these elements reduces the carrier concentration. Other examples of elements that reduce carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, replacing oxygen with nitrogen, phosphorus, arsenic, or antimony reduces the carrier concentration.

[0108] On the other hand, the range of high carrier concentration R2 is the range of low resistance; for example, it can be said to be the range of carrier concentrations suitable for use in the source and drain regions of transistors, resistive bodies, or transparent conductive films. The range R2 includes carrier concentrations of 1 × 10⁻⁶. 20 cm -3 The range, for example, is 1×10 19 cm -3 Above and 1×10 22 cm -3 The following range. By sufficiently increasing the carrier concentration, it is expected that the resistivity can be reduced to 1×10⁻⁶. -4 Below Ω·cm.

[0109] Furthermore, in indium oxide, the region with a carrier concentration in the range R2 can contain elements that increase the carrier concentration. For example, it is preferable to include the same elements as the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, tantalum, tungsten, molybdenum, tin, silicon, germanium, zirconium, hafnium, and boron. In particular, it is more preferable to use elements whose oxides have conductive or semiconductor properties.

[0110] Thus, in indium oxide, regions with low carrier concentration are used for the channel formation region of the transistor, while regions with high carrier concentration are used for the source and drain regions. In other words, indium oxide can also be considered an oxide capable of controlling valence electrons. Note that valence electron control in silicon transistors is generally known. On the other hand, valence electron control in indium oxide transistors is a novel technical concept that is not usually considered. Based on this technical concept, transistors with high mobility, low off-state current, and the ability to be normally off can be realized.

[0111] Furthermore, the concentration of the first element can be evaluated using methods such as inductively coupled plasma mass spectrometry (ICP-MS), XPS, secondary ion mass spectrometry (SIMS), time-of-flight secondary ion mass spectrometry (ToF-SIMS), Auger electron spectrometry (AES), energy dispersive X-ray spectrometry (EDX), or inductively coupled plasma atomic emission spectrometry (ICP-AES).

[0112] Hydrogen contained in oxide semiconductors reacts with oxygen bonded to metal atoms to form water, sometimes creating oxygen vacancies. This can cause electrical properties to fluctuate, leading to decreased reliability. On the other hand, hydrogen present at grain boundaries can sometimes terminate dangling bonds at grain boundaries, improving the electrical properties and reliability of transistors. Therefore, while it is preferable to reduce the hydrogen concentration in the indium oxide film, the hydrogen concentration can sometimes be higher than the concentration of the first element.

[0113] Indium oxide has a band gap of 2.5 eV or higher and 3.7 eV or lower. By using indium oxide, which has a larger band gap than silicon, in semiconductor layer 30, the off-state current of transistors can be reduced, thus significantly reducing the power consumption of semiconductor devices.

[0114] OS transistors are accumulation transistors where electrons are the majority carriers. In other words, the carriers in an OS transistor are electrons. Assuming a constant relaxation time for the carriers, the smaller the effective mass of the electrons (carriers), the higher the electron mobility (carrier mobility). That is, by using metal oxides with small effective electron mass in the semiconductor layer of the transistor, the on-state current or field-effect mobility of the transistor can be improved.

[0115] Table 2 shows the effective masses of single-crystal indium oxide (In₂O₃ in this case) and single-crystal silicon (Si). The effective masses of electrons and holes shown in Table 2 are values ​​calculated using first-principles electronic state calculations.

[0116] [Table 2] Effective mass of In2O3 Effective mass of Si electronic Hole 0.26 0.17

[0117] As shown in Table 2, indium oxide (IO) has a low effective electron mass. Therefore, by using IO, which has a low effective electron mass, in semiconductor layer 30, transistors with high on-state current, high field-effect mobility, and high frequency characteristics (also known as f-characteristics) can be realized. Furthermore, IO has the characteristic that the effective electron mass is almost independent of crystal orientation. Moreover, the effective electron mass of IO is, for example, smaller than that of silicon. Therefore, from the viewpoint of effective electron mass, transistors using IO in the channel formation region exhibit higher f-characteristics than Si transistors.

[0118] As shown in Table 2, indium oxide (IO) has a large effective hole mass. Therefore, by using IO with a large effective hole mass in semiconductor layer 30, transistors with extremely low off-state current can be realized. Furthermore, the effective hole mass of IO is, for example, greater than that of silicon. Therefore, from the viewpoint of effective hole mass, the off-state current of transistors using IO in the channel formation region is significantly smaller than that of Si transistors.

[0119] In a transistor where indium oxide is used as semiconductor layer 30, the off-state current value per channel width of 1 μm at room temperature (25 °C) can be set to 1 A (1 × 10⁻⁶). -18 A) or below or 1zA(1×10 -21 A) Below. Furthermore, the off-state current value per channel width of 1 μm at 85°C can be set to 1 × 10⁻⁶. -16 Below A / μm, preferably 1×10 -17 A / μm or less, more preferably 1×10 -18 Below A / μm. Furthermore, the off-state current at 125°C with a channel width of 1μm can be set to 1fA (1×10⁻⁶). -15 A) or below or 1aA(1×10 -18 A) The following.

[0120] Furthermore, miniaturizing the OS transistor can improve its high-frequency characteristics. For example, the transistor's cutoff frequency (fT) can be increased. Specifically, at room temperature (25°C), the transistor's cutoff frequency can be 50 GHz or higher, preferably 100 GHz or higher, and more preferably 150 GHz or higher.

[0121] Indium oxide films can contain one or more of the periodic elements with high period numbers in the periodic table, within a range that exhibits crystallinity. There is a tendency for greater overlap of the orbitals of metal elements in metal oxides to result in greater carrier conduction. Therefore, by including periodic elements with high period numbers in the periodic table, the field-effect mobility of transistors can sometimes be improved. Examples of periodic elements with high period numbers in the periodic table include elements belonging to period 5 and period 6. Specifically, examples of such elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, and light rare earth elements (lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium).

[0122] Figure 1A An example of a single-layer structure for semiconductor layer 30 is shown. Furthermore, semiconductor layer 30 can have a stacked structure of two or more layers. For example, in the case where semiconductor layer 30 has a two-layer structure of a first semiconductor layer and a second semiconductor layer on the first semiconductor layer, it is preferable to use a metal oxide (typically indium oxide) suitable for the aforementioned semiconductor layer 30 as the first semiconductor layer, and a metal oxide whose conduction band bottom is closer to the vacuum level than that of the first semiconductor layer as the second semiconductor layer. In this case, the first semiconductor layer can be primarily used as a current path (channel). That is, the surface of the first semiconductor layer on the side of the second semiconductor layer and its vicinity have a channel forming region.

[0123] By employing the above structure, the number of carriers trapped at and near the interface of the first semiconductor layer can be reduced. Furthermore, by positioning the channel away from the surface of the insulating layer 50, the effects of surface scattering can be reduced. This, in turn, improves the electric field mobility of the transistor.

[0124] As metal oxides that can be used for the second semiconductor layer, examples include indium gallium oxide (In-Ga oxide), In-Zn oxide, indium tin oxide (In-Sn oxide, also denoted as ITO), indium titanium oxide (In-Ti oxide), indium aluminum zinc oxide (In-Al-Zn oxide, also denoted as IAZO), In-Ga-Zn oxide, indium tin zinc oxide (also denoted as In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), and indium tin oxide containing silicon oxide (also denoted as ITSO). Alternatively, zinc oxide, aluminum zinc oxide (Al-Zn oxide, also denoted as AZO), and aluminum tin oxide (Al-Sn oxide) can be used.

[0125] Specifically, the In-Zn oxide used for the second semiconductor layer can have an In:Zn ratio of 1:1 or similar, an In:Zn ratio of 2:1 or similar, or an In:Zn ratio of 4:1 or similar. Specifically, the IGZO used for the second semiconductor layer can have an In:Ga:Zn ratio of 1:1:1 or similar, an In:Ga:Zn ratio of 1:3:2 or similar, or an In:Ga:Zn ratio of 1:3:4 or similar. Note that "similar" includes a range of ±30% of the desired atomic ratio.

[0126] There are no particular restrictions on the crystallinity of the metal oxide contained in the second semiconductor layer. For example, the second semiconductor layer may sometimes contain one or more of the following: amorphous semiconductor (semiconductor with an amorphous structure), single-crystal semiconductor (semiconductor with a single-crystal structure), and semiconductor with crystallinity other than single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or a portion thereof having a crystalline region).

[0127] exist Figure 1E and Figure 1F In the middle, an island-shaped layer 29 is provided in contact with the top surface of the insulating layer 20, and a semiconductor layer 30 is provided as a cover layer 29.

[0128] Layer 29 contains crystals. When a process is performed to improve the crystallinity of semiconductor layer 30, layer 29 is used as a seed or nucleus. In other words, layer 29 is used as a seed or nucleus during the crystal growth of semiconductor layer 30. In this specification, layer 29 or the crystals contained in layer 29 may be referred to as seed crystals or nuclei. Furthermore, since layer 29 contains crystals, layer 29 may be referred to as a crystalline portion.

[0129] Indium oxide has a cubic crystal structure (manganese permanganate type). When indium oxide is used in semiconductor layer 30, layer 29 preferably contains, for example, hexagonal or trigonal crystals. In this case, by making layer 29 contain crystals with a crystal orientation relative to the surface of layer 29 or the surface to which it is formed... <001> The crystallization can form crystals with a crystal orientation of <111> The crystalline semiconductor layer 30. The crystal orientation of the crystals contained in layer 29 relative to the surface of layer 29 or the surface in which they are formed is as follows: <001> At this time, the c-axis of the crystal is perpendicular or substantially perpendicular to the surface of layer 29 or the surface on which it is formed. Note that hexagonal or trigonal crystals can sometimes be referred to as crystals with layered structures, so the above structure can be considered as a structure in which a semiconductor layer 30 containing cubic crystals is formed on a layer 29 containing crystals with layered structures. In other words, it can also be considered as a stacked structure manufactured using heteroepitaxial growth technology or a technique such as heteroepitaxial growth.

[0130] In this specification, space groups are represented using shortnotation with international symbols (or Hermann-Mauguin notation). Furthermore, Miller indices are used to represent crystal faces and crystal orientations. In crystallography, a superscript is added to numbers to indicate space groups, crystal faces, and crystal orientations. However, in this specification, due to the notation limitations in the patent application, a - (negative number symbol) is sometimes added before numbers to indicate space groups, crystal faces, and crystal orientations instead of a superscript. Additionally, "[]" indicates the individual orientation within a crystal, "<>" indicates the collective orientation of all equivalent orientations, "()" indicates an individual crystal face, and "{}" indicates a collective face with equivalent symmetry.

[0131] In this specification and the like, the crystal orientation of crystallization refers to its orientation relative to the surface of the substrate. Therefore, for example, the crystal orientation is... <100> The crystallization can be described as the (100) plane being parallel to the substrate surface. However, it is not limited to this; the crystal orientation can also be described as the orientation relative to the surface of the insulating layer 20 or the surface of the insulating layer 20 that is formed.

[0132] Specifically, zinc oxide, In-Ga oxide, gallium zinc oxide (Ga-Zn oxide, also denoted as GZO), aluminum zinc oxide (Al-Zn oxide, also denoted as AZO), In-Al-Zn oxide, In-Ga-Zn oxide, or In-Sn-Zn oxide can be used as layer 29. In-Ga-Zn oxide is preferred as layer 29. In this case, layer 29 contains indium, gallium, zinc, and oxygen. Furthermore, its composition is preferably In:Ga:Zn = 1:1:1 [atomic ratio] or close to it, or In:Ga:Zn = 1:3:2 [atomic ratio] or close to it. Since the metal oxides with the above compositions readily form layered structures, they are suitable for use as layer 29.

[0133] In-Ga-Zn oxides and In-Sn-Zn oxides readily possess a CAAC structure. When an oxide with a CAAC structure is used as layer 29, the c-axis of the crystals contained in layer 29 is perpendicular or substantially perpendicular to the surface of layer 29 or the plane to which it is formed. In other words, the crystal orientation of the crystals contained in layer 29 relative to the surface of layer 29 or the plane to which it is formed is... <001> Therefore, by using oxides that readily possess CAAC structures for layer 29, the controllability of the crystal orientation of the crystal nuclei can be improved.

[0134] Here, Figures 4A to 4E The crystal structure of the metal oxide is shown. Figure 4A This is a diagram of the crystal structure of an In-Ga-Zn oxide with an In:Ga:Zn ratio of 1:1:1 [atomic number ratio], viewed from a direction perpendicular to the c-axis. Figure 4B Viewed from the c-axis direction Figure 4A The diagram shows the surface indicated by the dashed lines. Figure 4C Viewed from the c-axis direction Figure 4A The dotted lines in the diagram represent the surface, and Figure 4D Viewed from the c-axis direction Figure 4A The diagram shows the surface indicated by the double-dotted line. Figure 4A , Figure 4C and Figure 4D In this context, Mx represents either a Ga atom or a Zn atom. Note that in... Figure 4A In Chinese, the surfaces shown by dashed lines, dotted lines, and double-dotted lines are sometimes collectively referred to as surface c. Furthermore, Figure 4E This is a diagram of the crystal structure of indium oxide viewed from the direction perpendicular to the (111) plane.

[0135] The interatomic spacing of the metal on the c-plane ( Figures 4B to 4D The arrows shown are considered to be 0.330 nm. Furthermore, the In-In distance in the (111) plane ( Figure 4E The arrows shown are considered to be 0.334 nm and 0.385 nm. In other words, the c-plane of the CAAC structure is similar to the metal atom configuration of the (111) plane of indium oxide. Therefore, oxides that readily have a CAAC structure can be used as layer 29.

[0136] When an oxide that readily possesses a CAAC structure is used for layer 29, a crystal orientation can be formed. <111> The crystalline semiconductor layer 30. Figure 5 A cross-sectional view of layer 29 and its adjacent insulating layer 20 and semiconductor layer 30 is shown. Figure 5 In the diagram, arrows indicate the crystalline structures contained within semiconductor layer 30. <111> Orientation. For example... Figure 5 As shown, the semiconductor layer 30 contains crystalline... <111> The orientation is readily perpendicular or substantially perpendicular to the substrate surface (not shown) above layer 29, near the side of layer 29, and away from layer 29. This is a property that is distinct from the CAAC structure in which the c-axis of the crystal is perpendicular or substantially perpendicular to the formed surface or plane of semiconductor layer 30.

[0137] Layer 29 can also be an oxide with a cubic crystal structure. By making layer 29 have the same crystal structure as semiconductor layer 30, semiconductor layer 30 can be epitaxially grown using layer 29 as a seed or nucleus, thereby improving the crystallinity of semiconductor layer 30. The crystal structure of oxides containing elements of Group 3 in the periodic table is prone to be cubic. Furthermore, the Group 3 elements in this crystal mainly exist as trivalent cations. Therefore, layer 29 preferably contains at least one element that can be a trivalent cation. The element that can be a trivalent cation contained in layer 29 is preferably scandium, yttrium, cerium, gadolinium, erbium, or ytterbium.

[0138] As layer 29, for example, oxides containing one or both of yttrium and zirconium, erbium oxide, etc., can be used. Examples of oxides containing one or both of yttrium and zirconium include yttrium oxide, zirconium oxide, and yttrium zirconium oxide.

[0139] Furthermore, the difference between the lattice constant or the length of a unit lattice vector of the crystal nucleus and the lattice constant or the length of a unit lattice vector of the crystal contained in the semiconductor layer 30 (also known as lattice mismatch) is preferably small. By using an oxide with small lattice mismatch in layer 29, the crystallinity of the semiconductor layer 30 can be improved.

[0140] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch degree shown below. The lattice mismatch degree Δa[%] of the crystals contained in the formed film (here, the indium oxide film) relative to the crystals contained in the film being formed is calculated according to the following formula (1). Hereinafter, the lattice mismatch degree Δa of the crystals contained in the formed film relative to the crystals contained in the film being formed is sometimes simply referred to as the lattice mismatch degree Δa of the formed film relative to the film being formed.

[0141] [Equation 1]

[0142] In formula (1), L1 represents the lattice constant or the length of the unit lattice vector of the crystal contained in the above-formed film, and L2 represents the lattice constant or the length of the unit lattice vector of the crystal contained in the above-formed film.

[0143] The lattice mismatch Δa of the grains contained in the semiconductor layer 30 relative to the crystal nucleus is preferably -10% or more and 10% or less, more preferably -5% or more and 5% or less, and even more preferably -3% or more and 3% or less. By using a material with a small lattice mismatch relative to the semiconductor layer 30 in layer 29, the crystallinity of the semiconductor layer 30 can be improved.

[0144] For example, the lattice constant of indium oxide crystal (argentite type) is considered to be 1.01194 nm. Furthermore, the lattice constant of yttrium oxide crystal (argentite type) is considered to be 1.05976 nm. Therefore, the lattice mismatch of indium oxide crystal relative to yttrium oxide crystal is -4.5%. Therefore, when indium oxide is used in semiconductor layer 30, yttrium oxide can be used in layer 29.

[0145] For example, the lattice constant of erbium oxide crystal (argentite-manganese type) is considered to be 1.0582 nm. Therefore, the lattice mismatch of indium oxide crystal relative to erbium oxide crystal is -4.4%. When indium oxide is used for semiconductor layer 30, erbium oxide can be used for layer 29.

[0146] For example, Zr, as an example of yttrium zirconium oxide 0.9 Y 0.1 O 1.95 The lattice constant of the crystal (fluorite type) is 0.51481 nm (refer to ICSD coll.code.248790). Therefore, the lattice constant of indium oxide crystal relative to Zr... 0.9 Y 0.1 O 1.95 The lattice mismatch of the crystal is -1.7%. Therefore, when indium oxide is used for semiconductor layer 30, yttrium zirconium oxide can be used for layer 29. Note that yttrium zirconium oxide contains yttrium, zirconium, and oxygen.

[0147] By adding yttrium or yttrium oxide to zirconium oxide, i.e., setting the yttrium content in yttrium zirconium oxide to be greater than 0 atomic%, the crystal structure of zirconium oxide can be stabilized. Note that when this content increases, the crystal structure of yttrium zirconium oxide sometimes changes from a cubic crystal system to other crystal systems; therefore, this content is preferably not too high. Thus, for example, the yttrium content contained in yttrium zirconium oxide is preferably 2 atomic% or more and 15 atomic% or less, more preferably 5 atomic% or more and 10 atomic% or less.

[0148] Alternatively, indium oxide can be used as layer 29. By using indium oxide as layer 29, the semiconductor layer 30 can be homoepitaxially grown using layer 29 as a seed or nucleus, thereby improving the crystallinity of the semiconductor layer 30. In this case, the crystal orientation of the crystals contained in layer 29 is consistent with or substantially consistent with the crystal orientation of the crystals contained in semiconductor layer 30.

[0149] There are no particular restrictions on the materials that can be used for layer 29. Layer 29 can be made of insulating, semiconductor, or conductive materials. When a semiconductor material is used for layer 29, layer 29 can also be considered as part of semiconductor layer 30.

[0150] Figure 1E An example is shown where layer 29 appears circular when viewed from a plane. Note that the invention is not limited to this. The shape of layer 29 when viewed from a plane can be, for example, a circle or an ellipse, or an approximate circle; a polygon such as a triangle, a quadrilateral (including a rectangle, rhombus, or square), a pentagon, or a star-shaped polygon; or a shape where the corners of these polygons are rounded. Furthermore, when sputtered particles are used as layer 29, layer 29 may sometimes appear triangular or hexagonal when viewed from a plane.

[0151] In addition, such as Figure 6A and Figure 6BAs shown, layer 29 can also be conical. For example, the angle formed between the top surface of insulating layer 20 and the side surface of layer 29 can be less than 90°, preferably 30° or more and less than 90°. By making layer 29 conical, the coverage of semiconductor layer 30 can be improved, thereby reducing defects such as voids. In addition, it can promote the crystal growth of semiconductor layer 30.

[0152] Figure 1A An example with an island-shaped layer 29 is shown. Note that the invention is not limited to this. For example, layer 29 may also have a direction perpendicular to the Z direction ( Figure 6C The region extending in the X direction.

[0153] Figure 1A An example is shown where layer 29 is disposed in contact with the top surface of insulating layer 20. Note that the invention is not limited thereto. For example, as Figure 6D and Figure 6E As shown, layer 29 can also be provided in a recess embedded in the insulating layer 20. This allows the top surface of the insulating layer 20 to be flattened, improving the crystallinity of the semiconductor layer 30. Furthermore, the recess can also be an opening penetrating the insulating layer 20. Additionally, layer 29 embedded in the recess can also have an extended region (see reference). Figure 6F ).

[0154] The thickness of layer 29 is preferably thin. For example, the thickness of layer 29 is preferably smaller than the thickness of semiconductor layer 30. Specifically, layer 29 preferably has a region with a thickness of 0.1 nm or more and less than 2 nm, and more preferably has a region with a thickness of 0.5 nm or more and less than 2 nm. By reducing the thickness of layer 29, the step between layer 29 and insulating layer 20 is reduced. Therefore, the coverage of semiconductor layer 30 is improved, and defects such as voids can be reduced. In addition, the crystal growth of semiconductor layer 30 can be promoted. Note that layer 29 can be layered or granular.

[0155] The top surface of the insulating layer 20 is preferably flat. When the top surface of the insulating layer 20, where the layer 29 is to be disposed, is uneven, crystal nuclei may form due to the unevenness, hindering large grain formation. Therefore, by making the top surface of the insulating layer 20 flat, the generation of crystal nuclei can be suppressed, and crystallization and crystal growth in the semiconductor layer 30 with layer 29 as seed or nucleus can be promoted.

[0156] In this specification, the flat top surface of a membrane or layer includes cases where the top surface of the membrane or layer has fine convex surfaces, convex curved surfaces, concave surfaces, concave curved surfaces, uneven shapes, etc.

[0157] Here, Figure 7 A cross-sectional schematic diagram of the insulating layer 20 is shown. Figure 7 This diagram also illustrates the shape of the top surface of the insulating layer 20. Figure 7In the diagram, a double arrow indicates the height difference H between adjacent convex and concave portions, and r represents the radius of curvature of the convex portion. The height difference H is preferably 0 nm or more and less than 3 nm. By making the height difference H less than the preferred thickness of the semiconductor layer 30 described later, crystallization and crystal growth in the semiconductor layer 30 can be suppressed. Furthermore, the height difference H is more preferably 0 nm or more and less than 2 nm, even more preferably 0 nm or more and less than 1 nm, further preferably 0 nm or more and less than 0.3 nm, and even more preferably 0 nm or more and less than 0.1 nm. Note that a height difference H of 0 nm means that no convex or concave portions are observed on the top surface of the film or layer. By making the height difference H less than the preferred thickness of the layer 29 described above, the coverage of the semiconductor layer 30 is improved, and defects such as voids can be reduced. Furthermore, the radius of curvature r is preferably 1 nm or more and less than 100 nm, more preferably 10 nm or more and less than 100 nm. The top surface where the convex and concave portions exist can be considered flat.

[0158] The height difference H and radius of curvature r can be evaluated by image analysis of a TEM image of the cross-section. In evaluating the height difference H and radius of curvature r of the top surface of the first layer using TEM image analysis of the cross-section, a sample including the first layer and a second layer on top of the first layer is first prepared. Next, a TEM image of the cross-section of this sample is obtained, and the contrast (the boundary of different brightness) observed in this TEM image is assumed to be the interface between the first and second layers, i.e., the top surface of the first layer. The height difference H and radius of curvature r can be calculated based on the assumed top surface of the first layer. Note that the height difference H can be calculated as an average value for each field of view (e.g., 100 nm). Similarly, the radius of curvature r can be calculated as an average value for each field of view (e.g., 100 nm).

[0159] Furthermore, in this specification, when the average surface roughness (Ra) of the top surface of the film or layer is less than 3 nm, the top surface of the film or layer can also be considered flat. Note that the average surface roughness (Ra) refers to the arithmetic mean roughness defined in JIS B 0601:2001 (ISO 4287:1997) extended to three dimensions to be applicable to curved surfaces. The average surface roughness (Ra) can be evaluated using an atomic force microscope (AFM). Note that the average surface roughness (Ra) can be calculated, for example, in a square region with a side length of 1 mm. Furthermore, if the layer has island-like structures and there is no square region with a side length of 1 mm when viewed from a plane, it can also be calculated over the entire region of the layer when viewed from a plane. Note that the average surface roughness (Ra) described in this specification can also be referred to as root mean square surface roughness (Rq or RMS) or maximum height roughness (Rz). For example, if at least one of the average surface roughness (Ra), root mean square surface roughness (Rq or RMS), and maximum height roughness (Rz) of the top surface of the film or layer is less than 3 nm, the top surface of the film or layer can also be said to be flat.

[0160] Furthermore, the flatness of the top surface of the film or layer can also be evaluated through image analysis of the TEM image described above. For example, the contrast observed in the TEM image can be assumed to be the interface between the first and second layers, and the shape of this interface can be assumed to be the roughness curve of the first layer. The arithmetic mean roughness can then be calculated from the assumed roughness curve. Note that the reference length can be the length of the top surface of the first layer observed in the TEM image, or the length of the overlapping region between the first and second layers. For example, the reference length is 100 nm. In this case, the longitudinal and transverse lengths are preferably 100 nm or more, serving as the observation range of the TEM image. If the arithmetic mean roughness of the top surface of the first layer calculated using this method is less than 3 nm, the top surface of the first layer can also be considered flat.

[0161] The average surface roughness (Ra) or arithmetic mean roughness of the top surface of the insulating layer 20 is preferably 0 nm or more and less than 3 nm. By making the average surface roughness (Ra) or arithmetic mean roughness of the top surface of the insulating layer 20 less than the preferred thickness of the semiconductor layer 30 described later, crystallization and crystal growth in the semiconductor layer 30 can be suppressed. Furthermore, the average surface roughness (Ra) or arithmetic mean roughness of the top surface of the insulating layer 20 is more preferably 0 nm or more and less than 2 nm, even more preferably 0 nm or more and less than 1 nm, further preferably 0 nm or more and less than 0.5 nm, even more preferably 0 nm or more and less than 0.3 nm, and even more preferably 0 nm or more and less than 0.2 nm. By making the average surface roughness (Ra) or arithmetic mean roughness of the top surface of the insulating layer 20 less than the preferred thickness of the layer 29 described above, the coverage of the semiconductor layer 30 can be improved and defects such as voids can be reduced.

[0162] Note that the thickness of the semiconductor layer 30 is preferably greater than the average surface roughness (Ra) or arithmetic mean roughness of the top surface of the insulating layer 20, for example, preferably 3 nm or more and 50 nm or less. This suppresses crystallization in the semiconductor layer 30 and prevents crystal growth from being hindered.

[0163] The insulating layer 50 preferably has the function of supplying oxygen to the semiconductor layer 30. The insulating layer 50 preferably has, for example, a region containing oxygen that has been released by heating (hereinafter sometimes referred to as excess oxygen). By contacting the semiconductor layer 30 with the insulating layer having the region containing excess oxygen, oxygen can be supplied to the semiconductor layer 30. The oxygen supplied to the semiconductor layer 30 repairs oxygen vacancies, thereby reducing the amount of oxygen vacancies in the semiconductor layer 30. Examples of insulating materials that readily form regions containing excess oxygen include silicon oxide, silicon oxynitride, or porous silicon oxide.

[0164] Furthermore, the insulating layer 50 preferably has the function of trapping or fixing (also known as gettering) oxygen. As mentioned above, indium oxide film is a film in which oxygen readily migrates. Therefore, when the insulating layer 50 has the function of trapping or fixing oxygen, excess oxygen in the semiconductor layer 30 diffuses to the insulating layer 50, and this oxygen can be trapped or fixed. Therefore, the OS transistor can suppress the positive drift degradation caused by excess oxygen in the +GBT stress test. Examples of insulating materials with the function of trapping or fixing oxygen include alumina, hafnium oxide, hafnium zirconium oxide, and oxides containing hafnium and silicon (hafnium silicate).

[0165] Note that aluminum oxide, hafnium oxide, hafnium zirconium oxide, and hafnium silicate have the function of capturing or fixing hydrogen. As mentioned above, indium oxide film is a film in which hydrogen easily migrates. Therefore, when the insulating layer 50 has the function of capturing or fixing hydrogen, hydrogen diffuses from the semiconductor layer 30 to the insulating layer 50, and the hydrogen can be captured or fixed. As a result, the hydrogen concentration in the semiconductor layer 30 (especially the hydrogen concentration in the channel formation region) can be reduced.

[0166] Figure 1A An example of a single-layer structure for the insulating layer 50 is shown. Note that the insulating layer 50 may have a stacked structure of two or more layers. When the insulating layer 50 has a stacked structure of two or more layers, the insulating material (typically alumina) that can be used in the insulating layer 50 is preferably the layer that contacts the semiconductor layer 30 among the two or more layers included in the insulating layer 50. By adopting this structure, oxygen can be supplied to the semiconductor layer 30 and the amount of oxygen vacancies can be reduced. In addition, excess oxygen in the semiconductor layer 30 can be discharged to the insulating layer 50. Furthermore, hydrogen in the semiconductor layer 30 can be trapped or fixed.

[0167] The insulating layer 20 preferably has the function of supplying oxygen to the semiconductor layer 30. For example, the insulating layer 20 preferably has a region containing excess oxygen. Furthermore, the insulating layer 50 preferably has the function of trapping or fixing oxygen. By employing this structure, oxygen can be forced into the semiconductor layer 30 from the insulating layer 20 side to reduce the amount of oxygen vacancies in the semiconductor layer 30, and excess oxygen in the semiconductor layer 30 can be pulled out from the insulating layer 50 side to reduce excess oxygen in the semiconductor layer 30. Thus, a semiconductor device with high reliability can be provided.

[0168] Alternatively, an insulating layer 20 can be configured to trap or fix oxygen, and an insulating layer 50 can be configured to supply oxygen to the semiconductor layer 30. By employing this structure, oxygen can be forced into the semiconductor layer 30 from the insulating layer 50 side to reduce the amount of oxygen vacancies in the semiconductor layer 30, and excess oxygen in the semiconductor layer 30 can be pulled out from the insulating layer 20 side to reduce excess oxygen in the semiconductor layer 30. Thus, a semiconductor device with high reliability can be provided.

[0169] Furthermore, the insulating layer 20 preferably uses a material with a smaller coefficient of thermal expansion than the metal oxide used for the semiconductor layer 30. For example, the insulating layer 20 can use a material with a smaller coefficient of thermal expansion than indium oxide. Specifically, the coefficient of thermal expansion of the insulating layer 20 is preferably 0.01 × 10⁻⁶. -6 K -1 Above and 5.5×10 -6 K -1 Hereinafter, 0.01×10 is more preferred. -6 K -1 Above and 5.0×10 -6 K-1 Hereinafter, 0.01×10 is further preferred. -6 K -1 Above and 3.0×10 -6 K -1 The following is a further preferred value of 0.01×10 -6 K -1 Above and 1.0×10 -6 K -1 The following describes how, through this structure, by placing the semiconductor layer 30 containing indium oxide in contact with or near an insulating layer 20 with a low coefficient of thermal expansion, tensile stress is applied to the indium oxide upon cooling, making it energy-unstable. As a result, the indium oxide becomes a more energy-stable cubic crystal. Furthermore, crystal growth can be promoted to form large-grained cubic crystals. Since silicon oxide has a lower coefficient of thermal expansion than indium oxide, it is suitable for use in the insulating layer 20.

[0170] Table 3 shows the coefficients of thermal expansion for oxide semiconductors and insulators. In Table 3, the coefficients of thermal expansion for IGZO and indium oxide (In2O3) are shown as oxide semiconductors, and the coefficients of thermal expansion for silicon oxide (SiO2), silicon nitride (Si3N4), and yttrium-stabilized zirconium oxide (YSZ) are shown as insulators. As can be seen from Table 3, silicon nitride is also suitable for use as the insulating layer 20.

[0171] [Table 3]

[0172] Figure 1F An example of a single-layer structure for the insulating layer 20 is shown. Alternatively, the insulating layer 20 may have a stacked structure of two or more layers. When the insulating layer 20 has a stacked structure of two or more layers, the layer in contact with the semiconductor layer 30 among the two or more layers included in the insulating layer 20 is preferably an insulating material suitable for the aforementioned insulating layer 20 (typically silicon oxide). By employing this structure, the crystallinity of the semiconductor layer 30 can be improved.

[0173] Figure 1F An example is shown where the insulating layer 20 and the semiconductor layer 30 are both island-shaped. Note that the invention is not limited to this. For example, as... Figure 8A As shown, the insulating layer 20 may also have a shape with protrusions in the portion overlapping with the semiconductor layer 30 instead of an island shape.

[0174] As the conductive layer 60, a material with high conductivity, such as tungsten, is preferably used. Furthermore, as the conductive layer 60, a conductive material that is not easily oxidized or a conductive material that has the function of inhibiting oxygen diffusion is preferably used. Examples of such conductive materials include nitrogen-containing conductive materials (e.g., titanium nitride or tantalum nitride) and oxygen-containing conductive materials (e.g., ruthenium oxide). This helps to suppress the decrease in conductivity of the conductive layer 60.

[0175] Furthermore, the conductive layer 60 preferably uses a conductive material containing the metal element and oxygen contained in the metal oxide forming the channel. For example, one or more selected from ITO, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, In-Zn oxide, and ITSO can also be used. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above materials, hydrogen contained in the metal oxide forming the channel can sometimes be trapped. Alternatively, hydrogen mixed in from the insulating layer or the like outside the transistor can sometimes be trapped.

[0176] An insulating layer 80 serves as an interlayer film. An insulating layer 50 and a conductive layer 60 are provided with an opening 89 embedded within the insulating layer 80. The opening 89 is preferably located in a position that does not overlap with layer 29. The portion of the semiconductor layer 30 that does not overlap with layer 29 is flatter than the portion that overlaps with layer 29. Therefore, by providing the opening 89 in a position that does not overlap with layer 29, a channel is formed in the flat region of the semiconductor layer 30, thereby improving the electrical characteristics of the transistor.

[0177] like Figure 8B As shown, one aspect of the semiconductor device of the present invention may include conductive layers 40a and 40b, which are separated from each other, on the semiconductor layer 30. Conductive layers 40a and 40b are respectively used as the source electrode or drain electrode of a transistor. Figure 8B In this structure, conductive layers 40a and 40b are in contact with at least a portion of the top surface and at least a portion of the side surface of the semiconductor layer 30, respectively. By adopting this structure, the contact area between conductive layer 40a or conductive layer 40b and the semiconductor layer 30 can be increased, thereby reducing the contact resistance between conductive layer 40a and the semiconductor layer 30 and the contact resistance between conductive layer 40b and the semiconductor layer 30.

[0178] In addition, such as Figure 8C As shown, in one embodiment of the present invention, a semiconductor device may include a conductive layer 15 at a location where the semiconductor layer 30 overlaps with the conductive layer 60. Furthermore, Figure 8C The semiconductor device shown includes an insulating layer 16. A conductive layer 15 is covered by the insulating layer 16 and has a portion that overlaps with the semiconductor layer 30 across the insulating layer 20.

[0179] exist Figure 8C In the structure shown, conductive layer 60 is used as the first gate electrode of the transistor, insulating layer 50 is used as the first gate insulating layer of the transistor, conductive layer 15 is used as the second gate electrode of the transistor, and insulating layers 16 and 20 are used as the second gate insulating layers of the transistor.

[0180] also, Figure 8C The semiconductor device shown may also exclude the insulating layer 50 and the conductive layer 60. In this case, the conductive layer 15 is used as the gate electrode of the transistor, and the insulating layers 16 and 20 are used as the gate insulating layers of the transistor. In this case, the structure of the transistor can be described as a bottom-gate type.

[0181] <Example 1 of Semiconductor Device Manufacturing Methods> The following describes an example of a method for manufacturing a semiconductor device according to one aspect of the present invention. One example of the method for manufacturing a semiconductor device described herein includes a method for manufacturing a semiconductor layer.

[0182] Figure 9A , Figure 9C , Figure 9E , Figure 9G , Figure 10A and Figure 10C This is a three-dimensional schematic diagram of a semiconductor device. Figure 9B , Figure 9D , Figure 9F , Figure 9H , Figure 10B and Figure 10D This is a cross-sectional view of a semiconductor device viewed from the X direction.

[0183] The layers constituting the semiconductor device (insulating layer 20, layer 29, semiconductor layer 30, conductive layer 40a and conductive layer 40b, insulating layer 80, insulating layer 50 and conductive layer 60, etc.) can be formed by sputtering, chemical vapor deposition (CVD), vacuum evaporation, molecular beam epitaxy (MBE), pulsed laser deposition (PLD) or ALD, etc.

[0184] Unlike deposition methods that deposit particles released from a target or similar material, ALD (Alternating Layer Deposition) is a deposition method that forms a film through a reaction on the surface of the workpiece. Therefore, ALD is a deposition method with good step coverage, less affected by the shape of the workpiece. In particular, ALD exhibits excellent step coverage and thickness uniformity, making it suitable for covering surfaces with high aspect ratios, such as openings or grooves.

[0185] The precursors used in ALD (Alternating Discharge) methods sometimes contain elements such as carbon or chlorine. Therefore, films formed using ALD methods sometimes contain more carbon or chlorine than films formed using other deposition methods. Furthermore, the quantification of these elements can be performed using XPS or SIMS. Note that by employing one or both of the following methods during ALD, the amount of carbon and chlorine contained in the film can sometimes be reduced compared to using ALD without employing these methods: high substrate temperature during deposition and impurity removal processes.

[0186] Examples of ALD methods include thermal ALD (thermal ALD) which uses only thermal energy to react precursors and reactants, and plasma ALD (PEALD) which uses reactants excited by plasma.

[0187] In a deposition apparatus utilizing the ALD method, a first source gas (sometimes referred to as a precursor, precursor, or metal precursor) and a second source gas (sometimes referred to as a reactant, reactant, oxidant, or nonmetal precursor) are alternately introduced into the chamber, and this introduction of source gases is repeated to achieve deposition. Note that, for example, the introduced source gas can be switched by switching various on / off valves (sometimes referred to as high-speed valves). Furthermore, inert gases such as nitrogen (N2), argon (Ar), or helium (He) can be used as carrier gases when introducing the source gas, and they are introduced into the chamber along with the source gas. By using a carrier gas, even if the source gas has low volatility or vapor pressure, adsorption of the source gas into the pipes and valves can be suppressed, thereby allowing the source gas to be introduced into the chamber. Furthermore, the uniformity of the formed film is improved, making this method preferred.

[0188] When using the ALD method, films of arbitrary composition can be deposited by simultaneously introducing multiple different precursors. Alternatively, by controlling the number of cycles for each precursor when introducing multiple different precursors, films of arbitrary composition can be deposited.

[0189] First, such as Figure 9A and Figure 9B As shown, a substrate 10 is prepared, and an insulating layer 20 is formed on the substrate 10. The top surface of the insulating layer 20 is preferably flat. For example, to improve the flatness of the top surface of the insulating layer 20, it is preferably planarized using a planarization process such as chemical mechanical polishing (CMP). By making the top surface of the insulating layer 20 flat, the crystallinity of the subsequently formed semiconductor layer 30 can be improved. For example, lateral growth of the crystals contained in the semiconductor layer 30 during the first heat treatment described later can be promoted.

[0190] The insulating layer 20 can be formed, for example, by sputtering in an oxygen-containing atmosphere. By using a sputtering method that does not require the use of hydrogen-containing molecules as a deposition gas, the hydrogen concentration in the insulating layer 20 can be reduced. Furthermore, by forming the insulating layer 20 using a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the insulating layer 20. Since the heat applied after the formation of the semiconductor layer 30 can supply oxygen from the insulating layer 20 to the semiconductor layer 30, oxygen vacancies can be reduced. For example, by forming a silicon oxide film as the insulating layer 20 using a sputtering method, the top surface of the insulating layer 20 can be flattened.

[0191] Before forming layer 29, a heat treatment is preferably performed. As a heat treatment, for example, it can be performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. By keeping the temperature within the above range, even if this heat treatment is performed, substrate deformation (strain or warping) can be minimized.

[0192] The heat treatment is performed in an atmosphere of nitrogen or an inert gas, or in an atmosphere containing 10 ppm (0.001%) or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen and oxygen gas, the ratio of oxygen gas is preferably set to about 20%. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in a nitrogen or inert gas atmosphere, and then, in order to replenish the detached oxygen, the heat treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. By performing the above-described heat treatment, impurities such as hydrogen or water contained in the insulating layer 20, etc., can be reduced before the deposition of the semiconductor layer 30.

[0193] Furthermore, the gas used in the above-described heat treatment is preferably of high purity. For example, the water content in the gas used in the above-described heat treatment is preferably 1 ppb (1 × 10⁻⁶). -3 ppm or less, more preferably 0.1 ppb (1×10⁻⁶ ppm). -4 ppm or less, more preferably 0.05 ppb (5 × 10⁻⁶ ppm). -5 (ppm) or less. By using highly purified gas for heating treatment, it is possible to minimize the absorption of moisture and other substances by the insulating layer 20.

[0194] There are no particular restrictions on the heating device used for heat treatment; devices that utilize heat conduction or thermal radiation generated by heating elements such as resistance heating elements can also be used to heat the workpiece. For example, electric furnaces or RTA (Rapid Thermal Annealing) devices such as LRTA (Lamp Rapid Thermal Annealing) devices and GRTA (Gas Rapid Thermal Annealing) devices can be used. LRTA devices heat the workpiece using radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, or high-pressure mercury lamps. GRTA devices use high-temperature gas for heat treatment.

[0195] Furthermore, it is preferable to perform the oxygen supply process before forming layer 29. Oxygen is thus supplied to insulating layer 20, and oxygen can be supplied from insulating layer 20 to semiconductor layer 30 by applying heat or the like after forming semiconductor layer 30.

[0196] Examples of oxygen supply methods include heating in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere. Note that plasma treatment in this specification includes microwave plasma treatment, which will be described later. Alternatively, oxygen can be supplied to the insulating layer 20 by depositing an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere using a sputtering method. The deposited oxide film can be removed immediately or left as a residue. When the deposited oxide film is left as a residue, it can be used as part of the semiconductor layer 30. In addition to oxygen gas (O2), the oxygen-containing atmosphere may include an atmosphere containing oxygen-containing compounds such as ozone (O3) or nitrous oxide (N2O). Furthermore, the substrate temperature in the plasma treatment is above room temperature (25°C) and below 450°C.

[0197] Next, layer 29 is formed on insulating layer 20. Figure 9A and Figure 9B Layer 29 is used as a seed or nucleus for the crystal growth of semiconductor layer 30. Therefore, layer 29 can be referred to as a seed layer, seed crystal, etc.

[0198] There are no particular limitations on the method of forming layer 29. For example, insulating layer 29 can be formed by forming and processing the film that will become layer 29. The film can be formed by sputtering, CVD, vacuum evaporation, MBE, PLD or ALD, etc.

[0199] Layer 29 can also be formed using sputtering. By forming layer 29 using sputtering, the crystallinity of layer 29 can be improved. Furthermore, by forming insulating layer 29 using sputtering in an oxygen-containing atmosphere, oxygen can be added to insulating layer 20.

[0200] When a sputtering target has multiple grains with a layered structure and easily cleavable interfaces exist within the grains, ions can collide with the sputtering target, sometimes causing the grains to cleave and resulting in plate-shaped or granular sputtered particles. Plate-shaped or granular sputtered particles deposited on the insulating layer 20 can also be used as layer 29.

[0201] Furthermore, when forming and processing the film that will become layer 29, the processing of the film can be performed using one or both of wet etching and dry etching. Wet etching is more preferred. Compared to dry etching, wet etching sometimes causes less damage. Therefore, damage to the insulating layer 20 can be reduced, and the flatness of the top surface of the insulating layer 20 can be maintained.

[0202] Alternatively, by forming a recess in the insulating layer 20, and after the film that will become layer 29 is embedded in the recess, polishing the film using CMP or the like until the surface of the insulating layer 20 is exposed, a layer can be formed. Figure 6D and Figure 6E Layer 29 or shown Figure 6F Layer 29 is shown. Therefore, the surface on which the semiconductor layer 30 is formed can be flattened.

[0203] As described above, by forming layer 29 before forming semiconductor layer 30, the effect of heat on semiconductor layer 30 can be reduced, thereby suppressing the miniaturization of crystals contained in semiconductor layer 30 and the increase of grain boundaries.

[0204] Next, as Figure 9C and Figure 9D As shown, a semiconductor layer 30 is formed as a capping layer 29. The semiconductor layer 30 is preferably formed using a sputtering method. As the sputtering gas, a rare gas (typically argon) or a single gas of oxygen, or a mixture of a rare gas and oxygen, can be used. The proportion of the rare gas (typically argon) in the total sputtering gas is, for example, 50% or more and 100% or less, preferably 70% or more and 100% or less, more preferably 90% or more and 100% or less. By increasing the proportion of the rare gas (typically argon) in the total sputtering gas, a semiconductor layer 30 with low crystallinity can be formed. Furthermore, a semiconductor layer 30 with many dangling bonds can be formed. Therefore, the etching rate of the semiconductor layer 30 can be increased. Thus, the processing of the semiconductor layer 30 becomes easier, and the productivity of semiconductor devices can be improved. Note that the semiconductor layer 30 with low crystallinity has, for example, an amorphous structure.

[0205] Note that the sputtering gas may also contain hydrogen (H2). By introducing hydrogen during the formation of the semiconductor layer 30 using sputtering, a semiconductor layer 30 with low crystallinity can be formed. Furthermore, during the formation of the semiconductor layer 30, the generation of crystal nuclei can be suppressed or the elimination of crystal nuclei can be promoted. Moreover, when there are many crystal nuclei, the growing crystals collide with each other, thereby suppressing large-size crystals. In other words, small-size crystals are formed. However, by further reducing the number of crystal nuclei by eliminating some of the crystal nuclei in the film while suppressing the generation of crystal nuclei, and performing the first heat treatment described later, crystal growth can be promoted with fewer crystal nuclei, thereby increasing the grain size in the semiconductor layer 30.

[0206] The semiconductor layer 30 can also be formed by sputtering in an oxygen-containing atmosphere. In this case, by using a sputtering method that does not require the use of hydrogen-containing molecules as the deposition gas, the hydrogen concentration in the semiconductor layer 30 can be reduced. For example, oxygen or a mixture of oxygen and rare gases can be used as the sputtering gas.

[0207] Furthermore, the semiconductor layer 30 can also be formed using the ALD method. When forming the semiconductor layer 30, a first precursor and a first oxidant can be used. The first precursor preferably contains indium. At this time, an indium oxide film is formed as the semiconductor layer 30. In other words, an oxide film containing a single element other than oxygen is deposited. Note that when the first precursor contains indium, the ALD method can be a thermal ALD method.

[0208] As precursors containing indium, for example, trimethylindium, triethylindium, ethyl dimethylindium, tris(1-methylethyl)indium, tris(2,2,6,6-tetramethyl-3,5-heptanoic acid)indium, cyclopentadienylindium, iridium(III) acetylacetonate, 3-(dimethylamino)propyl)dimethylindium, (diethylphosphine)dimethylindium, dimethylchloroindium, dimethylbromoindium, dimethyl(2-propanol)indium, etc.

[0209] In addition, inorganic precursors that do not contain hydrocarbons can also be used as indium-containing precursors. Halogenated indium compounds such as indium trifluoride (indium(III) fluoride), indium trichloride (indium(III) chloride), indium tribromide (indium(III) bromide), and indium triiodide (indium(III) iodide) can be used as indium-containing inorganic precursors. The decomposition temperature of indium trichloride is approximately 500°C to 700°C. Therefore, by using indium trichloride, deposition can be performed using the ALD method while heating the substrate to approximately 500°C (between 400°C and 600°C).

[0210] In the method for forming the semiconductor layer 30, it is preferable to use a precursor with low impurity concentration, i.e., high purity. For example, by using a precursor with a purity of 3N (99.9%) or higher, preferably 4N (99.99%) or higher, more preferably 5N (99.999%) or higher, and even more preferably 6N (99.9999%) or higher, impurities in the semiconductor layer 30 can be reduced.

[0211] The gallium and aluminum content of the indium-containing precursor is preferably 1000 ppm or less, more preferably 500 ppm or less, even more preferably 100 ppm or less, further preferably 50 ppm or less, even more preferably 10 ppm or less, and even more preferably 1 ppm or less. By using a precursor with low gallium content, the gallium concentration in the semiconductor layer 30 can be reduced, thereby improving the reliability of the transistor. By using a precursor with low aluminum content, the aluminum concentration in the semiconductor layer 30 can be reduced, thereby improving the crystallinity of the semiconductor layer 30.

[0212] Furthermore, as the precursor used in this embodiment, it is preferable to use a precursor purified by performing two or more distillations (also known as rectification or precision distillation). Using the aforementioned precursor allows for the easy deposition of metal oxides with few impurities, which is therefore preferred. Performing multiple distillations further suppresses the residue of impurities from the starting materials used in the precursor's production, which is also preferred. Note that the present invention is not limited to the above structure; a precursor purified by a single distillation can also be used. Using single distillation reduces manufacturing costs, which is therefore preferred.

[0213] By performing one or more distillations, the aluminum content of the indium-containing precursor can be set to below 100 ppm, below 1 ppm, or below 1 ppb (0.001 ppm). Using this indium-containing precursor, it may be possible to form an indium oxide film with a purity equivalent to that of silicon (10N) used for semiconductor layers.

[0214] As the first oxidant, ozone (O3), oxygen (O2), water (H2O), hydrogen peroxide (H2O2), etc., can be used. The first oxidant preferably includes at least one of ozone and oxygen. By using ozone, oxygen, etc., which do not contain hydrogen, as the first oxidant, the amount of hydrogen mixed into the insulating layer 20 can be reduced. Furthermore, the first oxidant can include at least one of water and hydrogen peroxide. Thus, a semiconductor layer 30 with low crystallinity can be formed.

[0215] In this specification and the like, unless otherwise specified, when ozone, oxygen, and water are used as oxidants, they also include plasma states, free radical states, and ionic states, and are not limited to gaseous states or molecular states.

[0216] The pulse duration for introducing the first oxidant is preferably 0.1 seconds or more and 30 seconds or less, more preferably 0.3 seconds or more and 15 seconds or less, and even more preferably 0.3 seconds or more and 10 seconds or less. By shortening the pulse duration for introducing the first oxidant, the amount of the first oxidant introduced is reduced, and most of the hydrogen contained in the first precursor remains in the membrane. By allowing more hydrogen to remain in the membrane, the formation of crystal nuclei can be suppressed while eliminating some of the crystal nuclei in the membrane, thereby reducing the number of crystal nuclei in the membrane.

[0217] Here, the substrate heating temperature when the first precursor is introduced into the reaction chamber is preferably a temperature corresponding to the decomposition temperature of the first precursor. In the thermal ALD method using triethylindium as the indium-containing precursor, the substrate heating temperature can be, for example, 100°C or higher and 350°C or lower, preferably 150°C or higher and 300°C or lower. When layer 29 is provided, the substrate heating temperature can be room temperature (25°C) or higher and 300°C or lower, preferably room temperature or higher and 200°C or lower, more preferably room temperature or higher and 150°C or lower. By lowering the substrate heating temperature, the crystallinity of the semiconductor layer 30 during deposition can be reduced.

[0218] When the semiconductor layer 30 has a stacked structure, it can be formed, for example, using sputtering and ALD (Alternating Deposition) methods. For instance, when the semiconductor layer 30 has a two-layer structure consisting of a first semiconductor layer and a second semiconductor layer on the first semiconductor layer, the first semiconductor layer can be deposited using ALD, and the second semiconductor layer can be deposited using sputtering. Because ALD offers superior coverage compared to sputtering, depositing the first semiconductor layer using ALD improves the coverage of the semiconductor layer 30. Furthermore, it reduces damage to the substrate (in this case, the insulating layer 20) and suppresses the formation of a mixed layer at the interface between the substrate and the semiconductor layer 30, thereby further improving crystallinity. Additionally, depositing the second semiconductor layer using sputtering increases productivity.

[0219] Alternatively, a first semiconductor layer can be deposited using sputtering, and a second semiconductor layer can be deposited using ALD. Even if pinholes or breaks are formed in the first semiconductor layer deposited using sputtering, the overlapping portions with the aforementioned pinholes or breaks can be filled using a second semiconductor layer deposited using the well-covering ALD method.

[0220] Next, the semiconductor layer 30 is processed into the desired shape. Figure 9E and Figure 9F In this process, the semiconductor layer 30 and the insulating layer 20 are processed into island shapes to form a structure including the semiconductor layer 30 and the insulating layer 20. Specifically, the semiconductor layer 30 and the insulating layer 20 are processed in a manner in which multiple structures are separated in the X and Y directions.

[0221] In addition, such as Figure 9G and Figure 9H As shown, the insulating layer 20 can also be processed such that the portion that does not overlap with the semiconductor layer 30 remains. In this case, it can be said that the insulating layer 20 has a protrusion in the portion that overlaps with the semiconductor layer 30.

[0222] Furthermore, it is preferable to supply the second element (or add or implant the second element) to the semiconductor layer 30 before processing the semiconductor layer 30. This supplies the second element to the semiconductor layer 30. By supplying the second element to the semiconductor layer 30, the crystallinity of the semiconductor layer 30 can be reduced. Therefore, the processing of the semiconductor layer 30 becomes easier, and the productivity of the semiconductor device can be improved.

[0223] As the second element, one or more of hydrogen and rare gases (helium, neon, argon, krypton, xenon, etc.) are preferred.

[0224] Plasma processing can be applied when supplying the second element. The second element can be supplied by generating plasma in a gas atmosphere containing the supplied second element. As an apparatus for generating the plasma, a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, or a high-density plasma CVD apparatus can be used. By accelerating the supply of the second element, the collision energy during the supply of the second element to the semiconductor layer 30 increases, which can more effectively reduce the crystallinity of the semiconductor layer 30, and is therefore preferred.

[0225] Note that the supply of the second element is not limited to the methods described above; for example, ion implantation can also be used. Ion implantation can precisely control the concentration distribution in the depth direction based on the ion acceleration energy and dosage. Furthermore, by using ion implantation to mass-separate the ions by ionizing the source gas, a specific mass of ions can be supplied, and the purity of the supplied second element can be improved. Alternatively, by using ion implantation to supply ions without mass separation, productivity can be improved. In this specification, unless otherwise specified, the presence or absence of mass separation is not limited. Note that sometimes the method of supplying ions by mass separation is called ion implantation, and the method of supplying ions without mass separation is called ion doping.

[0226] As the source gas, a gas containing the second element can be used. When argon is used as the second element, argon gas can be used as the source gas. Furthermore, when argon and hydrogen are used as the second element, a mixture of argon and hydrogen gas can be used as the source gas. Alternatively, a mixture of a gas containing the second element and other gases can also be used. Note that the raw material used to supply the second element is not limited to a gas; it can also be a solid or liquid that has been heated to vaporize it.

[0227] Next, a first heat treatment is performed. The first heat treatment is preferably performed, for example, in an atmosphere containing at least one of hydrogen (H2) and nitrogen (N2), more preferably in an atmosphere containing both hydrogen (H2) and nitrogen (N2). At this time, the hydrogen flow rate ratio is preferably 3% or more and 15% or less, more preferably 5% or more and 10% or less. Note that the hydrogen flow rate ratio refers to the proportion of hydrogen gas flow rate to the total gas flow rate. Furthermore, the temperature of the first heat treatment is preferably 120°C or more and 300°C or less, more preferably 120°C or more and 250°C or less, and even more preferably 120°C or more and 200°C or less. Furthermore, the duration of the first heat treatment is preferably 1 hour or more and 8 hours or less.

[0228] By performing a first heat treatment, using layer 29 as a seed or nucleus, the epitaxial growth and lateral grain growth of semiconductor layer 30 can be advanced, thereby improving the crystallinity of semiconductor layer 30. In particular, using a material with a low coefficient of thermal expansion in insulating layer 20 can promote crystal growth. For example, grains formed in the portion of semiconductor layer 30 overlapping with layer 29 undergo lateral growth, thereby allowing semiconductor layer 30 to crystallize along the formed surface. That is, as... Figure 10A and Figure 10B As shown, using layer 29 as a seed or nucleus, crystallization occurs laterally, causing region 31c to expand. Region 31c is a region with higher crystallinity than region 31a. As the processing time progresses, region 31c further expands along the formed surface. Then, at the end of the first heat treatment, region 31c diffuses into the entire semiconductor layer 30. Figure 10C and Figure 10D This improves the crystallinity of semiconductor layer 30. Thus, indium oxide that improves crystallinity by growing crystals laterally from a crystal nucleus is called Lateral Growth Indium Oxide (LGIO).

[0229] Furthermore, by using silicon oxide, which has a low coefficient of thermal expansion, for the insulating layer 20 and applying tensile stress from the top of the insulating layer 20 to the indium oxide during cooling, the crystal growth of the semiconductor layer 30 can be promoted.

[0230] Next, a second heat treatment is performed. The second heat treatment is preferably performed in an atmosphere containing nitrogen and oxygen (typically, a nitrogen:oxygen volume ratio of 4:1). The temperature of the second heat treatment is preferably higher than that of the first heat treatment. For example, it is preferably 300°C or higher and 400°C or lower, more preferably 300°C or higher and 350°C or lower. Furthermore, the duration of the second heat treatment is preferably 1 hour or more and 4 hours or less.

[0231] The gas used for the second heating process is preferably highly purified. By using a highly purified gas for heating, the absorption of moisture and other substances by the semiconductor layer 30 can be minimized.

[0232] There are no particular restrictions on the heating treatment used for the second heating treatment; for example, an electric furnace or an RTA device can be used.

[0233] By performing the first heat treatment at a temperature lower than that of the second heat treatment, the generation of crystal nuclei can be suppressed, and the crystals can be made larger in size. Furthermore, since the first heat treatment is performed in a reducing atmosphere, the amount of oxygen vacancies contained in the semiconductor layer 30 increases. Therefore, by performing the second heat treatment, oxygen can be supplied to the semiconductor layer 30, and the supplied oxygen can fill the oxygen vacancies (making them null). Furthermore, by performing the first heat treatment at a temperature lower than that of the second heat treatment, impurities sometimes remain in the semiconductor layer 30. Therefore, by performing the second heat treatment at a temperature higher than that of the first heat treatment, the impurity concentration in the semiconductor layer 30 can be reduced. Furthermore, the hydrogen concentration in the semiconductor layer 30 can be reduced. Moreover, by performing the second heat treatment, the grains in the semiconductor layer 30 can be made larger.

[0234] As described above, by sequentially performing the first heating treatment and the second heating treatment, the amount of oxygen vacancies and impurities in the semiconductor layer 30 can be reduced while the semiconductor layer 30 is crystallizing and growing.

[0235] Alternatively, microwave plasma treatment can be performed after depositing the semiconductor layer 30. This microwave plasma treatment can reduce the concentration of impurities such as hydrogen or water contained in the semiconductor layer 30. Furthermore, sometimes crystalline regions of the semiconductor layer 30 are grown.

[0236] In this specification and the like, microwaves refer to electromagnetic waves with frequencies of 300 MHz or higher and 300 GHz or lower. Microwave plasma treatment, for example, refers to a process using a device that includes a power source for generating high-density plasma using microwaves. Microwave plasma treatment may also be referred to as microwave-excited high-density plasma treatment.

[0237] By performing microwave plasma treatment in an oxygen-containing atmosphere, the impurity concentration in the semiconductor layer 30 can be reduced. Carbon is an example of an impurity. Note that the above describes a structure in which the semiconductor layer 30 is subjected to microwave plasma treatment in an oxygen-containing atmosphere, but the method is not limited thereto. For example, an insulating film disposed near the semiconductor layer 30, more specifically, a silicon oxide film, can also be subjected to microwave plasma treatment in an oxygen-containing atmosphere. Furthermore, due to the heat generated during microwave plasma treatment, the crystallinity of the semiconductor layer 30 is sometimes improved.

[0238] Microwave plasma treatment is preferably carried out under reduced pressure, preferably 10 Pa or more and 1000 Pa or less, more preferably 50 Pa or more and 700 Pa or less, and even more preferably 100 Pa or more and 400 Pa or less. Furthermore, the treatment temperature is preferably room temperature (25°C) or more and 750°C or less, more preferably 300°C or more and 500°C or less, and can be 400°C or more and 450°C or less.

[0239] During microwave plasma treatment, the substrate can also be heated. The heating temperature of the substrate is preferably above room temperature (e.g., 25°C), above 100°C, above 200°C, above 300°C, or above 400°C and below 500°C, or below 450°C. For example, the heating temperature of the substrate is preferably above room temperature and below 500°C, more preferably above 100°C and below 450°C, even more preferably above 200°C and below 450°C, even more preferably above 300°C and below 450°C, and still even more preferably above 400°C and below 450°C.

[0240] For example, oxygen and argon gases can be used for microwave plasma treatment. However, when the oxygen flow ratio (O2 / (O2+Ar)) in microwave plasma treatment is too high, stable discharge is difficult to achieve. Therefore, for example, the oxygen flow ratio (O2 / (O2+Ar)) is preferably greater than 0% and less than 50%, more preferably greater than 0% and less than 40%, and even more preferably greater than 0% and less than 30%.

[0241] In microwave plasma processing using oxygen and argon gases, the main oxygen free radicals can be triplet oxygen (O(2,2-O2)2-O2). 3 P j )), singlet oxygen (O( 1 D2)) and oxygen ions (O2) + The three states of oxygen free radicals are as follows. Furthermore, oxygen ions play an effective role in reducing the hydrogen concentration in the oxide film through microwave plasma treatment. Moreover, the amount of oxygen free radicals in each state varies depending on the oxygen flow rate ratio or pressure during microwave plasma treatment. For example, under conditions of low oxygen flow rate ratio and low pressure, there is a tendency for the amount of oxygen ions to increase. On the other hand, when the oxygen flow rate ratio or pressure is too low, there are concerns such as: unstable control of the oxygen flow rate makes it difficult to stabilize the discharge; and etching of the oxide film, etc. Therefore, for example, the oxygen flow rate ratio (O2 / (O2+Ar)) during microwave plasma treatment is preferably greater than 0% and less than 10%, more preferably more than 0.5% and less than 5%, further preferably more than 0.5% and less than 3%, and typically preferably 1%.

[0242] The shorter the processing time of microwave plasma treatment, the higher the productivity. Therefore, for example, the processing time of microwave plasma treatment is preferably more than 1 minute and less than 60 minutes, more preferably more than 1 minute and less than 30 minutes, and even more preferably more than 1 minute and less than 10 minutes.

[0243] By performing microwave plasma treatment in an oxygen-containing atmosphere, oxygen gas can be plasmaized using microwaves or high frequencies such as RF, and the oxygen free radicals generated by this plasmaization can act on the oxide semiconductor layer. Due to the effects of plasma, microwaves, and oxygen free radicals, hydrogen can be removed from the oxide semiconductor layer. This reduces the hydrogen concentration in the oxide semiconductor layer. Sometimes, carbon bonded to oxygen or hydrogen can also be removed. Thus, microwave plasma treatment reduces impurities. Furthermore, by supplying the aforementioned oxygen free radicals to oxygen vacancies formed in the oxide semiconductor layer, the number of oxygen vacancies in the oxide semiconductor layer can be further reduced.

[0244] Furthermore, when some of the oxygen in the oxide semiconductor present before microwave plasma treatment reacts with hydrogen in the oxide semiconductor, i.e., when the reaction "2H + O → H₂O↑" occurs, this hydrogen can be removed as H₂O (also known as dehydration or dehydrogenation). Since H₂O is one of the main factors hindering the improvement of crystallinity, it is preferable to remove H₂O from the oxide semiconductor. Removing hydrogen from the oxide semiconductor as H₂O reduces the hydrogen concentration in the oxide semiconductor, thereby promoting improved crystallinity. Furthermore, by increasing the temperature in the microwave plasma treatment, the hydrogen concentration in the oxide semiconductor can be further reduced.

[0245] Alternatively, the heating process can be performed continuously after microwave plasma treatment without exposure to the atmosphere. The heating temperature is preferably 100°C or higher and 750°C or lower, more preferably 300°C or higher and 500°C or lower, and even more preferably 400°C or higher and 450°C or lower. By keeping the temperature within the above range, substrate deformation (strain or warping) can be minimized even when this heating process is performed.

[0246] Note that plasma treatment containing oxygen gas can also be used instead of microwave plasma treatment to improve crystallinity.

[0247] The oxygen supplied to the oxide semiconductor layer can take various forms, such as oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or oxygen molecules), and oxygen free radicals (oxygen atoms, oxygen molecules, or oxygen ions containing unpaired electrons). Furthermore, the oxygen implanted into the oxide semiconductor layer is preferably one or more of the aforementioned forms, and particularly preferably oxygen free radicals.

[0248] Alternatively, a hydrogen supply process (also known as hydrogenation) can be performed on the semiconductor layer 30 before the insulating layer 50 is formed. By supplying hydrogen to the semiconductor layer 30, dangling bonds present at grain boundaries or the like can sometimes be terminated, thereby improving the electrical characteristics and reliability of the transistor. Other examples of hydrogen supply processes include heating in a hydrogen-containing atmosphere or plasma treatment.

[0249] Next, an insulating layer 80 is formed to cover the semiconductor layer 30, and an opening 89 is formed in the insulating layer 80 that overlaps with a portion of the semiconductor layer 30. As described above, it is preferable to form the opening 89 at a location that does not overlap with the layer 29.

[0250] Next, an insulating layer 50 is formed to cover the opening 89. The insulating layer 50 is preferably formed by an ALD (Alternating Discharge) method. When forming the insulating layer 50, a second precursor and a second oxidant can be used. The second precursor preferably contains one of aluminum and hafnium. At this time, an alumina film or a hafnium oxide film is formed as the insulating layer 50. In other words, an oxide film containing a single element other than oxygen is deposited. Note that when the second precursor contains one of aluminum and hafnium, a thermal ALD method can be used as the ALD method.

[0251] As aluminum-containing precursors, aluminum chloride or trimethylaluminum can be used, for example. As hafnium-containing precursors, hafnium tetrachloride, tetra(ethylmethylamide)hafnium (TEMAHf) can be used, for example.

[0252] The second oxidizing agent can be any of the materials described above that can be used with the first oxidizing agent. The first and second oxidizing agents can be the same or different oxidizing agents.

[0253] In the ALD process, a precursor is introduced into the chamber and adsorbed onto the substrate surface. Here, because the precursor adheres to the substrate surface, the self-limiting mechanism of the surface chemical reaction is activated, preventing further adhesion of the precursor to the substrate's precursor layer. Note that the appropriate range of substrate temperature that enables the self-limiting mechanism of the surface chemical reaction is called the ALD window. The ALD window is determined based on the temperature characteristics, vapor pressure, and decomposition temperature of the precursor. In other words, the ALD window varies depending on the precursor. Therefore, when depositing oxide films containing multiple elements besides oxygen, the ALD window of each precursor must be considered to adjust the deposition conditions. On the other hand, when depositing oxide films such as indium oxide or alumina films containing only a single element besides oxygen, the ALD window of only one precursor can be considered to adjust the deposition conditions, making it easier to adjust the deposition conditions and thus depositing high-quality oxide films.

[0254] Preferably, microwave plasma treatment is performed after the deposition of the insulating layer 50. This microwave plasma treatment can reduce the concentration of impurities such as hydrogen or water contained in the semiconductor layer 30. Details of the microwave plasma treatment can be found in the above description.

[0255] Next, a conductive layer 60 is formed on the insulating layer 50 such that the opening 89 is embedded. As described above, it is possible to manufacture... Figures 1A to 1F The semiconductor device shown.

[0256] In addition, such as Figure 8B As shown, when conductive layers 40a and 40b are provided on the semiconductor layer 30, after forming the crystalline semiconductor layer 30, conductive layers that will become conductive layers 40a and 40b are formed on the semiconductor layer 30. An insulating layer 80 is formed on this conductive layer, and an opening 89 is formed in the insulating layer 80 to remove the portion of the conductive layer that overlaps with the opening 89. Thus, conductive layers 40a and 40b are formed using this conductive layer.

[0257] In addition, Figures 1A to 1F In this process, layer 29 and the semiconductor layer 30 near layer 29 remain intact. This reduces the number of manufacturing steps in the semiconductor device. Note that the invention is not limited thereto. For example, layer 29 and the semiconductor layer 30 near layer 29 can also be removed.

[0258] Note that when forming the semiconductor layer 30 using the ALD method, it is sometimes possible to form a crystalline semiconductor layer 30 using layer 29 as a seed or nucleus during the formation of the semiconductor layer 30. For example, by setting the substrate heating temperature during ALD deposition within the range of 100°C to 300°C or 150°C to 250°C, a crystalline semiconductor layer 30 can be formed during deposition. In this case, the heating treatment for crystal growth of the semiconductor layer 30 may not be performed. Note that if the substrate heating temperature is too high, crystal nuclei may form, hindering large grain formation. On the other hand, if the substrate heating temperature is too low, crystal growth may not occur during the formation of the semiconductor layer 30. Figure 11A and Figure 11B Shown in reference Figure 9C and Figure 9D The semiconductor layer 30 is formed in the process described. Figure 10C and 10D The structure of the crystalline semiconductor layer 30 is shown. Note that... Figure 11A and Figure 11B The case of using layer 29, which has a region extending in the X direction, is shown.

[0259] Furthermore, when a crystalline semiconductor layer 30 can be formed during the formation of the semiconductor layer 30, at least one of the above-described first heat treatment, second heat treatment, microwave plasma treatment, and hydrogenation treatment can be performed. This can sometimes further improve the crystallinity of the semiconductor layer 30.

[0260] Furthermore, if a crystalline semiconductor layer 30 can be formed during the formation of the semiconductor layer 30, layer 29 can be removed in a subsequent process. For example, as... Figure 11C and Figure 11D As shown, layer 29 can be removed while the semiconductor layer 30 and insulating layer 20 are processed into an island shape. Thus, a semiconductor layer 30 with a flat top surface can be formed.

[0261] Furthermore, when a crystalline semiconductor layer 30 can be formed during the formation of the semiconductor layer 30, the semiconductor layer 30 can be processed into a desired shape after the layer is formed on the semiconductor layer 30. For example, as... Figures 11E to 11H As shown, layer 35 can be formed on semiconductor layer 30, and layer 29 can be removed while processing layer 35, semiconductor layer 30, and insulating layer 20 into an island shape. Note that layer 35 can have a single-layer structure or a stacked structure of two or more layers. Furthermore, when layer 35 has a stacked structure, a stacked structure of the same material can be used, or a stacked structure of different materials can be used. Note that different materials include the use of two or more materials selected from semiconductor materials, insulating materials, and conductive materials.

[0262] <Example 2 of Semiconductor Device Manufacturing Methods> The following describes an example of a semiconductor device manufacturing method that differs in some aspects from the semiconductor layer manufacturing method described above. Note that, to avoid repetition, descriptions of the parts identical to the manufacturing method described above are omitted; only the differences are explained in detail. Note that, unless otherwise specified, the omitted parts can be referred to in the description of Example 1 of the semiconductor device manufacturing method above.

[0263] In the example of a semiconductor device manufacturing method shown below, a layer 29 that will serve as a nucleus can be formed using one of the grains contained in a polycrystalline film. More specifically, layer 29 is formed by selecting one of a plurality of grains contained in the polycrystalline film and removing the other unused grains by etching. Figures 12A to 12E and Figure 12G These are three-dimensional schematic diagrams of each stage of the manufacturing method example shown below.

[0264] First, an insulating layer 20 is formed on a substrate 10 (not shown), and a film 29f is formed on the insulating layer 20. Then, a resist mask 25 is formed to cover the film 29f. Figure 12A ).

[0265] Film 29f is a portion of which later becomes layer 29. Film 29f has a polycrystalline structure. Film 29f includes multiple grains 29a and grain boundaries 29b between two grains 29a. Figure 12A Different shaded lines are added to represent different grains 29a. In addition, grain boundaries 29b are represented by dashed lines.

[0266] As the photoresist mask 25, a so-called negative photosensitive resin with reduced solubility of the photosensitive portion is preferably used. Furthermore, the photoresist mask 25 preferably has a specific wavelength region with no sensitivity. In particular, it is preferable to have no sensitivity to the wavelength regions of visible light or X-rays.

[0267] Next, the film 29f is observed through the resist mask 25, and one grain 29a that meets the requirements from among a plurality of grains 29a within a specified range of the film 29f is selected and its coordinates are specified. Examples of such requirements include size, shape, and position. Preferably, it has at least the following shape: a shape that can accommodate the smallest irradiation area of ​​the exposure apparatus used in subsequent exposure processes. In this case, if the resist mask 25 has no sensitivity to the wavelength region of visible light (i.e., it is transparent), an observation method using visible light can be used.

[0268] The extraction and coordinate assignment of grain 29a are preferably performed using an optical microscope utilizing visible light. Note that images captured by a camera mounted on the optical microscope, rather than through visual inspection, allow for image analysis to automatically extract the grain 29a that meets the requirements, making this preferred method. As for image analysis, in addition to pattern matching, analysis methods utilizing AI (artificial intelligence) can also be used.

[0269] To clearly show the shape of grain 29a, a portion of the grain boundary can be etched by wet etching. Furthermore, the shape of grain 29a can also be clearly defined by utilizing the difference in etching rate caused by differences in crystal orientation, resulting in height non-uniformity among multiple grains 29a. For example, when using metal oxide films such as indium oxide or IGZO for film 29f, a developer, an aqueous solution of tetramethylammonium hydroxide (TMAH), dilute hydrofluoric acid, oxalic acid, phosphoric acid, acetic acid, nitric acid, or a mixture containing two or more of these is preferably used. As the etching solution, acidic or alkaline solutions can be used. Furthermore, by using an aqueous solution diluted with the above-mentioned solution, the etching rate can be reduced, thus preventing the target grain from disappearing.

[0270] Furthermore, the crystal orientation of grain 29a can also be determined by XRD analysis using X-rays in addition to the optical microscope described above. When multiple island-shaped semiconductor layers 30 are formed in the substrate, by making the crystal orientations of the individual seed grains 29a close to each other, the crystal orientations of the individual semiconductor layers 30 can be made closer together, which can sometimes reduce the inhomogeneity of the electrical characteristics of transistors caused by non-uniform crystal orientation. Note that when the crystal orientation can be estimated using the above-described AI, XRD analysis may not be necessary.

[0271] Next, exposure and development processes are performed. Light 27 is irradiated onto the region inside the designated grain 29a, causing the upper portion of the resist mask 25 located in that region to be photosensitive. Figure 12B Then, by performing a development process, a resist mask 25m is formed on the specified grain 29a. Figure 12C Light 27 is light in a wavelength range that the resist mask 25 is sensitive to, for example, light in the wavelength range of visible light or ultraviolet light can be used. In this case, the irradiated area of ​​light 27 preferably does not include grain boundaries 29b. Because grain boundaries 29b are areas with many defects, avoiding grain boundaries 29b can prevent the subsequently formed layer 29 from containing defects.

[0272] Next, by etching away the portion of film 29f not covered by the resist mask 25m, island layers 29 can be formed. Figure 12D The layer 29 thus formed is part of grain 29a, and therefore has a single-crystal structure. Etching can be performed using either dry etching or wet etching.

[0273] Subsequently, similarly as described above, a single-crystal semiconductor layer 30 can be formed by forming a semiconductor layer 30 in the manner of a capping layer 29. Figure 12E ). Figure 12F It includes Figure 12E A cross-sectional schematic diagram of the region of layer 29.

[0274] Here, semiconductor layer 30 and layer 29 preferably use the same metal oxide. This allows for homoepitaxial growth of semiconductor layer 30 using layer 29 as a seed or nucleus. In this case, the crystal orientation of layer 29 is consistent with the crystal orientation of semiconductor layer 30.

[0275] Then, an island-shaped semiconductor layer 30 can also be formed by etching away a portion of the semiconductor layer 30. Figure 12G ). Figure 12G This illustrates the case where layer 29 is also removed by etching.

[0276] A single-crystal semiconductor layer 30 can be formed in this way. By using the semiconductor layer 30 formed as described above, transistors with both high on-state current and high reliability can be manufactured.

[0277] Alternatively, a single-crystal semiconductor film can be formed by using the single-crystal semiconductor layer 30 formed as described above as a seed crystal to cover the semiconductor layer 30. For example, if layer 29 contains an element different from that of semiconductor layer 30, that element may diffuse into semiconductor layer 30 as an impurity. Therefore, by using a portion of the region of semiconductor layer 30 away from layer 29 as a seed crystal and crystallizing it into a semiconductor film with the same composition as semiconductor layer 30, a single-crystal semiconductor film with low impurity concentration and high purity can be obtained.

[0278] <Example 3 of Semiconductor Device Manufacturing Methods> While the above describes a method for manufacturing a crystalline semiconductor layer 30 by forming a semiconductor layer 30 on the layer 29 that will serve as the nucleus, the method is not limited thereto. An example of forming the layer 29 that will serve as the nucleus on the semiconductor layer 30 is described below.

[0279] First, a semiconductor layer 30a is formed on the insulating layer 20. Figure 13A The semiconductor layer 30a is a film with low crystallinity, such as an amorphous film or a microcrystalline film. For example, by forming the semiconductor layer 30a under conditions of low substrate temperature during deposition (e.g., below 150°C, below 100°C, below 50°C, or room temperature), a film with low crystallinity can be deposited. Furthermore, when the semiconductor layer 30a is formed using a sputtering method, by using a gas with a low proportion of oxygen (e.g., 5% or less, preferably 0%) as the deposition gas during deposition, crystallization during deposition can be suppressed, thereby allowing the deposition of a semiconductor layer 30a with low crystallinity.

[0280] Next, an island layer 29 is formed on the semiconductor layer 30a. Figure 13B Layer 29 has a single-crystal structure. Note that in... Figure 13B In the middle, the outline shape of layer 29 when viewed from the plane is hexagonal, but it is not limited to this. It can also be any shape other than hexagon, such as polygon, circle or ellipse.

[0281] The method for forming layer 29 is as follows: for example, a polycrystalline film is formed by the method shown in Example 2 of the above manufacturing method, and then a portion of a specified grain is left, while the other portion is removed by etching.

[0282] When forming a polycrystalline film as layer 29, deposition is preferably performed at a substrate temperature that is as low as possible (e.g., below 150°C, preferably below 100°C). This prevents the semiconductor layer 30a from crystallizing and forming a polycrystalline layer during the deposition of layer 29. When layer 29 is formed using a sputtering method, by using a gas with a high proportion of oxygen (e.g., 10% or more, preferably 20% or more, more preferably 30% or more) as the deposition gas, layer 29 with higher crystallinity than semiconductor layer 30a can be formed.

[0283] Furthermore, etching is preferably performed using methods that minimize the application of heat. For example, by using a wet etching method to etch the film, not only can the process be carried out at low temperatures, but etching damage can also be suppressed, thereby forming a layer 29 with fewer defects.

[0284] Alternatively, layer 29 can be formed by sputtering using a masking method such as a metal mask. This allows island-shaped layers 29 to be formed at desired locations. By employing this method, the film processing steps can be omitted, thus simplifying the process. In this case, by using a polycrystalline sputtering target, microparticles (also called particles) with a single-crystal structure reflecting the crystal structure of the sputtering target can be attached to specific locations on the semiconductor layer 30a, and these microparticles can also be used as layer 29.

[0285] Next, by performing a heat treatment, using layer 29 as a seed crystal, semiconductor layer 30a is crystallized, thereby obtaining single-crystal semiconductor layer 30. Figure 13C As a method of heat treatment, refer to the description of the first heat treatment above.

[0286] Then, the unwanted portions of semiconductor layer 30 and layer 29 are removed by etching to obtain island-shaped semiconductor layer 30. Figure 13D Note that layer 29 may not be removed.

[0287] This allows the formation of a single-crystal semiconductor layer 30. By using the semiconductor layer 30 formed as described above, transistors with both high on-state current and high reliability can be manufactured.

[0288] [Application Examples] By using a method for forming a metal oxide layer according to one aspect of the present invention, a large-area semiconductor layer 30 can be formed. Therefore, transistors using the semiconductor layer 30 and semiconductor chips using the transistors can be mass-produced with high yield. Reference is made below. Figures 14A to 14D This describes the manufacturing method of semiconductor chip 81.

[0289] Figure 14A A three-dimensional schematic diagram of substrate 70 is shown. (As shown) Figure 14A As shown, a layer 29 is formed near the outer periphery of the substrate 70, and then a semiconductor layer 30 is formed over the entire surface of the substrate 70 as a capping layer 29. Thus, as... Figure 14B As shown, layer 29 can be used as a seed crystal for crystal growth to form a single-crystal or polycrystalline semiconductor layer 30 with a uniform crystal orientation across the entire surface of the substrate 70. More specifically, the crystal orientation of layer 29 is... <001> In this case, crystal orientation can be formed. <111> A crystalline semiconductor layer 30 is perpendicular to the top surface of the substrate 70. Figure 14BIn the diagram, the dividing line 85 is shown as a dashed line. Layer 29 is preferably positioned at a location overlapping the dividing line 85.

[0290] Silicon wafers can typically be used as the substrate 70. In addition, insulating substrates such as glass substrates, quartz substrates, sapphire substrates, and yttrium-stabilized zirconia substrates (yttrium-stabilized zirconia substrates), as well as semiconductor substrates such as germanium substrates, silicon carbide substrates, silicon-germanium substrates, gallium arsenide substrates, indium phosphide substrates, zinc oxide substrates, and gallium oxide substrates can be used. The substrate 70 can, for example, be a substrate with a diameter of 3 inches, 5 inches, 8 inches, or 12 inches. In particular, even when using a large substrate such as a 12-inch substrate, a semiconductor layer 30 with good crystallinity can be obtained, thereby improving productivity.

[0291] Then, by forming transistors having a semiconductor layer 30, wiring, electrodes, etc., multiple semiconductor chips 81 can be formed. Next, as... Figure 14D As shown, multiple semiconductor chips 81 can be separated by dividing the substrate 70, on which semiconductor chips 81 are formed, along the dividing line 85. At this time, by placing the layer 29 at a position overlapping with the dividing line 85, a structure in which the layer 29 is not left inside the semiconductor chip 81 can be achieved.

[0292] Furthermore, layer 29 can also be located outside the dividing line 85. Moreover, layer 29 is not limited to one; two or more layers can be provided. For example, multiple layers 29 can be provided at equal intervals and configured to overlap with the dividing line 85 respectively.

[0293] Figure 14C Show Figure 14B This is a cross-sectional schematic diagram showing the stages of forming the semiconductor layer 30. A layer 29 is disposed at a position overlapping the dividing line 85, and the semiconductor layer 30 is formed as a cover layer 29. The semiconductor layer 30 is formed along the side and bottom surfaces of the opening 91 provided in the insulating layer 20. Furthermore, the semiconductor layer 30 also covers the structure 83 formed on the insulating layer 20. Thus, even if the semiconductor layer 30 is disposed in a manner that covers the uneven shape of the substrate 70, a single-crystal or polycrystalline film with consistent crystal orientation as described above can be formed.

[0294] Examples of structures 83 include wiring, electrodes, or protrusions in the insulating layer 20. Furthermore, structure 83 may also be a component of a transistor having a structure different from that of the transistor disposed in the opening 91.

[0295] This embodiment can be appropriately combined with other embodiments or examples. Furthermore, where multiple structural examples are shown in one embodiment in this specification, these structural examples can be appropriately combined.

[0296] Implementation Method 2 In this embodiment, a semiconductor device using the structure described in Embodiment 1 will be described.

[0297] <Example 1 of semiconductor device structure> Reference Figures 15A to 26D An example of the structure of a semiconductor device according to one aspect of the present invention is provided.

[0298] Figure 15A It is a plan view of a semiconductor device including transistor 200. Figure 15B It is along Figure 15A The section shown by the dotted lines A1-A2 is a cross-sectional view of the part, and is a cross-sectional view along the channel length of transistor 200. Figure 15C It is along Figure 15A The section shown by the dotted lines A3-A4 is a cross-sectional view of the transistor 200 in the channel width direction. Figure 15D It is along Figure 15A The cross-sectional view of the dashed section in A5-A6 format. Figure 15A In the plan view, some constituent elements are omitted for clarity. Sometimes, some constituent elements are also omitted in subsequent plan views.

[0299] Transistor 200 includes a conductive layer 205, an insulating layer 221 on the conductive layer 205, an insulating layer 222 on the insulating layer 221, an insulating layer 224 on the insulating layer 222, a layer 229 on the insulating layer 224, a semiconductor layer 230 on the capping layer 229, conductive layers 242a and 242b on the semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.

[0300] Insulating layer 224, semiconductor layer 230, layer 229, insulating layer 250, and conductive layer 260 correspond to insulating layer 20, semiconductor layer 30, layer 29, insulating layer 50, and conductive layer 60 as described in Embodiment 1, respectively. Therefore, the structure (material, thickness, etc.) and formation method of insulating layer 224, semiconductor layer 230, layer 229, insulating layer 250, and conductive layer 260 can be referred to the structure and formation method of insulating layer 20, semiconductor layer 30, layer 29, insulating layer 50, and conductive layer 60 as described in Embodiment 1. Furthermore, conductive layer 205 corresponds to conductive layer 15 as described in Embodiment 1. Furthermore, conductive layers 242a and 242b correspond to conductive layers 40a and 40b as described in Embodiment 1, respectively.

[0301] In transistor 200, conductive layer 260 is used as the first gate electrode (also referred to as the upper gate electrode or top gate electrode), and insulating layer 250 is used as the first gate insulating layer. Furthermore, conductive layer 205 is used as the second gate electrode (also referred to as the lower gate electrode or bottom gate electrode), and insulating layers 224, 222, and 221 are all used as second gate insulating layers. Additionally, conductive layer 242a is used as one of the source and drain electrodes, and conductive layer 242b is used as the other of the source and drain electrodes.

[0302] An insulating layer 275 is provided on conductive layers 242a and 242b, and an insulating layer 280 is provided on the insulating layer 275. An opening 289 is formed in the insulating layers 280 and 275, reaching the insulating layer 222 and the semiconductor layer 230. This opening 289 overlaps with the area between the conductive layers 242a and 242b. When viewed in plan view, the side surface of the insulating layer 280 in the opening 289 is consistent with or substantially consistent with the side surface of the conductive layers 242a and 242b. The insulating layer 280 corresponds to the insulating layer 80 described in Embodiment 1.

[0303] Insulating layer 250 and conductive layer 260 are disposed inside opening 289. Furthermore, insulating layer 282 is disposed in contact with the top surface of insulating layer 280, the upper end of insulating layer 250, and the top surface of conductive layer 260. Furthermore, insulating layer 283 is disposed on insulating layer 282. Furthermore, insulating layer 216 is disposed below insulating layer 221, insulating layer 214 is disposed below insulating layer 216 and conductive layer 205, and insulating layer 212 is disposed below insulating layer 214. Insulating layer 212 is disposed on a substrate (not shown). This substrate corresponds to substrate 10 described in Embodiment 1. Insulating layers 212, 214, 280, 282, 283, and 285 are used as interlayer films.

[0304] An opening is formed in insulating layers 285, 283, 282, 280, and 275 to reach conductive layer 242a. Conductive layer 243a and insulating layer 241a are disposed within this opening. Insulating layer 241a is disposed in contact with the sidewall of this opening, and conductive layer 243a is disposed inside insulating layer 241a. Similarly, an opening is formed in insulating layers 285, 283, 282, 280, and 275 to reach conductive layer 242b. Conductive layer 243b and insulating layer 241b are disposed within this opening. Insulating layer 241b is disposed in contact with the sidewall of this opening, and conductive layer 243b is disposed inside insulating layer 241b. Conductive layers 243a and 243b are used as vias to connect wiring or other components disposed on transistor 200 to the source or drain of transistor 200.

[0305] The semiconductor layer 230 contains a channel forming region for the transistor 200, as well as a source region and a drain region disposed in a manner that clamps the channel forming region. That is, the semiconductor layer 230 includes a channel forming region, a source region, and a drain region. At least a portion of the channel forming region overlaps with the conductive layer 260. The source region overlaps with the conductive layer 242a, and the drain region overlaps with the conductive layer 242b. Note that the source and drain regions can also be interchanged. The source and drain regions are n-type regions (low-resistance regions) with a higher carrier concentration than the channel forming region. The semiconductor layer 230 can have a single-layer structure or a stacked structure of two or more layers.

[0306] Between adjacent transistors 200 along the channel length, the semiconductor layer 230 is physically separated. This structure prevents the row hammer effect and the passing gate effect when the transistors 200 are used in memory cells. Note that the row hammer effect refers to the phenomenon where, in a structure where the word lines (conductive layers 260) of two transistors are adjacent and the channel formation regions of the two transistors are connected, stored charge leaks to the adjacent word lines, causing malfunctions. The passing gate effect refers to the phenomenon where charge transfers to the floating gate or gate insulating layer, thereby creating unintended current paths or causing characteristic changes such as threshold fluctuations.

[0307] exist Figures 15A to 15D In the semiconductor device shown, the opening where the conductive layer 243a is provided is positioned where it does not overlap with layer 229. Furthermore, when viewed in plan view, the conductive layer 243a is positioned between layer 229 and conductive layer 260. By employing this structure, the opening can have a favorable shape. Therefore, poor contact can be suppressed, thereby providing a highly reliable semiconductor device.

[0308] Although Figure 15A and Figure 15B The illustration shows an example where layer 229 is located on a straight line connecting conductive layers 243a and 243b, but the invention is not limited to this structure. For example, as... Figures 16A to 16D As shown, layer 229 may not be located on the straight line connecting conductive layers 243a and 243b. This structure can also suppress poor contact, thereby providing a highly reliable semiconductor device. Note that... Figures 16A to 16D These are plan and cross-sectional views of a semiconductor device including transistor 200, respectively corresponding to... Figures 15A to 15D The plan view and cross-sectional view are shown.

[0309] Although Figure 15A and Figure 15BThe illustration shows an example where the opening of the conductive layer 243a is located in a position that does not overlap with layer 229, but the invention is not limited to this structure. For example, as... Figures 17A to 17D As shown, the opening where the conductive layer 243a is disposed can also be formed with a portion overlapping layer 229. By employing this structure, miniaturization and high integration of semiconductor devices can be achieved. Note that... Figures 17A to 17D These are plan and cross-sectional views of a semiconductor device including transistor 200, respectively corresponding to... Figures 15A to 15D The plan view and cross-sectional view are shown.

[0310] Figures 18 to 19C Show Figures 17A to 17D A magnified cross-sectional view of the transistor 200 along its channel length.

[0311] By performing heat treatment with an insulating layer containing excess oxygen near the oxide semiconductor layer, oxygen can be supplied from the insulating layer to the oxide semiconductor layer, reducing oxygen vacancies. Note that supplying excessive oxygen to the source or drain region may cause a decrease in the on-state current or field-effect mobility of the transistor 200. Furthermore, when the amount of oxygen supplied to the source or drain region is uneven within the substrate surface, the characteristics of the semiconductor device, including the transistor, become uneven. In addition, excessive oxygen supplied from the insulating layer to the oxide semiconductor layer can sometimes negatively impact the electrical characteristics and reliability of the transistor. Moreover, there is the concern that oxygen diffuses into the conductive layers such as the gate, source, and drain electrodes, causing oxidation and a decrease in conductivity.

[0312] Firstly, preferably, at least one of an insulating layer that blocks hydrogen and an insulating layer that traps or fixes hydrogen is formed near the semiconductor layer 230 to reduce the hydrogen concentration in and around the channel formation region of the semiconductor layer 230.

[0313] At least one of insulating layers 212, 214, 221, 222, 275, 282, and 283 is preferably used as a hydrogen barrier insulating layer. Furthermore, at least one of insulating layers 212, 214, 221, 222, 275, 282, and 283 is preferably used as an impurity barrier insulating layer. Additionally, at least one of insulating layers 212, 214, 221, 222, 275, 282, and 283 is preferably used as an oxygen barrier insulating layer. Note that it is not necessary to provide all of insulating layers 212, 214, 221, 222, 275, 282, and 283. As long as it provides sufficient barrier properties against hydrogen, impurities, oxygen, etc., it can be formed by appropriately selecting from insulating layer 212, insulating layer 214, insulating layer 221, insulating layer 222, insulating layer 275, insulating layer 282, and insulating layer 283. For example, it is also possible to form an insulating layer 216 and conductive layer 205 by not providing insulating layer 214, but by having them in contact with the top surface of insulating layer 212.

[0314] Insulating layers 212, 221, 275, and 283 preferably have the function of suppressing hydrogen diffusion. For example, insulating layers 212, 221, 275, and 283 can be made of silicon nitride, which has higher hydrogen barrier properties.

[0315] Insulating layers 214, 222, and 282 preferably have the function of trapping or fixing hydrogen. For example, aluminum oxide can be used as insulating layers 214 and 282. For example, hafnium oxide, which is a material with a high relative permittivity (high-k), is preferably used as insulating layer 222, which is used as the second gate insulating layer.

[0316] like Figure 18 As shown, by providing an insulating layer 212 that has the function of suppressing hydrogen diffusion under the transistor 200, hydrogen diffusion from the lower layer of the transistor 200 can be suppressed. Furthermore, by providing an insulating layer 214 that has the function of trapping or fixing hydrogen, the insulating layer 214 can trap or fix the hydrogen contained in the insulating layer 216, etc. Thus, the hydrogen concentration in and around the semiconductor layer 230 can be reduced.

[0317] Furthermore, by providing an insulating layer 221 that has the function of suppressing hydrogen diffusion under the semiconductor layer 230, hydrogen diffusion from below the semiconductor layer 230 can be suppressed. Furthermore, by providing an insulating layer 222 that has the function of trapping or fixing hydrogen, the insulating layer 222 can trap or fix the hydrogen contained in the insulating layer 224, etc. Thus, the hydrogen concentration in and around the semiconductor layer 230 can be reduced.

[0318] Furthermore, by providing an insulating layer 275 that has the function of suppressing hydrogen diffusion in a manner that covers the semiconductor layer 230, conductive layer 242a, conductive layer 242b, etc., hydrogen diffusion from the insulating layer 280 to the semiconductor layer 230, conductive layer 242a, conductive layer 242b, etc., can be suppressed.

[0319] Furthermore, by providing an insulating layer 283 that has the function of suppressing hydrogen diffusion on the transistor 200, hydrogen diffusion from above the transistor 200 can be suppressed. Additionally, by providing an insulating layer 282 that has the function of trapping or fixing hydrogen, the insulating layer 282 can trap or fix the hydrogen contained in the insulating layer 280, etc. Thus, the hydrogen concentration in and around the semiconductor layer 230 can be reduced.

[0320] Thus, by employing a structure in which a hydrogen-barrier insulating layer surrounds the top and bottom of the transistor 200, hydrogen diffusion into the oxide semiconductor can be reduced, thereby lowering the hydrogen concentration in the channel formation region. This improves the electrical characteristics and reliability of the transistor 200.

[0321] Furthermore, it is preferable that the insulating layer 280 contains excess oxygen. By supplying this oxygen through the insulating layer 250 to the semiconductor layer 230 using a heat treatment, oxygen vacancies in the channel formation region can be reduced.

[0322] The insulating layer 282 is preferably deposited by sputtering in an atmosphere containing oxygen gas. This allows oxygen to be added to the insulating layer 280. The insulating layer 282 can have a single-layer structure or a stacked structure of two or more layers.

[0323] As described above, by heating the insulating layer 280, which contains excess oxygen, an appropriate amount of oxygen can be supplied to the semiconductor layer 230 through the insulating layer 250. During this heating process, since oxygen-barrier insulating layers 282 and 283 are formed on the insulating layer 280, excessive diffusion of oxygen contained in the insulating layer 280 from the insulating layer 280 can be prevented. Furthermore, since an oxygen-barrier insulating layer 275 is formed between the insulating layer 280 and the semiconductor layer 230, conductive layers 242a, and conductive layers 242b, excessive diffusion of oxygen contained in the insulating layer 280 from the insulating layer 280 can be prevented. Moreover, by performing this heating process with openings formed in a portion of the insulating layers 280, 282, and 283, a portion of the oxygen contained in the insulating layer 280 can diffuse outwards, thereby adjusting the amount of oxygen supplied from the insulating layer 280 to the semiconductor layer 230.

[0324] Figure 18 An example of a single-layer structure is shown for semiconductor layer 230. Alternatively, semiconductor layer 230 may have a stacked structure of two or more layers. For example... Figure 19AAs shown, semiconductor layer 230 may have a two-layer structure consisting of semiconductor layer 230_1 and semiconductor layer 230_2 on semiconductor layer 230_1. Semiconductor layer 230_1 and semiconductor layer 230_2 correspond to the first semiconductor layer and the second semiconductor layer described in Embodiment 1, respectively. Therefore, the structure (material, thickness, etc.) and formation method of semiconductor layer 230_1 and semiconductor layer 230_2 can refer to the structure and formation method of the first semiconductor layer and the second semiconductor layer described in Embodiment 1.

[0325] Notice, Figure 19A The diagram shows a structure where the insulating layer 250 contacts the top surface of the semiconductor layer 230_2, but the invention is not limited thereto. For example, as... Figure 19B As shown, the semiconductor layer 230_2 in the region overlapping with the opening 289 can be removed, allowing the insulating layer 250 to contact the side surface of the semiconductor layer 230_2 and the top surface of the semiconductor layer 230_1. By employing this structure, the distance between the conductive layer 260 and the semiconductor layer 230_1 can be shortened. Therefore, an electric field from the gate electrode can be appropriately applied to the semiconductor layer 230_1.

[0326] The insulating layer 250 preferably has a structure that allows oxygen to diffuse from the insulating layer 280 to the semiconductor layer 230 and suppresses the oxidation of the conductive layers 242a, 242b and 260.

[0327] The insulating layer 250 is formed in the opening 289 in such a way that it contacts the top surface of the insulating layer 222, the side surface of the insulating layer 224, the side surface and top surface of the semiconductor layer 230, the side surface of the conductive layer 242a, the side surface of the conductive layer 242b, the side surface of the insulating layer 275, and the side surface of the insulating layer 280.

[0328] Figure 17B An example of a single-layer structure for the insulating layer 250 is shown. Note that the insulating layer 250 may have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed from two or more films. By using two or more films as the insulating layer 250, the insulating layer 250 can have multiple functions. Examples of functions of the insulating layer 250 include the function of extracting excess oxygen from the semiconductor layer 230, the function of extracting hydrogen from the semiconductor layer 230, and the function of inhibiting hydrogen diffusion into the semiconductor layer 230.

[0329] Here, as Figure 18 As shown, the insulating layer 250 preferably has a stacked structure of an insulating layer 250_1 in contact with the semiconductor layer 230, an insulating layer 250_2 on the insulating layer 250_1, and an insulating layer 250_3 on the insulating layer 250_2.

[0330] As insulating layer 250_1, the insulating material described above that can be used in insulating layer 50 can be used. For example, when insulating layer 250_1, having a region in contact with the side surfaces of conductive layer 242a and conductive layer 242b, has the function of trapping or fixing oxygen, the oxidation of the side surfaces of conductive layer 242a and conductive layer 242b to form an oxide film on those side surfaces can be suppressed. Therefore, the decrease in on-state current or field-effect mobility of transistor 200 can be suppressed. Furthermore, by adopting this structure, the amount of oxygen absorbed by conductive layer 242a and conductive layer 242b in insulating layer 250_2 can be reduced. Therefore, an appropriate amount of oxygen can be supplied to semiconductor layer 230 from insulating layer 250_2, thereby reducing oxygen vacancies in the channel formation region of semiconductor layer 230.

[0331] Furthermore, by providing an insulating layer 250_1 between insulating layer 280 and insulating layer 250_2, and between insulating layer 250_2 and semiconductor layer 230, excessive oxygen supply from insulating layer 280 to semiconductor layer 230 can be suppressed, and an appropriate amount of oxygen can be supplied to semiconductor layer 230. Therefore, the oxygen content in and around the channel formation region of semiconductor layer 230 can be controlled to an appropriate level, thus preventing excessive normally-off operation of transistor 200 and improving reliability. In addition, excessive oxidation of the source and drain regions can be suppressed, preventing a decrease in the on-state current or field-effect mobility of transistor 200.

[0332] By adopting the above structure, the channel formation region can be i-type or substantially i-type, and the source and drain regions can be n-type, providing a semiconductor device with excellent electrical characteristics. By adopting the above structure, even with miniaturization or high integration of the semiconductor device, it can still possess excellent electrical characteristics. Furthermore, miniaturizing the transistor 200 can improve high-frequency characteristics. Specifically, the cutoff frequency can be increased.

[0333] Furthermore, the insulating layer 250_1 can be made of a high-k material. As an example of a high-k material, there are oxides containing one or both of aluminum and hafnium. When a high-k material is used as the insulating layer 250_1, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulator. Furthermore, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0334] Therefore, as the insulating layer 250_1, an oxide containing one or both of aluminum and hafnium is preferred, and an oxide having an amorphous structure and containing one or both of aluminum and hafnium is more preferred. Since alumina can be easily deposited into an amorphous film using the ALD method, alumina with an amorphous structure is preferred. Alumina has the function of trapping or fixing oxygen and hydrogen, so it is suitable for use in the insulating layer 250_1. Alternatively, hafnium oxide has a high function of trapping or fixing oxygen and hydrogen, so it is suitable for use in the insulating layer 250_1.

[0335] For example, the insulating layer 250_2 is preferably made of a material with a low relative permittivity. For example, the insulating layer 250_2 preferably includes a silicon oxide film or a silicon oxynitride film.

[0336] Furthermore, silicon oxide or silicon nitride are insulating materials with high dielectric strength. This reduces the leakage current of the transistor. Additionally, silicon oxide or silicon oxynitride films are also highly hydrogen permeable. Therefore, the insulating layer 250 can also have a three-layer structure consisting of insulating layer 250_2, insulating layer 250_1 on insulating layer 250_2, and insulating layer 250_3 on insulating layer 250_1. By employing this structure, hydrogen in the semiconductor layer 230 diffuses through insulating layer 250_2 to insulating layer 250_1, whereby the hydrogen can be trapped or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0337] The insulating layer 250_3 preferably has hydrogen-blocking properties. By employing this structure, hydrogen diffusion into the semiconductor layer 230 can be suppressed. Furthermore, the insulating layer 250_3 preferably has oxygen-blocking properties. The insulating layer 250_3 is disposed between the channel formation region of the semiconductor layer 230 and the conductive layer 260. By employing this structure, oxygen diffusion from the channel formation region of the semiconductor layer 230 into the conductive layer 260, thus preventing the formation of oxygen vacancies in the channel formation region of the semiconductor layer 230, can be suppressed. Furthermore, oxygen diffusion from the semiconductor layer 230 into the conductive layer 260, preventing oxidation of the conductive layer 260, can be suppressed. The insulating layer 250_3 is preferably at least less permeable to oxygen than the insulating layer 250_2. Furthermore, the insulating layer 250_3 preferably has the function of suppressing hydrogen diffusion. Thus, impurities such as hydrogen in the conductive layer 260 can be prevented from diffusing into the semiconductor layer 230. For example, silicon nitride is preferably used as the insulating layer 250_3.

[0338] For example, the insulating layer 250 may have a three-layer structure in which a hafnium oxide film, a silicon oxide film, and a silicon nitride film are sequentially stacked from one side of the semiconductor layer 230. Furthermore, the thicknesses of the hafnium oxide film, silicon oxide film, and silicon nitride film are 2 nm, 2 nm, and 1 nm, respectively. By adopting this structure, excess oxygen in the semiconductor layer 230 can be expelled to the insulating layer 250, thereby reducing the excess oxygen in the semiconductor layer 230. Furthermore, hydrogen in the semiconductor layer 230 can be trapped or fixed. Therefore, the electrical characteristics and reliability of the transistor 200 can be improved. Alternatively, the insulating layer 250 may also have a three-layer structure in which a silicon oxide film, a hafnium oxide film, and a silicon nitride film are sequentially stacked from one side of the semiconductor layer 230.

[0339] In addition, such as Figure 19C As shown, a structure in which an insulating layer 250_4 is provided on the insulating layer 250_2 can also be adopted. The insulating material that can be used for the insulating layer 250_1 can be used as the insulating layer 250_4. For example, by providing an insulating layer 250_4 with the function of trapping or fixing hydrogen between the insulating layer 250_3 and the insulating layer 250_2, hydrogen in the insulating layer 250_2, etc., can be trapped or fixed.

[0340] Specifically, the insulating layer 250 preferably has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are sequentially stacked from one side of the semiconductor layer 230. By adopting this structure, hydrogen diffuses from the semiconductor layer 230 to the insulating layer 250_1 or the insulating layer 250_4, whereby the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0341] The insulating layer 250 is preferably a thin film. For example, by setting the thickness of the insulating layer 250 to be 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also known as the S-value) can be reduced. The S-value refers to the amount of change in gate voltage when the drain current changes by one digit at a constant drain voltage in the subthreshold region.

[0342] Furthermore, the thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm or more and 20 nm or less, more preferably 0.1 nm or more and 10 nm or less, even more preferably 0.1 nm or more and 5.0 nm or less, even more preferably 0.5 nm or more and 5.0 nm or less, even more preferably 1.0 nm or more and less than 5.0 nm, and even more preferably 1.0 nm or more and 3.0 nm or less. At least a portion of each layer constituting the insulating layer 250 may include a region having the aforementioned thickness.

[0343] Alternatively, insulating layer 250_3 in the four-layer insulating layer 250 structure may not be provided. For example, insulating layer 250_1 can be an insulating layer with the function of trapping or fixing oxygen, insulating layer 250_2 can be an insulating layer containing a material with a low relative permittivity, and insulating layer 250_4 can be an insulating layer with the function of trapping or fixing hydrogen. Specifically, insulating layer 250 may have a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are sequentially stacked from the semiconductor layer 230 side.

[0344] In order to reduce the thickness of insulating layers 250_1 to 250_4 as described above, it is preferable to use the ALD method for deposition. Furthermore, in order to form insulating layers 250_1 to 250_4 with high coverage within the opening 289, it is preferable to use the ALD method for deposition.

[0345] Furthermore, in the formation of the insulating layer 250 with a multilayer insulating film structure, it is preferable to perform the ALD process twice or more. For example, two or more of the multiple insulating films included in the insulating layer 250 are preferably formed by the ALD process. By forming at least two or more insulating films using the ALD process, the coverage and thickness uniformity of the insulating layer 250 can be improved. In addition, for example, by continuously forming two or more insulating films using the ALD process, productivity can be improved.

[0346] Note that the above description illustrates the case where the insulating layer 250 has a three-layer or four-layer structure, but the present invention is not limited thereto. The insulating layer 250 may have a structure including at least one of insulating layers 250_1 to 250_4. By having the insulating layer 250 composed of one, two, or three of insulating layers 250_1 to 250_4, the manufacturing process of semiconductor devices can be simplified, thereby improving productivity.

[0347] The conductive layer 205 is disposed in a manner that overlaps with the semiconductor layer 230 and the conductive layer 260. As the conductive layer 205, a conductive material described later in the section on [conductive layers] can be used. Here, the conductive layer 205 is disposed in a manner that embeds it into an opening formed in the insulating layer 216. Furthermore, as... Figure 17A and Figure 17C As shown, the conductive layer 205 preferably extends in the channel width direction. By employing this structure, the conductive layer 205 is used as wiring when multiple transistors are disposed.

[0348] like Figure 18As shown, the conductive layer 205 preferably includes a conductive layer 205_1 and a conductive layer 205_2. The conductive layer 205_1 is disposed in contact with the bottom surface and sidewalls of the opening. The conductive layer 205_2 is disposed in a recess of the conductive layer 205_1 formed along the opening. Here, the height of the top surface of the conductive layer 205 is the same as or approximately the same as the height of the top surface of the insulating layer 216.

[0349] Here, the conductive layer 205_1 preferably comprises a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to comprise a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).

[0350] By using a conductive material that reduces hydrogen diffusion as conductive layer 205_1, impurities such as hydrogen contained in conductive layer 205_2 can be prevented from diffusing to semiconductor layer 230 through insulating layer 216 and the like. Furthermore, by using a conductive material that inhibits oxygen diffusion as conductive layer 205_1, oxidation of conductive layer 205_2 and subsequent decrease in conductivity can be prevented. Examples of conductive materials that inhibit oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Conductive layer 205_1 can have a single-layer structure or a multilayer structure of the aforementioned conductive materials. For example, conductive layer 205_1 preferably contains titanium nitride.

[0351] Furthermore, the conductive layer 205_2 is preferably made of a highly conductive material. For example, the conductive layer 205_2 is preferably made of a conductive material with tungsten, copper, or aluminum as its main components. For example, the conductive layer 205_2 preferably contains tungsten.

[0352] The conductive layer 205 can be used as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by independently changing the potential applied to the conductive layer 205 without linking it to the potential applied to the conductive layer 260. In particular, by applying a negative potential to the conductive layer 205, the Vth of the transistor 200 can be further increased, thereby reducing the off-state current. Therefore, compared to not applying a negative potential to the conductive layer 205, applying a negative potential to the conductive layer 205 can reduce the drain current when the potential applied to the conductive layer 260 is 0V.

[0353] Note that in Figure 18The diagram shows a stacked structure of conductive layers 205_1 and 205_2, but the invention is not limited to this. Conductive layer 205 can have a single-layer structure or a stacked structure of three or more layers. For example, a structure can be adopted where conductive layer 205_1 has a two-layer structure consisting of a tantalum nitride film and a titanium nitride film on the tantalum nitride film, and a conductive layer 205_2 including a tungsten film is disposed on conductive layer 205_1. By adopting this structure, the diffusion of impurities such as hydrogen and metallic impurities such as copper contained in the lower layer of transistor 200 to conductive layer 205 can be suppressed.

[0354] Insulating layer 224, insulating layer 221 and insulating layer 222 are all used as the second gate insulating layer.

[0355] The insulating layer 224 preferably comprises, for example, a silicon oxide film or a silicon oxynitride film. This allows oxygen to be supplied from the insulating layer 224 to the semiconductor layer 230 to reduce oxygen vacancies. Furthermore, the insulating layer 224 may also have a stacked structure of two or more layers. In this case, it is not limited to a stacked structure made of the same material; it can have a stacked structure made of different materials.

[0356] Furthermore, the insulating layer 224 is preferably processed into an island shape in the same way as the semiconductor layer 230. Thus, when multiple transistors 200 are provided, each transistor 200 includes an insulating layer 224 of approximately the same size. Therefore, the amount of oxygen supplied from the insulating layer 224 to the semiconductor layer 230 in each transistor 200 is approximately equal. This suppresses non-uniformity in the electrical characteristics of the transistors 200 within the substrate surface.

[0357] By employing an island-shaped structure for the insulating layer 224, at least a portion of the bottom surface of the conductive layer 260 can be disposed below the bottom surface of the semiconductor layer 230 (see reference). Figure 17C Therefore, the conductive layer 260 can be disposed opposite to the top and side surfaces of the semiconductor layer 230, so that the electric field of the conductive layer 260 can act on the top and side surfaces of the semiconductor layer 230.

[0358] Note that it is not necessary to process the insulating layer 224 into an island shape. For example, as Figures 20A to 20D As shown, the insulating layer 224 can also be partially formed into an open shape instead of being island-shaped. Here, Figures 20A to 20D Corresponding to Figures 17A to 17D Apart from the difference in shape of insulating layer 224, it is similar to Figures 17A to 17D same.

[0359] exist Figures 20A to 20DIn the insulating layer 224 shown, the thickness of the region that does not overlap with the semiconductor layer 230 is smaller than the thickness of the region that overlaps with the semiconductor layer 230. Furthermore, openings are formed in the region that does not overlap with the semiconductor layer 230 but overlaps with the insulating layer 250. When multiple transistors are disposed on the same substrate, by forming the insulating layer 224 in this way, the semiconductor layer 230 of each transistor is formed on the same insulating layer 224. This reduces the non-uniformity of oxygen supply from the insulating layer 224 to the semiconductor layer 230 of each transistor. Therefore, the non-uniformity of the electrical characteristics of each transistor can be reduced.

[0360] Note that in Figures 20A to 20D In the insulating layer 224 shown, an opening is formed in the region that does not overlap with the semiconductor layer 230 but overlaps with the insulating layer 250, but this opening may not be provided.

[0361] The conductive materials described in the section on [Conductive Layers], which will be explained later, can be used as conductive layers 242a and 242b. In particular, conductive materials that are not easily oxidized or that have the function of inhibiting oxygen diffusion are preferably used as conductive layers 242a and 242b. Examples of such conductive materials include nitrogen-containing conductive materials and oxygen-containing conductive materials. This suppresses the decrease in conductivity of conductive layers 242a and 242b.

[0362] Metal nitrides are preferably used as conductive layers 242a and 242b. For example, nitrides containing tantalum, titanium, molybdenum, tungsten, tantalum and aluminum, or titanium and aluminum are preferred. For instance, tantalum nitride can be used as conductive layers 242a and 242b. Furthermore, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, ITO, ITSO, and In-Zn oxides can also be used. These materials are preferred because they are conductive materials that are not easily oxidized or maintain conductivity even after absorbing oxygen.

[0363] Furthermore, both conductive layers 242a and 242b can have a stacked structure. In this case, the aforementioned conductive material can be used as the lower layer (the layer with the largest contact area with the semiconductor layer 230) of conductive layers 242a and 242b, while a conductive material with higher conductivity can be used as the upper layer. For example, tantalum nitride can be used as the lower layer, and tungsten can be used as the upper layer. Alternatively, for example, ITO or ITSO can be used as the lower layer, and tungsten can be used as the upper layer.

[0364] The conductive layer 260 is disposed such that it covers the top surface of the insulating layer 222, the side surface of the insulating layer 224, and the side and top surfaces of the semiconductor layer 230 in the opening 289, with the insulating layer 250 in between. Furthermore, the height of the top surface of the conductive layer 260 is the same as or approximately the same as the height of the upper end of the insulating layer 250 and the height of the top surface of the insulating layer 280.

[0365] The sidewalls of the opening 289 can be perpendicular or substantially perpendicular to the top surface of the insulating layer 222, or they can be conical. By having conical sidewalls, the coverage of the insulating layer 250 provided in the opening 289 can be improved, thus reducing defects such as voids.

[0366] like Figure 17A and Figure 17C As shown, the conductive layer 260 preferably extends in the channel width direction. By employing this structure, the conductive layer 260 is used as wiring when multiple transistors are disposed.

[0367] like Figure 17C As shown, when viewed in a cross-section along the channel width direction of the transistor 200, a curved surface can also be present between the side surface and the top surface of the semiconductor layer 230. That is, the ends of the side surface and the ends of the top surface can also be curved.

[0368] like Figure 18 As shown, the conductive layer 260 preferably has a two-layer structure. Here, the conductive layer 260 preferably includes a conductive layer 260_1 and a conductive layer 260_2 disposed on the conductive layer 260_1. For example, the conductive layer 260_1 is preferably disposed in such a way that it surrounds the bottom surface and the side surface of the conductive layer 260_2.

[0369] For example, titanium nitride is preferably used as conductive layer 260_1, and tungsten is preferably used as conductive layer 260_2. Alternatively, tantalum nitride is preferably used as conductive layer 260_1, and copper is preferably used as conductive layer 260_2. By adopting this structure, the conductivity of conductive layer 260 can be improved.

[0370] Furthermore, the conductive layer 260 may also have a stacked structure of three or more layers. For example, the conductive layer 260 may also have a three-layer structure of a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

[0371] The relative permittivity of insulating layers 216, 280, and 285 is preferably lower than that of insulating layer 222. By using a material with a low relative permittivity for the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0372] For example, insulating layers 216, 280, and 285 can all be made of materials with low relative permittivity, as described later in the section on [insulating layers]. In particular, silicon oxide and silicon oxynitride are preferred due to their thermal stability. Furthermore, materials such as silicon oxide, silicon oxynitride, and porous silicon oxide are preferred because they readily form regions containing excess oxygen.

[0373] In addition, the top surfaces of insulating layer 216 and insulating layer 280 can also be planarized.

[0374] The concentration of impurities such as water and hydrogen in the insulating layer 280 is preferably reduced. For example, the insulating layer 280 preferably contains silicon oxides such as silicon oxide and silicon oxynitride.

[0375] Conductive layers 243a and 243b may use conductive materials described in the section on [Conductive Layers], which will be explained later. For example, conductive layers 243a and 243b are preferably made of conductive materials with tungsten, copper, or aluminum as their main components. Furthermore, conductive layers 243a and 243b may also have a laminated structure.

[0376] For example, such as Figure 18 As shown, conductive layers 243a and 243b can also have a two-layer stacked structure. Conductive layer 243a includes a conductive layer 243a1 formed along the opening and a conductive layer 243a2 formed inside the conductive layer 243a1. Furthermore, conductive layer 243b includes a conductive layer 243b1 formed along the opening and a conductive layer 243b2 formed inside the conductive layer 243b1.

[0377] Conductive layers 243a1 and 243b1 can be formed as a single layer or in stacks using conductive materials suitable for conductive layer 205_1. By providing conductive layers 243a1 and 243b1, impurities such as water and hydrogen can be suppressed from entering the semiconductor layer 230 through conductive layers 243a2 and 243b2. Furthermore, conductive layers 243a2 and 243b2 can be formed using the aforementioned conductive materials suitable for conductive layers 243a and 243b.

[0378] In addition, such as Figure 17B As shown, the height of the top surfaces of conductive layers 243a and 243b is the same as or approximately the same as the height of the top surface of insulating layer 285. Furthermore, as... Figure 18 As shown, the lower portion of conductive layer 243a is sometimes formed by embedding it in conductive layer 242a. Similarly, the lower portion of conductive layer 243b is sometimes formed by embedding it in conductive layer 242b.

[0379] As insulating layers 241a and 241b, barrier insulating layers suitable for insulating layers 275 and the like can be used. For example, silicon nitride can be used as insulating layers 241a and 241b. Insulating layers 241a and 241b are arranged in contact with insulating layers 285, 283, 282, and 275. This prevents impurities such as water and hydrogen contained in insulating layers 280 from entering the semiconductor layer 230 via conductive layers 243a and 243b. In particular, silicon nitride has high hydrogen barrier properties and is therefore preferred. Furthermore, it prevents oxygen contained in insulating layer 280 from being absorbed by conductive layers 243a and 243b.

[0380] Furthermore, insulating layers 241a and 241b may also have a laminated structure. In this case, an oxygen-barrier insulating layer and a hydrogen-barrier insulating layer are preferably used in combination as the first insulating layer that contacts the sidewall of the opening of the insulating layer 280, etc., and the second insulating layer inside it.

[0381] [Example of variation 1] exist Figure 17B In the example, the insulating layer 250 contacts the side of the insulating layer 280 in the opening 289, but the present invention is not limited to this structure. For example, an insulating layer may also be provided between the insulating layer 250 and the insulating layer 280 in the opening 289.

[0382] Reference Figures 21A to 22C Reference Figures 17A to 17D Examples of variations of the semiconductor device are illustrated. Figures 21A to 21D These are plan and cross-sectional views of a semiconductor device including transistor 200, respectively corresponding to... Figures 17A to 17D The plan view and cross-sectional view are shown. In addition, Figures 22A to 22C This is an enlarged cross-sectional view of the transistor 200 along its channel length.

[0383] Figures 21A to 21D The transistor 200 shown includes an insulating layer 254, mainly in this respect with Figures 17A to 17D The transistor 200 shown is different. The following mainly describes the parts that differ from the above description; for repeated parts, the description is sometimes omitted as they are mentioned above.

[0384] In addition, Figures 21A to 21DIn this structure, both conductive layers 242a and 242b have a two-layer structure. Conductive layer 242a has a stacked structure of conductive layer 242a1 and conductive layer 242a2 on conductive layer 242a1. Conductive layer 242b has a stacked structure of conductive layer 242b1 and conductive layer 242b2 on conductive layer 242b1. Conductive layers 242a1 and 242b1 correspond to the lower layers of conductive layers 242a and 242b, respectively, and conductive layers 242a2 and 242b2 correspond to the upper layers of conductive layers 242a and 242b, respectively.

[0385] like Figure 21B and Figure 21C As shown, the insulating layer 254 is disposed inside the opening 289 and contacts the side surfaces of the insulating layer 280, the conductive layer 242a2, the conductive layer 242b2, the top surface of the conductive layer 242a1, the top surface of the conductive layer 242b1, and the top surface of the insulating layer 222 in the opening 289. In other words, the insulating layer 254 can be described as being formed as a sidewall in contact with the sidewall of the opening 289. Here, the sidewall of the opening 289 corresponds, for example, to the side surface of the insulating layer 280, etc., in the opening 289.

[0386] The insulating layer 254 preferably has oxygen-barrier properties. When the insulating layer 254 has oxygen-barrier properties, the oxidation of the sides of the conductive layers 242a and 242b, resulting in the formation of an oxide film on those sides, can be suppressed. Therefore, the decrease in the on-state current or the decrease in the field-effect mobility of the transistor 200 can be suppressed. An oxygen-barrier insulating layer can also be used as the insulating layer 254. For example, silicon nitride can be used as the insulating layer 254.

[0387] The opening 289 overlaps with the area between conductive layers 242a2 and 242b2. When viewed in plan view, the side surface of the insulating layer 280 in the opening 289 coincides with or substantially coincides with the side surface of conductive layers 242a2 and 242b2. Furthermore, portions of conductive layers 242a1 and 242b1 are formed to protrude inwards from the opening 289. In other words, in conductive layer 242a1, the portion on its top surface where the insulating layer 254 is formed (hereinafter, sometimes referred to as the protrusion of conductive layer 242a1) is formed in such a way that it protrudes towards conductive layer 260 from conductive layer 242a2. Similarly, in conductive layer 242b1, the portion on its top surface where the insulating layer 254 is formed (hereinafter, sometimes referred to as the protrusion of conductive layer 242b1) is formed in such a way that it protrudes towards conductive layer 260 from conductive layer 242b2.

[0388] Here, a portion of the top surface of conductive layer 242a1 contacts conductive layer 242a2, and a portion of the top surface of conductive layer 242b1 contacts conductive layer 242b2. Therefore, insulating layer 254 contacts other portions of the top surface of conductive layer 242a1, other portions of the top surface of conductive layer 242b1, the side surface of conductive layer 242a2, and the side surface of conductive layer 242b2 inside the opening 289. Furthermore, insulating layer 250 contacts the top surface of semiconductor layer 230, the side surface of conductive layer 242a1, the side surface of conductive layer 242b1, and the side surface of insulating layer 254.

[0389] The insulating layer 254 is formed into a sidewall shape by anisotropic etching to contact the sidewall of the opening 289. The insulating layer 254 is formed to contact the sidewalls of the conductive layer 242a2 and the sidewalls of the conductive layer 242b2, and has the function of protecting the conductive layer 242a2 and the conductive layer 242b2.

[0390] Furthermore, when the conductive layers 242a1 and 242b1 are separated, the insulating layer 254 is used as a mask. Therefore, as... Figure 22A As shown, in the cross-sectional view of transistor 200, the side end of insulating layer 254 is consistent with or substantially consistent with the side end of conductive layer 242a1 and conductive layer 242b1.

[0391] After separating the conductive layers 242a1 and 242b1 and before depositing the insulating layer 250, heat treatment is preferably performed in an oxygen-containing atmosphere. At this time, since the insulating layer 254 is formed in contact with the sides of the conductive layers 242a2 and 242b2, excessive oxidation of the conductive layers 242a2 and 242b2 can be prevented. Furthermore, even after microwave plasma treatment is performed after separating the conductive layers 242a1 and 242b1, the formation of oxide films on the sides of the conductive layers 242a1 and 242b2 can be suppressed.

[0392] The insulating layer 254, the insulating layer 250, and the conductive layer 260 reflect the shape of the opening 289. Therefore, the insulating layer 254 is provided in such a way that it covers the sidewall of the opening 289, the insulating layer 250 is provided in such a way that it covers the bottom of the opening 289 and the insulating layer 254, and the conductive layer 260 is provided in such a way that it is embedded in the recess of the insulating layer 250.

[0393] As described above, the insulating layer 250 can also have a laminated structure. For example, such as Figure 22A As shown, insulating layer 250 can also have a three-layer structure consisting of insulating layers 250_1 to 250_3. Furthermore, for example, as... Figure 22B As shown, the insulating layer 250 can also have a four-layer structure consisting of insulating layers 250_1 to 250_4.

[0394] Furthermore, the thickness of the insulating layer 254 is preferably 0.5 nm or more and 20 nm or less, more preferably 0.5 nm or more and 10 nm or less, and even more preferably 0.5 nm or more and 3 nm or less. When the insulating layer 254 has the above-mentioned thickness, excessive oxidation of the conductive layers 242a2 and 242b2 can be suppressed. Note that the insulating layer 254 only needs to have a region with the above-mentioned thickness in at least a portion thereof. In addition, since the insulating layer 254 is provided in contact with the sidewall of the opening 289, it is preferable to use a deposition method such as ALD with high coverage. When the thickness of the insulating layer 254 is too large, the deposition time of the insulating layer 254 using the ALD method is long, resulting in a decrease in productivity. Therefore, it is preferable to set the thickness of the insulating layer 254 approximately within the above-mentioned range. Furthermore, the thickness of the insulating layer 254 is preferably such that it does not excessively block the diffusion of excess oxygen from the insulating layer 280 to the insulating layer 250-2 and from the insulating layer 250-2 to the semiconductor layer 230.

[0395] like Figure 22A As shown, in a cross-sectional view along the channel length of transistor 200, the distance L1 between conductive layers 242a1 and 242b1 is smaller than the distance L2 between conductive layers 242a2 and 242b2. Here, distance L1 refers to the shortest distance between conductive layers 242a1 and 242b1, and distance L2 refers to the shortest distance between conductive layers 242a2 and 242b2. By adopting this structure, the distance between the source and drain can be further reduced, and the channel length can be reduced accordingly. Therefore, the frequency characteristics of transistor 200 can be improved. Thus, by miniaturizing the semiconductor device, a semiconductor device with improved operating speed can be provided.

[0396] exist Figure 22A In the structure shown, the difference between distance L2 and distance L1 is equal to twice the thickness of insulating layer 254. In other words, distance L2 is equal to or approximately equal to distance L1 plus twice the thickness of insulating layer 254. Here, the thickness of insulating layer 254 refers to the width of at least a portion of insulating layer 254 in the A1-A2 direction.

[0397] Furthermore, the insulating layer 254 may also have a stacked structure of two or more layers. In this case, at least one layer is preferably an inorganic insulating layer that is not easily oxidized, as described above. For example, the first insulating layer of the insulating layer 254 may be an inorganic insulating layer that is not easily oxidized, and the second insulating layer on the first insulating layer of the insulating layer 254 may be an insulating material suitable for the insulating layer 250_2 (e.g., silicon oxide). The relative permittivity of the second insulating layer of the insulating layer 254 is preferably lower than that of the first insulating layer of the insulating layer 254. In this way, by adopting a two-layer structure to increase the thickness of the insulating layer 254, the distance between the conductive layer 260 and the conductive layer 242a or the conductive layer 242b can be increased to reduce parasitic capacitance.

[0398] The above illustrates an example of forming the insulating layer 254 into a sidewall shape through anisotropic etching, but the invention is not limited thereto. Figure 22C As shown, the insulating layer 254 may also have a shape with an opening inside the opening 289. In this case, the opening of the insulating layer 254 can be formed by removing part of the insulating film that will become the insulating layer 254 using photolithography. The opening of the insulating layer 254 preferably overlaps with the area between the conductive layers 242a1 and 242b1.

[0399] like Figure 22C As shown in the cross-sectional view, a protrusion is formed at the lower part of the insulating layer 254. The protrusion of the insulating layer 254 overlaps with the protrusions of the conductive layer 242a1 and the conductive layer 242b1.

[0400] [Variation Example 2] In Modified Example 1, a structure is described in which the insulating layer 254 is provided in contact with the sidewall of the opening 289; however, the present invention is not limited to this structure. For example, the insulating layer 254 may not be provided in the opening 289.

[0401] Reference Figures 23A to 24 This section describes a modified example of the semiconductor device described in Modified Example 1. Figures 23A to 23D These are plan and cross-sectional views of a semiconductor device including transistor 200, respectively corresponding to... Figures 21A to 21D The plan view and cross-sectional view are shown. In addition, Figure 24 This is a magnified cross-sectional view of the channel length of transistor 200, corresponding to... Figure 22C The enlarged cross-section shown.

[0402] Figures 23A to 23D The transistor 200 shown does not include the insulating layer 254, mainly in this respect compared to Figures 21A to 21D The transistor 200 shown is different. The following mainly describes the parts that differ from the above description; for repeated parts, the description is sometimes omitted as they are mentioned above.

[0403] like Figure 24 As shown, without the insulating layer 254, a portion of the insulating layer 250 is configured to overlap with the protrusions of the conductive layer 242a1 and the conductive layer 242b1. Furthermore, a portion of the conductive layer 260 is sometimes configured to overlap with the protrusions of the conductive layer 242a1 and the conductive layer 242b1. Here, the protrusions of the conductive layer 242a1 and the conductive layer 242b1 are in contact with the insulating layer 250. Additionally, the side surface of the insulating layer 250 is in contact with the side surface of the insulating layer 280, the side surface of the insulating layer 275, the side surface of the conductive layer 242a2, and the side surface of the conductive layer 242b2.

[0404] The insulating layer 250 is formed in accordance with the shape of the opening 289. Therefore, the insulating layer 250 is formed in accordance with the shape of the conductive layers 242a1 and 242b1 that protrude into the opening 289.

[0405] like Figure 24 As shown, in a cross-section along the channel length of transistor 200, the distance L1 between conductive layers 242a1 and 242b1 is smaller than the distance L2 between conductive layers 242a2 and 242b2. By employing this structure, the distance between the source and drain can be further reduced, and the channel length can be correspondingly reduced. Therefore, the frequency characteristics of transistor 200 can be improved. Thus, by miniaturizing the semiconductor device, a semiconductor device with improved operating speed can be provided.

[0406] Furthermore, by adopting Figure 24 The structure shown allows the width of the upper portion of the conductive layer 260 to be greater than the distance L1. This reduces the wiring resistance of the conductive layer 260, thereby reducing the power consumption of the semiconductor device.

[0407] <Structure Example of a Semiconductor Device 2> Reference Figures 25A to 25D An example of the structure of a semiconductor device according to one aspect of the present invention is provided.

[0408] Figure 25A This is a plan view of a semiconductor device including transistor 200A. Figure 25B It is along Figure 25A The section shown by the dotted lines A1-A2 in the diagram is a cross-sectional view, which is also a cross-sectional view of the channel length direction of transistor 200A. Figure 25C It is along Figure 25A The section shown by the dotted lines A3-A4 in the figure is a cross-sectional view, which is also a cross-sectional view of the channel width direction of transistor 200A. Figure 25D It is along Figure 25A The cross-sectional view of the portion shown by the dashed lines A5-A6 in the figure.

[0409] Transistor 200A and Figures 17A to 17D The main differences of the transistor 200 shown are: in transistor 200A, the side end of conductive layer 242a is aligned or substantially aligned with the side end of semiconductor layer 230; in transistor 200A, the side end of conductive layer 242b is aligned or substantially aligned with the side end of semiconductor layer 230; transistor 200A includes insulating layers 271a and 271b; and transistor 200A does not include layer 229; etc. The following mainly describes the parts that differ from the above description; repeated parts are sometimes omitted with reference to the above description.

[0410] Insulating layer 271a is disposed on conductive layer 242a, and insulating layer 271b is disposed on conductive layer 242b.

[0411] Transistor 200A, for example, can be referenced Figures 11E to 11H The manufacturing method described herein is as follows. Specifically, a crystalline semiconductor layer 30 is formed, a conductive film that will become conductive layers 242a and 242b is formed on the semiconductor layer 30, an insulating layer that will become insulating layers 271a and 271b is formed on the conductive film, the conductive film is processed using the insulating layer as a mask to form a conductive layer overlapping the insulating layer, and the semiconductor layer 30 is processed. Thus, an island-shaped structure of insulating layer, conductive layer, and semiconductor layer 30 can be manufactured. In this case, the two-layer structure of island-shaped insulating layer and conductive layer corresponds to the island layer 35 described in Embodiment 1.

[0412] Furthermore, by removing the portion of the island-shaped insulating layer that overlaps with the opening 289, insulating layers 271a and 271b can be formed. Similarly, by removing the portion of the island-shaped conductive layer that overlaps with the opening 289, conductive layers 242a and 242b can be formed. Thus, the side end of conductive layer 242a is aligned or substantially aligned with the side end of semiconductor layer 230, and the side end of conductive layer 242b is aligned or substantially aligned with the side end of semiconductor layer 230. This enables miniaturization and high integration of the semiconductor device.

[0413] Since the insulating layer is used as a mask for the conductive layer, conductive layers 242a and 242b do not have curved surfaces between their side and top surfaces. Therefore, the ends where the side and top surfaces of conductive layers 242a and 242b intersect are angled. When the ends where the side and top surfaces of conductive layers 242a and 242b intersect are angled, the cross-sectional area of ​​conductive layers 242a and 242b increases compared to the case where these ends are curved. Consequently, the resistance of conductive layers 242a and 242b decreases, thus increasing the transistor's on-state current.

[0414] Furthermore, at least one of the structures described in <Structure Example 1 of Semiconductor Device> above can also be used in transistor 200A.

[0415] <Structure Example of a Semiconductor Device 3> Reference Figures 26A to 26D An example of the structure of a semiconductor device according to one aspect of the present invention is provided.

[0416] Figure 26A It is a plan view of a semiconductor device including transistor 200B. Figure 26B It is along Figure 26A The cross-sectional view of the dotted line A1-A2 shown. Figure 26C It is along Figure 26A The cross-sectional view shown is the dotted-dash line A3-A4. Figure 26D It is along Figure 26B The cross-sectional view shown is the dotted-dash line A5-A6.

[0417] Transistor 200B includes a conductive layer 220, a conductive layer 240, a semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.

[0418] A conductive layer 220 is disposed on an insulating layer 210, an insulating layer 280 is disposed on the conductive layer 220, and a conductive layer 240 is disposed on the insulating layer 280. An opening 290 is formed in the conductive layer 240 and the insulating layer 280, extending to the conductive layer 220. A semiconductor layer 230 is disposed along the bottom and sidewalls of the opening 290. The semiconductor layer 230 has a portion that contacts the conductive layer 240 and a portion that contacts the conductive layer 220.

[0419] In transistor 200B, conductive layer 260 is used as the gate electrode, and insulating layer 250 is used as the gate insulating layer. Furthermore, conductive layer 220 is used as one of the source and drain electrodes, and conductive layer 240 is used as the other of the source and drain electrodes.

[0420] Semiconductor layer 230 has a region overlapping conductive layer 260 with insulating layer 250 as a boundary. At least a portion of this region is used as a channel formation region for transistor 200B. One of the regions near conductive layer 220 and conductive layer 240 of semiconductor layer 230 is used as a source region, and the other is used as a drain region. That is, the channel formation region is sandwiched between the source region and the drain region.

[0421] Semiconductor layer 230 is disposed inside opening 290. Furthermore, in transistor 200B, one of the source and drain electrodes (here, conductive layer 220) is located below, and the other (here, conductive layer 240) is located above, so current flows in the vertical direction. That is, a channel is formed along the side of opening 290. Therefore, compared to planar transistors where the channel forming region, source region, and drain region are respectively provided on the XY plane, transistor 200B can reduce the occupied area. This allows for high integration of semiconductor devices. Furthermore, when transistor 200B is used in a memory device, the storage capacity per unit area can be increased. Moreover, it can be said that the channel length direction of transistor 200B has a vertical component; therefore, this transistor can also be called VFET (Vertical Field Effect Transistor), vertical transistor, vertical channel transistor, vertical channel type transistor, etc.

[0422] Transistor 200B corresponds to the transistor provided in the opening 91 as described in Embodiment 1.

[0423] like Figure 26D As shown, the semiconductor layer 230, insulating layer 250, and conductive layer 260 are arranged in a concentric circle by forming the opening 290 in a circular shape when viewed from the plane. As a result, the distance between the conductive layer 260 and the semiconductor layer 230 is approximately uniform, so a gate electric field can be applied to the semiconductor layer 230 approximately uniformly.

[0424] Furthermore, in this embodiment, an example is shown where the opening 290 is circular when viewed from a plane. By using a circle, the processing accuracy when forming the opening can be improved, and openings of minute size can be formed. Note that the present invention is not limited thereto. The shape of the opening 290 when viewed from a plane can be, for example, a circle, an ellipse or other approximate circle, a triangle, a quadrilateral (including rectangles, rhombuses, and squares), a pentagon, a star-shaped polygon, or a polygon with rounded corners.

[0425] The structure (material, thickness, etc.) of semiconductor layer 230, insulating layer 250, conductive layer 260 and insulating layer 280 can be referred to the structure of semiconductor layer 230, insulating layer 250, conductive layer 260 and insulating layer 280 described in <Structure Example 1 of Semiconductor Device> above.

[0426] Conductive layers 220 and 240 may use the conductive materials described in the section on [Conductive Layers] which will be explained later. Alternatively, the materials described above that can be used for conductive layers 242a and 242b may be used.

[0427] Materials Constituting Semiconductor Devices The following describes the materials that can be used in the semiconductor device of this embodiment. Each layer constituting the semiconductor device of this embodiment may have a single-layer structure or a stacked structure.

[0428] [Oxide semiconductor layer] Regarding the oxide semiconductor layer of the transistor that can be used as one aspect of the present invention, refer to the description in <Structure of Semiconductor Device>.

[0429] The carrier concentration in the channel formation region is preferably below 1×10⁻⁶. 19 cm -3 Below, less than 1×10 18 cm -3 Below, less than 5×10 17 cm -3 Less than 1×10 17 cm -3 Less than 1×10 16 cm -3 Less than 1×10 15 cm -3 Less than 1×10 14 cm -3 Less than 1×10 13 cm -3 Less than 1×10 12 cm -3 Less than 1×10 11 cm -3 Or less than 1×10 10 cm -3 Note that there is no specific limit to the lower limit of carrier concentration in the channel formation region; for example, it can be 1 × 10⁻⁶. -7 cm -3 .

[0430] As described above, in an OS transistor, when oxygen vacancies (V0) exist in the channel formation region of the oxide semiconductor... O When impurities are present, the electrical characteristics can easily change, leading to a decrease in reliability. Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of the OS transistor. To further reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. Examples of impurities include hydrogen, carbon, and nitrogen.

[0431] When nitrogen is present in oxide semiconductors, trapped states sometimes form. As a result, the electrical characteristics of the transistor can sometimes be unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor, as measured by SIMS, is set to 1 × 10⁻⁶. 20 atoms / cm 3 The following is preferred: 5×10 19atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is more preferably 5×10 18 atoms / cm 3 Hereinafter, 1×10 is more preferred. 18 atoms / cm 3 The following is a further preferred option: 5×10 17 atoms / cm 3 the following.

[0432] Furthermore, when oxide semiconductors contain alkali metals or alkaline earth metals, defect states sometimes form, leading to unstable electrical characteristics in the transistor. Therefore, the concentration of alkali metals or alkaline earth metals in the channel formation region of the oxide semiconductor, measured using SIMS, is set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 16 atoms / cm 3 the following.

[0433] By using oxide semiconductors with sufficiently reduced impurities in the channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0434] [Insulating layer] Inorganic insulating films are preferably used for the insulating layers (insulating layers 210, 212, 214, 216, 221, 222, 224, 241a, 241b, 250, 254, 271a, 271b, 275, 280, 283, 285, etc.) included in the semiconductor device. Examples of inorganic insulating films include oxide insulating films, nitride insulating films, oxynitride insulating films, and oxynitride insulating films. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, tantalum oxide films, cerium oxide films, gallium zinc oxide films, and hafnium aluminum oxide films. Examples of silicon nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxynitride insulating films include silicon oxynitride films, aluminum oxynitride films, gallium oxynitride films, yttrium oxynitride films, and hafnium oxynitride films. Examples of oxynitride insulating films include silicon oxynitride films and aluminum oxynitride films. Furthermore, organic insulating films can also be used as insulating layers included in semiconductor devices.

[0435] For example, when miniaturizing and highly integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulating layer. By using a high-k material as the gate insulating layer, low voltage can be achieved during transistor operation while maintaining the physical thickness. Furthermore, the equivalent oxide thickness (EOT) of the gate insulating layer can be reduced. On the other hand, by using a material with a low relative permittivity as the insulating layer used as an interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select the material based on the function of the insulating layer. Moreover, materials with a low relative permittivity are also materials with high dielectric strength.

[0436] Materials with relatively high permittivity include, for example, aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0437] Examples of materials with low relative permittivity include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon oxynitride, as well as resins such as polyesters, polyolefins, polyamides (nylon and aramids, etc.), polyimides, polycarbonates, and acrylic resins. Furthermore, examples of inorganic insulating materials with low relative permittivity other than those mentioned above include fluorine-containing silicon oxide, carbon-containing silicon oxide, and silicon oxide containing both carbon and nitrogen. Additionally, porous silicon oxide can be used as an example. Moreover, these silicon oxides may contain nitrogen.

[0438] Furthermore, ferroelectric materials can be used as the insulating layer included in the semiconductor device. As a ferroelectric material, an oxide containing one or both of hafnium and zirconium is preferred. Examples of such oxides include hafnium oxide, zirconium oxide, and hafnium-zirconium oxide. Additionally, as a ferroelectric material, a material containing one of hafnium and zirconium with added element J1 (here, element J1 is one or more selected from the other of hafnium and zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, and strontium) can also be used.

[0439] Furthermore, by adding a Group 3 element from the periodic table to an oxide containing one or both of hafnium and zirconium, the oxygen vacancy concentration in the oxide increases, thereby facilitating the formation of crystals with an orthorhombic crystal structure. This increases the proportion of crystals with an orthorhombic crystal structure, enhancing remanent polarization, which is therefore preferable. On the other hand, excessive addition of a Group 3 element may reduce the crystallinity of the oxide, making it less likely to exhibit ferroelectricity. Therefore, the content of a Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% or more and 10 atomic% or less, more preferably 0.1 atomic% or more and 5 atomic% or less, and even more preferably 0.1 atomic% or more and 3 atomic% or less. Here, the content of a Group 3 element refers to the percentage of Group 3 element atoms in the sum of the atomic numbers of all metal elements contained in the layer. The Group 3 element is preferably selected from one or more of scandium, lanthanum, and yttrium, more preferably from one or both of lanthanum and yttrium.

[0440] Furthermore, as materials capable of exhibiting ferroelectric properties, examples include metal nitrides comprising at least one of elements M1 and M2 and nitrogen. Here, element M1 is selected from one or more of aluminum, gallium, and indium. Furthermore, element M2 is selected from one or more of boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, and chromium. Furthermore, as materials capable of exhibiting ferroelectric properties, examples include materials incorporating element M3 into the aforementioned metal nitrides. Furthermore, element M3 is selected from one or more of magnesium, calcium, strontium, zinc, and cadmium.

[0441] Furthermore, perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, as well as κ-type alumina such as GaFeO3, can be cited as materials that can exhibit ferroelectric properties. Additionally, lead titanate (PbTiO2) can also be used as a material that can exhibit ferroelectric properties. X Piezoelectric ceramics with perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate.

[0442] Note that while examples of metal oxides and metal nitrides are shown in the above description, the invention is not limited to these. For example, metal oxynitrides with nitrogen added to the aforementioned metal oxides or metal oxynitrides with oxygen added to the aforementioned metal nitrides may also be used.

[0443] Furthermore, as a material that can exhibit ferroelectricity, for example, a mixture or compound composed of multiple materials selected from the above-mentioned materials can be used. Note that the crystal structure (properties) of the materials listed above may vary not only depending on the deposition conditions but also depending on various processes, etc. Therefore, in this specification, materials exhibiting ferroelectricity are referred to not only as ferroelectric materials but also as materials that can exhibit ferroelectricity.

[0444] In this specification and the like, a ferroelectric material formed in a layered manner is sometimes referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Furthermore, in this specification and the like, a device comprising a ferroelectric layer, a metal oxide film, or a metal nitride film is sometimes referred to as a ferroelectric device.

[0445] The ferroelectric layer preferably has an orthorhombic crystal structure, thereby exhibiting ferroelectricity. The crystal structure contained in the ferroelectric layer can be one or more selected from the tetragonal, orthorhombic, monoclinic, and hexagonal crystal systems. Alternatively, the ferroelectric layer can also have an amorphous structure. In this case, the ferroelectric layer can also have a composite structure of amorphous and crystalline structures.

[0446] Metal oxides containing one or both of hafnium and zirconium are also insulating materials with the function of trapping or fixing hydrogen. Therefore, by using a metal oxide containing one or both of hafnium and zirconium in at least a portion of the gate insulating layer, hydrogen contained in the oxide semiconductor layer can be trapped or fixed, thereby reducing the hydrogen concentration in the oxide semiconductor layer. Furthermore, the transistor including this gate insulating layer can be used as a FeFET (Ferroelectric Field Effect Transistor).

[0447] Furthermore, by surrounding a transistor using metal oxides with an insulating layer that suppresses the permeation of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. For example, the insulating layer that suppresses the permeation of impurities and oxygen can be a single layer or a stack of insulating layers selected from one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the material used for the insulating layer that suppresses the permeation of impurities and oxygen can be metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, as well as nitrides such as aluminum nitride and silicon nitride, and oxynitrides such as silicon oxynitride.

[0448] Specifically, materials used as insulating layers that suppress the permeation of impurities such as water and hydrogen, as well as oxygen, include, for example, metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Additionally, nitrides such as aluminum nitride, titanium aluminum nitride, and silicon nitride can be used as examples. Furthermore, nitrogen oxides such as silicon oxynitride can be used as examples. Moreover, gallium oxide can be used as an insulating layer material that suppresses oxygen permeation.

[0449] Furthermore, the insulating layer, such as the gate insulating layer, that contacts the oxide semiconductor layer or is disposed near the oxide semiconductor layer is preferably an insulating layer having regions containing excess oxygen. For example, by making the insulating layer having regions containing excess oxygen contact the oxide semiconductor layer or located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Regarding insulating layers that easily form regions containing excess oxygen, please refer to the description in <Structure of Semiconductor Devices>.

[0450] A hydrogen-barrier insulating layer is preferably used as an insulating layer in contact with or near the oxide semiconductor layer. This insulating layer's hydrogen-barrier properties suppress hydrogen diffusion into the oxide semiconductor layer. In other words, a hydrogen-barrier insulating layer is an insulating layer that functions to suppress hydrogen diffusion.

[0451] Examples of insulating materials that can trap or fix hydrogen include oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing both aluminum and hafnium (hafnium aluminate), and hafnium silicate. Furthermore, these metal oxides may also contain zirconium; for example, oxides containing both hafnium and zirconium can be cited.

[0452] An insulating layer with the function of capturing or fixing hydrogen preferably has an amorphous structure. In metal oxides with an amorphous structure, the ability to capture or fix hydrogen is high because some oxygen atoms have dangling bonds. Therefore, by making the insulating layer have an amorphous structure, the function of capturing or fixing hydrogen can be improved.

[0453] By giving the insulating layer an amorphous structure, the formation of grain boundaries can be suppressed. Suppressing grain boundary formation improves the flatness of the insulating layer. This results in a more uniform thickness distribution of the insulating layer, reducing extremely thin sections and thus improving its withstand voltage. Furthermore, the thickness distribution of the film disposed on the insulating layer can be made more uniform. Moreover, by suppressing grain boundary formation in the insulating layer, leakage current originating from defect states at grain boundaries can be reduced. Therefore, the insulating layer can be used as an insulating film with low leakage current.

[0454] Furthermore, the function of capturing or fixing the corresponding substance can also be described as possessing the property that the corresponding substance is not easily diffused. Therefore, the function of capturing or fixing the corresponding substance can also be referred to as barrier property.

[0455] In this specification, the term "barrier insulating layer" refers to an insulating layer that possesses barrier properties. Furthermore, barrier properties refer to the property that makes it difficult for the corresponding substance to diffuse (also referred to as the property that makes it difficult for the corresponding substance to pass through, the property that the corresponding substance has low permeability, or the function of inhibiting the diffusion of the corresponding substance). Note that hydrogen, as described as the corresponding substance, refers to hydrogen atoms, hydrogen molecules, water molecules, and OH-. - At least one of the following: substances bonded to hydrogen. Furthermore, unless otherwise specified, the impurity described as the corresponding substance refers to impurities in the channel forming region or semiconductor layer, such as at least one of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N₂O, NO, NO₂, etc.), copper atoms, etc. Furthermore, the oxygen described as the corresponding substance refers to at least one of oxygen atoms and oxygen molecules, for example.

[0456] Materials that can be used as hydrogen barrier insulating layers include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), silicon nitride, or silicon oxynitride.

[0457] Inorganic insulating layers, exemplified as insulating layers that trap or fix hydrogen and those that inhibit hydrogen diffusion, also possess oxygen-barrier properties. Materials that serve as oxygen-barrier insulating layers include, for example, oxides containing one or both of aluminum and hafnium, magnesium oxide, zinc gallium oxide, silicon nitride, and silicon oxynitride. Furthermore, oxides containing one or both of aluminum and hafnium include, for example, aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and hafnium silicate.

[0458] [Conductive layer] The conductive layers (conductive layer 205, conductive layer 220, conductive layer 240, conductive layer 242a, conductive layer 242b, conductive layer 243a, conductive layer 243b, conductive layer 260, etc.) included in the semiconductor device preferably use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, and lanthanum, an alloy containing the above-mentioned metallic elements, or an alloy combining the above-mentioned metallic elements. As alloys containing the above-mentioned metallic elements, nitrides or oxides of the alloys may also be used. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc., are preferred. In addition, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicides can also be used.

[0459] Furthermore, nitrogen-containing conductive materials such as tantalum nitrides, titanium nitrides, molybdenum nitrides, tungsten nitrides, ruthenium nitrides, tantalum and aluminum nitrides, or titanium and aluminum nitrides; oxygen-containing conductive materials such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metallic elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are not easily oxidized, have the function of inhibiting oxygen diffusion, or maintain conductivity even when absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, ITO, indium tin oxide containing titanium oxide, ITSO, In-Zn oxide, and indium zinc oxide containing tungsten oxide. In this specification, conductive films deposited using oxygen-containing conductive materials are sometimes referred to as oxide conductive films.

[0460] Furthermore, multiple conductive layers formed from the aforementioned materials can be stacked. For example, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing oxygen can also be used. Furthermore, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing nitrogen can also be used. Additionally, a stacked structure combining materials containing the aforementioned metallic elements, conductive materials containing oxygen, and conductive materials containing nitrogen can also be used.

[0461] Furthermore, when using metal oxides in the channel formation region of a transistor, a stacked structure combining a material containing the aforementioned metal element and an oxygen-containing conductive material is preferably used as the conductive layer serving as the gate electrode. In this case, it is preferable to provide the oxygen-containing conductive material on one side of the channel formation region. By providing the oxygen-containing conductive material on one side of the channel formation region, oxygen detached from this conductive material can be easily supplied to the channel formation region.

[0462] [Substrate] Substrates for forming transistors can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconium oxide substrates (yttrium-stabilized zirconium oxide substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates composed of silicon carbide, silicon-germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon on Insulator) substrates, can also be used. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can be used. Furthermore, examples include insulating substrates with conductors or semiconductors, semiconductor substrates with conductors or insulators, and conductive substrates with semiconductors or insulators. Substrates on which components are disposed can also be used. Examples of components mounted on a substrate include capacitors, resistors, switching elements, light-emitting elements, and storage elements.

[0463] The above is a description of the materials that can be used in the semiconductor device of this embodiment.

[0464] This embodiment can be appropriately combined with other embodiments or examples. Furthermore, where multiple structural examples are shown in one embodiment in this specification, these structural examples can be appropriately combined.

[0465] Implementation 3 In this embodiment, a semiconductor device 900 according to one aspect of the present invention is described. The semiconductor device 900 can be used as a storage device.

[0466] Figure 27 This is a block diagram illustrating a structural example of a semiconductor device 900. Figure 27 The semiconductor device 900 shown includes a driving circuit 910 and a memory array 920. The memory array 920 includes one or more memory cells 950. Figure 27 An example of a memory array 920 including multiple memory cells 950 configured in a matrix is ​​shown.

[0467] The semiconductor device (transistor 200, transistor 200A, or transistor 200B) described in Embodiment 2 can be used in the memory cell 950. By using the transistors described in Embodiment 2, the operating speed of the memory device can be improved. Furthermore, miniaturization and high integration of the memory device can be achieved. In addition, the capacity per unit area of ​​the memory device can be increased.

[0468] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and peripheral circuit 915. The peripheral circuit 915 includes peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0469] In the semiconductor device 900, the aforementioned circuits, signals, and voltages can be appropriately selected or omitted as needed. Alternatively, other circuits or signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are signals input from the outside, while signal RDA is a signal output to the outside. Signal CLK is the clock signal.

[0470] In addition, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data signal, and signal RDA is the read data signal. Signals PON1 and PON2 are power gating control signals. Alternatively, signals PON1 and PON2 can also be generated in the control circuit 912.

[0471] The control circuit 912 is a logic circuit that controls the overall operation of the semiconductor device 900. For example, the control circuit 912 performs logical operations on signals CE, GW, and BW to determine the operating mode of the semiconductor device 900 (e.g., write operation, read operation). Alternatively, the control circuit 912 generates control signals for the peripheral circuit 911 to execute the aforementioned operating mode.

[0472] The voltage generation circuit 928 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input signal CLK to the voltage generation circuit 928. For example, when the signal WAKE is given a signal of level H, the signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage.

[0473] The peripheral circuit 911 is used to write and read data from the storage unit 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0474] Row decoder 941 and column decoder 942 are used to decode the signal ADDR. Row decoder 941 is used to specify the row to be accessed, and column decoder 942 is used to specify the column to be accessed. Row driver 923 is used to select the row specified by row decoder 941. Column driver 924 has the following functions: writing data to memory cell 950; reading data from memory cell 950; and storing the read data.

[0475] Input circuit 925 has the function of holding signal WDA. The data held in input circuit 925 is output to column driver 924. The output data of input circuit 925 is the data written to memory cell 950 (Din). The data read from memory cell 950 by column driver 924 (Dout) is output to output circuit 926. Output circuit 926 has the function of holding Dout. In addition, output circuit 926 has the function of outputting Dout to the outside of semiconductor device 900. The data output from output circuit 926 is signal RDA.

[0476] PSW931 controls the supply of V to the external circuit 915. DD The PSW932 has the function of controlling the supply of V to the line driver 923. HM The function of the semiconductor device 900. Here, the high power supply potential of the semiconductor device 900 is V. DD The low power supply potential is GND (ground potential). Additionally, V HM It is a high power supply potential used to make the word line high, which is higher than V. DD The PSW931 is controlled to turn on / off using signal PON1, and the PSW932 is controlled to turn on / off using signal PON2. Figure 27 In the middle, the peripheral circuit 915 is supplied with V DD The number of power domains can be 1, but it can also be multiple. In this case, a power switch can be set for each power domain.

[0477] Reference Figures 28A to 28G This section describes structural examples of other storage units that can be used in storage unit 950.

[0478] [DOSRAM] Figure 28A An example circuit structure of a DRAM (Dynamic Random Access Memory) type memory cell is shown. In this specification, DRAM using OS transistors is referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). Memory cell 951 includes transistor M1 and capacitor CA.

[0479] Transistor M1 may also include a front gate (sometimes simply referred to as the gate) and a back gate. In this case, the back gate can be connected to a wiring supplied with a constant potential or signal, or the front gate can be connected to the back gate.

[0480] The first terminal of transistor M1 is connected to the first terminal of capacitor CA, the second terminal of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL. The second terminal of capacitor CA is connected to wiring CAL.

[0481] The BIL (Bite Line) is used as the bit line, and the WOL (Word Line) is used as the word line. The CAL (Chip Line) is used to apply a specified potential to the second terminal of the capacitor CA. During data writing and reading, it is preferable to apply a low-level potential (sometimes called a reference potential) to the CAL.

[0482] Data writing and reading are performed by applying a high-level potential to the wiring WOL, which turns on the transistor M1, thereby making the wiring BIL and the first terminal of the capacitor CA conductive (allowing current to flow).

[0483] Furthermore, the memory cell that can be used as memory cell 950 is not limited to memory cell 951, and the circuit structure can be changed. For example, it can also be used... Figure 28B The structure of memory cell 952 is shown. Memory cell 952 is an example excluding capacitor CA and wiring CAL. The first terminal of transistor M1 is in a floating state.

[0484] In memory cell 952, the potential written by transistor M1 is maintained in the capacitance (also called parasitic capacitance) between the first terminal and the gate, as shown by the dashed line. By adopting this structure, the structure of the memory cell can be greatly simplified.

[0485] An OS transistor is preferably used as transistor M1. Using an OS transistor improves the operating speed of the memory device. Furthermore, OS transistors have extremely low off-state current. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made very small. This means that written data can be held in transistor M1 for a longer period, thereby reducing the refresh frequency of the memory cells. Furthermore, the refresh operation of the memory cells can be eliminated. Moreover, due to the very low leakage current, multi-valued data or analog data can be held in memory cells 951 and 952.

[0486] Here, refer to Figure 29 An example illustrating the structure of DOSRAM. Note that in Figure 29In the diagram, the X direction is parallel to the channel width direction of the transistor, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to both the X and Y directions.

[0487] like Figure 29 As shown, the memory cell 951 includes a transistor M1 and a capacitor CA. An insulating layer 284 is provided on the transistor M1. The insulating layer 284 can be an insulator that can be used for the insulating layer 216. Furthermore, the transistor M1 has the same structure as the transistor 200A shown in Embodiment 2, and the same reference numerals are used for the same constituent elements. For details about the transistor 200A, please refer to Embodiment 2. In addition, conductive layers 240b (conductive layers 240b1 and 240b2) are provided in contact with one of the source electrode and drain electrode (conductive layer 242b) of the transistor M1. The conductive layer 240b extends in the Z direction and is used as a wiring BIL. In addition, the conductive layer 260 of the transistor M1 extends in the X direction and is used as a wiring WOL.

[0488] The capacitor CA includes a conductive layer 453 on the conductive layer 242a, an insulating layer 454 on the conductive layer 453, and a conductive layer 460 (conductive layer 460a and conductive layer 460b) on the insulating layer 454.

[0489] At least a portion of each of the conductive layer 453, insulating layer 454, and conductive layer 460 is disposed inside the openings provided in insulating layers 271a, 275, 280, 282, 283, and 285. The end of each of the conductive layer 453, insulating layer 454, and conductive layer 460 is located at least on insulating layer 283, preferably on insulating layer 285. Insulating layer 454 is provided to cover the end of conductive layer 453. Thus, conductive layer 453 and conductive layer 460 are electrically insulated.

[0490] The deeper the openings in insulating layers 271a, 275, 280, 282, 283, and 285 (that is, increasing the thickness of one or more of insulating layers 271a, 275, 280, 282, 283, and 285), the larger the electrostatic capacitance of capacitor CA can be. By increasing the electrostatic capacitance per unit area of ​​capacitor CA, miniaturization or high integration of the memory device can be achieved. For example, the electrostatic capacitance of capacitor CA can be set by adjusting the thickness of insulating layer 285. Specifically, the thickness of insulating layer 285 is set in the range of 50 nm or more and 250 nm or less, and the depth of the openings can be approximately 150 nm or more and 350 nm or less. By forming capacitor CA within the above range, capacitor CA has sufficient electrostatic capacitance, and in a semiconductor device with multiple layers of memory cells stacked, the height of one layer is not excessively increased. In each of the multiple memory cell layers, the electrostatic capacitance of the capacitors provided in each memory cell can be different. When using this structure, for example, the thickness of the insulating layer 285 disposed in the layers of each memory cell can be different.

[0491] In capacitor CA, conductive layer 453 has a region serving as one electrode (lower electrode), and insulating layer 454 has a region serving as a dielectric. Conductive layer 460 has a region serving as the other electrode (upper electrode). Furthermore, the top of conductive layer 460 can be extended and used as wiring CAL. Capacitor CA constitutes a MIM (Metal-Insulator-Metal) capacitor.

[0492] Furthermore, the conductive layer 242a disposed on the semiconductor layer 230 in a manner overlapping with the semiconductor layer 230 is used as an electrode electrically connected to the lower electrode of the capacitor CA.

[0493] Conductive layers 453 and 460 can be formed using conductors suitable for conductive layers 205 and 260, respectively. Both conductive layers 453 and 460 are preferably deposited using high-coverage deposition methods such as ALD or CVD. For example, titanium nitride or tantalum nitride deposited using ALD or CVD can be used as conductive layer 453.

[0494] The top surface of conductive layer 242a is in contact with the bottom surface of conductive layer 453. Here, by using a conductive material with good conductivity as conductive layer 242a, the contact resistance between conductive layer 453 and conductive layer 242a can be reduced.

[0495] Furthermore, titanium nitride deposited using ALD or CVD methods can be used as conductive layer 460a, and tungsten deposited using CVD methods can be used as conductive layer 460b. Here, when the adhesion of the tungsten to the insulating layer 454 is sufficiently high, a single-layer structure of tungsten deposited using CVD methods can also be used as conductive layer 460.

[0496] The insulating layer 454 included in the capacitor CA is preferably made of a high-k material as described in the above embodiments. By using this high-k material, the insulating layer 454 can be thickened to the extent that leakage current can be suppressed, and the electrostatic capacitance of the capacitor CA can also be sufficiently ensured. Furthermore, the insulating layer 454 is preferably deposited using a deposition method with high coverage, such as ALD or CVD.

[0497] Furthermore, it is preferable to use insulators made of the aforementioned materials in a laminated manner, and it is preferable to use a laminated structure of materials with higher dielectric strength than high-k materials. For example, as insulating layer 454, an insulating film can be used that is laminated in the order of zirconium oxide, alumina, zirconium oxide. Alternatively, an insulating film can be used that is laminated in the order of zirconium oxide, alumina, zirconium oxide, alumina. Furthermore, an insulating film can be used that is laminated in the order of hafnium zirconium oxide, alumina, hafnium zirconium oxide, alumina. By using insulators with relatively high dielectric strength, such as alumina, in a laminated manner, the dielectric strength is increased, and thus electrostatic discharge damage to the capacitor CA can be suppressed.

[0498] Furthermore, as the insulating layer 454, a ferroelectric material described in the [insulating layer] of Embodiment 2 may also be used.

[0499] Ferroelectric materials are insulators that exhibit internal polarization when an external electric field is applied, and maintain polarization even when the electric field is zero. Therefore, non-volatile storage elements can be formed by using a capacitor (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. Non-volatile storage elements using ferroelectric capacitors are sometimes called FeRAM (Ferroelectric Random Access Memory), ferroelectric memory, etc. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, with one of the source and drain terminals of the transistor electrically connected to a terminal of the ferroelectric capacitor. Thus, when a ferroelectric capacitor is used as the capacitor CA, the storage device shown in this embodiment is used as a ferroelectric memory.

[0500] In the opening where the capacitor CA is located, the sidewall of the opening may be perpendicular or substantially perpendicular to the top surface of the insulating layer 222, and may also have a tapered shape. By having a tapered sidewall, the coverage of the conductive layer 453 and the like in the opening can be improved, thereby reducing defects such as voids.

[0501] A conductive layer 242b disposed on the semiconductor layer 230 in a manner overlapping the semiconductor layer 230 is used as wiring electrically connected to the conductive layer 240b. For example, in Figure 29 In the middle, the top surface and side ends of the conductive layer 242b are electrically connected to the conductive layer 240b extending in the Z direction.

[0502] When the conductive layer 240b directly contacts at least one of the top surface and side ends of the conductive layer 242b, no additional electrodes for connection are required, thus reducing the footprint of the memory array. Furthermore, the integration density of the memory cells is improved, allowing for an increase in the storage capacity of the memory device. Preferably, the conductive layer 240b contacts a portion of the top surface and the side ends of the conductive layer 242b. By having multiple surfaces of the conductive layer 240b in contact with the conductive layer 242b, the contact resistance between the conductive layers 240b and 242b can be reduced.

[0503] The conductive layer 240b is disposed in the openings formed in the insulating layers 216, 221, 222, 271b, 275, 280, 282, 283, 285 and 284.

[0504] In addition, such as Figure 29 As shown, the insulating layer 241b is preferably disposed in contact with the side surface of the conductive layer 240b. Specifically, the insulating layer 241b is disposed in contact with the inner wall of the opening of the insulating layers 216, 221, 222, 224, 271b, 275, 280, 282, 283, 285, and 284. Furthermore, an insulating layer 241b is also formed on the side surface of the semiconductor layer 230 protruding inside the opening. Here, at least a portion of the conductive layer 242b is exposed from the insulating layer 241b and in contact with the conductive layer 240b. That is, the conductive layer 240b is disposed in a manner that is embedded inside the opening through the insulating layer 241b.

[0505] like Figure 29 As shown, the uppermost part of the insulating layer 241b formed below the conductive layer 242b is preferably located below the top surface of the conductive layer 242b. With this structure, the conductive layer 240b can contact at least a portion of the side end of the conductive layer 242b. Furthermore, the insulating layer 241b formed below the conductive layer 242b preferably has a region that contacts the side surface of the semiconductor layer 230. With this structure, impurities such as water and hydrogen contained in the insulating layer 280 can be suppressed from mixing into the semiconductor layer 230 through the conductive layer 240b.

[0506] In the opening where the conductive layer 240b and the insulating layer 241b are disposed, the sidewall of the opening may be perpendicular or substantially perpendicular to the top surface of the insulating layer 222, or it may be tapered. By having a tapered sidewall, the coverage of the insulating layer 241b and the like provided in the opening is improved.

[0507] [NOSRAM] Figure 28C An example circuit structure of a gain-cell type memory cell including two transistors and one capacitor is shown. Memory cell 953 includes transistor M2, transistor M3, and capacitor CB. In this specification and the like, memory devices that include a gain-cell type memory cell using transistor OS as transistor M2 are sometimes referred to as NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0508] Transistor M2's first terminal is connected to capacitor CB's first terminal; transistor M2's second terminal is connected to wiring WBL; and transistor M2's gate is connected to wiring WOL. Capacitor CB's second terminal is connected to wiring CAL. Transistor M3's first terminal is connected to wiring RBL; transistor M3's second terminal is connected to wiring SL; and transistor M3's gate is connected to capacitor CB's first terminal.

[0509] Wiring WBL is used as the write bit line, wiring RBL as the read bit line, and wiring WOL as the word line. Wiring CAL is used to apply a predetermined potential to the second terminal of capacitor CB. During data writing, data holding, and data reading, it is preferable to apply a low-level potential (sometimes called a reference potential) to wiring CAL.

[0510] Data writing is performed by applying a high-level potential to wiring WOL, which turns on transistor M2, thus connecting wiring WBL to the first terminal of capacitor CB. Specifically, when transistor M2 is on, a potential corresponding to the information to be recorded is applied to wiring WBL to write that potential to the first terminal of capacitor CB and the gate of transistor M3. Then, a low-level potential is applied to wiring WOL, which turns on transistor M2, thereby maintaining the potential of the first terminal of capacitor CB and the potential of the gate of transistor M3.

[0511] Data is read out by applying a predetermined potential to the wiring SL. Since the current flowing between the source and drain of transistor M3 and the potential of the first terminal of transistor M3 are determined by the potential of the gate and the second terminal of transistor M3, the potential held by the first terminal of capacitor CB (or the gate of transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of transistor M3. In other words, the information written to the memory cell can be read from the potential held by the first terminal of capacitor CB (or the gate of transistor M3).

[0512] For example, a structure that combines the wiring WBL and wiring RBL into a single wiring BIL can also be adopted. Figure 28D An example of the circuit structure of the memory cell in this case is shown. In memory cell 954, the wiring WBL and wiring RBL of memory cell 953 are combined into a single wiring BIL, and the second terminal of transistor M2 and the first terminal of transistor M3 are connected to the wiring BIL. That is, memory cell 954 operates by combining the write bit line and the read bit line into a single wiring BIL.

[0513] Figure 28E The memory cell 955 shown is an example where the capacitor CB and wiring CAL of memory cell 953 are omitted. Furthermore, Figure 28F The memory cell 956 shown is an example of omitting the capacitor CB and wiring CAL found in memory cell 954. This structure improves the integration density of the memory cells.

[0514] Note that it is preferable to use the OS transistor as at least as transistor M2. In particular, it is preferable to use the OS transistor as both transistor M2 and transistor M3. By using the OS transistor as transistor M2, the written data can be held for a longer period of time using transistor M2, thereby reducing the refresh frequency of the memory cell. Furthermore, the refresh operation of the memory cell can be omitted. In addition, since the leakage current is very small, multi-value data or analog data can be held in memory cells 953 to 956.

[0515] The memory cells 953 to 956, which use OS transistors as transistor M2, are a form of NOSRAM.

[0516] Si transistors can also be used as transistor M3. Si transistors can improve field-effect mobility and can be p-channel transistors, thus increasing the freedom of circuit design.

[0517] also, Figure 28G A gain-cell type memory cell 957 with three transistors and one capacitor is shown. The memory cell 957 includes transistors M4 to M6 and capacitor CC.

[0518] Transistor M4's first terminal is connected to capacitor CC's first terminal; transistor M4's second terminal is connected to wiring BIL; and transistor M4's gate is connected to wiring WOL. Capacitor CC's second terminal is connected to transistor M5's first terminal and wiring GNDL. Transistor M5's second terminal is connected to transistor M6's first terminal; transistor M5's gate is connected to capacitor CC's first terminal. Transistor M6's second terminal is connected to wiring BIL; and transistor M6's gate is connected to wiring RWL.

[0519] The BIL (Bite Line) is used as the bit line, the WOL (Write Word Line) is used as the write word line, and the RWL (Read Word Line) is used as the read word line. The GNDL (Read Word Line) is used to supply a low-level potential.

[0520] Data writing is performed by applying a high-level potential to the wiring WOL, which turns on transistor M4, thus connecting the wiring BIL and the first terminal of capacitor CC. Specifically, when transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL to write that potential to the first terminal of capacitor CC and the gate of transistor M5. Then, a low-level potential is applied to the wiring WOL, which turns off transistor M4, thereby maintaining the potential of the first terminal of capacitor CC and the potential of the gate of transistor M5.

[0521] Data readout is performed by pre-charging the wiring BIL to a predetermined potential, then making the wiring BIL electrically floating and applying a high-level potential to the wiring RWL. By making the wiring RWL high, transistor M6 is turned on, and the wiring BIL and the second terminal of transistor M5 are connected. At this time, the potential of the wiring BIL is applied to the second terminal of transistor M5, but the potential of the second terminal of transistor M5 and the potential of the wiring BIL will change correspondingly to the potential held by the first terminal of capacitor CC (or the gate of transistor M5). Here, the potential held by the first terminal of capacitor CC (or the gate of transistor M5) can be read by reading the potential of the wiring BIL. In other words, the information written to the memory cell can be read from the potential held by the first terminal of capacitor CC (or the gate of transistor M5).

[0522] Note that it is preferable to use the OS transistor as at least transistor M4.

[0523] Si transistors can also be used as transistors M5 and M6. As mentioned above, the field-effect mobility of Si transistors is sometimes higher than that of OS transistors, depending on factors such as the crystallization state of the silicon used in the semiconductor layer.

[0524] The driving circuitry 910 and memory array 920 of the semiconductor device 900 can also be disposed on the same plane. Furthermore, as... Figure 30A As shown, the driving circuit 910 and the memory array 920 can also overlap. By overlapping the driving circuit 910 and the memory array 920, the signal transmission distance can be shortened. Figure 30B As shown, multiple memory arrays 920 can also be stacked on the drive circuit 910.

[0525] Here, refer to Figure 31 This section describes a structural example of a semiconductor device 900 formed by stacking multiple memory arrays 920.

[0526] Figure 31 The semiconductor device 900 shown includes: a driving circuit 910 having layers such as transistors 310; and memory arrays 920[1] to 920[m] on the driving circuit 910. Here, in Figure 31 In this invention, the layer located in the first (bottom) layer is denoted as memory array 920[1], the layer located in the second layer is denoted as memory array 920[2], and the layer located in the m-th (top) layer is denoted as memory array 920[m]. That is, in a storage device according to one aspect of the present invention, multiple layers including storage units may be included and multiple layers may be stacked.

[0527] Figure 31 The diagram shows a transistor 310 included in the drive circuit 910. The transistor 310 is disposed on a substrate 311 and includes a conductive layer 316 serving as a gate, an insulating layer 315 serving as a gate insulating layer, a semiconductor region 313 encompassing a portion of the substrate 311, and low-resistance regions 314a and 314b serving as source or drain regions. Furthermore, a component separation layer 318 is preferably provided between adjacent transistors 310. The transistor 310 can be a p-channel transistor or an n-channel transistor. For example, a single-crystal silicon substrate can be used as the substrate 311.

[0528] Here, in transistor 310, the semiconductor region 313 (a portion of substrate 311) forming the channel has a convex shape. Furthermore, a conductive layer 316 is provided such that it covers the sides and top surface of the semiconductor region 313 with an insulating layer 315 in between. The conductive layer 316 can also be made of a material with an adjustable work function. Because of the convex portion of the semiconductor substrate, this transistor 310 is also called a FIN-type transistor. Furthermore, an insulating layer for forming the convex portion can be provided such that it contacts the top of the convex portion. Although the case of forming the convex portion by processing a portion of the semiconductor substrate is shown here, a semiconductor film with a convex shape can also be formed by processing an SOI substrate.

[0529] Notice, Figure 31The structure of transistor 310 shown is only an example and is not limited to the above structure. Appropriate transistors can be used depending on the circuit structure or driving method.

[0530] Wiring layers, including interlayer films, wiring, and plugs, can also be provided between the various structures. Furthermore, multiple wiring layers can be provided depending on the design. Here, in conductive layers that function as plugs or wiring, the same symbol is sometimes used to represent multiple structures. Furthermore, in this specification, wiring and plugs electrically connected to wiring can also be considered as a single component. That is, a portion of the conductive layer is sometimes used as wiring, and a portion of the conductive layer is sometimes used as a plug.

[0531] For example, on transistor 310, insulating layers 320, 322, 324, and 326 are sequentially stacked as interlayer films. Furthermore, conductive layers 328 and the like are embedded in insulating layers 320 and 322. Furthermore, conductive layers 330 and the like are embedded in insulating layers 324 and 326. Furthermore, conductive layers 328 and 330 are used as contact plugs or wiring.

[0532] Furthermore, the insulating layer used as an interlayer film can also be used as a planarization film covering the uneven shape beneath it. For example, planarization can also be achieved by CMP treatment to improve the flatness of the top surface of the insulating layer 322.

[0533] As insulating layers that can be used as interlayer films, there are oxides, nitrides, oxynitrides, nitrogen oxides, metal oxides, metal oxynitrides, and metal nitrogen oxides, etc., which have insulating properties.

[0534] For example, by using a material with a low relative permittivity in the insulating layer used as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select the material according to the function of the insulating layer.

[0535] An insulating layer 208 is provided on the driving circuit 910, and a conductive layer 207 is provided in the opening formed in the insulating layer 208. Furthermore, an insulating layer 210 is provided on the insulating layer 208, and a conductive layer 209 is provided in the opening formed in the insulating layer 210. Additionally, an insulating layer 212 is provided on the insulating layer 210, and an insulating layer 214 is provided on the insulating layer 212. A portion of the conductive layer 240b provided in the memory array 920 [1] is embedded in the openings formed in the insulating layers 212 and 214. Here, the insulating layers 208 and 210 can be made of an insulator that can be used as the insulating layer 216.

[0536] The conductive layer 207 is used as wiring for electrical connection to the drive circuit 910. Furthermore, the top surface of the conductive layer 207 is arranged to contact the bottom surface of the conductive layer 209. Additionally, the top surface of the conductive layer 209 contacts the bottom surface of the conductive layer 240b disposed in the memory array 920 [1]. By employing this structure, the conductive layer 240b, which corresponds to the wiring BIL, can be electrically connected to the drive circuit 910.

[0537] The memory arrays 920[1] to 920[m] each include multiple memory cells 951. The conductive layer 240b included in each memory cell 951 is electrically connected to the upper conductive layer 240b and the lower conductive layer 240b.

[0538] like Figure 31 As shown, adjacent memory cells 951 share a common conductive layer 240b. Furthermore, in adjacent memory cells 951, the structures on the right and left sides are arranged symmetrically with the conductive layer 240b as the boundary.

[0539] Multiple memory arrays 920[1] to 920[m] can be stacked in the memory array 920 described above. By arranging the memory arrays 920[1] to 920[m] included in the memory array 920 in a direction perpendicular to the surface of the substrate on which the drive circuit 910 is provided, the storage density of the memory cell 951 can be increased. Furthermore, the memory array 920 can be manufactured by repeatedly using the same manufacturing process in the vertical direction. The semiconductor device 900 can reduce the manufacturing cost of the memory array 920.

[0540] Next, an example of an arithmetic processing device that may include the aforementioned storage device or other semiconductor device will be described.

[0541] Figure 32 This is a block diagram of the arithmetic unit 960. Figure 32 The computing device 960 shown can be used, for example, as a CPU. Furthermore, the computing device 960 can also be used with processors such as GPUs (Graphics Processing Units), TPUs (Tensor Processing Units), and NPUs (Neural Processing Units), which have more (tens or hundreds) processor cores than a CPU capable of parallel processing.

[0542] Figure 32The illustrated arithmetic unit 960 includes, on a substrate 961: an ALU 962 (ALU: Arithmetic Logic Unit), an ALU controller 962c, an instruction decoder 963, an interrupt controller 964, a timing controller 965, a register 966, a register controller 967, a bus interface 968, a cache 969, and a cache interface 969i. The substrate 961 can be a semiconductor substrate, an SOI substrate, a glass substrate, etc. It may also include a rewritable ROM and a ROM interface. The cache 969 and the cache interface 969i can also be located on different chips.

[0543] The cache 969 is connected to the main memory located on different chips via the cache interface 969i. The cache interface 969i has the function of supplying a portion of the data stored in the main memory to the cache 969. In addition, the cache interface 969i has the function of outputting a portion of the data held in the cache 969 to the ALU 962 or register 966, etc., via the bus interface 968.

[0544] As described later, the memory array 920 can be arranged in a manner that stacks on the computing device 960. The memory array 920 can be used as a cache. In this case, the cache interface 969i can have the function of supplying data held in the memory array 920 to the cache 969. Furthermore, in this case, it is preferable that a portion of the cache interface 969i includes a drive circuit 910.

[0545] Note that you can also omit cache 969 and use only memory array 920 as a cache.

[0546] Figure 32 The arithmetic device 960 shown is merely an example with a simplified structure; therefore, the actual arithmetic device 960 has various structures depending on its application. For example, it is preferable to include... Figure 32 The computing device 960 shown has a multi-core structure, which consists of a single core and multiple cores that operate simultaneously. The more cores, the better the computing performance. More cores are preferred; for example, two cores are preferred, four cores are more preferred, eight cores are even more preferred, twelve cores are still more preferred, and sixteen cores or more are even more preferred. Furthermore, when used in servers or other applications requiring very high computing performance, a multi-core structure with 16 or more cores is preferred, more preferably 32 or more cores, and more preferably 64 or more cores. Additionally, the number of bits that can be processed in the internal computing circuitry, data bus, etc., of the computing device 960 can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0547] Instructions input to the arithmetic unit 960 via the bus interface 968 are input to the instruction decoder 963 and, after being decoded, are input to the ALU controller 962c, interrupt controller 964, register controller 967, and timing controller 965.

[0548] The ALU controller 962c, interrupt controller 964, register controller 967, and timing controller 965 perform various controls based on the decoded instructions. Specifically, the ALU controller 962c generates signals to control the operation of the ALU 962. Furthermore, when the arithmetic unit 960 executes a program, the interrupt controller 964 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc., based on their priority and mask state. The register controller 967 generates the address of register 966 and reads or writes register 966 according to the state of the arithmetic unit 960.

[0549] Furthermore, the timing controller 965 generates signals for controlling the operating timing of the ALU 962, ALU controller 962c, instruction decoder 963, interrupt controller 964, and register controller 967. For example, the timing controller 965 has an internal clock generation unit that generates an internal clock signal based on a reference clock signal and supplies the internal clock signal to the aforementioned circuits.

[0550] exist Figure 32 In the illustrated arithmetic unit 960, the register controller 967 selects the holding operation of register 966 based on instructions from ALU 962. In other words, the register controller 967 selects whether data is held in the memory cells of register 966 by flip-flops or by capacitors. When data is held by flip-flops, a power supply potential is supplied to the memory cells in register 966. When data is held by capacitors, the data is overwritten to the capacitors, and the power supply potential to the memory cells in register 966 can be stopped.

[0551] The memory array 920 and the arithmetic unit 960 can be arranged overlappingly. Figure 33A and Figure 33B This is a perspective view of semiconductor device 970A. Semiconductor device 970A includes a layer 930 on a computing device 960, on which memory arrays are disposed. Layer 930 houses memory arrays 920L1, 920L2, and 920L3. The computing device 960 and each memory array have overlapping areas. To facilitate understanding of the structure of semiconductor device 970A, in... Figure 33B The computing device 960 and the layer 930 are shown separately in the middle.

[0552] By overlapping the layer 930, which includes the memory array, and the computing device 960, the connection distance between them can be shortened. This improves the communication speed between them. Furthermore, the shorter connection distance reduces power consumption.

[0553] As a stacking method for the layer 930 including the memory array and the arithmetic device 960, the following methods can be used: directly stacking the layer 930 including the memory array on the arithmetic device 960 (also known as monolithic stacking); or forming the arithmetic device 960 and the layer 930 on different substrates, bonding the two substrates together, and connecting them using bonding techniques such as through-holes or conductive films (Cu-Cu bonding, etc.). The former method does not require consideration of misalignment during bonding, thus reducing both chip size and manufacturing costs.

[0554] Here, the memory arrays 920L1, 920L2, and 920L3, which are disposed in layer 930 and do not include cache 969, can all be used as caches. For example, memory arrays 920L1, 920L2, and 920L3 can be used as L1 cache (also called level 1 cache), L2 cache (also called level 2 cache), and L3 cache (also called level 3 cache), respectively. Among the three memory arrays, memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, memory array 920L1 has the smallest capacity and the highest access frequency.

[0555] Note that when the cache 969 in the arithmetic unit 960 is used as an L1 cache, the memory arrays in layer 930 can be used as lower-level caches or main memory. Main memory is memory with a larger capacity and lower access frequency than cache.

[0556] In addition, such as Figure 33B As shown, drive circuits 910L1, 910L2, and 910L3 are provided. Drive circuit 910L1 is connected to memory array 920L1 via connection electrode 940L1. Similarly, drive circuit 910L2 is connected to memory array 920L2 via connection electrode 940L2, and drive circuit 910L3 is connected to memory array 920L3 via connection electrode 940L3.

[0557] Note that although the case shown here is a three-array memory used as a cache, it can also be one, two, or more than four.

[0558] When the memory array 920L1 is used as a cache, the driver circuit 910L1 can also be used as part of the cache interface 969i, and the driver circuit 910L1 can also be connected to the cache interface 969i. Similarly, the driver circuits 910L2 and 910L3 can also be used as part of the cache interface 969i or connected to a part of the cache interface 969i.

[0559] Whether the memory array 920 is used as a cache or as main memory depends on the control circuit 912 included in each drive circuit 910. The control circuit 912 can use a portion of the multiple memory cells 950 contained in the semiconductor device 900 as RAM based on signals supplied from the arithmetic unit 960.

[0560] In the semiconductor device 900, a portion of the multiple storage cells 950 can be used as a cache and the remainder as main memory. That is, the semiconductor device 900 can function as both a cache and main memory. The semiconductor device 900 according to one embodiment of the invention can, for example, be used as a general-purpose memory.

[0561] Alternatively, a layer 930 including a memory array 920 may be provided in a manner that overlaps with the computing device 960. Figure 34A This is a 3D view of the semiconductor device 970B.

[0562] In the semiconductor device 970B, a memory array 920 can be divided into multiple regions and assigned different functions for use. Figure 34A This shows an example of using region L1, region L2, and region L3 as L1 cache, L2 cache, and L3 cache, respectively.

[0563] Furthermore, in the semiconductor device 970B, the capacity of each of regions L1 to L3 can be changed according to the situation. For example, the capacity of the L1 cache can be increased by increasing the area of ​​region L1. By adopting this structure, efficient computational processing can be achieved, thereby increasing processing speed.

[0564] In addition, multiple memory arrays can be stacked. Figure 34B This is a 3D view of the semiconductor device 970C.

[0565] Semiconductor device 970C includes a layer 930L1 comprising a memory array 920L1, a layer 930L2 comprising a memory array 920L2, and a layer 930L3 comprising a memory array 920L3. The memory array 920L1, physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, furthest from the arithmetic unit 960, can be used as a lower-level cache or main memory. By employing this structure, the capacity of each memory array can be increased, thus further improving processing power.

[0566] This embodiment can be appropriately combined with other embodiments or examples. Furthermore, where multiple structural examples are shown in one embodiment in this specification, these structural examples can be appropriately combined.

[0567] Implementation Method 4 In this embodiment, refer to Figure 35 This section illustrates an example of the scope of a semiconductor device that can be used according to one aspect of the present invention. One aspect of the present invention provides a memory device that uses a transistor (hereinafter sometimes referred to as an OS transistor) that uses oxide as a semiconductor and a capacitor. Because the off-state current of an OS transistor is extremely small, a memory device using an OS transistor has excellent retention characteristics and can therefore be used as a non-volatile memory.

[0568] Semiconductor devices such as computers use various storage devices depending on their application. Figure 35 This is a conceptual diagram illustrating the hierarchy of a memory device used in semiconductor devices. Figure 35 In the diagram, a triangle is used to illustrate the hierarchy of storage devices. The higher up the triangle, the faster the operating speed of the storage device is required, while the lower down the triangle, the larger the storage capacity and the higher the recording density are required.

[0569] Figure 35 Starting from the top layer of the triangle, the diagram shows, in order, the memory installed as registers in computing devices such as CPU, GPU, and NPU; cache memory (sometimes simply referred to as cache; in addition, L1, L2, and L3 caches are typical); main memory, typically DRAM; and storage devices, typically 3D NAND and hard disk drives (HDDs).

[0570] Because the memory installed along with registers in computing devices such as CPUs, GPUs, and NPUs is used for temporary storage of computation results, it is accessed frequently by these devices. Therefore, a faster operating speed is required compared to a larger storage capacity. Furthermore, registers also have the function of holding settings information for the computing device.

[0571] Cache memory has the function of copying and maintaining a portion of the data held in DRAM. By copying and maintaining frequently used data in cache memory, the speed of data access can be improved. Cache memory requires less storage capacity than DRAM, but requires a faster operating speed. Furthermore, data that is overwritten in cache memory is copied and supplied to DRAM.

[0572] One embodiment of the present invention provides a storage device that can be used as DRAM.

[0573] Note that, although Figure 35 The cache memory shown in the diagram only illustrates L1 to L3 caches, but is not limited to this. For example, the storage device of one aspect of the present invention can also be used as the lowest level LLC (Last Level cache) or FLC (Final Level cache) in the cache.

[0574] DRAM has the function of storing programs, data, etc. read from 3D NAND.

[0575] 3D NAND has the ability to retain data that needs to be stored for a long time and various programs used by computing devices (such as models of artificial neural networks). Therefore, 3D NAND is required to have larger storage capacity and higher recording density compared to faster operating speeds.

[0576] Hard drives offer large capacity and non-volatility. Alternatively, SSDs (Solid State Drives) can be used as replacements for hard drives.

[0577] By using OS transistors, a storage device according to one aspect of the present invention can have a monolithic structure with integrated peripheral circuitry. Furthermore, by using OS transistors, a monolithic stack-up of integrated peripheral circuitry can also be achieved. Therefore, it offers advantages in data access with peripheral circuitry. In addition, since it can be stacked on top of peripheral circuitry, integration density can be increased. Moreover, a storage device according to one aspect of the present invention can use OS transistors to retain data for extended periods. Therefore, when using this storage device as DRAM, the refresh rate can be reduced.

[0578] Furthermore, a storage device according to one aspect of the present invention can use an OS transistor to reduce leakage current. Therefore, for example, even if the capacitor c...

Claims

1. A method for manufacturing a metal oxide layer, comprising the following steps: Formation of crystallization; and A crystalline metal oxide layer is formed using the crystalline portion as a nucleus. in, The metal oxide layer contains indium.

2. The method for manufacturing a metal oxide layer according to claim 1, The crystalline portion is formed by one grain of a polycrystalline film during its formation.

3. The method for manufacturing a metal oxide layer according to claim 1 further includes the following steps: An amorphous metal oxide film is formed before the formation of the crystalline portion. The crystalline portion is formed on the amorphous metal oxide film during the formation of the crystalline portion. Furthermore, the metal oxide layer is formed by crystallizing the amorphous metal oxide film during the formation of the crystalline metal oxide layer.

4. The method for manufacturing a metal oxide layer according to claim 1, The metal oxide layer is formed using atomic layer deposition. Furthermore, the substrate heating temperature is above 100℃ and below 300℃.

5. The method for manufacturing a metal oxide layer according to claim 1, The metal oxide layer is formed using atomic layer deposition. Furthermore, the substrate heating temperature is above 150°C and below 250°C.

6. A method for manufacturing a metal oxide layer, comprising the following steps: Crystallization is formed on the insulating layer; and A crystalline metal oxide layer is formed on the crystalline portion. in, The metal oxide layer contains indium. Furthermore, before forming the crystalline metal oxide layer, the top surface of the insulating layer is planarized by chemical mechanical polishing to set the average surface roughness of the top surface of the insulating layer to be greater than 0 nm and less than 3 nm.

7. The method for manufacturing a metal oxide layer according to claim 6, After the formation of the crystalline metal oxide layer, the metal oxide layer is subjected to lateral crystal growth.

8. The method for manufacturing a metal oxide layer according to claim 6, The crystalline portion is formed by forming a film that becomes the crystalline portion during the formation of the crystalline portion, and the film is processed by a wet etching method to form the crystalline portion.

9. The method for manufacturing a metal oxide layer according to claim 6, The crystal orientation of the grains contained in the metal oxide layer is as follows: <111> .

10. The method for manufacturing a metal oxide layer according to claim 9, The crystal orientation of the crystalline portion is as follows: <001> .

11. The method for manufacturing a metal oxide layer according to claim 9, The crystalline portion contains indium, gallium, and zinc. Furthermore, the atomic ratio of the crystallized portion is In:Ga:Zn = 1:1:1 or similar, or In:Ga:Zn = 1:3:2 or similar.

12. The method for manufacturing a metal oxide layer according to claim 6, The crystal orientation of the grains contained in the metal oxide layer is consistent with or substantially consistent with the crystal orientation of the crystalline portion.

13. The method for manufacturing a metal oxide layer according to claim 12, The crystalline portion contains indium.

14. A method for manufacturing a semiconductor device, comprising the following steps: Crystallization is formed on the first insulating layer; A crystalline metal oxide layer is formed using the crystalline portion as a nucleus; The metal oxide layer is processed into an island shape; A second insulating layer is formed covering the metal oxide layer; An opening overlapping the metal oxide layer is formed in the second insulating layer; A third insulating layer is formed in the opening; as well as A conductive layer is formed on the third insulating layer. The metal oxide layer therein contains indium.

15. The method for manufacturing a semiconductor device according to claim 14, The crystalline portion is formed by one grain of a polycrystalline film during its formation.

16. The method for manufacturing a semiconductor device according to claim 14, The metal oxide layer is formed using atomic layer deposition. Furthermore, the substrate heating temperature is above 100℃ and below 300℃.

17. The method for manufacturing a semiconductor device according to claim 14, The metal oxide layer is formed using atomic layer deposition. Furthermore, the substrate heating temperature is above 150°C and below 250°C.

18. The method for manufacturing a semiconductor device according to claim 14, The crystal orientation of the grains contained in the metal oxide layer is as follows: <111> .

19. The method for manufacturing a semiconductor device according to claim 18, The crystal orientation of the crystalline portion is as follows: <001> .

20. The method for manufacturing a semiconductor device according to claim 18, The crystalline portion contains indium, gallium, and zinc. Furthermore, the atomic ratio of the crystallized portion is In:Ga:Zn = 1:1:1 or similar, or In:Ga:Zn = 1:3:2 or similar.

21. The method for manufacturing a semiconductor device according to claim 14, The crystal orientation of the grains contained in the metal oxide layer is consistent with or substantially consistent with the crystal orientation of the crystalline portion.

22. The method for manufacturing a semiconductor device according to claim 21, The crystalline portion contains indium.

23. The method for manufacturing a metal oxide layer according to claim 1, The crystal orientation of the grains contained in the metal oxide layer is as follows: <111> .

24. The method for manufacturing a metal oxide layer according to claim 23, The crystal orientation of the crystalline portion is as follows: <001> .

25. The method for manufacturing a metal oxide layer according to claim 23, The crystalline portion contains indium, gallium, and zinc. Furthermore, the atomic ratio of the crystallized portion is In:Ga:Zn = 1:1:1 or similar, or In:Ga:Zn = 1:3:2 or similar.

26. The method for manufacturing a metal oxide layer according to claim 1, The crystal orientation of the grains contained in the metal oxide layer is consistent with or substantially consistent with the crystal orientation of the crystalline portion.

27. The method for manufacturing a metal oxide layer according to claim 26, The crystalline portion contains indium.

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