Preparation method of efficient N-type solar cell

Abstract

The invention provides a preparation method of a high-efficiency N-type solar cell, which comprises the following steps of: preparing a tunneling oxide layer of 1-2nm by adopting an ALD (Atomic Layer Deposition) technology, alternately and circularly introducing a precursor into a reaction cavity in a pulse form, and blowing before alternation at the temperature of 200-300 DEG C for 50-100 times; the polycrystalline silicon in-situ phosphorus doping is carried out by adopting LPCVD (Low Pressure Chemical Vapor Deposition), and phosphorus and phosphorus are simultaneously introduced into an LPCVD reaction chamber at the temperature of 600-700 DEG C; the tunneling oxide layer is prepared through ALD, a traditional chemical oxidation method or a thermal oxidation method is replaced, the uniformity and compactness of the tunneling oxide layer are improved, and the passivation effect is enhanced; the polycrystalline silicon layer deposition and doping process is optimized, the LPCVD in-situ doping technology is adopted, annealing steps and defects are reduced, the doping efficiency of the polycrystalline silicon layer is improved, the process steps are simplified, the cost is reduced, interface defects are reduced, and the long-term stability of the battery is improved.

Description

Technical Field

[0001] This invention belongs to the field of photovoltaic power generation technology, specifically relating to a method for preparing a high-efficiency N-type solar cell. Background Technology

[0002] TOPCon cells are high-efficiency solar cells based on tunneling silicon oxide passivation contact technology. Their core advantage lies in the superior surface passivation achieved through a combination of ultra-thin silicon oxide and polycrystalline silicon layers. Compared to PERC cells, TOPCon cells exhibit higher open-circuit voltage and conversion efficiency, making them a hot research topic in the photovoltaic field.

[0003] The existing fabrication technology for N-type TOPCon cells has the following main problems:

[0004] 1. Insufficient uniformity and density of tunnel oxide layer: The thickness of tunnel oxide layer prepared by traditional chemical oxidation or thermal oxidation method is not uniform, resulting in poor local passivation effect, which affects the open circuit voltage (Voc) and fill factor (FF) of battery.

[0005] 2. Low doping efficiency of polycrystalline silicon layer: Existing technologies typically use PECVD to deposit an amorphous silicon layer and then convert it into a polycrystalline silicon layer through high-temperature annealing. However, the doping efficiency is low, and multiple annealing processes are required, which increases the complexity and cost of the process.

[0006] 3. Numerous interface defects: The PECVD process easily introduces dangling bonds and interface state defects, reducing the long-term stability and reliability of the battery.

[0007] With the increasing demand in the industry for ultra-thin (<1.5nm) and pinhole-free tunneling layers, the existing N-type TOPCon cell fabrication technology can no longer meet the requirements and urgently needs to be improved. Summary of the Invention

[0008] The purpose of this invention is to provide a method for preparing a high-efficiency N-type solar cell, overcoming the aforementioned technical problems in the prior art.

[0009] Therefore, the technical solution provided by the present invention is as follows:

[0010] A method for fabricating a high-efficiency N-type solar cell, employing ALD technology to prepare a 1nm~2nm tunneling oxide layer, and a precursor... and The reaction chamber is alternately circulated in the form of pulses, and purging is performed before each alternation. The temperature is 200℃~300℃, and the number of cycles is 50~100.

[0011] In-situ phosphorus doping of polycrystalline silicon was performed using LPCVD, with the reaction chamber simultaneously circulated with... and The temperature is 600℃~700℃.

[0012] The precursor and The flow ratio is 1:5 to 1:10, where, The pulse waveform is a stepped pulse: The initial flow rate was 70 sccm~90 sccm, and the pulse duration was 0.1 s, after which... The flow rate is 10 sccm to 50 sccm, and the pulse duration is 0.1 s to 0.5 s; The flow rate is 50 sccm ~ 200 sccm, and the pulse time is 0.2s ~ 1s.

[0013] The chamber pressure of the ALD reaction chamber is 0.1 Torr~1 Torr.

[0014] The purging gas is nitrogen or Ar, with a flow rate of 200 sccm ~ 500 sccm;

[0015] The purging time is 3s~10s. The purging time is 5s~15s.

[0016] When performing in-situ phosphorus doping of polycrystalline silicon, simultaneously introducing... and During the process, dilution gas is introduced. ,in, and The flow ratio is 1:10 to 1:15. The flow rate is 80 sccm ~ 150 sccm. The flow rate is 50 sccm ~ 20 sccm, and dilution gas is introduced. The flow rate is 300 sccm to 800 sccm.

[0017] When performing in-situ phosphorus doping of polycrystalline silicon using LPCVD, the temperature is controlled by a gradient. The temperature in the inlet region of the reaction chamber is 615℃~625℃, the temperature in the center region is 645℃~655℃, and the temperature in the outlet region is 675℃~685℃.

[0018] When using LPCVD for in-situ phosphorus doping deposition in polycrystalline silicon, the pressure is 0.2 Torr~0.5 Torr, and the pressure during purging is no greater than 0.01 Torr.

[0019] Introducing into the LPCVD reaction chamber The time is 5s~6s, and It circulates continuously for 10 to 15 seconds.

[0020] A method for fabricating a high-efficiency N-type solar cell specifically includes the following steps:

[0021] Step 1) Texturing: The silicon wafer is etched with an alkaline solution to form a pyramidal textural structure;

[0022] Step 2) Frontal boron diffusion: Surface diffusion is performed using a boron source;

[0023] Step 3) Backside etching: Remove the BSG layer wrapped around the backside and polish with alkaline solution;

[0024] Step 4) Preparation of tunneling oxide layer: A 1nm~2nm ultrathin silicon oxide layer is prepared by ALD;

[0025] Step 5) In-situ phosphorus doping of polycrystalline silicon: In-situ phosphorus doping of polycrystalline silicon is performed on the back side using LPCVD;

[0026] Step 6) Front etching: Etch away the polysilicon thin film and PSG layer deposited around the edges and front side, and perform RCA cleaning;

[0027] Step 7) Front-side alumina passivation: A front-side alumina film is deposited using ALD atomic deposition.

[0028] Step 8) Front and back films: Hydrogen passivation is performed on the front and back sides of the silicon wafer by chemical vapor deposition, and silicon nitride films are deposited on the surface;

[0029] Step 9) Print and sinter.

[0030] The beneficial effects of this invention are:

[0031] The method for fabricating this high-efficiency N-type solar cell provided by this invention uses ALD to prepare a tunneling oxide layer, replacing the traditional chemical oxidation or thermal oxidation method, thereby improving the uniformity and density of the tunneling oxide layer and enhancing the passivation effect. The method also optimizes the polycrystalline silicon layer deposition and doping process by using LPCVD in-situ doping technology, reducing annealing steps and defects, improving the doping efficiency of the polycrystalline silicon layer, simplifying the process steps, reducing costs, reducing interface defects, and improving the long-term stability of the cell. Attached Figure Description

[0032] Figure 1 This is a flowchart of the method of the present invention. Detailed Implementation

[0033] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0034] Exemplary embodiments of the present invention will now be described with reference to the accompanying drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided to fully and completely disclose the invention and to fully convey its scope to those skilled in the art. The terminology used in the exemplary embodiments illustrated in the drawings is not intended to limit the invention.

[0035] Unless otherwise stated, the terms used herein (including technical terms) have their common meaning as understood by one of ordinary skill in the art. Furthermore, it is understood that terms defined in commonly used dictionaries should be understood to have a meaning consistent with the context of their relevant field, and not to be interpreted as having an idealized or overly formal meaning.

[0036] Example 1

[0037] This invention provides a method for fabricating a high-efficiency N-type solar cell, using ALD technology to prepare a 1nm~2nm tunneling oxide layer, and a precursor. and The reaction chamber is alternately circulated in the form of pulses, and purging is performed before each alternation. The temperature is 200℃~300℃, and the number of cycles is 50~100.

[0038] In-situ phosphorus doping of polycrystalline silicon was performed using LPCVD, with the reaction chamber simultaneously circulated with... and The temperature is 600℃~700℃.

[0039] Because early TOPCon cells had relatively low requirements for the density of the tunnel oxide layer, traditional oxidation methods (dry / wet oxidation) could meet the requirements, and the equipment was mature and inexpensive. PECVD silicon oxidation was attempted, but it resulted in poor uniformity, easily leading to localized pinhole defects and affecting passivation. ALD, due to its precursor ( + The cost is lower than that of traditional thermal oxidation (direct Si + Due to higher costs and temperature matching issues, it was not used for the preparation of tunnel oxide layers.

[0040] However, as the industry's demand for ultra-thin (<1.5nm), pinhole-free dense tunneling layers increases, this invention uses ALD technology to achieve precise deposition of tunneling oxide layers with atomic-level precision, especially in N-type TOPCon cells that pursue >25% efficiency.

[0041] The method for fabricating this high-efficiency N-type solar cell provided by this invention uses ALD to prepare a tunneling oxide layer, replacing the traditional chemical oxidation or thermal oxidation method, thereby improving the uniformity and density of the tunneling oxide layer and enhancing the passivation effect. The method also optimizes the polycrystalline silicon layer deposition and doping process by using LPCVD in-situ doping technology, reducing annealing steps and defects, improving the doping efficiency of the polycrystalline silicon layer, simplifying the process steps, reducing costs, reducing interface defects, and improving the long-term stability of the cell.

[0042] Example 2

[0043] Based on Example 1, this example provides a method for preparing a high-efficiency N-type solar cell, wherein the precursor... and The flow ratio is 1:5 to 1:10, where, The pulse waveform is a stepped pulse. The initial flow rate was 70 sccm~90 sccm, and the pulse duration was 0.1 s, after which... The flow rate is 10 sccm to 50 sccm, and the pulse duration is 0.1 s to 0.5 s; The flow rate is 50 sccm ~ 200 sccm, and the pulse time is 0.2s ~ 1s.

[0044] The chamber pressure of the ALD reaction chamber is 0.1 Torr to 1 Torr.

[0045] The purging gas is nitrogen or Ar, with a flow rate of 200 sccm ~ 500 sccm;

[0046] The purging time is 3s~10s. The purging time is 5s-15s.

[0047] ALD was used to prepare the tunneling oxide layer. The chamber pressure was 0.1 Torr to 1 Torr. The low-pressure environment improved the uniformity of the film layer, and the low temperature of 200℃ to 300℃ reduced the thermal budget and avoided damage to the substrate. The number of cycles was 50 to 100, resulting in a tunneling oxide layer thickness of 1 nm to 2 nm, with a single-cycle growth rate of 0.02 nm / cycle.

[0048] The flow rate is 10 sccm to 50 sccm, the pulse time is 0.1 s to 0.5 s to ensure surface saturation adsorption, and the purging time is 3 s to 10 s to avoid gas phase reaction.

[0049] The flow rate is 50 sccm ~ 200 sccm, the pulse time is 0.2s ~ 1s, and the purging time is 5s ~ 15s to ensure complete oxidation.

[0050] precursor and The flow ratio is 1:5 to 1:10 to achieve a pinhole-free ultrathin oxide layer.

[0051] The differences between this invention and existing methods for preparing tunneling oxide layers are shown in Table 1.

[0052] Table 1 Comparison between the present invention and the prior art

[0053]

[0054] To further illustrate the effectiveness of ALD in preparing the tunneling oxide layer in this invention, the following experimental examples and comparative examples were conducted.

[0055] Comparative Example 1:

[0056] Traditional thermal oxidation method (dry oxygen oxidation): The silicon wafer is placed in a quartz furnace tube, an inert gas (such as nitrogen or Ar) is introduced, the temperature is raised to 1000℃, and then switched to high-purity dry oxygen, so that the silicon wafer reacts directly with pure oxygen (O2) to produce The oxidation time is 5 minutes, followed by annealing under an inert atmosphere and finally cooling.

[0057] Comparative Example 2:

[0058] Using PECVD technology: The silicon wafer is placed in the PECVD reaction chamber, evacuated to a base pressure of 1 Torr, and heated to 300°C. Then, air is introduced... Plasma deposition was performed at a ratio of 1:10, followed by annealing.

[0059] Comparative Example 3:

[0060] ALD technology is used: precursor and The gas is alternately and cyclically introduced into the reaction chamber in pulses, and a purging process is performed before each alternation. : =1:3, The purging time is 2 seconds. The purging time is 3 seconds.

[0061] Experimental Group 1:

[0062] ALD technology is used: precursor and The reaction chamber is circulated alternately in pulses, and purging is performed before each pulse.

[0063] in, The pulse waveform is a stepped pulse, that is... The initial flow rate was 80 sccm to 50 sccm, and the pulse duration was 0.1 s. The flow rate was reduced to 30 sccm, and the pulse duration was 0.3 s; The flow rate is 50 sccm ~ 200 sccm, and the pulse duration is 0.6s. The number of cycles is 80.

[0064] The chamber pressure is 0.5 Torr - 1 Torr, and the temperature is 250℃.

[0065] The purging gas is nitrogen or Ar, with a flow rate of 200 sccm ~ 500 sccm;

[0066] The purging time is 3s-10s. The purging time is 5s-15s;

[0067] =1:8, The pulse duration is 0.3s. The pulse duration is 0.6s. The purging time is 10 seconds. The purging time is 15 seconds.

[0068] The parameters and performance of Comparative Example 1, Comparative Example 2, Comparative Example 3 and Experimental Example 1 were tested, and the results are shown in Table 1.

[0069] Table 1 Performance Comparison Data

[0070]

[0071] Table 1 shows that Comparative Example 1, using the dry oxidation method, resulted in a tunnel oxide layer with uneven thickness and high interface defects. Comparative Example 2, using PECVD technology, produced a tunnel oxide layer with pinhole defects, and compared to Comparative Example 3's ALD method, the VOC difference was greater than 20 mV. Although Comparative Example 3 used ALD technology, it did not... and The proportions were optimized, but insufficient purging resulted in a porous film and a minority carrier lifetime of less than 1 ms. Example 1 shows a tunneling oxide layer prepared using the optimized ALD method of this invention, with a thickness uniformity of ±0.1 nm and an interface defect density of <5 × 10¹. 0 cm -2 The deposition rate was increased by 20%, the film layer was dense, and the minority carrier lifetime was 2.3ms.

[0072] Example 3

[0073] Based on Example 1, this example provides a method for fabricating a high-efficiency N-type solar cell, wherein during in-situ phosphorus doping of polycrystalline silicon, a method is simultaneously introduced... and During the process, dilution gas is introduced. ,in, and The flow ratio is 1:10 to 1:15. The flow rate is 80 sccm ~ 150 sccm. The flow rate is 50 sccm ~ 20 sccm, and dilution gas is introduced. The flow rate is 300 sccm to 800 sccm.

[0074] When performing in-situ phosphorus doping of polycrystalline silicon using LPCVD, the temperature is controlled by a gradient. The temperature in the inlet region of the reaction chamber is 615℃-625℃, the temperature in the center region is 645℃-655℃, and the temperature in the outlet region is 675℃-685℃.

[0075] When using LPCVD for in-situ phosphorus doping deposition in polycrystalline silicon, the pressure is 0.2 Torr ~ 0.5 Torr, and the pressure during purging is no greater than 0.01 Torr.

[0076] Introducing into the LPCVD reaction chamber The time is 5s~6s, and It circulates continuously for 10 to 15 seconds.

[0077] To further illustrate the effect of LPCVD in-situ phosphorus doping of polycrystalline silicon in this invention, the following experimental examples and comparative examples were conducted.

[0078] Comparative Example 4:

[0079] Traditional two-step method (LPCVD + phosphorus diffusion): First, phosphorus is introduced into the LPCVD reaction chamber. The intrinsic polycrystalline silicon was deposited at a flow rate of 100-200 sccm at 600℃, and then POCl3 was introduced into a tube diffusion furnace for phosphorus diffusion at 850℃.

[0080] Comparative Example 5:

[0081] In-situ doping using LPCVD:

[0082] Simultaneously introduce into the LPCVD reaction chamber and The temperature is kept constant at 650℃. and The flow ratio is 1:20.

[0083] Comparative Example 6:

[0084] Polycrystalline silicon is doped using PECVD: Simultaneously, the reaction chamber is irradiated with... and The temperature is 450℃, and dilution gas is introduced. .

[0085] Experimental Example 2:

[0086] In-situ doping using LPCVD:

[0087] Simultaneously introduce into the LPCVD reaction chamber and Temperature gradient in three zones: inlet 620°C → center 650°C → outlet 680°C; The insertion time is 5 seconds. Continuous flow, flow time 10s, and through dilution, =120:10:500 (sccm). Excessive amounts were introduced. ,make The doping reaction was complete.

[0088] The vacuum level of the LPCVD reaction chamber is <1×10⁻⁶. -3 Torr (to reduce impurity contamination), substrate preheating: 600°C for 5 minutes (to eliminate thermal stress).

[0089] Temperature gradient control:

[0090] Entry zone: 620°C → Center zone: 650°C → Exit zone: 680°C, solving the doping fluctuation problem caused by axial temperature inhomogeneity in traditional LPCVD.

[0091] Pressure control:

[0092] Deposition stage: 0.2-0.5 Torr (balancing growth rate and film quality)

[0093] Purging phase: <0.01 Torr (complete removal of residual gas)

[0094] Deposition rate:

[0095] 2-5 nm / min (through) (Flow and temperature regulation)

[0096] Comparative Examples 4, 5, and 6, and Experimental Example 2 were tested for various parameters and performance. The results are shown in Table 2.

[0097] Table 2 Performance Comparison Data

[0098]

[0099] Table 2 shows that Comparative Example 4, due to the use of the traditional two-step method, has high interfacial recombination and uneven sheet resistance (±20%); Comparative Example 5, using LPCVD in-situ doping, has... and The flow rate and temperature were not optimized, resulting in large fluctuations in doping concentration (±15%). Comparative Example 6 used PECVD to dope polycrystalline silicon, which led to grain boundary defects, small grain size (<30nm), increased carrier scattering, reduced mobility, and minority carrier lifetime of 0.7ms.

[0100] Experimental Example 2 employs a temperature gradient to address the doping fluctuation problem caused by axial temperature inhomogeneity in traditional LPCVD, thereby improving doping uniformity (±8%). Compared to Comparative Example 4, it reduces... The flow rate is adjusted to avoid excessive deposition. Introduced for 5 seconds, SiH4 continued to flow for 10 seconds to prevent gas-phase nucleation; sheet resistance 80±5Ω / □; Dilution optimization adjusts reaction rate and improves homogeneity. =120:10:500 (sccm) makes the grain size >50nm, improves mobility, and increases minority carrier lifetime to 2ms.

[0101] LPCVD in-situ doping avoids subsequent diffusion steps, reducing defects and improving doping efficiency. Furthermore, compared to the traditional two-step method, this invention completes the process in one step, saving 30% of the process time; the interface defect density of the traditional two-step method is >1×10⁻⁶. 11 cm -2 This invention <5×10 10 cm -2 This can reduce the impact of high temperature diffusion on The destruction.

[0102] Example 4

[0103] Based on Example 1, this example provides a method for fabricating a high-efficiency N-type solar cell, such as... Figure 1 As shown, the specific steps include:

[0104] Step 1) Texturing: The silicon wafer is etched with an alkaline solution to form a pyramidal textural structure;

[0105] Step 2) Frontal boron diffusion: Surface diffusion is performed using a boron source;

[0106] Step 3) Backside etching: Remove the BSG layer wrapped around the backside and polish with alkaline solution;

[0107] Step 4) Preparation of tunneling oxide layer: A 1nm~2nm ultrathin silicon oxide layer is prepared by ALD;

[0108] Step 5) In-situ phosphorus doping of polycrystalline silicon: In-situ phosphorus doping of polycrystalline silicon is performed on the back side using LPCVD;

[0109] Step 6) Front etching: Etch away the polysilicon thin film and PSG layer deposited around the edges and front side, and perform RCA cleaning;

[0110] Step 7) Front-side alumina passivation: A front-side alumina film is deposited using ALD atomic deposition.

[0111] Step 8) Front and back films: Hydrogen passivation is performed on the front and back sides of the silicon wafer by chemical vapor deposition, and silicon nitride films are deposited on the surface;

[0112] Step 9) Print and sinter.

[0113] In step 4), =1:8, The pulse duration is 0.3s. The pulse duration is 0.6s. The purging time is 10 seconds. The purging time is 15 seconds.

[0114] In step 5), =120sccm, =10sccm, inlet 620°C → center 650°C → outlet 680°C, 0.3Torr.

[0115] Comparative Example 7:

[0116] In step 4), =1:8, The pulse duration is 0.3s. The pulse duration is 0.6s. The purging time is 10 seconds. The purging time is 15 seconds.

[0117] In step 5), =120sccm, =10 sccm, 650℃, 0.3 Torr. All other steps are the same as in Example 4.

[0118] Comparative Example 8:

[0119] In step 4), =1:8, The pulse duration is 0.3s. The pulse duration is 0.6s. The purging time is 10 seconds. The purging time is 15 seconds.

[0120] In step 5), =100sccm, =10 sccm, 650℃, 0.3 Torr. All other steps are the same as in Example 4.

[0121] Comparative Example 9:

[0122] In step 4), =1:5, The pulse duration is 0.3s. The pulse duration is 0.6s. The purging time is 10 seconds. The purging time is 15 seconds.

[0123] In step 5), =120sccm, =10 sccm, 650℃, 0.3 Torr. All other steps are the same as in Example 4.

[0124] Comparative Example 10:

[0125] In step 4), =1:10, The pulse duration is 0.3s. The pulse duration is 0.6s. The purging time is 10 seconds. The purging time is 15 seconds.

[0126] In step 5), =120sccm, =10 sccm, 650℃, 0.3 Torr. All other steps are the same as in Example 4.

[0127] Comparative Example 11

[0128] Step 4) Prepare the tunneling oxide layer using the traditional thermal oxidation method (dry oxygen oxidation): Place the silicon wafer in a quartz furnace tube, introduce an inert gas (such as nitrogen or Ar), heat to 1000℃, and then switch to high-purity dry oxygen, so that the silicon wafer is in contact with pure oxygen ( Direct reaction generates The oxidation time is 5 minutes, followed by annealing under an inert atmosphere and finally cooling.

[0129] Step 5) Using the traditional two-step method (LPCVD + phosphorus diffusion): First, introduce phosphorus into the LPCVD reaction chamber. Intrinsic polycrystalline silicon deposition was performed at 600°C with a flow rate of 100-200 sccm, followed by phosphorus diffusion at 850°C using POCl3 at a flow rate of 500-1000 sccm and nitrogen as the carrier gas, after which POCl3 was introduced into a tube diffusion furnace.

[0130] The electrical performance of the solar cells prepared in Example 4 and Comparative Examples 7, 8, 9, 10 and 11 was tested, and the results are shown in Table 3.

[0131] Table 3 Electrical performance test data

[0132]

[0133] The electrical performance of each cell was tested using an IV tester. As shown in Table 3, the cell prepared by Example 4 of the present invention achieved a conversion efficiency of 26.175%, which is significantly higher than that of the comparative examples, and significantly higher than that of Comparative Example 11 (26.010%). Moreover, it had the lowest reverse current (Irev2) (0.0141), proving that the synergistic effect of using ALD to prepare the tunneling oxide layer and using LPCVD in-situ doping can improve the cell efficiency and stability.

[0134] The above examples are merely illustrative of the present invention and do not constitute a limitation on the scope of protection of the present invention. All designs that are the same as or similar to the present invention are within the scope of protection of the present invention.

Claims

1. A method for preparing a high-efficiency N-type solar cell, characterized in that: A1nm~2nm tunneling oxide layer was prepared using ALD technology, precursor and The reaction chamber is alternately circulated in the form of pulses, and purging is performed before each alternation. The temperature is 200℃~300℃, and the number of cycles is 50~100. In-situ phosphorus doping of polycrystalline silicon was performed using LPCVD, with the reaction chamber simultaneously circulated with... and The temperature is 600℃~700℃.

2. The method for preparing a high-efficiency N-type solar cell according to claim 1, characterized in that: The precursor and The flow ratio is 1:5 to 1:10, where, The pulse waveform is a stepped pulse: The initial flow rate was 70 sccm~90 sccm, and the pulse duration was 0.1 s, after which... The flow rate is 10 sccm to 50 sccm, and the pulse duration is 0.1 s to 0.5 s; The flow rate is 50 sccm ~ 200 sccm, and the pulse time is 0.2s ~ 1s.

3. The method for preparing a high-efficiency N-type solar cell according to claim 1, characterized in that: The chamber pressure of the ALD reaction chamber is 0.1 Torr~1 Torr.

4. The method for preparing a high-efficiency N-type solar cell according to claim 1, characterized in that: The purging gas is nitrogen or Ar, with a flow rate of 200 sccm ~ 500 sccm; The purging time is 3s~10s. The purging time is 5s~15s.

5. The method for preparing a high-efficiency N-type solar cell according to claim 1, characterized in that: When performing in-situ phosphorus doping of polycrystalline silicon, simultaneously introducing... and During the process, dilution gas is introduced. ,in, and The flow ratio is 1:10 to 1:

15. The flow rate is 80 sccm ~ 150 sccm. The flow rate is 50 sccm ~ 20 sccm, and dilution gas is introduced. The flow rate is 300 sccm to 800 sccm.

6. The method for preparing a high-efficiency N-type solar cell according to claim 1, characterized in that: When performing in-situ phosphorus doping of polycrystalline silicon using LPCVD, the temperature is controlled by a gradient. The temperature in the inlet region of the reaction chamber is 615℃~625℃, the temperature in the center region is 645℃~655℃, and the temperature in the outlet region is 675℃~685℃.

7. The method for preparing a high-efficiency N-type solar cell according to claim 1, characterized in that: When using LPCVD for in-situ phosphorus doping deposition in polycrystalline silicon, the pressure is 0.2 Torr~0.5 Torr, and the pressure during purging is no greater than 0.01 Torr.

8. The method for preparing a high-efficiency N-type solar cell according to claim 1, characterized in that: Introducing into the LPCVD reaction chamber The time is 5s~6s, and It circulates continuously for 10 to 15 seconds.

9. A method for preparing a high-efficiency N-type solar cell according to any one of claims 1-8, characterized in that: Specifically, the following steps are included: Step 1) Texturing: The silicon wafer is etched with an alkaline solution to form a pyramidal textural structure; Step 2) Frontal boron diffusion: Surface diffusion is performed using a boron source; Step 3) Backside etching: Remove the BSG layer wrapped around the backside and polish with alkaline solution; Step 4) Preparation of tunneling oxide layer: A 1nm~2nm ultrathin silicon oxide layer is prepared using ALD; Step 5) In-situ phosphorus doping of polycrystalline silicon: In-situ phosphorus doping of polycrystalline silicon is performed on the back side using LPCVD; Step 6) Front etching: Etch away the polysilicon thin film and PSG layer deposited around the edges and front side, and perform RCA cleaning; Step 7) Front-side alumina passivation: A front-side alumina film is deposited using ALD atomic deposition. Step 8) Front and back films: Hydrogen passivation is performed on the front and back sides of the silicon wafer by chemical vapor deposition, and silicon nitride films are deposited on the surface; Step 9) Print and sinter.

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