System conversion method and device based on dynamic mapping rule

Abstract

The invention provides a system conversion method and device based on a dynamic mapping rule, and belongs to the technical field of computer systems. According to the system conversion method based on the dynamic mapping rule, the binary data set is dynamically converted into the ternary data sets in parallel by adopting the preset compression code table and the bit parallel conversion logic, so that the storage cost and hardware resource occupation are remarkably reduced, and the storage efficiency is improved. The efficient, flexible and reliable large-scale binary-to-ternary data conversion is realized, the conversion time is greatly shortened, and the conversion throughput is improved.

Description

Technical Field

[0001] This invention relates to the field of computer system technology, and in particular to a number system conversion method and apparatus based on dynamic mapping rules. Background Technology

[0002] With the evolution of computing architectures, particularly in areas such as novel storage media (e.g., high-speed multi-level cell), quantum computing, and dedicated AI chips, non-binary computing systems have demonstrated enormous potential in terms of information density and energy efficiency. Therefore, achieving data conversion between binary and ternary systems has become a crucial foundational technology.

[0003] While existing technologies offer solutions for specific scenarios, they still face significant limitations in meeting the demands for higher performance, lower power consumption, and more flexible applications. Traditional hardware lookup tables are a common method for number system conversion. For binary-to-ternary conversion, hardware lookup tables require pre-storing all mapping relationships. Taking a 4-bit binary number as an example, 4 bits can represent 16 different values ​​from 0 to 15. When converting 4 bits to a 2-Trit (2 bits in ternary can represent 0-8, but a more complex mapping relationship may be needed to cover 16 binary values), 16 mapping entries need to be stored. These entries consume storage resources, acting like a "code table," with each possible binary input corresponding to a ternary output.

[0004] For example, in hardware circuitry, this can be implemented using a memory. Each memory cell stores one mapping relationship. For the 4-bit binary to 2-Trit conversion described above, at least 16 memory cells are needed to store these mapping relationships. These memory cells will occupy a certain area on the physical chip, with an area ≥ 85 μm. 2 As the number of binary bits (n) increases, the number of mapping relationships that need to be stored grows exponentially (4n). This results in the memory occupying an increasingly larger area on the chip to store these mapping relationships. In large-scale data conversion scenarios, this storage method is clearly inefficient. For example, in big data processing or large-scale digital signal processing systems, if frequent binary-to-ternary conversions are required, storing a large number of mapping relationships using the traditional hardware lookup table method would make the memory area cost too high, limiting the system's scale and performance.

[0005] Therefore, improving the storage efficiency of hardware code tables is an urgent problem to be solved. Summary of the Invention

[0006] This invention provides a number system conversion method and apparatus based on dynamic mapping rules, which solves the problem of low storage efficiency of hardware code tables in the prior art and achieves the effect of improving conversion efficiency.

[0007] This invention provides a number system conversion method based on dynamic mapping rules, comprising:

[0008] Receives N-bit binary input data;

[0009] The N-bit binary input data is divided into multiple binary data groups;

[0010] According to the conversion mapping rules in the preset compression code table, the multiple binary data groups are converted into multiple ternary data groups in parallel through a combinational logic array composed of multiple parallel micro-conversion units; the conversion mapping rules are used to indicate non-carry mapping relationships; the preset compression code table is used to store the mapping rules when the value of a 2-bit binary group is not 11.

[0011] The generated multiple ternary data groups are concatenated to form an M-bit ternary output data; N and M are positive integers greater than 1.

[0012] According to the present invention, a number system conversion method based on dynamic mapping rules is provided. The method receives external control signals or input data through a rule selector, determines switching selection information, and dynamically switches between multiple sets of mapping rules in the preset compression code table to change the reconstruction logic of the ternary data group.

[0013] According to a number system conversion method based on dynamic mapping rules provided by the present invention, the binary input data is divided into a high-order binary data group and a low-order binary data group, and the method of converting the multiple binary data groups into multiple ternary data groups in parallel includes:

[0014] The high-order binary data group and the low-order binary data group are converted into two ternary data groups in parallel.

[0015] According to the present invention, a number system conversion method based on dynamic mapping rules is provided, wherein each of the micro-conversion units is a stateless combinational logic circuit;

[0016] Each of the micro-conversion units is used to convert a fixed-width binary data group to a corresponding ternary data group, and the conversion capability of the combinational logic array can be scaled by increasing or decreasing the number of the micro-conversion units.

[0017] According to the present invention, a number system conversion method based on dynamic mapping rules is provided, wherein the method is triggered by hardware data conversion instructions, the hardware data conversion instructions including loading instructions and conversion execution instructions.

[0018] According to the present invention, a number system conversion method based on dynamic mapping rules is provided, wherein the binary data group is a 4-bit hexadecimal data group.

[0019] The present invention also provides a number system conversion device based on dynamic mapping rules, comprising:

[0020] The receiving module is used to receive N-bit binary input data;

[0021] The first processing module is used to divide the N-bit binary input data into multiple binary data groups;

[0022] The second processing module is used to convert the multiple binary data groups into multiple ternary data groups in parallel through a pure combinational logic circuit composed of multiple parallel micro-conversion units, according to the conversion mapping rules in the preset compression code table; the conversion mapping rules are used to indicate non-carry mapping relationships; the preset compression code table is used to store the mapping rules when the value of a 2-bit binary group is not 11.

[0023] The splicing module is used to splice the generated multiple ternary data groups to form an M-bit ternary output data; N and M are positive integers greater than 1.

[0024] According to the present invention, a number system conversion device based on dynamic mapping rules is provided, the device being configured to adapt to N-bit binary input data of different bit widths by increasing or decreasing the number of micro-conversion units in the combinational logic array.

[0025] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the number system conversion method based on dynamic mapping rules as described above.

[0026] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the number system conversion method based on dynamic mapping rules as described above.

[0027] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements a number system conversion method based on dynamic mapping rules as described above.

[0028] The present invention provides a binary conversion method and apparatus based on dynamic mapping rules, which dynamically converts binary data groups into multiple ternary data groups in parallel by using a preset compressed code table and bit-parallel conversion logic. While significantly reducing storage costs and hardware resource consumption, it achieves efficient, flexible and reliable large-scale binary to ternary data conversion, greatly shortening the conversion time and improving the conversion throughput. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0030] Figure 1 This is a flowchart illustrating the number system conversion method based on dynamic mapping rules provided by the present invention.

[0031] Figure 2 This is a schematic diagram of the number system conversion device based on dynamic mapping rules provided by the present invention;

[0032] Figure 3 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0034] The following is combined Figures 1-3 The present invention describes a number system conversion method and apparatus based on dynamic mapping rules.

[0035] like Figure 1 As shown, the number system conversion method based on dynamic mapping rules in this embodiment of the invention can be implemented by a computer system, hereinafter referred to as the system. The number system conversion method based on dynamic mapping rules in this embodiment of the invention mainly includes steps 110, 120, 130, and 140.

[0036] Step 110: Receive N-bit binary input data.

[0037] The system can receive N-bit binary data from external sources via a data input interface or data bus. This data can originate from various data sources, such as sensors, storage devices, and network transmissions. For example, data collected by sensors is typically represented in binary form and is sent to the system for processing.

[0038] N is any positive integer greater than 1, indicating that the input data consists of an N-bit binary number. The binary data is a sequence of 0s and 1s, where each bit represents a specific numerical weight, numbered 2 from right to left. 0 2 1 2 2 ...For example, 4 bits of binary data can represent a decimal value between 0 and 15.

[0039] Step 120: Divide the N-bit binary input data into multiple binary data groups.

[0040] According to a preset partitioning rule, the received N-bit binary data can be divided into several smaller binary data groups. The purpose of this partitioning is to facilitate subsequent parallel processing and conversion. The number of bits in each data group can be determined according to actual needs and system design. For example, for 8-bit binary input data, it can be divided into two 4-bit binary data groups, or four 2-bit binary data groups, etc.

[0041] Step 130: According to the conversion mapping rules in the preset compression code table, multiple binary data groups are converted into multiple ternary data groups in parallel through a combinational logic array composed of multiple parallel micro-conversion units.

[0042] The conversion mapping rules are used to indicate non-carry mapping relationships; the preset compression code table is used to store the mapping rules when the value of a 2-bit binary group is not 11.

[0043] Ternary data is a sequence of numbers consisting of 0, 1, and 2. Each ternary number represents a specific numerical weight, starting with 3 from right to left. 0 3 1 3 2 Converting binary data to ternary data can better meet certain specific computing and data processing needs, such as in ternary computing systems or specific mixed-base computing scenarios.

[0044] Conversion mapping rules refer to mapping rules that can be dynamically adjusted according to certain conditions or needs during the number system conversion process. Unlike static mapping rules, these rules can flexibly change the mapping relationship between binary and ternary data based on different input data or external control signals, thereby better adapting to different data processing scenarios and needs.

[0045] The preset compressed code table is a specially designed and optimized mapping table used to store the mapping relationship between binary data and ternary data. The preset compressed code table only stores a portion of the key mapping entries, rather than storing all possible mapping relationships. In this embodiment, the compressed code table is mainly used to store the mapping rules when the value of a 2-bit binary group is not 11. This effectively reduces the storage space required by the code table and improves storage efficiency.

[0046] The combinational logic array composed of micro-conversion units is a circuit composed of various logic gates (such as AND gates, OR gates, NOT gates, NAND gates, NOR gates, etc.). This circuit has the characteristics of high speed and low latency, and is suitable for fast parallel processing and conversion of data. In this embodiment, it can be used to convert multiple binary data groups into ternary data groups in parallel.

[0047] Understandably, based on the conversion mapping rules in the preset compression code table, multiple binary data groups can be converted into multiple ternary data groups in parallel through a pure combinational logic circuit composed of multiple parallel micro-conversion units.

[0048] First, the divided binary data groups are input into their respective micro-conversion units. Each micro-conversion unit is a pure combinational logic circuit that converts the input binary data groups according to the conversion mapping rules in a preset compression code table.

[0049] Binary data groups can be 4-bit hexadecimal data groups. Hexadecimal is a commonly used number system, where each hexadecimal digit can be represented by 4 binary digits, with a value range of 0-15, corresponding to binary representations of 0000-1111. In this embodiment, the binary input data is divided into 4-bit binary data groups, and each such data group can be considered a hexadecimal data group. For example, the binary data 10110100 can be divided into two 4-bit hexadecimal data groups: 1011 and 0100.

[0050] Understandably, processing and converting binary data into 4-bit hexadecimal data groups can better utilize the advantages of hexadecimal and improve data processing efficiency and readability.

[0051] Based on this, during the conversion process, since a compressed code table is used, which only stores the mapping rules for 2-bit binary groups whose values ​​are not 11, for the input binary data group, if its value is not 11, it can be directly converted according to the mapping rules in the compressed code table; if its value is 11, it can be processed in a special way, such as converting it to a preset ternary value (such as TC, which represents carry or special mark) or deducing and converting it according to certain logical rules.

[0052] Understandably, multiple parallel micro-conversion units simultaneously convert their respective binary data sets, achieving parallel processing and significantly improving conversion efficiency. For example, if there are four binary data sets input into four parallel micro-conversion units, and each micro-conversion unit converts one binary data set simultaneously, then four conversion operations can be completed in the same amount of time, which is a significant speed improvement compared to the traditional serial conversion method.

[0053] Step 140: Concatenate the generated multiple ternary data groups to form an M-bit ternary output data.

[0054] Based on this, multiple generated ternary data groups can be concatenated to form an M-bit ternary output data, where M is a positive integer greater than 1.

[0055] After completing the parallel conversion of all binary data groups, the resulting multiple ternary data groups are concatenated in a specific order to form the final M-bit ternary output data. The concatenation order should correspond to the order in which the binary data groups were divided to ensure the correctness and integrity of the converted ternary data. For example, if 8-bit binary data is divided into two 4-bit binary data groups, and each is converted into two 2-bit ternary data groups, then during concatenation, these two 2-bit ternary data groups are combined into a single 4-bit ternary output data.

[0056] Understandably, by dividing N-bit binary input data into multiple binary data groups and using a pure combinational logic circuit composed of multiple parallel micro-conversion units for parallel conversion, the conversion time is significantly shortened and the conversion throughput is improved. Compared with traditional serial conversion methods, this achieves an order-of-magnitude performance improvement, making it particularly suitable for large-scale data conversion scenarios and meeting the real-time requirements of applications.

[0057] Furthermore, by employing a pre-defined compressed code table, which stores only the mapping rules for 2-bit binary groups whose values ​​are not 11, the storage space required for the code table is significantly reduced. For example, in the conversion from 4-bit binary to 2-bit ternary, the traditional method requires storing 16 mapping entries, while the compressed code table using this technology only requires storing 9 mapping entries, reducing storage space by 44%. For large-scale data conversion systems, this can significantly reduce storage costs and hardware resource consumption.

[0058] According to an embodiment of the present invention, a binary-to-ternary conversion method based on dynamic mapping rules is provided. By employing a preset compressed code table and bit-parallel conversion logic, binary data groups are dynamically converted into multiple ternary data groups in parallel. This significantly reduces storage costs and hardware resource consumption while achieving efficient, flexible, and reliable large-scale binary-to-ternary data conversion, greatly shortening the conversion time and improving the conversion throughput.

[0059] In some embodiments, a rule selector can be used to receive external control signals or input data to determine switching selection information, so as to dynamically switch between multiple sets of mapping rules in a preset compression code table to change the reconstruction logic of the ternary data group.

[0060] A rule selector is a logic circuit or control unit used to select and switch mapping rules. It can dynamically determine which mapping rule should be used for conversion based on conditions such as external control signals or the characteristics of input data, and transmit the corresponding selection information to the micro-conversion unit to control its conversion logic.

[0061] In this embodiment, information generated by the rule selector indicates the switching between multiple sets of mapping rules in a preset compression code table. This information includes the identifier of the currently selected mapping rule or other relevant control parameters, which guide the micro-conversion unit on how to convert the input binary data group to achieve dynamic changes in the reconstruction logic of the ternary data group.

[0062] Dynamic switching can be performed at different times, for different input data, or according to different external control signals, enabling the system to flexibly adapt to various complex and ever-changing data processing scenarios and meet different application needs.

[0063] Specifically, the rule selector can receive control signals or input data from external sources through a dedicated signal interface or data channel. External control signals can be instructions sent by system software, control parameters input by the user, or signals sent by other external devices; input data can be binary data to be converted or other relevant data characteristic information.

[0064] For example, in an application scenario that requires different conversion processes based on different sensor data types, the rule selector can receive signals from the sensor type recognition module to determine which mapping rule should be used for the conversion.

[0065] The rule selector analyzes and processes received external control signals or input data, and determines the current switching selection information based on preset rule selection logic. This switching selection information includes an indication of which mapping rule to select from a preset compression code table for conversion. For example, if three sets of mapping rules are preset to process different types of data (such as image data, voice data, sensor data, etc.), the rule selector can determine the type of the current data based on the characteristics of the received external control signals or input data, and determine the corresponding mapping rule to generate the corresponding switching selection information.

[0066] The rule selector can send the generated switching selection information to each micro-conversion unit. The micro-conversion unit dynamically switches between multiple sets of mapping rules in a preset compression code table based on the received switching selection information. Different mapping rules correspond to different conversion logics and ternary data group generation methods. By switching mapping rules, the reconstruction logic of ternary data groups can be changed, thereby achieving flexible adaptation to different input data or different application scenarios.

[0067] For example, when processing image data, one can choose a mapping rule that emphasizes data accuracy and detail; while when processing voice data, one can choose a mapping rule that focuses more on data compression and transmission efficiency, in order to meet the different requirements of different data types for the conversion results.

[0068] Understandably, through rule selectors and dynamic switching mechanisms, the system can flexibly choose appropriate mapping rules for transformation based on different external conditions and input data characteristics, better adapting to various complex and ever-changing application scenarios and data types. This gives the system wider applicability and stronger versatility, meeting the diverse needs of different users and business scenarios. For different types of data and application scenarios, specially optimized mapping rules can be used for transformation, thereby improving the accuracy and reliability of the transformation results. For example, when processing high-precision scientific computing data, more accurate mapping rules can be used to reduce transformation errors; when processing data transmission scenarios with high real-time requirements, more efficient mapping rules can be used to ensure the timeliness and integrity of the data.

[0069] Furthermore, by utilizing the dynamic switching function, the system can flexibly switch between different mapping rules, which is equivalent to having multiple different number system conversion functions. This gives the system good versatility and reconfigurability. It can support different data processing tasks through simple rule switching without large-scale modifications to the hardware circuit, thus reducing the system's development cost and maintenance difficulty.

[0070] In some embodiments, binary input data is divided into a high-order binary data group and a low-order binary data group, and multiple binary data groups are converted into multiple ternary data groups in parallel, including: converting the high-order binary data group and the low-order binary data group into two ternary data groups in parallel.

[0071] After dividing N-bit binary input data into a high-order binary data group and a low-order binary data group, the high-order binary data group refers to the group containing the higher-order bits of the binary data. For example, in 8-bit binary data, if it is divided into two groups of high 4 bits and low 4 bits, then the binary data group consisting of the high 4 bits is the high-order binary data group, which represents the larger numerical weight.

[0072] Corresponding to the high-order binary data group, the low-order binary data group contains the lower-order portions of the binary data. In the example of dividing 8-bit binary data above, the low-order binary data group, consisting of the lower 4 bits, represents the smaller numerical weight portion.

[0073] It should be noted that parallel conversion can process multiple data groups simultaneously, rather than sequentially. In this embodiment, the high-order binary data group and the low-order binary data group are input into their respective micro-conversion units. The two micro-conversion units simultaneously convert their respective binary data groups, thereby achieving parallel conversion and improving conversion efficiency.

[0074] Specifically, based on the number of bits in the data and the system design requirements, the received N-bit binary input data can be divided into a high-order binary data group and a low-order binary data group. The division can be of equal length or unequal length depending on the actual needs. For example, for 16-bit binary input data, it can be divided into two binary data groups: a high 8-bit group and a low 8-bit group; or for 12-bit binary input data, it can be divided into two data groups: a high 5-bit group and a low 7-bit group, and so on. The purpose of this division is to separate the data into two parts for parallel conversion processing, thereby fully utilizing the advantages of parallel conversion and improving the conversion speed.

[0075] Understandably, the high-order and low-order binary data groups are input into two different micro-conversion units. Each micro-conversion unit converts the input binary data group according to the conversion mapping rules in a preset compression code table. During the conversion process, the two micro-conversion units work simultaneously, independently processing their respective binary data groups and outputting the converted ternary data groups in parallel. For example, if both the high-order and low-order binary data groups are 4 bits, then each micro-conversion unit converts the 4-bit binary data group into a 2-bit or 3-bit ternary data group, and both micro-conversion units complete the conversion and output the results simultaneously.

[0076] Finally, the two resulting ternary data groups can be concatenated in order of most significant byte first, least significant byte last, to form the final M-bit ternary output data. For example, if the ternary data group converted from the most significant binary data group is 3 bits and the ternary data group converted from the least significant binary data group is 2 bits, then the concatenated ternary output data will be 5 bits, with the most significant ternary data group first and the least significant ternary data group last, forming a complete ternary value.

[0077] In this embodiment, by dividing the binary input data into two groups, high-order bits and low-order bits, and performing parallel conversion on these two groups, parallel processing can be achieved at a finer granularity, making full use of hardware resources, further shortening conversion time, and improving system conversion efficiency. Compared with parallel conversion of only multiple large-order bit groups, this parallel conversion method based on high-order bit partitioning can more effectively exploit parallelism, and is especially suitable for medium-scale data conversion scenarios, achieving higher performance improvements with limited hardware resources.

[0078] Furthermore, dividing the data into high and low byte groups for processing simplifies the system's circuit design and logic control. Compared to dividing the data into multiple smaller groups for parallel conversion, this two-group parallel approach is relatively simple in terms of control logic and signal transmission, reducing the complexity of system design and implementation. It also reduces potential errors and failure points, improving the system's reliability and stability.

[0079] In some embodiments, each micro-conversion unit is a stateless combinational logic circuit; each micro-conversion unit is used to convert a fixed-width binary data group to a corresponding ternary data group, and the conversion capability of the combinational logic array is scaled by increasing or decreasing the number of micro-conversion units.

[0080] The micro-conversion unit is used to convert fixed-width binary data blocks into corresponding ternary data blocks. Each micro-conversion unit contains specific logic circuits that perform conversion operations on the input binary data according to the conversion mapping rules in a preset compression code table. It is a stateless circuit module whose output depends only on the current input signal, and it features fast and stable operation.

[0081] Fixed bit width means that the number of bits in a binary data group processed by each micro-conversion unit is fixed. For example, one micro-conversion unit can be designed to handle the conversion of a 2-bit binary data group to a 1-bit or 2-bit ternary data group; another micro-conversion unit can handle the conversion of a 4-bit binary data group to a 2-bit or 3-bit ternary data group, and so on. Fixed bit width design helps simplify the circuit structure of the micro-conversion unit, improves the accuracy and efficiency of the conversion, and also facilitates the selection and combination of appropriate micro-conversion units according to actual system requirements.

[0082] Understandably, by increasing or decreasing the number of micro-conversion units, the system's conversion capability can be easily adjusted to adapt to different data processing scales and needs. When the amount of data to be processed is large or the conversion speed requirement is high, the number of micro-conversion units can be increased to achieve larger-scale parallel conversion and improve system throughput; conversely, when the amount of data is small or the conversion speed requirement is low, the number of micro-conversion units can be reduced to lower hardware costs and power consumption.

[0083] For example, in a system that needs to convert 16-bit binary data, eight micro-conversion units can be used, each processing two bits of binary data, to achieve eight-way parallel conversion. If the subsequent requirement changes to converting 8-bit binary data, this can be reduced to four micro-conversion units, each processing two bits of binary data, or other suitable combinations can be used to meet different conversion capability requirements. For a micro-conversion unit that processes two bits of binary data into one ternary data, its combinational logic circuit can be designed as follows: when the input binary data is 00, the output ternary data is 0; when the input is 01, the output is 1; when the input is 10, the output is 2; and when the input is 11, the output is TC (special marker).

[0084] In some embodiments, the number system conversion method based on dynamic mapping rules of the present invention is triggered by hardware data conversion instructions, which include loading instructions and conversion execution instructions.

[0085] Hardware data conversion instructions are instructions that run on hardware devices (such as processors, application-specific integrated circuits, etc.) and are used to trigger and control the execution of number system conversion operations. These instructions are encoded in the hardware circuitry and can be directly recognized and executed by the hardware without the need for complex interpretation and conversion at the software level.

[0086] Load instructions are hardware data conversion instructions used to load binary data to be converted from memory or other data sources into the input buffer or registers of the radix conversion system. Load instructions typically include operands such as source address and destination address, indicating where the data is loaded from and where it is loaded to, preparing the data for subsequent conversion operations.

[0087] Conversion execution instructions are another type of hardware data conversion instruction used to initiate the conversion operation of a number system. They convert binary data loaded into the input buffer or register according to a preset conversion mapping rule and store the conversion result in a specified output buffer or register. Conversion execution instructions can control the start and end of the conversion, as well as various parameter configurations during the conversion process, and are the core instructions for implementing number system conversion functionality.

[0088] On hardware devices, corresponding program code is written and executed to issue hardware data conversion instructions. For example, in a processor-based system, a program containing specific machine code is compiled and run; the instructions corresponding to that machine code are the hardware data conversion instructions. When the processor executes this instruction, it triggers the conversion operation of the number system.

[0089] After the load instruction is recognized by the hardware, the N-bit binary input data to be converted is read from memory or other data sources according to the source address specified in the instruction, and loaded into the input buffer or register of the radix conversion system. During the loading process, the data may need to undergo bus transfer, buffering, alignment, and other operations to ensure that the data can be correctly and completely transmitted to the input terminal of the radix conversion system. For example, if the binary data is stored in external memory, the load instruction will trigger the data to be transferred from external memory to the processor's internal input buffer via the data bus.

[0090] Understandably, triggering the conversion process through hardware data conversion instructions enables efficient initiation and control of data conversion. Hardware instructions execute quickly with low latency, rapidly loading data into the conversion system and initiating the conversion operation, significantly improving the overall efficiency of data conversion and better meeting the needs of applications with high real-time requirements.

[0091] The following describes the number system conversion device based on dynamic mapping rules provided by the present invention. The number system conversion device based on dynamic mapping rules described below can be referred to in correspondence with the number system conversion method based on dynamic mapping rules described above.

[0092] like Figure 2 As shown, the number system conversion device based on dynamic mapping rules in this embodiment of the invention includes a receiving module 210, a first processing module 220, a second processing module 230, and a splicing module 240.

[0093] The receiving module 210 is used to receive N-bit binary input data;

[0094] The first processing module 220 is used to divide the N-bit binary input data into multiple binary data groups;

[0095] The second processing module 230 is used to convert multiple binary data groups into multiple ternary data groups in parallel through a pure combinational logic circuit composed of multiple parallel micro-conversion units, according to the conversion mapping rules in the preset compression code table; the conversion mapping rules are used to indicate non-carry mapping relationships; the preset compression code table is used to store the mapping rules when the value of a 2-bit binary group is not 11.

[0096] The splicing module 240 is used to splice multiple generated ternary data groups to form an M-bit ternary output data; N and M are positive integers greater than 1.

[0097] The binary conversion device based on dynamic mapping rules provided by the present invention dynamically converts binary data groups into multiple ternary data groups in parallel by using a preset compression code table and bit-parallel conversion logic. While significantly reducing storage costs and hardware resource consumption, it achieves efficient, flexible, and reliable large-scale binary-to-ternary data conversion, greatly shortening the conversion time and improving the conversion throughput.

[0098] In some embodiments, the number system conversion device based on dynamic mapping rules of the present invention is configured to adapt to N-bit binary input data of different bit widths by increasing or decreasing the number of micro-conversion units in the combinational logic array.

[0099] Figure 3 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 3 As shown, the electronic device may include: a processor 310, a communication interface 320, a memory 330, and a communication bus 340, wherein the processor 310, the communication interface 320, and the memory 330 communicate with each other through the communication bus 340. The processor 310 can call logic instructions in the memory 330 to execute a number base conversion method based on dynamic mapping rules. The method includes: receiving N-bit binary input data; dividing the N-bit binary input data into multiple binary data groups; converting the multiple binary data groups into multiple ternary data groups in parallel through a combinational logic array composed of multiple parallel micro-conversion units according to the conversion mapping rules in a preset compression code table; the conversion mapping rules are used to indicate non-carry mapping relationships; the preset compression code table is used to store the mapping rules when the value of a 2-bit binary group is not 11; and concatenating the generated multiple ternary data groups to form an M-bit ternary output data; where N and M are positive integers greater than 1.

[0100] Furthermore, the logical instructions in the aforementioned memory 330 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0101] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the number base conversion method based on dynamic mapping rules provided by the above methods. The method includes: receiving N-bit binary input data; dividing the N-bit binary input data into multiple binary data groups; converting the multiple binary data groups into multiple ternary data groups in parallel through a combinational logic array composed of multiple parallel micro-conversion units according to the conversion mapping rules in a preset compression code table; the conversion mapping rules are used to indicate non-carry mapping relationships; the preset compression code table is used to store the mapping rules when the value of a 2-bit binary group is not 11; and concatenating the generated multiple ternary data groups to form an M-bit ternary output data; where N and M are positive integers greater than 1.

[0102] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the number system conversion method based on dynamic mapping rules provided by the above methods. The method includes: receiving N-bit binary input data; dividing the N-bit binary input data into multiple binary data groups; converting the multiple binary data groups into multiple ternary data groups in parallel using a combinational logic array composed of multiple juxtaposed micro-conversion units according to conversion mapping rules in a preset compressed code table; the conversion mapping rules are used to indicate non-carry mapping relationships; the preset compressed code table is used to store mapping rules when the value of a 2-bit binary group is not 11; concatenating the generated multiple ternary data groups to form an M-bit ternary output data; where N and M are positive integers greater than 1.

[0103] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0104] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0105] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A number system conversion method based on dynamic mapping rules, characterized in that, include: Receives N-bit binary input data; The N-bit binary input data is divided into multiple binary data groups; According to the conversion mapping rules in the preset compression code table, the multiple binary data groups are converted into multiple ternary data groups in parallel through a combinational logic array composed of multiple parallel micro-conversion units; the conversion mapping rules are used to indicate non-carry mapping relationships; the preset compression code table is used to store the mapping rules when the value of a 2-bit binary group is not 11. The generated multiple ternary data groups are concatenated to form an M-bit ternary output data; N and M are positive integers greater than 1.

2. The number system conversion method based on dynamic mapping rules according to claim 1, characterized in that, The rule selector receives external control signals or input data to determine switching selection information, so as to dynamically switch between multiple sets of mapping rules in the preset compression code table to change the reconstruction logic of the ternary data group.

3. The number system conversion method based on dynamic mapping rules according to claim 1, characterized in that, The binary input data is divided into a high-order binary data group and a low-order binary data group. The process of converting the multiple binary data groups into multiple ternary data groups in parallel includes: The high-order binary data group and the low-order binary data group are converted into two ternary data groups in parallel.

4. The number system conversion method based on dynamic mapping rules according to claim 1, characterized in that, Each of the aforementioned micro-conversion units is a stateless combinational logic circuit; Each of the micro-conversion units is used to convert a fixed-width binary data group to a corresponding ternary data group, and the conversion capability of the combinational logic array can be scaled by increasing or decreasing the number of the micro-conversion units.

5. The number system conversion method based on dynamic mapping rules according to claim 1, characterized in that, The method is triggered by hardware data conversion instructions, which include loading instructions and conversion execution instructions.

6. The number system conversion method based on dynamic mapping rules according to any one of claims 1 to 5, characterized in that, The binary data group is a 4-digit hexadecimal data group.

7. A number system conversion device based on dynamic mapping rules, characterized in that, include: The receiving module is used to receive N-bit binary input data; The first processing module is used to divide the N-bit binary input data into multiple binary data groups; The second processing module is used to convert the multiple binary data groups into multiple ternary data groups in parallel through a pure combinational logic circuit composed of multiple parallel micro-conversion units, according to the conversion mapping rules in the preset compression code table; the conversion mapping rules are used to indicate non-carry mapping relationships; the preset compression code table is used to store the mapping rules when the value of a 2-bit binary group is not 11. The splicing module is used to splice the generated multiple ternary data groups to form an M-bit ternary output data; N and M are positive integers greater than 1.

8. The number system conversion device based on dynamic mapping rules according to claim 7, characterized in that, The device is configured to adapt to N-bit binary input data of different bit widths by increasing or decreasing the number of micro-conversion units in the combinational logic array.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and capable of running on the processor, characterized in that, When the processor executes the program, it implements the number system conversion method based on dynamic mapping rules as described in any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the number system conversion method based on dynamic mapping rules as described in any one of claims 1 to 7.

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