Image processing apparatus including non-linear analog network and electronic device

Abstract

The invention relates to an image processing apparatus including a nonlinear analog network and an electronic device. The image processing apparatus includes: a signal acquisition module configured to acquire a plurality of first analog signals of an input image; the non-linear analog network is configured to execute edge-preserving filtering operation, and the non-linear analog network comprises a plurality of non-linear resistor units and a plurality of fixed resistance resistors; and a control driving circuit. According to the image processing device comprising the nonlinear analog network, nanosecond processing speed of million-pixel-level images can be achieved through the inherent parallel computing characteristic of a physical system, and the millisecond processing speed is greatly improved compared with the millisecond processing speed of an existing framework.

Description

Technical Field

[0001] This invention relates to the field of machine vision technology, and in particular to an image processing device and electronic device including a nonlinear analog network, which is suitable for tasks such as noise reduction, high dynamic range imaging and detail enhancement, and is especially suitable for edge computing scenarios such as autonomous driving, real-time video processing, and AR / VR devices. Background Technology

[0002] Image filtering is a crucial technique in image preprocessing, used to improve image quality. Its effectiveness directly impacts the efficiency and reliability of subsequent image processing and analysis. Image filtering techniques can achieve various objectives, such as reducing image noise, sharpening images, and detecting image edges.

[0003] Edge-preserving filtering is widely used for tasks such as edge-preserving denoising, high dynamic range imaging, and detail enhancement. However, edge-preserving filtering algorithms (such as bilateral filtering) are computationally complex, making real-time processing of megapixel-level images difficult. Dimensional optimization of edge-preserving filtering algorithms is very challenging, involving a trade-off between accuracy and speed. Traditional GPU / FPGA architectures, limited by irregular memory access and nonlinear computation, can only process megapixel images in milliseconds. Fixed-resistance network architectures (comparison documents CN108269237B and CN 104700373B) can only achieve spatially invariant convolutions (such as Gaussian filtering), where the resistance values ​​are externally preset and remain unchanged during processing. Reconfiguring the resistance values ​​for different scenarios is not feasible for real-time adaptation. Summary of the Invention

[0004] To address some or all of the problems in the prior art, the present invention provides an image processing apparatus including a nonlinear analog network, the network comprising:

[0005] The signal acquisition module is configured to acquire multiple first analog signals of the input image;

[0006] A nonlinear analog network, configured to perform edge-preserving filtering operations, includes multiple nonlinear resistive elements and multiple fixed-value resistors; and

[0007] Control drive circuit;

[0008] The control drive circuit is configured to perform the following steps:

[0009] Set the resistance value of the fixed resistor, and write the optimized edge-preserving filter parameters into the fixed resistor; and

[0010] The plurality of first analog signals are input to the plurality of signal input terminals of the nonlinear analog network, and the first analog signals are subjected to edge-preserving filtering image processing by the nonlinear analog network. The plurality of second analog signals after edge-preserving filtering are obtained at the plurality of signal output terminals of the nonlinear analog network.

[0011] Furthermore, the signal acquisition module includes a digital signal acquisition circuit and a digital-to-analog conversion circuit;

[0012] The digital signal acquisition circuit is configured to acquire multiple initial digital signals of the input image;

[0013] The digital-to-analog converter circuit is configured to perform digital-to-analog conversion processing on the plurality of initial digital signals to obtain a plurality of first analog signals.

[0014] Furthermore, the digital signal acquisition circuit includes a sensor array.

[0015] Furthermore, the resistance value of the nonlinear resistor unit increases with increasing input voltage; and / or

[0016] Each of the nonlinear resistor units includes at least one nonlinear resistor.

[0017] Furthermore, each of the fixed-value resistors has the same resistance value, and the resistance value of the fixed-value resistor is adjusted according to the processing task.

[0018] Furthermore, the image processing apparatus including the nonlinear analog network further includes:

[0019] The output module is configured to acquire a second analog signal from the signal output terminal of the nonlinear analog network and convert the second analog signal into a digital signal to be output.

[0020] Furthermore, the output module includes an analog-to-digital conversion current and signal attenuator and a digital signal output circuit;

[0021] The analog-to-digital conversion circuit is configured to perform analog-to-digital conversion processing on the second analog signal to obtain the digital signal to be output;

[0022] The digital signal output circuit is configured to output the digital signal to be output.

[0023] Furthermore, the control drive circuit includes:

[0024] Circuit arrays for implementing matrix addition and subtraction; and / or

[0025] Circuit arrays for edge extraction; and / or

[0026] Circuit arrays for implementing compressed signals; and / or

[0027] A circuit array that implements matrix multiplication by a compression factor.

[0028] The present invention also provides an electronic device comprising:

[0029] External system-on-a-chip; and

[0030] The image processing device includes a nonlinear analog network.

[0031] The technical solution provided by this invention has the following advantages:

[0032] 1. The image processing device proposed in this invention, which includes a nonlinear analog network, realizes physical-level image processing through a nonlinear analog network composed of nonlinear resistor units and fixed-value resistors.

[0033] 2. The image processing device proposed in this invention, which includes a nonlinear analog network, generates adaptive convolution kernels by dynamically adjusting the conductance of nonlinear resistive units, achieving efficient parallel computing without external programming. Leveraging the inherent parallel computing characteristics of the physical system, nanosecond-level processing speeds for megapixel-level images can be achieved, representing a six-order-of-magnitude improvement over the millisecond-level processing speeds of existing architectures, resulting in a significant speed increase.

[0034] 3. The image processing device proposed in this invention, which includes a nonlinear analog network, outperforms traditional bilateral filtering algorithms in terms of peak signal-to-noise ratio (PSNR) and structural similarity index (SSIM) for image processing performance evaluation. Moreover, the improvement is more significant as the noise level increases.

[0035] 4. The image processing device based on a nonlinear analog network proposed in this invention is suitable for data-intensive edge computing scenarios such as autonomous driving, real-time video processing, and AR / VR devices due to its ultra-high-speed computing capabilities. Attached Figure Description

[0036] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the various embodiments of the present invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.

[0037] Figure 1 A schematic diagram of an image processing apparatus including a nonlinear analog network according to an embodiment of the present invention is shown;

[0038] Figure 2 A schematic diagram of the structure of a nonlinear simulation network according to an embodiment of the present invention is shown;

[0039] Figure 3 A schematic diagram of the structure of an image processing apparatus including a nonlinear analog network according to another embodiment of the present invention is shown;

[0040] Figure 4 A schematic diagram of an image processing apparatus including a nonlinear analog network according to another embodiment of the present invention is shown.

[0041] Figure 5 A schematic diagram of an image processing apparatus including a nonlinear analog network according to another embodiment of the present invention is shown; and

[0042] Figure 6 A schematic diagram of the structure of an electronic device according to an embodiment of the present invention is shown. Detailed Implementation

[0043] In the following description, the invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more specific details or with other alternatives and / or additional methods or components. In other instances, well-known structures or operations are not shown or described in detail so as not to obscure the inventive points of the invention. Similarly, for illustrative purposes, specific numbers and configurations are set forth to provide a comprehensive understanding of embodiments of the invention. However, the invention is not limited to these specific details.

[0044] In this specification, references to "an embodiment" or "this embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing throughout this specification does not necessarily refer to the same embodiment in all instances.

[0045] It should be noted that the embodiments of the present invention describe the method steps in a specific order; however, this is only for illustrating the specific embodiment and not for limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to actual needs.

[0046] In this invention, the modules of the system according to the invention can be implemented using software, hardware, firmware, or a combination thereof. When a module is implemented using software, its function can be implemented through computer program flow. For example, the module can be implemented using code segments (such as code segments in languages ​​like C and C++) stored in a storage device (such as a hard disk, memory, etc.), wherein the corresponding function of the module can be implemented when the code segment is executed by a processor. When a module is implemented using hardware, its function can be implemented by setting a corresponding hardware structure. For example, the module's function can be implemented by hardware programming a programmable device such as a field-programmable gate array (FPGA), or by designing an application-specific integrated circuit (ASIC) that includes multiple transistors, resistors, capacitors, and other electronic devices. When a module is implemented using firmware, the module's function can be written into a read-only memory such as an EPROM or EEPROM in the form of program code, and the corresponding function of the module can be implemented when the program code is executed by a processor. In addition, some functions of the module may need to be implemented by separate hardware or by working in cooperation with the hardware. For example, the detection function is implemented by the corresponding sensor (such as a proximity sensor, accelerometer, gyroscope, etc.), the signal transmission function is implemented by the corresponding communication device (such as a Bluetooth device, infrared communication device, baseband communication device, Wi-Fi communication device, etc.), the output function is implemented by the corresponding output device (such as a display, speaker, etc.), and so on.

[0047] Figure 1 A schematic diagram of an image processing apparatus including a nonlinear analog network according to an embodiment of the present invention is shown. Figure 1 As shown, the image processing device including the nonlinear analog network includes: a signal acquisition module, a nonlinear analog network, a control drive circuit, and an output module.

[0048] The signal acquisition module is configured to acquire a plurality of first analog signals of the input image. In one embodiment of the present invention, the signal acquisition module may include a digital signal acquisition circuit and a digital-to-analog converter circuit; the digital signal acquisition circuit is configured to acquire a plurality of initial digital signals of the input image; the digital-to-analog converter circuit is configured to perform digital-to-analog conversion processing on the plurality of initial digital signals to obtain a plurality of first analog signals. In one embodiment of the present invention, the digital signal acquisition circuit may include a sensor array.

[0049] The nonlinear simulation network is configured to perform edge-preserving filtering operations. The nonlinear simulation network includes multiple nonlinear resistor elements and multiple fixed-value resistors. Figure 2 A schematic diagram of the structure of a nonlinear simulation network according to an embodiment of the present invention is shown. Figure 2As shown, the nonlinear analog network includes: a nonlinear resistor unit 201, a fixed-value resistor 202, a signal input terminal 203, and a signal output terminal 204. For example... Figure 2 As shown, multiple nonlinear resistor elements 201 are arranged in a grid; multiple fixed-value resistors 202 are connected to the vertices of the grid, i.e., each vertex in the grid is connected to a fixed-value resistor 202; the signal input terminal 203 is connected to the floating terminal of the fixed-value resistors 202 (i.e., Figure 1 The square vertex in the diagram is connected; and the signal output terminal 204 is connected to the other end of the fixed resistance resistor 202 (i.e., Figure 1 Connect the circular vertices in the graph.

[0050] In one embodiment of the invention, two N-channel enhancement-mode MOS (metal oxide semiconductor) field-effect transistors form a nonlinear resistive unit, arranged in a back-to-back common-source configuration. Each pair of MOS field-effect transistors is activated by a single applied gate voltage. The MOS field-effect transistors operate in the linear or saturation region, i.e., when the gate voltage is above a threshold voltage, and the channel width can be, for example, 1 μm. It should be noted that this arrangement ensures that regardless of which side of the MOS field-effect transistor pair is at a higher voltage, if one MOS field-effect transistor enters the saturation region, the other MOS field-effect transistor remains in the linear region. The IV characteristics of this MOS field-effect transistor pair are primarily controlled by the MOS field-effect transistor in the saturation region, exhibiting bidirectional pinch-off behavior.

[0051] In one embodiment of the present invention, the transistor used can be a thin-film transistor, a field-effect transistor (e.g., a MOS field-effect transistor), or other switching devices with similar characteristics. In one embodiment of the present invention, the nonlinear resistor unit can be composed of any device whose IV characteristic curve satisfies that the resistance value increases with increasing input voltage. It is worth noting that using two MOS transistors in a series is one way to achieve a monotonically increasing resistance value with increasing input voltage; other devices or combinations of devices can also achieve a monotonically increasing resistance value with increasing input voltage. In one embodiment of the present invention, each nonlinear resistor unit includes at least one nonlinear resistor. In one embodiment of the present invention, the structure of the nonlinear resistor units can be a grid of any regular shape, and the signal output terminals can be symmetrically arranged square grids.

[0052] In this invention, the term "grid or vertex of grid cell" refers to the connection point of the terminals of nonlinear resistive cells that are connected to each other.

[0053] In this invention, the term "mesh" includes a plurality of polygonal mesh cells, each of a plurality of nonlinear resistive cells forming one of the edges of the mesh cell, and a plurality of fixed-value resistors connected to one of the vertices of the mesh cell.

[0054] In this invention, the term "N-gon" simply refers to a circuit formed by connecting N nonlinear resistor units together (N being an integer greater than 3), and does not necessarily conform to the strict definition of an N-gon. For example, when the nonlinear resistor units are curved, they may form circular, elliptical, or other curved shapes when connected together. Therefore, the N-gon grid cell covers all shapes of circuits formed by N nonlinear resistor units.

[0055] In one embodiment of the present invention, the mesh comprises a plurality of polygonal mesh cells, and the number of sides of different mesh cells may be the same or different. For example, some mesh cells have 3 sides, some mesh cells have 4 sides, or other numbers.

[0056] In one embodiment of the present invention, the resistance value of each fixed-value resistor is the same, and the resistance value of the fixed-value resistor can be adjusted according to the processing task. In one embodiment of the present invention, if the processing task is a noise reduction task, the resistance value of the fixed-value resistor is configured to 2MΩ; if the processing task is a high dynamic range imaging task, the resistance value of the fixed-value resistor is configured to 4MΩ. The fixed-value resistors here, like the spatial and temporal parameters of the bilateral filter, need to be optimized through different tasks and different nonlinear resistor devices. The optimal parameters can be found through gradual debugging in practice; these optimal parameters are the optimized edge-preserving filter parameters. Typically, the resistance value range can be... Where I s This represents the saturation current of the nonlinear resistive element. It should be noted that, according to calculations and verification, even differences in the resistance values ​​of different fixed-value resistors will not affect the performance of the nonlinear simulation network. In one embodiment of the invention, the resistance values ​​of different fixed-value resistors can typically vary within ±70% of the optimal value without affecting the performance of the nonlinear simulation network.

[0057] The conductivity of the nonlinear analog network provided by this invention can be dynamically adjusted according to the input voltage, enabling adaptive convolution operations without external programming. Unlike traditional static convolution architectures, the nonlinear analog network proposed in this invention can achieve parallel computation through physical input-output mapping, with each output pixel calculated using its unique adaptive convolution kernel. Leveraging the inherent parallel computing characteristics of the physical system, nanosecond-level processing speeds for megapixel-level images are achieved, which is six orders of magnitude faster than the most advanced existing architectures (processing speeds in milliseconds) and two orders of magnitude lower in energy consumption. Furthermore, its image processing performance metrics, Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index (SSIM), are superior to traditional bilateral filtering algorithms. Experiments show that the nonlinear analog network provided by this invention improves the PSNR by more than 0.5 dB and the SSIM by more than 0.05 dB compared to traditional bilateral filtering. Moreover, the improvement becomes more significant with increasing noise. These effects are achieved through the greater degree of freedom in the convolution kernel of the nonlinear analog network compared to bilateral filtering.

[0058] The nonlinear simulation network provided by this invention has an architecture equivalent to an adaptive convolution operation. The signal input and output terminals can be derived using Kirchhoff's laws as follows:

[0059]

[0060] Among them, V O V represents the output signal. I Indicates the input signal. Let C0 represent the identity matrix, C0 represent the conductance of the fixed-value resistor, and L represent the anisotropic Laplace matrix containing nonlinear resistive elements. This equation can be viewed as a convolution. Each row in the diagram represents the convolution kernel corresponding to each data point. The convolution kernel adaptively changes due to the influence of nonlinear resistive units. Under dynamic lighting conditions, the adaptive convolution kernel can quickly respond to sudden changes in brightness because the circuit response time is on the order of nanoseconds.

[0061] In one embodiment of the present invention, the control drive circuit includes: a circuit array for implementing matrix addition and subtraction; and / or a circuit array for implementing edge extraction; and / or a circuit array for implementing signal compression; and / or a circuit array for implementing matrix multiplication by a compression factor. The control drive circuit is configured to perform the following steps: setting the resistance value of a fixed-value resistor; writing the optimized edge-preserving filtering parameters into the fixed-value resistor; inputting multiple first analog signals into multiple signal input terminals of a nonlinear analog network; performing edge-preserving filtering image processing on the first analog signals through the nonlinear analog network; and acquiring multiple second analog signals after edge-preserving filtering processing at multiple signal output terminals of the nonlinear analog network.

[0062] The output module is configured to acquire a second analog signal from the signal output of the nonlinear analog network and convert the second analog signal into a digital signal to be output.

[0063] In one embodiment of the present invention, the output module includes an analog-to-digital conversion current and signal attenuator and a digital signal output circuit; the analog-to-digital conversion circuit is configured to perform analog-to-digital conversion processing on a second analog signal to obtain a digital signal to be output; the digital signal output circuit is configured to output the digital signal to be output.

[0064] Figure 3 A schematic diagram of an image processing apparatus including a nonlinear analog network, according to another embodiment of the present invention, is shown. Figure 3 In this circuit, the control drive circuit includes a circuit array that performs matrix addition and subtraction. Figure 3 The corresponding real-time edge-preserving filtering image processing method based on a nonlinear analog network includes: acquiring a first analog signal of the input image; setting a fixed resistance value and writing the optimized edge-preserving filtering parameters into the fixed resistance value; inputting the first analog signal into the signal input terminal of the nonlinear analog network, performing edge-preserving filtering image processing on the first analog signal through the nonlinear analog network, and acquiring a second analog signal after edge-preserving filtering at the signal output terminal of the nonlinear analog network; multiplying the difference between the first analog signal and the second analog signal by a factor greater than 1, and adding the second analog signal to obtain the target image, thereby achieving a detail enhancement effect.

[0065] Figure 4 A schematic diagram of an image processing apparatus including a nonlinear analog network, according to another embodiment of the present invention, is shown. Figure 4 In this circuit, the control drive circuit includes a circuit array for performing matrix addition and subtraction, as well as a circuit array for performing edge extraction. Figure 4 The corresponding real-time edge-preserving filtering image processing method based on nonlinear analog networks includes: acquiring a first analog signal of the input image; setting a fixed resistance value and writing the optimized edge-preserving filtering parameters into the fixed resistance value; inputting the first analog signal into the signal input terminal of the nonlinear analog network, performing edge-preserving filtering image processing on the first analog signal through the nonlinear analog network, and acquiring a second analog signal after edge-preserving filtering at the signal output terminal of the nonlinear analog network; performing an edge extraction operation on the difference between the first analog signal and the second analog signal, for example using the Sobel operator, and then subtracting it from the second analog signal to obtain the target image, thereby achieving an image rendering effect.

[0066] Figure 5 A schematic diagram of an image processing apparatus including a nonlinear analog network is shown according to another embodiment of the present invention. Figure 5In this circuit, the control drive circuit includes a circuit array for adding and subtracting matrices, a circuit array for compressing signals, and a circuit array for multiplying matrices by compression factors. Figure 5 The corresponding real-time edge-preserving filtering image processing method based on a nonlinear analog network includes: acquiring a first analog signal of the input image; extracting the luminance channel value from the first analog signal, where the luminance channel value is L = 0.299 × R + 0.587 × G + 0.114 × B, where R, G, and B are the values ​​of the three RGB channels in the input image, respectively. The input image is in RGB format, but the luminance is first calculated numerically based on a weighted sum, and the R, G, and B channels are processed separately subsequently; setting a fixed resistance value and writing the optimized edge-preserving filtering parameters into the fixed resistance value, for example, R = 4MΩ. In step 830, the L signal in the first analog signal is logarithmically processed and then input into the signal input terminal of the image processing device including the nonlinear analog network. The image processing device including the nonlinear analog network performs edge-preserving filtering image processing on the logarithmically processed first analog signal, and the edge-preserving filtered second analog signal is acquired at the signal output terminal of the image processing device including the nonlinear analog network. In step 840, the second analog signal V... O The signal is compressed and combined with the input signal L, resulting in 10((V) O -max(V O ))×CF+log(L)-V O ), where CF is defined as V I This represents the first analog signal after logarithmic processing. This result is then divided by L and multiplied by the original RGB image to obtain the target image, thereby achieving the HDR tone mapping effect.

[0067] It should be noted that acquiring the first analog signal of the input image includes: acquiring the initial digital signal of the input image; converting the initial digital signal into an analog signal using a digital-to-analog converter; and multiplying the analog signal by a magnification factor n to obtain the first analog signal. It should be noted that the magnification factor n is determined by the voltage range applied by the circuit. For example, when the voltage range applied by the circuit is 0-3V, the floating-point pixel values ​​of the image, which are in the range of 0-1, are multiplied by a magnification factor of 3. It is important to note that a larger magnification factor results in higher energy consumption and better processing performance; therefore, a trade-off must be made between processing performance and energy consumption.

[0068] In one embodiment of the present invention, a plurality of first analog signals are input signals to be subjected to edge-preserving filtering, and a plurality of second analog signals are output signals after edge-preserving filtering is performed on the input signals; the first analog signals are analog voltage signals, and the second analog signals are analog voltage signals.

[0069] In one embodiment of the present invention, when the signal to be subjected to edge-preserving filtering is a digital signal, it needs to be converted into an analog signal by a digital-to-analog converter, and then processed by an image processing device including a nonlinear analog network. For example, the multiple initial digital signals can be pre-stored digital signals or real-time acquired digital signals, and the multiple initial digital signals are subjected to digital-to-analog conversion to obtain multiple first analog signals.

[0070] In one embodiment of the present invention, the number of signal input terminals and signal output terminals is equal to the number of pixels in the input image, and the signal input terminals and signal output terminals are aligned with the rows and columns of the pixel matrix of the input image.

[0071] In one embodiment of the present invention, after obtaining the second analog signal after edge-preserving filtering, the method further includes: dividing the second analog signal by the amplification factor n to obtain the processed second analog signal; and converting the processed second analog signal into a digital signal to be output using an analog-to-digital converter.

[0072] The image processing device including a nonlinear analog network provided by the present invention can obtain all the results of the edge-preserving filtering operation in a single calculation, which greatly reduces the number of analog-to-digital conversions and the time required in the process of acquiring the first analog signal, thereby reducing power consumption and improving calculation speed.

[0073] The image processing device including a nonlinear analog network provided by this invention can be directly used for sensor data processing. For example, it can be used in camera system design to directly process the acquired analog domain image signals, such as denoising, detail enhancement, image rendering, HDR tone mapping, etc., without the need for digital-to-analog conversion. This further reduces the power consumption of the image processing process, improves the computing speed, and meets the strict power consumption and area requirements of edge device design.

[0074] In one embodiment of the present invention, when the input image is an irregular resolution image: the input image is divided into multiple sub-images, each sub-image having a size less than or equal to the size of the image processing device including the nonlinear analog network; the edge-preserving filtering image processing is performed independently on each sub-image to obtain a processed sub-image; and the processed sub-images are combined into a final output image.

[0075] This invention proposes an image processing device incorporating a nonlinear analog network. This network, composed of nonlinear resistive units and fixed-value resistors, enables physical-level image processing. Furthermore, by dynamically adjusting the conductance of the nonlinear resistive units to generate adaptive convolution kernels, this device achieves efficient parallel computing without external programming. Leveraging the inherent parallel computing characteristics of the physical system, nanosecond-level processing speeds for megapixel-level images can be achieved, representing a six-order-of-magnitude improvement over the millisecond-level processing speeds of existing architectures. The proposed image processing device, incorporating a nonlinear analog network, outperforms traditional bilateral filtering algorithms in both Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index (SSIM), with the improvement becoming more pronounced as noise levels increase. Based on its ultra-high-speed computing capabilities, this image processing device is suitable for data-intensive edge computing scenarios such as autonomous driving and real-time video processing.

[0076] The present invention also provides an electronic device. Figure 6 A schematic diagram of the structure of an electronic device according to an embodiment of the present invention is shown. Figure 6 As shown, the electronic device includes:

[0077] Image processing devices including nonlinear analog networks; and

[0078] External system-on-a-chip.

[0079] In one embodiment of the present invention, a nonlinear analog network can be integrated into existing image processing systems, such as mobile phones, cameras, and video processing devices. This nonlinear analog network can be positioned between a sensor array and a digital-to-analog converter (DAC), thereby replacing some of the computational functions of external system-on-a-chip (SoC) such as an ISP after the DAC, thus improving computational speed and saving power consumption.

[0080] Although various embodiments of the present invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined according to the technical solutions of the invention and their equivalents.

Claims

1. An image processing apparatus comprising a nonlinear analog network, characterized in that, include: The signal acquisition module is configured to acquire multiple first analog signals of the input image; A nonlinear analog network is configured to perform edge-preserving filtering operations, the nonlinear analog network comprising multiple nonlinear resistor units and multiple fixed-value resistors; as well as Control drive circuit; The control drive circuit is configured to perform the following steps: Set the resistance value of the fixed resistor, and write the optimized edge-preserving filter parameters into the fixed resistor; and The plurality of first analog signals are input to the plurality of signal input terminals of the nonlinear analog network, and the first analog signals are subjected to edge-preserving filtering image processing by the nonlinear analog network. The plurality of second analog signals after edge-preserving filtering are obtained at the plurality of signal output terminals of the nonlinear analog network.

2. The image processing apparatus including a nonlinear analog network according to claim 1, characterized in that, The signal acquisition module includes a digital signal acquisition circuit and a digital-to-analog conversion circuit; The digital signal acquisition circuit is configured to acquire multiple initial digital signals of the input image; The digital-to-analog converter circuit is configured to perform digital-to-analog conversion processing on the plurality of initial digital signals to obtain a plurality of first analog signals.

3. The image processing apparatus including a nonlinear analog network according to claim 2, characterized in that, The digital signal acquisition circuit includes a sensor array.

4. The image processing apparatus including a nonlinear analog network according to claim 1, characterized in that, The resistance value of the nonlinear resistor unit increases with the increase of the input voltage; and / or Each of the nonlinear resistor units includes at least one nonlinear resistor.

5. The image processing apparatus including a nonlinear analog network according to claim 1, characterized in that, Each of the fixed-value resistors has the same resistance value, and the resistance value of the fixed-value resistor is adjusted according to the processing task.

6. The image processing apparatus including a nonlinear analog network according to claim 1, characterized in that, Also includes: The output module is configured to acquire a second analog signal from the signal output terminal of the nonlinear analog network and convert the second analog signal into a digital signal to be output.

7. The image processing apparatus including a nonlinear analog network according to claim 6, characterized in that, The output module includes an analog-to-digital conversion current and signal attenuator and a digital signal output circuit; The analog-to-digital conversion circuit is configured to perform analog-to-digital conversion processing on the second analog signal to obtain the digital signal to be output; The digital signal output circuit is configured to output the digital signal to be output.

8. The image processing apparatus including a nonlinear analog network according to claim 6, characterized in that, The control drive circuit includes: Circuit arrays for implementing matrix addition and subtraction; and / or Circuit arrays for edge extraction; and / or Circuit arrays for implementing compressed signals; and / or A circuit array that implements matrix multiplication by a compression factor.

9. An electronic device, characterized in that, include: External system-on-a-chip; as well as The image processing apparatus comprising a nonlinear analog network as claimed in any one of claims 1-8.

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