Packaging structure and forming method thereof

Abstract

The invention discloses a packaging structure and a forming method thereof, and the forming method comprises the steps: providing a first wafer which comprises a plurality of first crystal grains; providing a second wafer, wherein the second wafer comprises a plurality of second crystal grains; etching the third surface of the second wafer, and forming a first groove in a part of the second crystal grains; providing a third wafer, wherein the third wafer comprises a plurality of third crystal grains; bonding the third surface of the second wafer with the second surface of the first wafer, so that a part of the second crystal grains are bonded with the corresponding first crystal grains, and the other part of the second crystal grains are not bonded with the corresponding first crystal grains due to the existence of the first grooves; bonding the sixth surface of the third wafer with the first surface of the first wafer, so that at least part of the third crystal grains are bonded with the corresponding first crystal grains; and segmenting the bonded first wafer, second wafer and third wafer to form a plurality of discrete first chip stacking structures. The bonding of a plurality of wafers of crystal grains with different sizes is realized, and the manufacturing efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of packaging technology, and in particular to a packaging structure and a method for forming the same. Background Technology

[0002] Wafer-to-wafer bonding is a process that tightly bonds two or more complete wafers (such as silicon wafers, glass wafers, or compound semiconductor wafers) together using physical or chemical methods. The bonded wafers form a multi-layered stacked structure, which is typically used to achieve 3D integration or the functional fusion of heterogeneous materials.

[0003] However, when the die sizes on the two wafers are different, the existing wafer-to-wafer bonding method is obviously no longer applicable, and only the existing die-to-wafer bonding method (that is, bonding each die to the wafer one by one) can be used, but this will seriously affect production efficiency. Summary of the Invention The purpose of this application is to provide a packaging structure and a method for forming the same, which enables the bonding of two wafers with different sized dies, thereby improving production efficiency. To achieve the above objectives, one embodiment of this application provides a method for forming an encapsulation structure, including: A first wafer is provided, the first wafer including opposing first and second surfaces, the first wafer including a plurality of first grains; A second wafer is provided, the second wafer including opposing third and fourth surfaces, the second wafer including a plurality of second grains, the size of the first grains being larger than the size of the second grains; The third surface is etched to form a first groove on a portion of the second grains; A third wafer is provided, the third wafer including opposing fifth and sixth surfaces, the third wafer including a plurality of third grains, the size of the first grains being equal to or greater than the size of the third grains; The third surface of the second wafer is bonded to the second surface of the first wafer, such that a portion of the second grains are bonded to the corresponding first grains, while another portion of the second grains will not be bonded to the corresponding first grains due to the presence of the first groove. The sixth surface of the third wafer is bonded to the first surface of the first wafer, such that at least a portion of the third grains are bonded to the corresponding first grains; The bonded first wafer, second wafer, and third wafer are divided to form multiple discrete first chip stack structures.

[0004] In some embodiments, the method further includes: providing a fourth wafer, the fourth wafer including opposing seventh and eighth surfaces, the fourth wafer including a plurality of fourth grains, the size of the second grain being equal to the size of the fourth grain; The seventh surface of the fourth wafer is bonded to the fourth surface of the second wafer, such that the fourth grain is bonded to the corresponding second grain; The bonded first wafer, second wafer, third wafer, and fourth wafer are divided to form multiple discrete first chip stack structures and multiple discrete second chip stack structures. The first chip stack structure includes a first die, a second die bonded to a second surface of the first die, a third die bonded to a first surface of the first die, and a fourth die bonded to a fourth surface of the second die. The second chip stack structure includes a second die and a fourth die bonded together. The first wafer further includes a first dicing channel located between adjacent first dies; the second wafer further includes a second dicing channel located between adjacent second dies; the third wafer further includes a third dicing channel located between adjacent third dies; and the fourth wafer further includes a fourth dicing channel located between adjacent fourth dies.

[0005] In some embodiments, the size of the first groove is greater than or equal to the size of the second grain.

[0006] In some embodiments, the size of the first groove is the sum of the size of the second grain and the size of the second kerf around the second grain.

[0007] In some embodiments, the size of the first wafer is equal to the size of the second wafer, the size of the third wafer is equal to the size of the first wafer, the size of the fourth wafer is equal to the size of the second wafer, the projection of the first dicing on the third surface of the second wafer coincides with the projection of a portion of the first grooves on the third surface, the projection of the third dicing on the first surface of the first wafer coincides with at least a portion of the projection of the first dicing on the first surface, and the projection of the fourth dicing on the third surface of the second wafer coincides with at least a portion of the projection of the second dicing on the third surface.

[0008] In some embodiments, the size of the first grain being larger than the size of the second grain includes: the size of the first grain being an integer multiple of the size of the second grain; The condition that the size of the first grain is greater than the size of the third grain includes: the size of the first grain being an integer multiple of the size of the third grain.

[0009] In some embodiments, the projection of one of the first grains on the third surface coincides with the projections of a plurality of the second grains on the third surface; When the size of the first grain is larger than the size of the third grain, the projection of one of the first grains on the first surface coincides with the projection of multiple third grains on the first surface.

[0010] In some embodiments, dividing the bonded first wafer, second wafer, third wafer, and fourth wafer includes dividing the bonded first wafer, second wafer, third wafer, and fourth wafer along the first dicing track, the second dicing track, and the fourth dicing track, respectively.

[0011] In some embodiments, bonding the sixth surface of the third wafer to the first surface of the first wafer such that at least a portion of the third grains are bonded to the corresponding first grains includes: bonding all the third grains on the third wafer to the corresponding first grains.

[0012] In some embodiments, the bonded first wafer, second wafer, and third wafer are divided to form multiple discrete first chip stack structures while obtaining a number of separate second dies; a first chip stack structure includes a first die, at least one second die bonded to a second surface of a first die, and at least one third die bonded to a first surface of a first die.

[0013] In some embodiments, bonding the sixth surface of the third wafer to the first surface of the first wafer such that at least a portion of the third grains are bonded to the corresponding first grains includes: bonding a portion of the third grains on the third wafer to the corresponding first grains, while another portion of the third grains are not bonded to the corresponding first grains.

[0014] In some embodiments, the third wafer further includes a third dicing pass located between adjacent third grains, and the forming method further includes: etching a sixth surface of a portion of the third wafer, and forming a second groove on a portion of the third grains; the size of the second groove is the sum of the size of the third grain and the size of the third dicing pass around the third grain; When the sixth surface of the third wafer is bonded to the first surface of the first wafer, a portion of the third grains are bonded to the corresponding first grains, while another portion of the third grains are not bonded to the corresponding first grains due to the presence of the second groove.

[0015] In some embodiments, the bonded first wafer, second wafer, and third wafer are divided to form multiple discrete first chip stack structures, while simultaneously obtaining a number of separate second and third dies.

[0016] In some embodiments, a first chip stack structure includes a first die and at least one second die bonded to a first die, and a second chip stack structure includes a second die and a fourth die bonded together.

[0017] In some embodiments, the method further includes: providing a fifth wafer, the fifth wafer including opposing ninth and tenth surfaces, the fifth wafer including a plurality of fifth grains, the size of the fifth grains being equal to the size of the third grain; The tenth surface of the fifth wafer is bonded to the fifth surface of the third wafer, such that at least a portion of the fifth grains are bonded to the corresponding third grains; The bonded first wafer, second wafer, third wafer, fourth wafer, and fifth wafer are divided to form multiple discrete first chip stack structures, multiple discrete second chip stack structures, and multiple discrete third chip stack structures.

[0018] In some embodiments, the first surface has a first bonding layer, the second surface has a second bonding layer, the third surface has a third bonding layer, and the sixth surface has a sixth bonding layer.

[0019] In some embodiments, the first bonding layer, the second bonding layer, the third bonding layer, and the sixth bonding layer are all made of the same material.

[0020] In some embodiments, the materials of the first bonding layer, the second bonding layer, the third bonding layer, and the fourth bonding layer include dielectric materials, or a combination of dielectric layer materials and metallic materials, or solder.

[0021] In some embodiments, the dielectric material includes silicon oxide or silicon carbide; the metallic material includes copper; and the solder includes tin or a tin alloy.

[0022] In some embodiments, after forming a plurality of first grains on the first wafer, the first bonding layer is formed on a first surface of the first wafer; and the second bonding layer is formed on a second surface of the first wafer.

[0023] In some embodiments, after the second grain is formed on the second wafer, the third bonding layer is formed on the third surface of the second wafer.

[0024] In some embodiments, the third bonding layer is etched to form the first groove in the third bonding layer.

[0025] In some embodiments, after the third grain is formed on the third wafer, the sixth bonding layer is formed on the sixth surface of the third wafer.

[0026] In some embodiments, the sixth bonding layer is etched to form a second groove in the sixth bonding layer.

[0027] In some embodiments, a direct bonding process, a dielectric bonding process, an anodic bonding process, or a hybrid bonding process is used to bond the third surface of the second wafer to the second surface of the first wafer, and to bond the sixth surface of the third wafer to the first surface of the first wafer.

[0028] This application also provides a packaging structure, including: A first wafer, the first wafer including opposing first and second surfaces, the first wafer including a plurality of first grains; The second wafer includes opposing third and fourth surfaces, and includes a plurality of second grains, the size of the first grains being larger than the size of the second grains, and a portion of the second grains having a first groove penetrating the third surface; The third wafer includes opposing fifth and sixth surfaces, and the third wafer includes a plurality of third grains, wherein the size of the first grain is equal to or greater than the size of the third grain; The third surface of the second wafer is bonded to the second surface of the first wafer, such that a portion of the second grains are bonded to the corresponding first grains, while another portion of the second grains will not be bonded to the corresponding first grains due to the presence of the first groove; The sixth surface of the third wafer is bonded to the first surface of the first wafer, such that at least a portion of the third grains are bonded to the corresponding first grains.

[0029] In some embodiments, the device further includes: a fourth wafer, the fourth wafer including opposing seventh and eighth surfaces, the fourth wafer including a plurality of fourth grains, the size of the second grain being equal to the size of the fourth grain; The seventh surface of the fourth wafer is bonded to the fourth surface of the second wafer, such that the fourth grain is bonded to the corresponding second grain; The first wafer further includes a first dicing channel located between adjacent first dies; the second wafer further includes a second dicing channel located between adjacent second dies; the third wafer further includes a third dicing channel located between adjacent third dies; and the fourth wafer further includes a fourth dicing channel located between adjacent fourth dies.

[0030] In some embodiments, the size of the first groove is greater than or equal to the size of the second grain.

[0031] In some embodiments, the size of the first groove is the sum of the size of the second grain and the size of the second kerf around the second grain.

[0032] In some embodiments, the size of the first grain being larger than the size of the second grain includes: the size of the first grain being an integer multiple of the size of the second grain; The condition that the size of the first grain is greater than the size of the third grain includes: the size of the first grain being an integer multiple of the size of the third grain.

[0033] In some embodiments, the projection of one of the first grains on the third surface coincides with the projections of a plurality of the second grains on the third surface; When the size of the first grain is larger than the size of the third grain, the projection of one of the first grains on the first surface coincides with the projection of multiple third grains on the first surface.

[0034] In some embodiments, the sixth surface of the third wafer is bonded to the first surface of the first wafer, such that at least a portion of the third grains are bonded to the corresponding first grains, including: all the third grains on the third wafer are bonded to the corresponding first grains.

[0035] In some embodiments, the sixth surface of the third wafer is bonded to the first surface of the first wafer, such that at least a portion of the third grains are bonded to the corresponding first grains, including: a portion of the third grains on the third wafer are bonded to the corresponding first grains, and another portion of the third grains are not bonded to the corresponding first grains.

[0036] In some embodiments, the third wafer further includes a third dicing channel located between adjacent third dies, and the third wafer further includes a second groove extending through the sixth surface on a portion of the third dies; the size of the second groove is the sum of the size of the third die and the size of the third dicing channel around the third die; When the sixth surface of the third wafer is bonded to the first surface of the first wafer, a portion of the third grains are bonded to the corresponding first grains, while another portion of the third grains are not bonded to the corresponding first grains due to the presence of the second groove.

[0037] In some embodiments, the device further includes: a fifth wafer, the fifth wafer including opposing ninth and tenth surfaces, the fifth wafer including a plurality of fifth grains, the size of the fifth grains being equal to the size of the third grain; The tenth surface of the fifth wafer is bonded to the fifth surface of the third wafer, such that at least a portion of the fifth grains are bonded to the corresponding third grains.

[0038] The beneficial effects of this application are: The packaging structure and its forming method of this application, wherein the forming method first forms a first groove penetrating a third surface on a portion of the second dies on a second wafer. When bonding the third surface of the second wafer to the second surface of the first wafer, a portion of the second dies are bonded to their corresponding first dies, while another portion of the second dies, due to the presence of the first groove, are not bonded to their corresponding first dies. Then, the sixth surface of the third wafer is bonded to the first surface of the first wafer, such that at least a portion of the third dies are bonded to their corresponding first dies. The bonded first, second, and third wafers are then divided to form multiple discrete first chip stack structures. That is, through the aforementioned steps, this application can achieve the bonding of multiple wafers with different die sizes to mass-produce first chip stack structures, improving the manufacturing efficiency of the first chip stack structures. Furthermore, excess second dies (and third dies) during the manufacturing process can be easily and without damage separated, and the separated second dies (and third dies) can be used for other packaging processes, thereby saving manufacturing costs. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In addition, in the following drawings, the components are not necessarily drawn to scale, and components with similar related characteristics or features may have the same or similar reference numerals.

[0040] Figure 1 This is a flowchart illustrating the method for forming the packaging structure provided in some embodiments of this application; Figure 2This is a schematic diagram of the structure after the first wafer is formed in the method of forming the packaging structure provided in some embodiments of this application; Figure 3 This is a schematic diagram showing the second wafer and the structure after forming the first groove in a method for forming a packaging structure provided in some embodiments of this application; Figure 4 This is a schematic diagram of the structure after providing a third wafer in the method of forming the packaging structure provided in some embodiments of this application; Figure 5 This is a schematic diagram of the structure formed by bonding the second wafer and the first wafer, and bonding the third wafer and the second wafer in the packaging structure formation method provided in some embodiments of this application; Figure 6 This is a schematic diagram of the structure after dividing the bonded first wafer, second wafer, and third wafer in the method for forming the packaging structure provided in some embodiments of this application; Figure 7 This is a schematic diagram of the structure formed by bonding the second wafer and the first wafer, and the third wafer and the second wafer after bonding, in a method for forming the packaging structure provided in other embodiments of this application; Figure 8 This is a schematic diagram of the structure after dividing the bonded first wafer, second wafer, and third wafer in the method for forming the packaging structure provided in other embodiments of this application; Figure 9 This is a schematic diagram of the structure formed by bonding the second wafer and the first wafer, and the third wafer and the second wafer after bonding, in a method for forming the packaging structure provided in other embodiments of this application; Figure 10 This is a schematic diagram of the structure after dividing the bonded first wafer, second wafer, and third wafer in the method for forming the packaging structure provided in other embodiments of this application. Detailed Implementation

[0041] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0043] In the description of this application, it should be noted that the use of terms such as "first" and "second" to define objects (such as elements, components, regions, layers, doping types and / or parts) is merely for the purpose of distinguishing different objects and is not necessarily used to describe a specific order or sequence. Unless the context clearly indicates otherwise, it should be understood that such data can be used interchangeably where appropriate.

[0044] In the description of this application, it should be understood that the singular forms “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “compose” and / or “comprise” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0045] In the description of this application, it should also be noted that when a component is referred to as "on another component," "connected to another component," or "in contact with another component," it can mean not only that a component is directly on, directly connected to, or directly in contact with another component, but also that an intermediate component can be inserted between the two components. Furthermore, "connection" includes not only fixed connections but also detachable connections or integral connections. Similarly, when an element is referred to as "electrically connected," "electrically contacted," "electrically coupled," or "electrically coupled to" another element, the two elements can be in direct electrical contact or point coupling, or they can be in electrical contact or point coupling through an intermediate component.

[0046] In the description of this application, it should also be noted that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0047] Furthermore, in the description of this application, spatial relation terms such as "below," "under," "below," "below," "below," "above," "on the upper surface of," "above," etc., can be used to describe the spatial positional relationship between one element or feature shown in the figures and other elements or features. It should be understood that spatial relation terms, in addition to the orientation shown in the figures, also include different orientations of elements or features in use and operation. For example, if an element or feature in the figures is flipped or inverted, an element or feature described as "below" or "below" other elements or features will be oriented "above" other elements or features. Furthermore, elements may also include other orientations (e.g., rotated by an angle or other orientations).

[0048] The structure of the embodiments of this application should not be limited to the specific shape shown in the accompanying drawings, but includes shape deviations due to, for example, manufacturing techniques.

[0049] It is understood that in the accompanying drawings of this application, some adjacent membrane layers with the same processed membrane material are drawn as connected to make them resemble the actual structure.

[0050] This application first provides a method for forming an encapsulation structure. Figure 1 This is a flowchart illustrating the method for forming the encapsulation structure provided in some embodiments of this application. (Refer to...) Figure 1 The method for forming the encapsulation structure includes the following steps: Step S101: Provide a first wafer, the first wafer including opposing first and second surfaces, the first wafer including a plurality of first grains; Step S102: Provide a second wafer, the second wafer including opposing third and fourth surfaces, the second wafer including a plurality of second grains, the size of the first grain being larger than the size of the second grain; Step S103: Etch a portion of the third surface to form a first groove on a portion of the second grains; Step S104: Provide a third wafer, the third wafer including opposing fifth and sixth surfaces, the third wafer including a plurality of third grains, the size of the first grain being equal to or greater than the size of the third grain; Step S105: Bond the third surface of the second wafer to the second surface of the first wafer, such that a portion of the second grains are bonded to the corresponding first grains, while another portion of the second grains will not be bonded to the corresponding first grains due to the presence of the first groove. Step S106: Bond the sixth surface of the third wafer to the first surface of the first wafer, such that at least a portion of the third grains are bonded to the corresponding first grains; Step S107: Divide the bonded first wafer, second wafer and third wafer to form multiple discrete first chip stack structures.

[0051] The method for forming the packaging structure is described in detail below with reference to the accompanying drawings in some embodiments.

[0052] First, refer to the reference Figure 1 and Figure 2 In step S101, a first wafer 101 is provided. The first wafer 101 includes opposing second surfaces 12 and first surfaces 12. The first wafer 101 includes a plurality of first dies 102. The size of the first dies 102 is larger than that of the second dies 202 on the subsequently provided second wafer 201 (see reference). Figure 3 (size).

[0053] The first wafer 101 is subsequently bonded to the second wafer 201. The first surface 11 of the first wafer 101 is subsequently bonded to the sixth surface of the third wafer, and the second surface of the first wafer 101 is subsequently bonded to the third surface of the second wafer.

[0054] The material of the first wafer 101 can be a semiconductor material. In one example, the semiconductor material can be silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other III-V compounds. In some embodiments, the material of the first wafer 101 can be the same as or different from the material of the second wafer 201, that is, wafer bonding of the same or different materials can be achieved.

[0055] The first wafer 101 has a plurality of first dies 102 and a first dicing channel 104 located between adjacent first dies 102. The plurality of first dies 102 can be arranged in rows and columns. One first die 102 can correspond to one semiconductor chip. The plurality of first dies 102 can be formed on the first wafer 101 by integrated circuit manufacturing process.

[0056] The first wafer 101 can be of different sizes. In specific examples, the first wafer 101 can be 6 inches, 8 inches, or 12 inches, or it can be other sizes. In some embodiments, the size of the first wafer 101 is equal to the size of the subsequent second wafer 201. After the first wafer 101 and the second wafer 201 are subsequently bonded, the projection of the first dicing 104 on the third surface 21 of the second wafer 201 coincides with the projection of a portion of the first grooves 205 on the third surface (see reference). Figure 5The projection of the first dicing channel 104 on the third surface of the second wafer 201 also coincides with the projection of a portion of the second dicing channels 204 on the third surface. This facilitates the division of multiple bonded wafers into a chip stacking structure by using the second dicing channel 204 and the first dicing channel 104 during subsequent dicing.

[0057] In some embodiments, a first bonding layer (not shown) may be formed on the second surface 12 of the first wafer 101, and a second bonding layer (not shown) may be formed on the second surface 12. The first bonding layer serves as a bonding medium for subsequent bonding of the first wafer 101 and the third wafer 301, and the second bonding layer serves as a bonding medium for subsequent bonding of the first wafer 101 and the second wafer 201, thereby improving the bonding strength. In some embodiments, after the first grain 102 is formed on the first wafer 101, the first bonding layer is formed on the second surface 12 of the first wafer 101, and the second bonding layer may be formed on the second surface 12. In some embodiments, the materials of the first and second bonding layers comprise dielectric materials; in one example, the dielectric material comprises silicon oxide or silicon carbide. In other embodiments, the material of the first bonding layer comprises a combination of dielectric material and a metallic material; in one example, the dielectric material comprises silicon oxide or silicon carbide, and the metallic material comprises copper. In still other embodiments, the material of the first bonding layer comprises solder, wherein the solder material is tin or a tin alloy.

[0058] Next, refer to Figure 1 and Figure 3 In step S102, a second wafer 201 is provided. The second wafer 201 includes opposing third surfaces 21 and fourth surfaces 22. The second wafer 201 includes a plurality of second dies 202, the size of which is smaller than the size of the first die 102 or the size of the first die 102 is larger than the size of the second die 202. Continuing with reference to... Figure 1 and Figure 3 In step S103, a portion of the third surface 21 is etched to form a first groove 205 on a portion of the second grains 202.

[0059] The third surface 21 of the second wafer 201 subsequently connects to the first wafer 101 (reference). Figure 2 The second surface 12 of the second wafer 201 is bonded to the first wafer 101. The subsequent surface of the second wafer 201 that is bonded to the first wafer 101 is the third surface 21, and the surface opposite to the third surface 21 is the fourth surface 22.

[0060] The material of the second wafer 201 can be a semiconductor material. In one example, the semiconductor material can be silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other III-V compounds. The second wafer 201 can be of different sizes. In a specific example, the second wafer 201 can be 6 inches, 8 inches, or 12 inches, or it can be other sizes.

[0061] The second wafer 201 has a plurality of second dies 202 and a second dicing channel 204 located between adjacent second dies 202. The plurality of second dies 202 can be arranged in rows and columns, and one second die 202 can correspond to one semiconductor chip. The plurality of second dies 202 can be formed on the second wafer 201 by integrated circuit fabrication processes. In some embodiments, the second die 202 and the first die 102 are semiconductor chips with different functions. The semiconductor chips may include logic chips and / or memory chips. In some embodiments, the logic chip may include, but is not limited to, gate arrays, cell substrate arrays, embedded arrays, structured application integrated circuits (ASICs), field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), graphics processing units (GPUs), central processing units (CPUs), microprocessor units (MPUs), microcontroller units (MCUs), logic integrated circuits (ICs), application processors (APs), display driver ICs (DDIs), radio frequency (RF) chips, power supply chips, or complementary metal-oxide-semiconductor (CMOS) image sensors. In some embodiments, the memory chip may include, but is not limited to, Dynamic Random Access Memory (DRAM), Static Random-Access Memory (SRAM), Magnetoresistive Random Access Memory (MRAM), Phase-Change Memory (PRAM), Resistive Random Access Memory (RRAM), or non-volatile memory chips (such as flash memory). In a specific embodiment, the memory chip may include High Bandwidth Memory (HBM) containing DRAM chips.

[0062] The size of the second grain 202 is the same as that of the first grain 102 on the first wafer 101 (reference). Figure 2The sizes of the two dies are different. Specifically, the size of the second die 202 is smaller than the size of the first die 102 on the first wafer 101, or the size of the first die 102 on the first wafer 101 is larger than the size of the second die 202 on the second wafer 201. In a specific example, the size of the first die 102 can be an integer multiple of the size of the second die 202, such as 2 times, 3 times, 4 times or more. That is, after the first wafer 101 and the second wafer 201 are bonded, the projection of one first die 102 on the first wafer 101 onto the third surface can coincide with the projections of two, three, four or more second dies 202 on the third surface of the second wafer, which facilitates wafer bonding and subsequent splitting after bonding.

[0063] A portion of the second dies 202 have a first groove 205 formed penetrating the third surface 21, while the other second dies 202 do not have the first groove formed. This will be achieved when the third surface 21 of the second wafer 201 is subsequently bonded to the second surface 12 of the first wafer 101 (see reference). Figure 5 This allows a portion of the second grains 202 to bond with their corresponding first grains 102, while another portion of the second grains 202 will not bond with their corresponding first grains 102 due to the presence of the first groove 205. In other words, in this application, the first groove 205 is formed on second grains 202 that do not subsequently need to bond with the first grain 102, while the first groove is not formed on second grains 202 that do subsequently need to bond with the first grain 102. The number of first grooves 205 is equal to the number of second grains 202 that do not need to bond with the first grain 102.

[0064] The size of the first groove 205 is greater than or equal to the size of the second grain 202. In some embodiments, the size of the first groove 205 is the sum of the size of the second grain 202 and the size of the second dicing 204 surrounding the second grain 202. When the third surface 21 of the second wafer 201 is subsequently bonded to the second surface 12 of the first wafer 101, there will be no bonding between the second grain 202 with the first groove 205 and the surrounding second dicing 204 and the corresponding first grain 102. This facilitates the separation of the second grain 202 from the corresponding first grain 102 during subsequent separation and prevents damage to the first grain 102 during separation.

[0065] In some embodiments, the depth of the first groove 205 is greater than or equal to 2 micrometers, so that there is a sufficient distance between the second grain 202 and the corresponding first grain 102. When the third surface of the second wafer 201 is subsequently bonded to the second surface of the first wafer 101, there will be no bonding between the second grain 202 and the corresponding first grain 102, and it is convenient to separate the two during dicing.

[0066] In some embodiments, a portion of the third surface is etched to form a first groove 205 corresponding to the portion of the second grains 202. The process for forming the first groove 205 includes laser etching, chemical etching, or plasma etching.

[0067] In some embodiments, a third bonding layer (not shown) may be formed on the third surface 21 of the second wafer 201. This third bonding layer serves as a bonding medium for subsequent bonding between the second wafer 201 and the first wafer 101, thereby improving bonding strength. In some embodiments, after forming the second die 202 on the second wafer 201, the second bonding layer is formed on the third surface 21 of the second wafer 201. In some embodiments, a portion of the second bonding layer is etched away, forming the first groove 205 in the second bonding layer on the second die 202. In some embodiments, the materials of the first bonding layer on the first surface and the second bonding layer on the second surface of the first wafer 101, the third bonding layer on the third surface of the second wafer 201, and the sixth bonding layer formed on the sixth surface of the subsequent third wafer are all the same, to improve bonding strength during subsequent bonding. In other embodiments, the materials of the first bonding layer, the second bonding layer, the third bonding layer, and the sixth bonding layer may be different or partially the same.

[0068] In some embodiments, the material of the third bonding layer includes a dielectric material, in one example, the dielectric material includes silicon oxide or silicon carbide. In other embodiments, the material of the third bonding layer includes a combination of a dielectric layer material and a metallic material, in one example, the dielectric material includes silicon oxide or silicon carbide, and the metallic material includes copper. In still other embodiments, the material of the third bonding layer includes solder, the solder being tin or a tin alloy.

[0069] Next, in conjunction with references Figure 1 and Figure 4 In step S104, a third wafer 301 is provided, the third wafer 302 including opposing fifth surface 31 and sixth surface 32, the third wafer 301 including a plurality of third grains 302, the size of the third grains 302 being equal to or smaller than the size of the first grain 102 (see reference). Figure 2The size of the first grain 102 is equal to or greater than the size of the third grain 302.

[0070] The sixth surface 32 of the third wafer 301 subsequently connects to the first wafer 101 (reference). Figure 5 The bonding of the first surface 11 of the third wafer 301 to the first wafer 101. The subsequent surface of the third wafer 301 that is bonded to the first wafer 101 is the sixth surface 32, and the surface opposite to the sixth surface 32 is the fifth surface 31.

[0071] The material of the third wafer 301 may include semiconductor materials. In one example, the semiconductor material may be silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it may also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it may be other materials, such as gallium arsenide or other group III-V compounds. The third wafer 301 may be of different sizes. In a specific example, the third wafer 301 may be 6 inches, 8 inches, or 12 inches, or it may be other sizes.

[0072] The third wafer 301 has a plurality of third dies 302 and third dicing channels 304 located between adjacent third dies 302. The plurality of third dies 302 can be arranged in rows and columns, and one third die 302 can correspond to one semiconductor chip. The plurality of third dies 302 can be formed on the third wafer 301 by integrated circuit manufacturing processes. In some embodiments, the third dies 302 and the first die 102 are semiconductor chips with different functions, and the semiconductor chips may include logic chips and / or memory chips.

[0073] The size of the third grain 302 is less than or equal to the size of the first grain 102 on the first wafer 101 (reference). Figure 5 The dimensions of ) are, in some embodiments, referenced Figure 4 The size of the third die 302 is smaller than the size of the first die 102 on the first wafer 101, or the size of the first die 102 on the first wafer 101 is larger than the size of the third die 302 on the third wafer 301. In a specific example, the size of the first die 102 can be an integer multiple of the size of the third die 302, such as 2, 3, 4, or more times. That is, after the first wafer 101 and the third wafer 301 are subsequently bonded, the projection of one first die 102 on the first surface 11 of the first wafer 101 can coincide with the projections of two, three, four, or more third dies 302 on the first surface 11 of the third wafer 301, which facilitates wafer bonding and subsequent slitting after bonding. In other embodiments, refer to... Figure 7The size of the third grain 302 on the third wafer 301 is equal to the size of the first grain 102 on the first wafer 101, that is, the projection of the third grain 302 on the first surface 11 coincides with the projection of the first grain 102 on the first surface 11.

[0074] In some embodiments, continue to refer to Figure 4 A portion of the third wafers 302 form second grooves 305 penetrating the sixth surface 32, while other third wafers 302 do not form second grooves. This will be achieved when subsequently bonding the sixth surface 32 of the third wafer 301 to the first surface 11 of the first wafer 101 (see reference). Figure 5 This allows a portion of the third wafers 302 to bond with their corresponding first wafers 102, while another portion of the third wafers 302 will not bond with their corresponding first wafers 102 due to the presence of the second groove 305. In other words, in this application, the second groove 305 is formed on the third wafers 302 that do not subsequently need to bond with the first wafer 102, while the second groove is not formed on the third wafers 302 that do subsequently need to bond with the first wafer 102. The number of second grooves 305 is equal to the number of third wafers 302 that do not need to bond with the first wafer 102, thereby achieving bonding between the third wafer 301 and the first wafer 101 with different wafer sizes. In other embodiments, the second groove 305 penetrating the sixth surface 32 may not be formed on the third grain 302. Subsequently, when the third wafer 301 is bonded to the first wafer 101, all the third grains 302 on the third wafer 301 will be bonded to the corresponding first grains 102 on the first wafer 101 (see reference). Figure 7 ).

[0075] Continue to refer to Figure 4 The size of the second groove 305 is greater than or equal to the size of the third grain 302. In some embodiments, the size of the second groove 305 is the sum of the size of the third grain 302 and the size of the third dicing 304 surrounding the third grain 302. When the sixth surface 32 of the third wafer 301 is subsequently bonded to the first surface 11 of the first wafer 101, there will be no bonding between the third grain 302 with the second groove 305 and the surrounding third dicing 304 and the corresponding first grain 102. Subsequent separation facilitates the separation of the third grain 302 from the corresponding first grain 102 and prevents damage to the first grain 102 during separation.

[0076] In some embodiments, the depth of the second groove 305 is greater than or equal to 2 micrometers, so that there is a sufficient distance between the third grain 302 and the corresponding first grain 102. When the sixth surface 32 of the third wafer 301 is subsequently bonded to the first surface 11 of the first wafer 101, there will be no bonding between the third grain 302 and the corresponding first grain 102, and it is convenient to separate the two during cutting.

[0077] In some embodiments, a portion of the sixth surface is etched to form a second groove 305 corresponding to the portion of the third grains 302. The process for forming the second groove 305 includes laser etching, chemical etching, or plasma etching.

[0078] In some embodiments, a sixth bonding layer (not shown) may be formed on the sixth surface 32 of the third wafer 301. This sixth bonding layer serves as a bonding medium for subsequent bonding between the third wafer 301 and the first wafer 101, thereby improving the bonding strength. In some embodiments, the sixth bonding layer is formed on the sixth surface 32 of the third wafer 301 after the third die 302 is formed on the third wafer 301. In some embodiments, a portion of the sixth bonding layer is etched away, forming the second groove 305 in the sixth bonding layer on the third die 302. In some embodiments, the material of the sixth bonding layer includes a dielectric material, in one example, the dielectric material includes silicon oxide or silicon carbide. In other embodiments, the material of the sixth bonding layer includes a combination of a dielectric layer material and a metallic material, in one example, the dielectric material includes silicon oxide or silicon carbide, and the metallic material includes copper. In still other embodiments, the material of the sixth bonding layer includes solder, the solder being tin or a tin alloy.

[0079] Next, in conjunction with references Figure 1 and Figure 5 In step S105, the third surface 21 of the second wafer 201 is bonded to the second surface 12 of the first wafer 101, such that a portion of the second grains 202 are bonded to the corresponding first grains 102, while another portion of the second grains 202 will not be bonded to the corresponding first grains 102 due to the presence of the first groove 205; in step S106, the sixth surface 32 of the third wafer 301 is bonded to the first surface 11 of the first wafer 101, such that at least a portion of the third grains 302 are bonded to the corresponding first grains 101.

[0080] In some embodiments, before bonding the second wafer 201 to the first wafer 101, and before bonding the third wafer 301 to the first wafer 101, the first surface 11, the second surface 12, the third surface 21, and the sixth surface 32 are cleaned and activated respectively to further improve the bonding strength between the second wafer 201 and the first wafer 101, and between the third wafer 301 and the first wafer 101.

[0081] In some embodiments, after aligning the second wafer 201 with the first wafer 101, the third surface 21 of the second wafer 201 is bonded to the second surface 12 of the first wafer 101; after aligning the third wafer 301 with the first wafer 101, the sixth surface 32 of the third wafer 301 is bonded to the first surface 11 of the first wafer 101. In some embodiments, direct bonding, dielectric bonding, anodic bonding, or hybrid bonding processes can be used to bond the third surface 21 of the second wafer 201 to the second surface 12 of the first wafer 101, and to bond the sixth surface 32 of the third wafer 301 to the first surface 11 of the first wafer 101. In one specific example, the second wafer 201 may be bonded to the first wafer 101 before the third wafer 301 is bonded to the first wafer 101; in another specific example, the first wafer 101 may be bonded to the third wafer 301 before the second wafer 201 is bonded to the first wafer 101.

[0082] In some embodiments, continue to refer to Figure 5 When the third surface 21 of the second wafer 201 is bonded to the second surface 12 of the first wafer 101, a portion of the second grains 202 are bonded to the corresponding first grains 102, while another portion of the second grains 202 will not be bonded to the corresponding first grains 102 due to the presence of the first groove 205. In a specific example, refer to... Figure 5 After the third surface 21 of the second wafer 201 is bonded to the second surface 12 of the first wafer 101, when the projection of the two second dies 202 on the third surface 21 coincides with the projection of the corresponding first die 102 on the third surface 21, only one of the second dies 202 will bond with the first die 102, while the other second die 202 will not bond with the first die 102 due to the presence of the first groove 205.

[0083] In some embodiments, continue to refer to Figure 5When the sixth surface 32 of the third wafer 301 is bonded to the first surface 11 of the first wafer 101, a portion of the third grains 302 are bonded to the corresponding first grains 102, while another portion of the third grains 302 will not be bonded to the corresponding first grains 102 due to the presence of the second groove 305. In a specific example, refer to... Figure 5 After the sixth surface 32 of the third wafer 301 is bonded to the first surface 11 of the first wafer 101, when the projections of two third dies 302 on the first surface 11 coincide with the projection of a corresponding first die 102 on the first surface 11, only one of the third dies 302 will bond to the first die 102. Due to the presence of the second groove 305, the other third die 302 will not bond to the first die 102. In other embodiments, refer to... Figure 7 When there is no second groove on the third grain 302, when the sixth surface 32 of the third wafer 301 is bonded to the first surface 11 of the first wafer 101, all the third grains 302 on the third wafer 301 are bonded together with the corresponding first grains 102 on the first wafer 101.

[0084] This application implements multi-wafer bonding with dies of different sizes. Specifically, the size of the first die 102 on the first wafer 101 is larger than the size of the second die 202 on the second wafer 201, and the size of the third die 302 on the third wafer 301 is less than or equal to the size of the first die 102 on the first wafer 101. In some embodiments, the size of the first die 102 is an integer multiple of the size of the second die 202, that is, the projection of one first die 102 on the third surface 21 can coincide with the projection of multiple second dies 202 on the third surface 21, and the projection of one first die 102 on the first surface 11 can coincide with the projection of one or more third dies 302 on the first surface 11. In a specific example, the size of the first die 102 can be 2, 3, 4 or more times the size of the second die 202, so that the projection of one first die 102 on the third surface can coincide with the projections of two, three, four or more second dies 202 on the third surface. Subsequently, after the second wafer 201 and the first wafer 101 are bonded, one first die 102 will only be bonded to a portion of the number of second dies 202 that coincide with the projection, while the other portion of the number of second dies 202 will not be bonded to the first die 102 due to the presence of the first groove 205. For example, if the projection of one first die 102 on the third surface 21 coincides with the projections of two second dies 202 on the third surface 21, then after bonding the second wafer 201 and the first wafer 101, one of the two second dies 202 will bond to the first die 102, while the other second die 202, which has a first groove 205, will not bond to the first die 102. As another example, if the projection of one first die 102 on the third surface 21 coincides with the projections of three second dies 202 on the third surface 21, then after bonding the second wafer 201 and the first wafer 101, one or two of the three second dies 202 will bond to the first die 102, while the remaining two or one second die 202, which has a first groove 205, will not bond to the first die 102. In a specific example, the size of the first grain 102 can be 1, 2, 3, 4, or more times the size of the third grain 302, such that the projection of one first grain 102 on the first surface 11 can coincide with the projections of one, two, three, four, or more third grains 302 on the first surface 11. Subsequently, after bonding the third wafer 301 and the first wafer 101, the projection of one first grain 102 coincides with the projection of the corresponding third grain 302 on the first surface 11 (see reference). Figure 7Alternatively, one of the first grains 102 may only bond to a portion of the third grains 302 whose projections overlap, while the other portion of the third grains 302 whose projections overlap will not bond to the first grain 102 due to the presence of the second groove 305. For example, the projection of one first grain 102 on the third surface 21 may overlap with the projections of two third grains 302 on the third surface 21 (see reference). Figure 5 Subsequently, after bonding the second wafer 201 and the first wafer 101, one of the two third dies 302 will bond to the first die 102, while the other third die 302, which has a first groove 205, will not bond to the first die 102. Alternatively, if the projection of one first die 102 on the third surface 21 coincides with the projections of the three third dies 302 on the third surface 21, after bonding the second wafer 201 and the first wafer 101, one or two of the three third dies 302 will bond to the first die 102, while the remaining two or one third die 302, which has a first groove 205, will not bond to the first die 102. Finally, referring to the references Figure 1 and Figure 6 In step S107, the bonded first wafer 101, second wafer 201 and third wafer 301 are divided to form multiple discrete first chip stack structures 51.

[0085] In some embodiments, continue to refer to Figure 6 A first chip stack structure 51 includes a first die 102, at least one second die 202 bonded to a second surface of the first die 102, and at least one third die 302 bonded to the first surface of the first die 102. The second die 202 is electrically connected to the first die 102, and the third die 302 is electrically connected to the die 102. For example, a first chip stack structure 51 may include a first die 102 and a second die 202 bonded to the second surface of the first die 102 and electrically connected, and a third die 302 bonded to the first surface of the first die 102. As another example, a first chip stack structure 51 may include a first die 102 and two or more second dies 202 bonded to the second surface of the first die 102, and two or more third dies 302 bonded to the first surface of the first die 102. In one example, refer to... Figure 6The bonded first wafer 101, second wafer 201, and third wafer 301 are divided to form multiple discrete first chip stack structures 51. Simultaneously, due to the presence of the first groove 205, other second dies 202 on the second wafer 201 will not bond with the first die 102, resulting in several separate second dies 202. Similarly, due to the presence of the second groove 305, other third dies 302 on the third wafer 301 will not bond with the first die 102, also resulting in several separate third dies 302. In another example, refer to... Figure 8 The bonded first wafer 101, second wafer 201, and third wafer 301 are divided to form multiple discrete first chip stack structures 51. Simultaneously, other second dies 202 on the second wafer 201 are not bonded to the first dies 102 due to the presence of the first groove 205, resulting in several separate second dies 202. All third dies 302 on the third wafer 301 are bonded to their corresponding first dies 102. That is, the aforementioned steps in this application enable the bonding of multiple wafers with different die sizes to batch-produce the first chip stack structure 51, improving the manufacturing efficiency of the first chip stack structure 51. Furthermore, excess second dies 202 (and third dies 302) can be easily and without damage separated during the manufacturing process. The separated second dies 202 (and third dies 302) can be used for other packaging processes, thereby saving manufacturing costs.

[0086] In some embodiments, dividing the bonded first wafer 101, second wafer 201 and third wafer 301 includes dividing the bonded first wafer 101, second wafer 201 and third wafer 301 along the first dicing track 104, the second dicing track 204 and the third dicing track 304 respectively.

[0087] In some embodiments, blades are used to slit the bonded first wafer 101, second wafer 201, and third wafer 301.

[0088] Other embodiments of this application also provide a method for forming an encapsulation structure; please refer to the following for details. Figures 9-10 The main difference between this embodiment and the previous embodiments is that: (Refer to...) Figure 9 It also includes: providing a fourth wafer 401, the fourth wafer 401 including opposing seventh surfaces 41 and eighth surfaces 42, the fourth wafer 401 including a plurality of fourth grains 402, the size of the fourth grains 402 being equal to the size of the second grains 202; bonding the seventh surface 41 of the fourth wafer 401 to the fourth surface 22 of the second wafer 201, such that the fourth grains 402 are bonded to corresponding second grains 202; Reference Figure 10The bonded first wafer 101, second wafer 201, third wafer 301 and fourth wafer 401 are divided to form multiple discrete first chip stack structures 51 and multiple discrete second chip stack structures 52. The first chip stack structure 51 includes a first die 102, a second die 202 bonded to the second surface of the first die 102, a third die 302 bonded to the first surface of the first die 102, and a fourth die 402 bonded to the fourth surface 22 of the second die 202. The second chip stack structure 52 includes the second die 202 and the fourth die 402 bonded together.

[0089] The material of the fourth wafer 401 can be a semiconductor material. In one example, the semiconductor material can be silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other III-V compounds. In some embodiments, the material of the fourth wafer 401 can be the same as or different from the material of the second wafer 201, that is, bonding of multiple wafers of the same or different materials can be achieved.

[0090] The fourth wafer 401 has a plurality of fourth dies 402 and fourth dicing channels 404 located between adjacent fourth dies 402. The plurality of fourth dies 402 can be arranged in rows and columns, and one fourth die 402 can correspond to one semiconductor chip. The plurality of fourth dies 402 can be formed on the fourth wafer 401 by integrated circuit manufacturing processes. In some embodiments, the fourth dies 402 and the second dies 202 are semiconductor chips with different functions, and the semiconductor chips may include logic chips and / or memory chips. In other embodiments, the fourth dies 402 and the second dies 202 may also be semiconductor chips with the same function.

[0091] The fourth wafer 401 can be of different sizes. In a specific example, the fourth wafer 401 can be 6 inches, 8 inches, or 12 inches, or it can be other sizes. In some embodiments, reference continues to... Figure 4 The size of the fourth wafer 401 is equal to the size of the second wafer 201, the size of the fourth die 402 is the same as the size of the second die 202, and the size of the fourth dicing 404 is the same as the size of the second dicing 204. Their positions correspond. After bonding the fourth wafer 401 and the second wafer 201, the projection of the fourth die 402 onto the fourth surface 22 coincides with the projection of the second die 202 onto the fourth surface 22 (reference). Figure 9The projection of the fourth dicing 404 on the fourth surface 22 of the second wafer 201 coincides with the projection of the second dicing 204 on the fourth surface 22 (see reference). Figure 9 This facilitates the alignment and bonding of the fourth wafer 401 and the second wafer 201, and also facilitates the subsequent segmentation of the fourth wafer 401, the second wafer 201, the first wafer 101, and the third wafer 301 after bonding.

[0092] In other embodiments, the size of the second die 202 is larger than the size of the fourth die 402. This larger size includes the second die 202 being an integer multiple of the size of the fourth die 402, i.e., the second die 202 being 2, 3, 4, or more times the size of the fourth die 402. When the fourth wafer 401 is subsequently bonded to the second wafer 201, the projection of one second die 202 on the fourth surface 22 coincides with the projections of multiple fourth dies 402 on the fourth surface 22. For example, the projection of one second die 202 on the fourth surface 22 coincides with the projections of two, three, four, or more fourth dies 402 on the fourth surface 22. The projection of the fourth dicing 404 on the fourth surface 22 of the second wafer 201 coincides with at least a portion of the projections of the second dicing 204 on the fourth surface 22. In some embodiments, when the size of the second grain 202 is an integer multiple of the size of the fourth grain 402, multiple fourth grains can be simultaneously bonded to one second grain 202 when the fourth wafer 401 is subsequently bonded to the second wafer 201. In other embodiments, a third groove penetrating the seventh surface 41 can be formed on some of the fourth grains 402, such that a portion of the fourth grains 402 are bonded to the corresponding second grains 202, while another portion of the fourth grains 402 will not be bonded to the corresponding second grains 202 due to the presence of the third groove.

[0093] In some embodiments, a seventh bonding layer (not shown) may be formed on the seventh surface 41 of the fourth wafer 401. This seventh bonding layer serves as a bonding medium for subsequent bonding of the fourth wafer 401 and the second wafer 201, thereby improving the bonding strength. In some embodiments, the seventh bonding layer is formed on the seventh surface 41 of the fourth wafer 401 after the fourth grain 402 is formed on the fourth wafer 401. In some embodiments, the material of the seventh bonding layer includes a dielectric material, and in one example, the dielectric material includes silicon oxide or silicon carbide. In other embodiments, the material of the seventh bonding layer includes a combination of a dielectric layer material and a metallic material, and in one example, the dielectric material includes silicon oxide or silicon carbide, and the metallic material includes copper. In still other embodiments, the material of the seventh bonding layer includes solder, and the solder material is tin or a tin alloy.

[0094] In this embodiment, the aforementioned steps enable the bonding of multiple wafers with different die sizes to batch-produce the first chip stack structure 51 and the second chip stack structure 52, thereby improving the manufacturing efficiency of the first chip stack structure 51 and the second chip stack structure 52, and enabling the simultaneous fabrication of first chip stack structures 51 and second chip stack structures 52 with different functions. In one example, the bonded first wafer 101, second wafer 201, third wafer 301, and fourth wafer 401 are divided to form multiple discrete first chip stack structures 51 and multiple discrete second chip stack structures 52. At the same time, several separated third dies 302 (and fourth dies 402) can be obtained, and the excess third dies 302 (and fourth dies 402) can be easily and without damage separated. The separated third dies 302 (and fourth dies 402) can be used for other packaging processes, thereby saving manufacturing costs.

[0095] Other embodiments of this application also provide a method for forming a packaging structure. The main difference between this embodiment and the foregoing embodiments is that it further includes: providing a fifth wafer (not shown in the figure), the fifth wafer including opposing ninth and tenth surfaces, the fifth wafer including a plurality of fifth grains, the size of the fifth grains being equal to the size of the third grain 302; The tenth surface of the fifth wafer is bonded to the fifth surface 31 of the third wafer 301, such that at least a portion of the fifth grains are bonded to the corresponding third grains 302; The bonded first wafer 101, second wafer 201, third wafer 301, fourth wafer 401, and fifth wafer 501 are divided to form multiple discrete first chip stack structures, multiple discrete second chip stack structures, and multiple discrete third chip stack structures. The first chip stack structure includes a first die 102, a second die 202 bonded to a second surface of the first die 102, a third die 302 bonded to a first surface of the first die 102, a fourth die 402 bonded to a fourth surface of the second die 202, and a fifth die bonded to a fifth surface of the third die 302. The second chip stack structure includes the second die 202 and the fourth die 402 bonded together. The third chip stack structure includes the third die 302 and the fifth die bonded together. In some examples, in addition to obtaining multiple discrete first chip stack structures, multiple discrete second chip stack structures, and multiple discrete third chip stack structures, several separate fourth dies 402 (and fifth dies) can also be obtained.

[0096] In some embodiments, all fifth grains on the fifth wafer are bonded to the corresponding third grains.

[0097] In some embodiments, a portion of the fifth grains on the fifth wafer are bonded to corresponding third grains 302. Specifically, a portion of the fifth grains have a fourth groove penetrating the tenth surface. When the tenth surface of the fifth wafer is bonded to the fifth surface of the third wafer, such that at least a portion of the fifth grains are bonded to the corresponding third grains, a portion of the fifth grains are bonded to the corresponding third grains, while another portion of the fifth grains are not bonded to the corresponding third grains due to the presence of the fourth groove.

[0098] In this embodiment, the first chip stack structure, the second chip stack structure, and the third chip stack structure are manufactured in batches, improving the manufacturing efficiency of the first chip stack structure, the second chip stack structure, and the third chip stack structure. It can also manufacture first chip stack structures, second chip stack structures, and third chip stack structures with different functions at the same time. In addition, the excess fifth die (and fourth die) during the manufacturing process can be easily and without damage separated. The separated fifth die (and fourth die) can be used for other packaging processes, thereby saving manufacturing costs.

[0099] This application also provides a packaging structure, see reference. Figure 5 ,include: A first wafer 101 includes opposing first surfaces 11 and second surfaces 12, and the first wafer 101 includes a plurality of first grains 102; The second wafer 201 includes opposing third surface 21 and fourth surface 22. The second wafer 201 includes a plurality of second dies 202. The size of the first die 102 is larger than the size of the second die 202. A portion of the second dies 202 have a first groove 205 penetrating the third surface 21. The third wafer 301 includes a fifth surface 31 and a sixth surface 32 opposite to each other, and the third wafer 301 includes a plurality of third grains 302, wherein the size of the first grain 102 is equal to or greater than the size of the third grain 302. The third surface 21 of the second wafer 201 is bonded to the second surface 12 of the first wafer 101, such that a portion of the second grains 202 are bonded to the corresponding first grains 102, while another portion of the second grains 202 will not be bonded to the corresponding first grains 102 due to the presence of the first groove 205. The sixth surface 32 of the third wafer 301 is bonded to the first surface 11 of the first wafer 101, such that at least a portion of the third grains 302 are bonded to the corresponding first grains 102.

[0100] In some embodiments, reference Figure 9 It also includes: a fourth wafer 401, the fourth wafer 401 including opposing seventh surface 41 and eighth surface 42, the fourth wafer 401 including a plurality of fourth grains 402, the size of the second grain 202 being equal to the size of the fourth grain 402; The seventh surface 41 of the fourth wafer 401 is bonded to the fourth surface 22 of the second wafer 201, so that the fourth grain 402 is bonded to the corresponding second grain 202. The first wafer 101 further includes a first dicing channel 104 located between adjacent first dies 102; the second wafer 201 further includes a second dicing channel 204 located between adjacent second dies 202; the third wafer 301 further includes a third dicing channel 304 located between adjacent third dies 302; and the fourth wafer 401 further includes a fourth dicing channel 404 located between adjacent fourth dies 402.

[0101] In some embodiments, the size of the first groove 205 is greater than or equal to the size of the second grain 202.

[0102] In some embodiments, the size of the first groove 205 is the sum of the size of the second grain 202 and the size of the second kerf 204 around the second grain 202.

[0103] In some embodiments, the size of the first grain 102 being larger than the size of the second grain 202 includes: the size of the first grain 102 being an integer multiple of the size of the second grain 202; The fact that the size of the first grain 102 is greater than the size of the third grain 302 includes: the size of the first grain 102 being an integer multiple of the size of the third grain 302.

[0104] In some embodiments, the projection of one of the first grains 102 on the third surface 21 coincides with the projection of a plurality of the second grains 202 on the third surface 21; When the size of the first grain 102 is larger than the size of the third grain 302, the projection of one first grain 102 on the first surface 11 coincides with the projection of multiple third grains 302 on the first surface 11.

[0105] In some embodiments, reference Figure 7 The sixth surface 32 of the third wafer 301 is bonded to the first surface 11 of the first wafer 101, such that at least a portion of the third grains 302 are bonded to the corresponding first grains 102, including: all the third grains 302 on the third wafer 301 are bonded to the corresponding first grains 102.

[0106] In some embodiments, continue to refer to Figure 5 The sixth surface 32 of the third wafer 301 is bonded to the first surface 11 of the first wafer 101, such that at least a portion of the third grains 302 are bonded to the corresponding first grains 102, including: a portion of the third grains 302 on the third wafer 301 are bonded to the corresponding first grains 102, and another portion of the third grains 302 are not bonded to the corresponding first grains 102.

[0107] In some embodiments, continue to refer to Figure 5 The third wafer 301 further includes a third dicing channel 304 located between adjacent third dies 302, and the third wafer 301 further includes a second groove 305 located on a portion of the third dies 302 and penetrating the sixth surface 32; the size of the second groove 305 is the sum of the size of the third die 302 and the size of the third dicing channel 304 around the third die 302; When the sixth surface 32 of the third wafer 301 is bonded to the first surface 11 of the first wafer 101, a portion of the third grains 302 are bonded to the corresponding first grains 102, while another portion of the third grains 302 will not be bonded to the corresponding first grains 102 due to the presence of the second groove 305.

[0108] In some embodiments, it further includes: a fifth wafer, the fifth wafer including opposing ninth and tenth surfaces, the fifth wafer including a plurality of fifth grains, the size of the fifth grains being equal to the size of the third grain 302; The tenth surface of the fifth wafer is bonded to the fifth surface 31 of the third wafer 301, such that at least a portion of the fifth grains are bonded to the corresponding third grains 302.

[0109] It should be noted that the limitations or descriptions of the same or similar parts in this embodiment (encapsulation structure) and the foregoing embodiment (method of forming encapsulation structure) will not be repeated in this embodiment. Please refer to the limitations or descriptions of the corresponding parts in the foregoing embodiment for details.

[0110] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0111] It should be noted that, where there is no conflict, the features in the different embodiments of this application described above can be combined with each other. Furthermore, in each of the above embodiments, the focus is on describing the differences from other embodiments; other specific descriptions of the same / similar parts between the embodiments can be referred to (or referenced) interchangeably. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this application.

[0112] Although this application has been disclosed above with reference to preferred embodiments, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.

Claims

1. A method for forming an encapsulation structure, characterized in that, include: A first wafer is provided, the first wafer including opposing first and second surfaces, the first wafer including a plurality of first grains; A second wafer is provided, the second wafer including opposing third and fourth surfaces, the second wafer including a plurality of second grains, the size of the first grains being larger than the size of the second grains; The third surface is etched to form a first groove on a portion of the second grains; A third wafer is provided, the third wafer including opposing fifth and sixth surfaces, the third wafer including a plurality of third grains, the size of the first grains being equal to or greater than the size of the third grains; The third surface of the second wafer is bonded to the second surface of the first wafer, such that a portion of the second grains are bonded to the corresponding first grains, while another portion of the second grains will not be bonded to the corresponding first grains due to the presence of the first groove. The sixth surface of the third wafer is bonded to the first surface of the first wafer, such that at least a portion of the third grains are bonded to the corresponding first grains; The bonded first wafer, second wafer, and third wafer are divided to form multiple discrete first chip stack structures.

2. The method for forming the packaging structure according to claim 1, characterized in that, Also includes: A fourth wafer is provided, the fourth wafer including opposing seventh and eighth surfaces, the fourth wafer including a plurality of fourth grains, the size of the second grain being equal to the size of the fourth grain; The seventh surface of the fourth wafer is bonded to the fourth surface of the second wafer, such that the fourth grain is bonded to the corresponding second grain; The bonded first wafer, second wafer, third wafer, and fourth wafer are divided to form multiple discrete first chip stack structures and multiple discrete second chip stack structures. The first chip stack structure includes a first die, a second die bonded to a second surface of the first die, a third die bonded to a first surface of the first die, and a fourth die bonded to a fourth surface of the second die. The second chip stack structure includes a second die and a fourth die bonded together. The first wafer further includes a first dicing channel located between adjacent first dies; the second wafer further includes a second dicing channel located between adjacent second dies; the third wafer further includes a third dicing channel located between adjacent third dies; and the fourth wafer further includes a fourth dicing channel located between adjacent fourth dies.

3. The method for forming the packaging structure according to claim 2, characterized in that, The size of the first groove is greater than or equal to the size of the second grain.

4. The method for forming the packaging structure according to claim 3, characterized in that, The size of the first groove is the sum of the size of the second grain and the size of the second kerf around the second grain.

5. The method for forming the packaging structure according to claim 2, characterized in that, The size of the first wafer is equal to the size of the second wafer, the size of the third wafer is equal to the size of the first wafer, the size of the fourth wafer is equal to the size of the second wafer, the projection of the first dicing on the third surface of the second wafer coincides with the projection of a portion of the first grooves on the third surface, the projection of the third dicing on the first surface of the first wafer coincides with at least a portion of the projection of the first dicing on the first surface, and the projection of the fourth dicing on the third surface of the second wafer coincides with at least a portion of the projection of the second dicing on the third surface.

6. The method for forming the packaging structure according to claim 5, characterized in that, The condition that the size of the first grain is greater than the size of the second grain includes: the size of the first grain being an integer multiple of the size of the second grain; The condition that the size of the first grain is greater than the size of the third grain includes: the size of the first grain being an integer multiple of the size of the third grain.

7. The method for forming the packaging structure according to claim 6, characterized in that, The projection of one of the first grains on the third surface coincides with the projections of multiple second grains on the third surface; When the size of the first grain is larger than the size of the third grain, the projection of one of the first grains on the first surface coincides with the projection of multiple third grains on the first surface.

8. The method for forming the packaging structure according to claim 7, characterized in that, Dividing the bonded first wafer, second wafer, third wafer, and fourth wafer includes dividing the bonded first wafer, second wafer, third wafer, and fourth wafer along the first dicing track, the second dicing track, and the fourth dicing track, respectively.

9. The method for forming the packaging structure according to claim 1, characterized in that, Bonding the sixth surface of the third wafer to the first surface of the first wafer, such that at least a portion of the third grains are bonded to the corresponding first grains, includes: bonding all the third grains on the third wafer to the corresponding first grains.

10. The method for forming the packaging structure according to claim 9, characterized in that, The bonded first wafer, second wafer, and third wafer are divided to form multiple discrete first chip stack structures, while obtaining several separate second dies. A first chip stack structure includes a first die, at least one second die bonded to a second surface of the first die, and at least one third die bonded to a first surface of the first die.

11. The method for forming the packaging structure according to claim 1, characterized in that, Bonding the sixth surface of the third wafer to the first surface of the first wafer, such that at least a portion of the third grains are bonded to the corresponding first grains, comprises: bonding a portion of the third grains on the third wafer to the corresponding first grains, while another portion of the third grains are not bonded to the corresponding first grains.

12. The method for forming the packaging structure according to claim 11, characterized in that, The third wafer further includes a third dicing located between adjacent third grains, and the forming method further includes: etching a sixth surface of a portion of the third wafer, and forming a second groove on a portion of the third grains; the size of the second groove is the sum of the size of the third grain and the size of the third dicing around the third grain; When the sixth surface of the third wafer is bonded to the first surface of the first wafer, a portion of the third grains are bonded to the corresponding first grains, while another portion of the third grains are not bonded to the corresponding first grains due to the presence of the second groove.

13. The method for forming the packaging structure according to claim 12, characterized in that, The bonded first wafer, second wafer, and third wafer are divided to form multiple discrete first chip stack structures, while simultaneously obtaining several separate second and third dies.

14. The method for forming the packaging structure according to claim 13, characterized in that, A first chip stack structure includes a first die and at least one second die bonded to the first die, and a second chip stack structure includes a second die and a fourth die bonded together.

15. The method for forming the packaging structure according to claim 1, characterized in that, Also includes: A fifth wafer is provided, the fifth wafer including opposing ninth and tenth surfaces, the fifth wafer including a plurality of fifth grains, the size of the fifth grains being equal to the size of the third grains; The tenth surface of the fifth wafer is bonded to the fifth surface of the third wafer, such that at least a portion of the fifth grains are bonded to the corresponding third grains; The bonded first wafer, second wafer, third wafer, fourth wafer, and fifth wafer are divided to form multiple discrete first chip stack structures, multiple discrete second chip stack structures, and multiple discrete third chip stack structures.

16. The method for forming the packaging structure according to claim 1, characterized in that, The first surface has a first bonding layer, the second surface has a second bonding layer, the third surface has a third bonding layer, and the sixth surface has a sixth bonding layer.

17. The method for forming the packaging structure according to claim 16, characterized in that, The first bonding layer, the second bonding layer, the third bonding layer, and the sixth bonding layer are all made of the same material.

18. The method for forming the packaging structure according to claim 17, characterized in that, The materials of the first bonding layer, the second bonding layer, the third bonding layer and the fourth bonding layer include dielectric materials, or a combination of dielectric layer materials and metallic materials, or solder.

19. The method for forming the packaging structure according to claim 18, characterized in that, The dielectric material includes silicon oxide or silicon carbide; the metallic material includes copper; and the solder includes tin or a tin alloy.

20. The method for forming the packaging structure according to claim 16, characterized in that, After forming a plurality of first grains on the first wafer, the first bonding layer is formed on the first surface of the first wafer; and the second bonding layer is formed on the second surface of the first wafer.

21. The method for forming the packaging structure according to claim 16, characterized in that, After the second grain is formed on the second wafer, the third bonding layer is formed on the third surface of the second wafer.

22. The method for forming the packaging structure according to claim 21, characterized in that, The third bonding layer is etched to form the first groove in the third bonding layer.

23. The method for forming the packaging structure according to claim 16, characterized in that, After the third grain is formed on the third wafer, the sixth bonding layer is formed on the sixth surface of the third wafer.

24. The method for forming the packaging structure according to claim 23, characterized in that, The sixth bonding layer is etched to form a second groove in the sixth bonding layer.

25. The method for forming the packaging structure according to claim 16, characterized in that, The third surface of the second wafer is bonded to the second surface of the first wafer using a direct bonding process, a dielectric bonding process, an anodic bonding process, or a hybrid bonding process, and the sixth surface of the third wafer is bonded to the first surface of the first wafer.

26. A packaging structure, characterized in that, include: A first wafer, the first wafer including opposing first and second surfaces, the first wafer including a plurality of first grains; The second wafer includes opposing third and fourth surfaces, and includes a plurality of second grains, the size of the first grains being larger than the size of the second grains, and a portion of the second grains having a first groove penetrating the third surface; The third wafer includes opposing fifth and sixth surfaces, and the third wafer includes a plurality of third grains, wherein the size of the first grain is equal to or greater than the size of the third grain; The third surface of the second wafer is bonded to the second surface of the first wafer, such that a portion of the second grains are bonded to the corresponding first grains, while another portion of the second grains will not be bonded to the corresponding first grains due to the presence of the first groove; The sixth surface of the third wafer is bonded to the first surface of the first wafer, such that at least a portion of the third grains are bonded to the corresponding first grains.

27. The packaging structure according to claim 26, characterized in that, Also includes: A fourth wafer, the fourth wafer including opposing seventh and eighth surfaces, the fourth wafer including a plurality of fourth grains, the size of the second grain being equal to the size of the fourth grain; The seventh surface of the fourth wafer is bonded to the fourth surface of the second wafer, such that the fourth grain is bonded to the corresponding second grain; The first wafer further includes a first dicing channel located between adjacent first dies; the second wafer further includes a second dicing channel located between adjacent second dies; the third wafer further includes a third dicing channel located between adjacent third dies; and the fourth wafer further includes a fourth dicing channel located between adjacent fourth dies.

28. The packaging structure according to claim 27, characterized in that, The size of the first groove is greater than or equal to the size of the second grain.

29. The packaging structure according to claim 28, characterized in that, The size of the first groove is the sum of the size of the second grain and the size of the second kerf around the second grain.

30. The packaging structure according to claim 26, characterized in that, The condition that the size of the first grain is greater than the size of the second grain includes: the size of the first grain being an integer multiple of the size of the second grain; The condition that the size of the first grain is greater than the size of the third grain includes: the size of the first grain being an integer multiple of the size of the third grain.

31. The packaging structure according to claim 30, characterized in that, The projection of one of the first grains on the third surface coincides with the projections of multiple second grains on the third surface; When the size of the first grain is larger than the size of the third grain, the projection of one of the first grains on the first surface coincides with the projection of multiple third grains on the first surface.

32. The packaging structure according to claim 26, characterized in that, The sixth surface of the third wafer is bonded to the first surface of the first wafer, such that at least a portion of the third grains are bonded to the corresponding first grains, including: all the third grains on the third wafer are bonded to the corresponding first grains.

33. The packaging structure according to claim 26, characterized in that, The sixth surface of the third wafer is bonded to the first surface of the first wafer, such that at least a portion of the third grains are bonded to the corresponding first grains, including: a portion of the third grains on the third wafer are bonded to the corresponding first grains, and another portion of the third grains are not bonded to the corresponding first grains.

34. The packaging structure according to claim 33, characterized in that, The third wafer further includes a third dicing channel located between adjacent third dies, and the third wafer further includes a second groove extending through the sixth surface on a portion of the third dies; the size of the second groove is the sum of the size of the third die and the size of the third dicing channel around the third die; When the sixth surface of the third wafer is bonded to the first surface of the first wafer, a portion of the third grains are bonded to the corresponding first grains, while another portion of the third grains are not bonded to the corresponding first grains due to the presence of the second groove.

35. The packaging structure according to claim 26, characterized in that, Also includes: The fifth wafer includes opposing ninth and tenth surfaces, and the fifth wafer includes a plurality of fifth grains, the size of which is equal to the size of the third grain; The tenth surface of the fifth wafer is bonded to the fifth surface of the third wafer, such that at least a portion of the fifth grains are bonded to the corresponding third grains.

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