Passivation layer structure and method of manufacture

Abstract

The application discloses a kind of passivation layer structure and preparation method, belong to power semiconductor surface passivation field.Structure contains silicon oxide-based first passivation layer, silane-silicon dioxide second passivation layer, silicon nitride-based third passivation layer, can add polyimide layer;Using PECVD, silane oxidation deposition preparation, cooperate stage gas control annealing and photolithography etching, while simplifying process and reducing cost, solve the stress cracking problem of traditional passivation layer, improve the water vapor and sodium ion blocking capacity, enhance the reliability of power semiconductor in complex environment, in electric vehicle motor controller, photovoltaic inverter, wind power converter and industrial frequency converter etc. Field has wide application prospect.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor surface passivation technology, specifically relating to a passivation layer structure and its preparation method. Background Technology

[0002] A passivation layer structure provided by existing technology, such as Figure 1 As shown, from bottom to top, they are: BPSG (borophosphosilicate glass), Barrier-Ti / TiN (barrier layer - titanium / titanium nitride), PMD (interlayer dielectric or metal front dielectric), AL Electrode (aluminum electrode), and Si3N4 (silicon nitride), with pure silicon nitride used as a surface passivation material.

[0003] Power semiconductor surface passivation technology effectively blocks the penetration of water vapor and sodium ions by depositing an insulating dielectric layer, namely pure silicon nitride, on the semiconductor surface, preventing device corrosion and electrical performance degradation. At the same time, its high dielectric strength and high hardness can effectively improve the withstand voltage and reduce wear to resist mechanical damage. However, its step coverage ability is poor, and uneven film or cracks are prone to appear on complex surface structures. In addition, the thermal expansion coefficient is not matched with that of the metal layer (such as aluminum), which can cause thermal cycling stress cracking problems in high temperature (>150℃), high voltage (>650V) and high humidity (85℃ / 85%RH) reliability tests.

[0004] On the other hand, in order to provide better protection for the device, CN101127357A provides a sandwich passivation layer structure with sidewalls, which uses multiple layers of passivation materials to protect the device. However, due to issues such as thermal expansion coefficient matching and stress accumulation, the surface passivation material will form local stress concentration, which will cause cracks in the passivation material, ultimately leading to increased leakage current or even failure of the device. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, the present invention is achieved through the following technical solution:

[0006] A first aspect of the present invention provides a passivation layer structure, the passivation layer structure comprising:

[0007] First passivation layer based on silicon oxide;

[0008] A second passivation layer on top of a first passivation layer;

[0009] A third passivation layer based on silicon nitride on the second passivation layer.

[0010] A polyimide layer is also formed on the silicon nitride-based third passivation layer.

[0011] The first passivation layer based on silicon oxide is a low-stress tetraethyl orthosilicate layer; the second passivation layer is a silane-silicon dioxide layer; and the third passivation layer based on silicon nitride is a high-resistivity silicon nitride layer.

[0012] The thickness of the low-stress tetraethyl orthosilicate layer is 0.05-0.3 μm, the thickness of the silane-silica layer is 0.05-0.5 μm, and the thickness of the high-resistivity silicon nitride layer is 0.5-3 μm.

[0013] The polyimide layer has a thickness of 10-20 μm before curing and a thickness of 5-10 μm after curing.

[0014] A second aspect of the present invention provides a method for preparing a passivation layer, comprising the following steps:

[0015] Forming a first passivation layer based on silicon oxide;

[0016] A second passivation layer is formed on the first passivation layer;

[0017] A silicon nitride-based third passivation layer is formed on the second passivation layer.

[0018] It also includes: forming a polyimide layer on the third passivation layer.

[0019] The first passivation layer based on silicon oxide and the third passivation layer based on silicon nitride are formed by plasma-enhanced chemical vapor deposition; the second passivation layer is formed by silane oxidation deposition, and the oxidant introduced during the formation process is nitrous oxide.

[0020] It also includes: annealing after forming the passivation layer structure; when the total thickness of the first, second, and third passivation layers is 0.6-1.4 μm, the annealing temperature is 300-350℃ and the annealing time is 30-90 min; when the total thickness of the first, second, and third passivation layers is 1.4-2.2 μm, the annealing temperature is 400-450℃ and the annealing time is 30-90 min; when the total thickness of the first, second, and third passivation layers is 2.2-3.0 μm, the annealing temperature is 450-500℃ and the annealing time is 30-90 min; when the total thickness of the first, second, and third passivation layers is 3.0-3.8 μm, the annealing temperature is 500℃ and the annealing time is 30-60 min.

[0021] It also includes: introducing nitrogen gas at a flow rate of 5000 sccm during the annealing heating and cooling stages; and introducing oxygen gas at a flow rate of 5000 sccm during the annealing isothermal stage.

[0022] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0023] The bottom layer of this invention uses low-stress tetraethyl orthosilicate (TEOS) to buffer the stress generated by the thermal expansion and contraction of the metal layer; the middle layer SiH4-SiO2 serves as a transition layer to further alleviate interlayer stress; the top layer high-resistivity silicon nitride (HRN) provides mechanical protection, and with the help of a specific annealing process, it releases internal stress, effectively improving the adhesion and density of the passivation layer, releasing internal stress, avoiding cracking problems caused by local stress concentration, and significantly improving the long-term reliability of the device under high temperature, high pressure, and high humidity environments. This enables the device to withstand more than 1000 cycles of temperature cycling tests from -55 to 175°C and 1000 hours of H3TRB verification, reducing water vapor permeability to below 1×10-9 g / cm²·day, and significantly improving sodium ion blocking ability and critical fracture toughness.

[0024] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0025] Figure 1 This is a diagram of a prior art passivation layer structure provided by an embodiment of the present invention;

[0026] Figure 2 This is a passivation layer structure diagram provided in the first embodiment of the present invention;

[0027] Figure 3 This is a passivation layer structure diagram provided in the second embodiment of the present invention;

[0028] Figure 4 This is a passivation layer structure diagram provided in the third embodiment of the present invention;

[0029] Figure 5 This is a passivation layer structure diagram provided in the fourth embodiment of the present invention. Detailed Implementation

[0030] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description of the solution according to the present invention is provided in conjunction with the accompanying drawings and specific embodiments.

[0031] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0032] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element.

[0033] Please see Figure 2 , Figure 2 The diagram shows a passivation layer structure provided in the first embodiment of the present invention. From bottom to top, the structure consists of BPSG (borophosphosilicate glass), Barrier-Ti / TiN (barrier layer - titanium / titanium nitride), PMD (interlayer dielectric or metal pre-dielectric), AL Electrode (aluminum electrode), a first passivation layer based on silicon oxide, a second passivation layer on the first passivation layer, and a third passivation layer based on silicon nitride on the second passivation layer.

[0034] The first passivation layer based on silicon oxide is a low-stress tetraethyl orthosilicate layer; the second passivation layer is a silane-silicon dioxide layer; and the third passivation layer based on silicon nitride is a high-resistivity silicon nitride layer. The thickness of the low-stress tetraethyl orthosilicate layer is 0.05-0.3 μm, the thickness of the silane-silicon dioxide layer is 0.05-0.5 μm, and the thickness of the high-resistivity silicon nitride layer is 0.5-3 μm.

[0035] Please see Figure 3 , Figure 3 The diagram shows a passivation layer structure provided in the second embodiment of the present invention. From bottom to top, the structure consists of BPSG (borophosphosilicate glass), Barrier-Ti / TiN (barrier layer - titanium / titanium nitride), PMD (interlayer dielectric or metal pre-dielectric), AL Electrode (aluminum electrode), a first passivation layer based on silicon oxide, a second passivation layer on the first passivation layer, a third passivation layer based on silicon nitride on the second passivation layer, and a polyimide layer formed on the third passivation layer based on silicon nitride.

[0036] The first passivation layer based on silicon oxide is a low-stress tetraethyl orthosilicate layer; the second passivation layer is a silane-silica layer; and the third passivation layer based on silicon nitride is a high-resistivity silicon nitride layer. The thickness of the low-stress tetraethyl orthosilicate layer is 0.05-0.3 μm, the thickness of the silane-silica layer is 0.05-0.5 μm, the thickness of the high-resistivity silicon nitride layer is 0.5-3 μm, and the thickness of the polyimide layer before curing is 10-20 μm, and the thickness after curing is 5-10 μm.

[0037] Please see Figure 4 , Figure 4 The diagram shows a passivation layer structure provided in the third embodiment of the present invention. From bottom to top, the structure consists of BPSG (borophosphosilicate glass), Barrier-Ti / TiN (barrier layer - titanium / titanium nitride), PMD (interlayer dielectric or metal pre-dielectric), AL Electrode (aluminum electrode), a first passivation layer based on silicon oxide, a second passivation layer on the first passivation layer, and a third passivation layer based on silicon nitride on the second passivation layer.

[0038] The first passivation layer based on silicon oxide is a low-stress tetraethyl orthosilicate layer; the second passivation layer is a silicon nitride (Si3N4) layer; the third passivation layer based on silicon nitride is a high-resistivity silicon nitride layer; wherein the thickness of the low-stress tetraethyl orthosilicate layer is 0.05-0.3μm, the thickness of the silicon nitride layer is 0.05-0.5μm, and the thickness of the high-resistivity silicon nitride layer is 0.5-3μm.

[0039] Please see Figure 5 , Figure 5 The following is a passivation layer structure diagram provided in the fourth embodiment of the present invention. From bottom to top, the structure consists of BPSG (borophosphosilicate glass), Barrier-Ti / TiN (barrier layer - titanium / titanium nitride), PMD (interlayer dielectric or metal pre-dielectric), AL Electrode (aluminum electrode), a silicon oxide-based first passivation layer, a second passivation layer on the first passivation layer, a silicon nitride-based third passivation layer on the second passivation layer, and a polyimide layer formed on the silicon nitride-based third passivation layer.

[0040] The first passivation layer based on silicon oxide is a low-stress tetraethyl orthosilicate layer; the second passivation layer is a silicon nitride (Si3N4) layer; the third passivation layer based on silicon nitride is a high-resistivity silicon nitride layer; wherein the thickness of the low-stress tetraethyl orthosilicate layer is 0.05-0.3μm, the thickness of the silicon nitride layer is 0.05-0.5μm, the thickness of the high-resistivity silicon nitride layer is 0.5-3μm, the thickness of the polyimide layer before curing is 10-20μm, and the thickness after curing is 5-10μm.

[0041] The fifth embodiment of the present invention provides a method for preparing a passivation layer, which is used to prepare the passivation layer structures of the first to fourth embodiments, including the following steps:

[0042] Forming a first passivation layer based on silicon oxide;

[0043] A second passivation layer is formed on the first passivation layer;

[0044] A silicon nitride-based third passivation layer is formed on the second passivation layer.

[0045] Preferably, after the passivation layer is deposited, the etching area is defined by photolithography, and plasma etching is performed in the etching area to remove the passivation layer in the non-protected area while retaining the passivation layer structure in the protected area.

[0046] A polyimide layer is formed on the third passivation layer.

[0047] Preferably, after the polyimide layer is formed, photolithography is performed to define the area to be protected. The polyimide layer of the protected area is removed by plasma etching, leaving only the area to be protected. The remaining polyimide layer covers the edge of the underlying passivation layer (i.e. the boundary between the passivation layer and the non-passivation area) with a width of at least 5 μm, forming a wrap-around protection for the edge of the passivation layer.

[0048] The first passivation layer based on silicon oxide and the third passivation layer based on silicon nitride are formed by plasma-enhanced chemical vapor deposition. By depositing at low temperature, thermal stress and damage to the underlying structure are reduced, improving the quality and uniformity of the film and adapting to the deposition of multilayer materials to simplify the process. The second passivation layer is formed by silane oxidation deposition. The oxidant introduced during the formation process is nitrous oxide, thereby forming a low-stress, dense and uniform silicon dioxide layer, relieving interlayer stress and enhancing barrier properties.

[0049] After the passivation layer structure is formed, annealing is performed. When the total thickness of the first, second, and third passivation layers is 0.6-1.4 μm, the annealing temperature is 300-350℃ and the annealing time is 30-90 min; when the total thickness of the first, second, and third passivation layers is 1.4-2.2 μm, the annealing temperature is 400-450℃ and the annealing time is 30-90 min; when the total thickness of the first, second, and third passivation layers is 2.2-3.0 μm, the annealing temperature is 450-500℃ and the annealing time is 30-90 min; when the total thickness of the first, second, and third passivation layers is 3.0-3.8 μm, the annealing temperature is 500℃ and the annealing time is 30-60 min.

[0050] The polyimide layer has a thickness of 10-20 μm before annealing and a thickness of 5-10 μm after annealing and curing. The annealing time and temperature are the same as those for the three-layer passivation layer structure with different thicknesses. For example, if the total thickness of the three-layer passivation layer structure is 0.6-1.4 μm, the annealing temperature is 300-350℃ and the annealing time is 30-90 min. Then the annealing temperature of the polyimide layer is also 300-350℃ and the annealing time is also 30-90 min. Annealing releases the internal stress of the passivation layer structure and improves the adhesion of the passivation layer structure.

[0051] Nitrogen gas is introduced during the annealing heating and cooling stages at a flow rate of 5000 sccm; oxygen gas is introduced during the annealing isothermal stage at a flow rate of 5000 sccm. By controlling the type and flow rate of the gas introduced during the annealing process in stages, oxidation and contamination during temperature changes can be avoided, and the thin film performance can be optimized during the isothermal stage. Ultimately, this reduces internal defects and stress concentration in the passivation layer and improves the stability of the device under high temperature and high humidity conditions.

[0052] This invention provides a composite passivation layer structure consisting of a silicon oxide-based first passivation layer (low-stress tetraethyl orthosilicate layer), a second passivation layer (silane-silicon dioxide layer or silicon nitride layer), and a silicon nitride-based third passivation layer (high-resistivity silicon nitride layer). A polyimide layer can be selectively added, and the structure is prepared by plasma-enhanced chemical vapor deposition and silane oxidation deposition. It is combined with a staged gas-controlled annealing process (nitrogen gas is introduced during the annealing heating and cooling stages, and oxygen gas is introduced during the annealing isothermal stage) and photolithography etching to optimize the protection range.

[0053] While simplifying the process and reducing costs, it effectively solves the stress cracking problem caused by the mismatch of thermal expansion coefficients in traditional passivation layers, improves the barrier properties against water vapor and sodium ions, and can withstand more than 1,000 temperature cycle tests and 1,000 hours of H3TRB verification. It has broad application prospects in fields such as electric vehicle motor controllers, photovoltaic inverters, wind power converters, and industrial frequency converters, and can meet the long-term reliability requirements under complex operating conditions such as high temperature, high pressure, and high humidity.

[0054] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A passivation layer structure, characterized in that The passivation layer structure comprises: a first passivation layer of silicon oxide base; a second passivation layer on the first passivation layer; a third passivation layer of silicon nitride base on the second passivation layer; The first passivation layer of silicon oxide base is a low-stress tetraethyl orthosilicate layer; the second passivation layer is a silane-silicon dioxide layer formed by passing in dinitrogen monoxide oxidant in a silane oxidation deposition process; the third passivation layer of silicon nitride base is a high-resistance silicon nitride layer; the thickness of the low-stress tetraethyl orthosilicate layer is 0.05-0.3 μm, the thickness of the silane-silicon dioxide layer is 0.05-0.5 μm; and the thickness of the high-resistance silicon nitride layer is 0.5-3 μm.

2. The passivation layer structure of claim 1, wherein A polyimide layer is further formed on the third passivation layer of silicon nitride base.

3. The passivation layer structure of claim 2, wherein The thickness of the polyimide layer before curing is 10-20 μm, and the thickness after curing is 5-10 μm.

4. A method of passivation layer preparation, characterized by, The method comprises the following steps: forming a first passivation layer of silicon oxide base, i.e., a low-stress tetraethyl orthosilicate layer; forming a second passivation layer on the first passivation layer, i.e., a silane-silicon dioxide layer; forming a third passivation layer of silicon nitride base on the second passivation layer, i.e., a high-resistance silicon nitride layer; After forming the passivation layer structure, annealing is performed; when the total thickness of the first passivation layer, the second passivation layer and the third passivation layer is 0.6-1.4 μm, the annealing temperature is 300-350 ℃, and the annealing time is 30-90 min; when the total thickness of the first passivation layer, the second passivation layer and the third passivation layer is 1.4-2.2 μm, the annealing temperature is 400-450 ℃, and the annealing time is 30-90 min; when the total thickness of the first passivation layer, the second passivation layer and the third passivation layer is 2.2-3.0 μm, the annealing temperature is 450-500 ℃, and the annealing time is 30-90 min; when the total thickness of the first passivation layer, the second passivation layer and the third passivation layer is 3.0-3.8 μm, the annealing temperature is 500 ℃, and the annealing time is 30-60 min; nitrogen gas is passed in during the annealing temperature rising stage and the annealing temperature falling stage, and the gas flow rate is 5000 sccm; oxygen gas is passed in during the annealing constant temperature stage, and the gas flow rate is 5000 sccm.

5. The method of claim 4, wherein the passivation layer is formed by a process selected from the group consisting of thermal oxidation, plasma oxidation, and nitridation. Further comprising: forming a polyimide layer on the third passivation layer.

6. The method of claim 4, wherein the passivation layer is formed by a process selected from the group consisting of thermal oxidation, plasma oxidation, and nitridation. The first passivation layer of silicon oxide base and the third passivation layer of silicon nitride base are formed by plasma enhanced chemical vapor deposition; and the second passivation layer is formed by silane oxidation deposition, and the oxidant passed in during the formation process is dinitrogen monoxide.

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