A method, system for modeling internal noise of a slave clock in a master-slave synchronous network

Abstract

The application relates to a method and system for simulating internal noise of a slave clock in a master-slave synchronization network in the technical field of clock synchronization, and comprises the following steps: establishing a first equivalent model and a second equivalent model; generating a first phase-locked loop output power spectral density function based on the first equivalent model and generating a second phase-locked loop output power spectral density function based on the second equivalent model; calculating a loop bandwidth condition equivalent to the first equivalent model and the second equivalent model; updating the second phase-locked loop output power spectral density function using the loop bandwidth condition, and calculating the gain coefficient and the slave clock bandwidth of the second equivalent model using a TDEV template and an MTIE template, and then updating the second phase-locked loop output power spectral density function again to obtain a noise generation time domain function. The method solves the problem that the existing method for simulating internal noise of a slave clock only considers a TDEV template and does not consider an MTIE template, so that the corresponding MTIE of the generated time domain noise exceeds the MTIE template limit, and the stability of the slave clock cannot be accurately simulated.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of clock synchronization, and particularly relates to a method and system for simulating internal noise of a slave clock in a master-slave synchronization network. BACKGROUND

[0002] The master-slave clock synchronization mode is the most widely used mode in the deployment of Synchronous Digital Hierarchy (SDH) transmission networks. The master-slave synchronization network adopts a clock hierarchical structure: the highest level is implemented by a high-precision oscillator, usually an atomic frequency standard, which has excellent short-term and long-term frequency stability; the reference timing signal generated by the highest level clock is distributed to the lower level clock in a tree structure, so that each clock in the entire synchronization network can be traced back to the highest level clock through the clock chain. In the synchronization network, the highest level clock is called the Primary Reference Clock (PRC), as shown in FIG. 1, in addition to the PRC, all clocks in the chain are slave clocks, which achieve phase locking of the input reference signal from a higher level or the same level through a phase-locked loop system to output a timing signal. Figure 1

[0003] In the synchronization technology of SDH transmission networks, two basic slave clock schemes are mainly used: one is the Synchronization Supply Unit (SSU), which is responsible for providing a time reference signal for all devices within the network node; the other is the Synchronous digital hierarchy Equipment Clock (SEC) built in each network unit. Since the internal noise of the slave clock oscillator and the change in medium temperature in the SDH transmission synchronization network chain will cause unnecessary jitter and drift of the timing signal, in order to calculate the accumulated jitter and drift at the end of the typical synchronization distribution chain, it is necessary to establish an internal noise model of the slave clock.

[0004] The accuracy of the internal noise model of the slave clock depends on whether the stability of the slave clock can be accurately simulated. The stability is mainly represented by two key indicators, namely Time Deviation (TDEV) and Maximum Time Interval Error (MTIE).

[0005] ​The existing method of simulating internal noise of a slave clock only according to a TDEV template, by time domain sampling on the known TDEV template, calculating a signal power spectrum through a conversion relationship between TDEV and the power spectrum, and obtaining a time domain noise sequence after a series of operations such as interpolation, adding phase information, and inverse Fourier transform on the power spectrum. Since the method is a method of inversely deducing a time domain noise sequence according to a known TDEV template, it is a method of deducing a time domain noise from known frequency domain information, and has high computational complexity such as sampling, interpolation, and inverse Fourier transform. Meanwhile, the method only considers the TDEV template and does not take the MTIE template into account, so that the MTIE corresponding to the generated time domain noise may exceed the MTIE template limit, thereby affecting the stability of the slave clock. SUMMARY

[0006] The present application provides a method and system for simulating internal noise of a slave clock in a master-slave synchronization network, which solves the problem that the existing method for simulating internal noise of a slave clock only considers the TDEV template and does not consider the MTIE template, thereby causing the MTIE corresponding to the generated time domain noise to exceed the MTIE template limit, and further failing to accurately simulate the stability of the slave clock.

[0007] To solve the above technical problems, the present application is achieved by the following technical solutions:

[0008] A method for simulating internal noise of a slave clock in a master-slave synchronization network, comprising the following steps:

[0009] establishing a first equivalent model of a phase-locked loop introducing noise and a second equivalent model of power spectrum noise of the slave clock;

[0010] generating a first phase-locked loop output power spectrum density function based on the first equivalent model, and generating a second phase-locked loop output power spectrum density function based on the second equivalent model;

[0011] calculating a loop bandwidth condition equivalent to the first equivalent model and the second equivalent model based on the first phase-locked loop output power spectrum density function and the second phase-locked loop output power spectrum density function;

[0012] updating the second phase-locked loop output power spectrum density function using the loop bandwidth condition, and calculating a gain coefficient of the second equivalent model and a slave clock bandwidth using the TDEV template and the MTIE template, and updating the second phase-locked loop output power spectrum density function twice using the gain coefficient and the slave clock bandwidth to obtain a noise generation time domain function;

[0013] inputting a noise source in the second equivalent model, and outputting a time domain sequence of internal noise of the slave clock based on the noise generation time domain function.

[0014] Optionally, generating a first phase-locked loop output power spectral density function based on the first equivalent model comprises the following steps:

[0015] The first equivalent model comprises a phase detector, a loop filter and a voltage-controlled oscillator, an output end of the phase detector is connected with an input end of the loop filter, and an output end of the loop filter is connected with an input end of the voltage-controlled oscillator.

[0016] Based on the first equivalent model, a first power spectral density function corresponding to the first phase-locked loop and a second power spectral density function corresponding to the second phase-locked loop are generated.

[0017] The first phase-locked loop output power spectral density function comprises the first power spectral density function and the second power spectral density function.

[0018] Optionally, generating a second phase-locked loop output power spectral density function based on the second equivalent model comprises the following steps:

[0019] The second equivalent model comprises a first Gaussian noise generator, a first gain amplifier, a filter one, a filter two, a second Gaussian noise generator, a second gain amplifier and a filter three, the first Gaussian noise generator, the first gain amplifier, the filter one and the filter two are connected in series, the second Gaussian noise generator, the second gain amplifier and the filter three are connected in series, and output ends of the filter two and the filter three are commonly connected.

[0020] Based on the second equivalent model, a third power spectral density function corresponding to an output end of the filter two and a fourth power spectral density function corresponding to an output end of the filter three are generated.

[0021] The second phase-locked loop output power spectral density function comprises the third power spectral density function and the fourth power spectral density function.

[0022] Optionally, the loop bandwidth condition equivalent to the first equivalent model and the second equivalent model is calculated, comprising the following steps:

[0023] The first power spectral density function and the third power spectral density function are equivalently associated, and the second power spectral density function and the fourth power spectral density function are equivalently associated.

[0024] Based on the two sets of equivalent association conditions for calculating the loop bandwidth, the loop bandwidth condition is obtained.

[0025] Optionally, the expression of the first phase-locked loop output power spectral density function is as follows:

[0026] wherein c and k are noise amplitude constants. represents a first power spectral density value; represents a second power spectral density value; f represents frequency, represents a gain factor of a voltage-controlled oscillator, represents a gain factor of a phase detector, represents a transfer function of a loop filter;

[0027] The expression of the second phase-locked loop output power spectral density function is:

[0028] , wherein, is an amplitude of a noise power spectral density; is a third power spectral density value, is a gain coefficient of a first gain amplifier, and respectively correspond to a transfer function of filter one and filter two; is a fourth power spectral density value, is a gain coefficient of a second gain amplifier, is a transfer function of filter three.

[0029] Optionally, the loop bandwidth condition is: , wherein, represents a loop bandwidth; K0 represents a gain factor of a voltage-controlled oscillator; K d represents a gain factor of a phase detector.

[0030] Optionally, the gain coefficient and slave clock bandwidth of the second equivalent model are calculated using a TDEV template and an MTIE template, including the following steps:

[0031] The third power spectral density function and the fourth power spectral density function are substituted into the TDEV template respectively to obtain a first time deviation function and a second time deviation function respectively, and the first time deviation function and the second time deviation function are both approximate expressions of time deviation with respect to integral time;

[0032] The third power spectral density function and the fourth power spectral density function are substituted into the MTIE template respectively to obtain a first maximum time interval error function and a second maximum time interval error function respectively, and the first maximum time interval error function and the second maximum time interval error function are both approximate expressions of maximum time interval error with respect to integral time;

[0033] The approximate values corresponding to the extreme values of the time deviation at the integral time are obtained and substituted into the first time deviation function, the second time deviation function, the first maximum time interval error function and the second maximum time interval error function respectively to obtain the gain coefficient and the slave clock bandwidth.

[0034] Optionally, the method further comprises the following steps:

[0035] The noise generation time domain function is verified by stability simulation.

[0036] A system for simulating internal noise of a slave clock in a master-slave synchronization network, the system performs the method for simulating internal noise of a slave clock in a master-slave synchronization network as claimed in any one of the above, and comprises a model construction unit, a function generation unit, a first calculation unit, a second calculation unit and a noise generation unit.

[0037] The model construction unit is configured to establish a first equivalent model of phase-locked loop introduced noise and a second equivalent model of slave clock power spectrum noise.

[0038] The function generation unit is configured to generate a first phase-locked loop output power spectrum density function based on the first equivalent model, and generate a second phase-locked loop output power spectrum density function based on the second equivalent model.

[0039] The first calculation unit is configured to calculate a loop bandwidth condition equivalent to the first equivalent model and the second equivalent model based on the first phase-locked loop output power spectrum density function and the second phase-locked loop output power spectrum density function.

[0040] The second calculation unit is configured to update the second phase-locked loop output power spectrum density function using the loop bandwidth condition, calculate a gain coefficient and a slave clock bandwidth of the second equivalent model using a TDEV template and an MTIE template, and update the second phase-locked loop output power spectrum density function twice using the gain coefficient and the slave clock bandwidth to obtain a noise generation time domain function.

[0041] The noise generation unit is configured to input a noise source in the second equivalent model, and output a slave clock internal noise time domain sequence based on the noise generation time domain function.

[0042] A computer storage medium, the computer storage medium stores computer program instructions, the computer program instructions are executed by a processor to implement the method for simulating internal noise of a slave clock in a master-slave synchronization network as claimed in any one of the above.

[0043] By using the technical scheme provided by the present application, compared with the prior art, the following beneficial effects are achieved:

[0044] The second equivalent model equivalent to the first equivalent model is established through a loop bandwidth condition, avoiding the use of Fourier transform and other high-complexity calculation methods to obtain the time domain sequence of the slave clock internal noise, reducing the complexity of the device or software platform in simulating the slave clock internal noise; on the other hand, the gain coefficient and the slave clock bandwidth of the second equivalent model are calculated by simultaneously introducing the TDEV template and the MTIE template, and the gain coefficient and the slave clock bandwidth are used to update the output power spectrum density function of the second phase-locked loop twice to obtain the noise generation time domain function, thereby ensuring that the generated time domain noise can accurately simulate the stability of the slave clock. BRIEF DESCRIPTION OF DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0046] Figure 1 It is a schematic diagram of a typical master-slave synchronization network architecture;

[0047] Figure 2 It is a flow chart of a method for simulating the internal noise of a slave clock in a master-slave synchronization network according to the first embodiment;

[0048] Figure 3 It is a first equivalent model of the phase-locked loop introduced noise established according to the first embodiment;

[0049] Figure 4 It is a second equivalent model of the slave clock power spectrum noise established according to the first embodiment;

[0050] Figure 5 It is a schematic diagram of the second equivalent model generating the time domain sequence of the slave clock internal noise according to the first embodiment;

[0051] Figure 6 It is a time domain noise sequence generated when the slave clock is an SSU according to the first embodiment;

[0052] Figure 7 It is a stability verification comparison graph when the slave clock is an SSU according to the first embodiment;

[0053] Figure 8 It is a time domain noise sequence generated when the slave clock is an SEC according to the first embodiment;

[0054] Figure 9 It is a stability verification comparison graph when the slave clock is an SEC according to the first embodiment. DETAILED DESCRIPTION

[0055] The present invention will be further described in detail below with reference to the embodiments. The following embodiments are explanations of the present invention, but the present invention is not limited to the following embodiments.

[0056] Example 1

[0057] First, since the primary function of the slave clock is to synchronize its internal clock with the input synchronization signal, and this function is achieved in one way through a phase-locked loop (PLL), this invention is modeled based on this operating mode. For a PLL, if the input signal contains additional noise, the loop will remove the noise as much as possible and reproduce the original signal, thus synchronizing the output signal with the input signal. Therefore, the phase-locked loop can be viewed as a filter that functions by transmitting the signal and suppressing noise.

[0058] like Figure 2 As shown, a method for simulating internal noise of the slave clock in a master-slave synchronization network includes the following steps: First, establish as shown... Figure 3 The first equivalent model of noise introduced by the phase-locked loop shown, and as follows Figure 4 The second equivalent model of clock power spectral noise is shown. The first equivalent model includes a phase detector, a loop filter, and a voltage-controlled oscillator. The output of the phase detector is connected to the input of the loop filter, and the output of the loop filter is connected to the input of the voltage-controlled oscillator. The second equivalent model includes a first Gaussian noise generator, a first gain amplifier, filter one, filter two, a second Gaussian noise generator, a second gain amplifier, and filter three. The first Gaussian noise generator, the first gain amplifier, filter one, and filter two are connected in series. The second Gaussian noise generator, the second gain amplifier, and filter three are connected in series. The outputs of filter two and filter three are the same.

[0059] Next, the output power spectral density function of the first phase-locked loop is generated based on the first equivalent model. Specifically, this includes the following steps: Based on the first equivalent model, the first power spectral density function corresponding to phase-locked loop one and the second power spectral density function corresponding to phase-locked loop two in the first equivalent model are generated; wherein, the output power spectral density function of the first phase-locked loop includes the first power spectral density function and the second power spectral density function.

[0060] More specifically, such as Figure 3 As shown, pure flicker phase noise is generated at the output terminal A of the phase detector, and white phase noise is generated at the output terminal B of the voltage-controlled oscillator (VCO), where c and k are noise amplitude constants. and Let A and B be the output power spectral densities at points A and B of the phase-locked loop, respectively, which can be expressed by the following formula:

[0061] The first power spectral density function:

[0062] The second power spectral density function: ; wherein, represents the first power spectral density value, i.e. the power spectral density output at the phase-locked loop A represented above; represents the second power spectral density value, i.e. the power spectral density output at the phase-locked loop B represented above; f represents frequency, represents the gain factor of the voltage-controlled oscillator, represents the gain factor of the phase detector, represents the transfer function of the loop filter.

[0063] After generating the first phase-locked loop output power spectral density function, the second phase-locked loop output power spectral density function is generated based on the second equivalent model, specifically including the following steps: based on the second equivalent model, generating a third power spectral density function corresponding to the output end of filter two, and generating a fourth power spectral density function corresponding to the output end of filter three; wherein the second phase-locked loop output power spectral density function includes the third power spectral density function and the fourth power spectral density function.

[0064] More specifically, as shown in Figure 4 , the power spectral density of the Gaussian white noise source is set to , is the amplitude of the noise power spectral density. The power spectral density output by the upper branch Gaussian white noise source after passing through the first gain amplifier, filter one A and filter two B in turn (i.e. the third power spectral density function) is:

[0065]

[0066] The power spectral density output by the lower branch Gaussian white noise source after passing through the second gain amplifier and filter three C in turn (i.e. the fourth power spectral density function) is:

[0067] , wherein, is the third power spectral density value, is the gain coefficient of the first gain amplifier, and correspond to the transfer functions of filter one and filter two, respectively; is the fourth power spectral density value, is the gain coefficient of the second gain amplifier, is the transfer function of filter three.

[0068] ​​Then, the loop bandwidth conditions equivalent to the first equivalent model and the second equivalent model are calculated, including the following steps: equivalent association of the first power spectral density function and the third power spectral density function, equivalent association of the second power spectral density function and the fourth power spectral density function; based on the two groups of equivalent association, the loop bandwidth limiting conditions are obtained, and the loop bandwidth conditions are obtained.

[0069] Specifically, according to the expressions of the third power spectral density function and the fourth power spectral density function, the transfer function of filter one A is expressed as:

[0070] , wherein, are filter coefficients, s is a complex frequency, and satisfies: . The transfer function in the frequency domain is denoted as H (s), is the transfer function in the Laplace transform, and the two can be converted into each other, and the essence is to describe the transfer function of the filter. Hereinafter and are the same.

[0071] Since filter one A is essentially a half-order integrator, it can be approximated as: , wherein, are filter coefficients; the transfer function of filter two B is expressed as: ; the transfer function of filter three C is expressed as: , wherein, , w is the loop bandwidth from the clock.

[0072] Therefore, according to the transfer functions of filter one, filter two and filter three, the following can be further simplified:

[0073] The third power spectral density function is: ;

[0074] The fourth power spectral density function is: .

[0075] Thus, the simplified third power spectral density function is equivalent to the first power spectral density function, and the fourth power spectral density function is equivalent to the second power spectral density function, and finally the equivalent condition is obtained:

[0076] Therefore, it can be seen that the internal noise generation model (the second equivalent model) of the clock in the application can be equivalent to a model (the first equivalent model) simulating the specific noise generated by a first-order phase-locked loop with a specific loop bandwidth .

[0077] After the second phase-locked loop output power spectral density function of the second equivalent model is determined, the second phase-locked loop output power spectral density function is updated using a loop bandwidth condition, and the gain coefficient and slave clock bandwidth of the second equivalent model are calculated using the TDEV template and the MTIE template, and the second phase-locked loop output power spectral density function is updated twice using the gain coefficient and the slave clock bandwidth to obtain a noise generation time domain function.

[0078] The gain coefficient and the slave clock bandwidth of the second equivalent model are calculated using the TDEV template and the MTIE template, including the following steps: the third power spectral density function and the fourth power spectral density function are substituted into the TDVE template respectively to obtain a first time deviation function and a second time deviation function respectively, and the first time deviation function and the second time deviation function are both approximate expressions of the time deviation with respect to the integral time; the third power spectral density function and the fourth power spectral density function are substituted into the MTIE template respectively to obtain a first maximum time interval error function and a second maximum time interval error function, and the first maximum time interval error function and the second maximum time interval error function are both approximate expressions of the maximum time interval error with respect to the integral time; an approximate value of the time deviation corresponding to the extreme value of the integral time is obtained and substituted into the first time deviation function, the second time deviation function, the first maximum time interval error function and the second maximum time interval error function respectively to obtain the gain coefficient and the slave clock bandwidth.

[0079] Specifically, according to the MTIE template and the TDEV template measured at the output end when the slave clock SSU is in a locked working mode under temperature constancy (temperature change less than ±1 K) in the prior art one (ITU-T Recommendation G.812 (2004), Timing requirements of slave clocks suitable for use as node clocks in synchronization networks) Table 3 and Table 6 respectively given; the MTIE template and the TDEV template measured at the output end when the slave clock SEC is in a locked working mode under temperature constancy (temperature change less than ±1 K) in the prior art two (ITU T Recommendation G.813 (1996), Timing requirements of SDH equipment slave clocks (SEC)) Table 1 and Table 3 respectively given.

[0080] After the MTIE template and the TDEV template are obtained, the noise power spectral approximation expression is obtained according to the MTIE template, the TDEV template and the noise power spectral approximation expression:

[0081] ;

[0082] where τ is the integration time, S out (f) is the noise power spectrum, is the TDEV value corresponding to the integration time τ, is the MTIE value corresponding to the integration time τ. Substituting the simplified third power spectral density function and the simplified fourth power spectral density function into the calculation formula of out (f), the approximate expressions of TDEV in the upper branch and the lower branch, respectively, can be obtained:

[0083] ;

[0084] where σ is the standard deviation of the Gaussian white noise, is the TDEV value corresponding to the integration time τ in the upper branch, is the TDEV value corresponding to the integration time τ in the lower branch.

[0085] Similarly, substituting the simplified third power spectral density function and the simplified fourth power spectral density function into the calculation formula of , the approximate expressions of MTIE in the upper branch and the lower branch, respectively, can be obtained.

[0086] Next, in order to further determine the gain coefficients and the slave clock bandwidth of the two branches, it is necessary to further obtain the approximate situation corresponding to the limit value of the integration time τ according to the TDEV template and the MTIE template, and finally arrange the extreme value situation as shown in Table 1 below, calculate the required gain coefficients and slave clock bandwidth, and then update the second phase-locked loop output power spectral density function using the gain coefficients and the slave clock bandwidth twice to obtain the noise generation time domain function.

[0087] Table 1

[0088]

[0089] After obtaining the noise generation time domain function, as Figure 5 ​As shown, in the second equivalent model, the input noise source is input, and the time domain function output from the clock internal noise time domain sequence is generated based on the noise. Specifically, first, two sets of Gaussian white noise sequences with a mean of 0 and a standard deviation of σ are generated based on a Gaussian white noise generator; then, according to the templates of the slave clock TDEV and MTIE, the gain values Gain_1, Gain_2 and the slave clock bandwidth w are calculated according to Table 1; then, one set of Gaussian white noise sequences is multiplied by the gain value Gain_1, and then sequentially passes through the filter A and the filter B, and the other set of Gaussian white noise sequences is multiplied by the gain value Gain_2 and then passes through the filter C; finally, the two sets of obtained sequences are added, and the corresponding slave clock internal noise time domain sequence can be obtained.

[0090] Finally, the stability simulation verification of the noise generation time domain function is performed. Specifically, when the slave clock is SSU, Table 3 and Table 6 in the prior art one respectively give the MTIE and TDEV templates measured at the output end when the slave clock SSU is in the locked working mode under the condition that the temperature is constant (the temperature change is less than ±1 K). According to the above steps, the simulation result is calculated to obtain Gain_1 = 11000, Gain_2 = 3 and w = 0.003 Hz. At this time, the generated time domain noise sequence is as shown in Figure 6 . The corresponding TDEV value and MTIE value are calculated by using the generated time domain noise sequence, and the comparison with the templates is performed for rechecking and verification. The result is as shown in Figure 7 . It can be seen from Figure 7 that the TDEV and MTIE calculated by the method provided in the application for generating the SSU clock noise sequence are well matched with the TDEV and MTIE templates, and do not exceed the template limits.

[0091] When the slave clock is SEC, Table 1 and Table 3 in the prior art two respectively give the MTIE and TDEV templates measured at the output end when the slave clock SEC is in the locked working mode under the condition that the temperature is constant (the temperature change is less than ±1 K). According to the above steps, the simulation result is calculated to obtain Gain_1 = 5953, Gain_2 = 5 and w = 0.003 Hz. At this time, the generated time domain noise sequence is as shown in Figure 8 . The corresponding TDEV value and MTIE value are calculated by using the generated time domain noise sequence, and the comparison with the templates is performed for rechecking and verification. The result is as shown in Figure 9 . It can be seen from Figure 9 that the TDEV and MTIE calculated by the method provided in the application for generating the SEC clock noise sequence are well matched with the TDEV template and the MTIE template, and do not exceed the template limits.

[0092] Embodiment two

[0093] A system for simulating slave clock internal noise in a master-slave synchronization network, comprising a model building unit, a function generating unit, a first calculating unit, a second calculating unit and a noise generating unit.

[0094] The model building unit is configured to establish a first equivalent model of phase-locked loop introduced noise and a second equivalent model of slave clock power spectrum noise.

[0095] The function generating unit is configured to generate a first phase-locked loop output power spectrum density function based on the first equivalent model and a second phase-locked loop output power spectrum density function based on the second equivalent model.

[0096] The first calculating unit is configured to calculate a loop bandwidth condition equivalent to the first equivalent model and the second equivalent model based on the first phase-locked loop output power spectrum density function and the second phase-locked loop output power spectrum density function.

[0097] The second calculating unit is configured to update the second phase-locked loop output power spectrum density function using the loop bandwidth condition, calculate a gain coefficient and a slave clock bandwidth of the second equivalent model using a TDEV template and an MTIE template, and update the second phase-locked loop output power spectrum density function twice using the gain coefficient and the slave clock bandwidth to obtain a noise generation time domain function.

[0098] The noise generating unit is configured to input a noise source in the second equivalent model and output a slave clock internal noise time domain sequence based on the noise generation time domain function.

[0099] Since the system performs the method for simulating slave clock internal noise in a master-slave synchronization network as described in Embodiment One, the method is not repeated in this embodiment.

[0100] A computer storage medium having computer program instructions stored thereon, the computer program instructions being executed by a processor to implement the method for simulating slave clock internal noise in a master-slave synchronization network as described in Embodiment One.

[0101] More specific examples of computer readable storage media can include but are not limited to an electrical connection having one or more conductive segments, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0102] In this application, a computer readable storage medium can be any tangible medium that can contain, or store computer readable program codes. In this application, a computer readable signal medium can include a data signal traveling in baseband or traveling as a component of a carrier wave. The program codes embodied on the computer readable signal medium can be transmitted using any appropriate medium, including but not limited to wireless, wired, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0103] In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other manners. For example, the described apparatus embodiments are merely schematic. The division of the modules, units or components is merely a logical function division. There can be another division manner for the actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In this way, the actual implementation can adopt the form that is different from the form described in the embodiments.

[0104] The units described as separate parts can or can not be physically separate, and parts displayed as units can be a physical unit, or can be distributed on a plurality of network units, and can be located in one place, or can be distributed on a plurality of different places. According to the actual needs, some or all of the units can be selected to implement the purposes of the embodiments.

[0105] In addition, each functional unit in the various embodiments of the present application can be integrated in a processing unit, or each unit can exist physically as a separate unit, or two or more units can be integrated in a unit. The integrated unit can be implemented in the form of hardware, or in the form of software functional units.

[0106] In particular, the processes described above with reference to the flow charts can be implemented as computer software programs in accordance with embodiments of the present disclosure. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a computer readable medium, the computer program comprising program code for executing the methods illustrated by the flow charts. In such embodiments, the computer program can be downloaded and installed from a network via a communication section, and / or installed from a detachable medium. When the computer program is executed by a central processing unit (CPU), the above-described functions defined in the methods of the present application are executed. It should be noted that the computer readable medium of the present application can be a computer readable signal medium or a computer readable storage medium or any combination of the two. The computer readable storage medium may, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus or device, or any combination of the above.

[0107] The flow charts and block diagrams in the drawings are illustrations of possible architectural, functional, and operational architectures of systems, methods, and computer program products according to various embodiments of the present application. In this regard, each block in the flow charts or block diagrams can represent a module, a segment, or a portion of code which comprises one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flow charts, and combinations thereof, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or combinations of hardware and software.

[0108] The above description is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any change or replacement within the technical scope disclosed by the present application should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

[0109] The above merely describes preferred embodiments of the present application, and is not intended to limit the present application in any form or in essence. It should be noted that those skilled in the art can make some improvements and supplements without departing from the method of the present application, and these improvements and supplements should also be considered as the protection scope of the present application. For those skilled in the art, some slight changes, modifications and equivalent changes made by using the disclosed technical content without departing from the spirit and scope of the present application are equivalent embodiments of the present application; meanwhile, any equivalent changes, modifications and evolution made according to the essential technology of the present application to the above embodiments are still within the scope of the technical solutions of the present application.

Claims

1. A method of modeling internal noise of a slave clock in a master-slave synchronous network, characterized by, The method comprises the following steps: establishing a first equivalent model of a phase-locked loop introducing noise and a second equivalent model of clock power spectrum noise, wherein the first equivalent model comprises a phase detector, a loop filter, a first adder, a voltage-controlled oscillator and a second adder, an output terminal of the phase detector is connected with an input terminal of the first adder, an output terminal of the first adder is connected with an input terminal of the loop filter, an output terminal of the loop filter is connected with an input terminal of the voltage-controlled oscillator, and an output terminal of the voltage-controlled oscillator is connected with an input terminal of the second adder; the second equivalent model comprises a first Gaussian noise generator, a first gain amplifier, a filter one, a filter two, a second Gaussian noise generator, a second gain amplifier and a filter three, the first Gaussian noise generator, the first gain amplifier, the filter one and the filter two are connected in series, the second Gaussian noise generator, the second gain amplifier and the filter three are connected in series, and output terminals of the filter two and the filter three are connected in common; generating a first power spectral density function corresponding to an output terminal of the first adder and a second power spectral density function corresponding to an output terminal of the second adder based on the first equivalent model; generating a third power spectral density function corresponding to an output terminal of the filter two and a fourth power spectral density function corresponding to an output terminal of the filter three based on the second equivalent model; equivalent setting of the first power spectral density function and the third power spectral density function and equivalent setting of the second power spectral density function and the fourth power spectral density function; obtaining a loop bandwidth condition based on two sets of equivalent setting for solving a limitation condition of the loop bandwidth; updating the third power spectral density function and the fourth power spectral density function using the loop bandwidth condition, and calculating a gain coefficient and a slave clock bandwidth of the second equivalent model using a TDEV template and an MTIE template, and twice updating the third power spectral density function and the fourth power spectral density function using the gain coefficient and the slave clock bandwidth, to obtain a noise generation time domain function; inputting a noise source in the second equivalent model and outputting a slave clock internal noise time domain sequence based on the noise generation time domain function.

2. The method of claim 1, wherein, expressions of the first power spectral density function and the second power spectral density function are as follows: where c and k are noise amplitude constants of generation; denotes a first power spectral density value; denotes a second power spectral density value; f denotes frequency, denotes a gain factor of a voltage controlled oscillator, denotes a gain factor of a phase detector, denotes a transfer function of a loop filter; expressions of the third power spectral density function and the fourth power spectral density function are as follows: wherein ƞ is the amplitude of the noise power spectral density; is a third power spectral density value, is a gain coefficient of the first gain amplifier, and corresponds to the transfer function of filter one and filter two, respectively; is a fourth power spectral density value, is a gain coefficient of the second gain amplifier, is the transfer function of filter three.

3. The method of claim 2, wherein the method further comprises: determining a noise floor of the slave clock; and determining a noise floor of the master clock. The loop bandwidth condition is: wherein, represents the loop bandwidth; K0represents a gain factor of the voltage-controlled oscillator; K d represents a gain factor of the phase detector.

4. The method of claim 1, wherein the method is performed by a slave clock in a master-slave synchronous network. calculating the gain coefficient and the slave clock bandwidth of the second equivalent model using the TDEV template and the MTIE template, comprising the following steps: substituting the third power spectral density function and the fourth power spectral density function into the TDVE template respectively to obtain a first time deviation function and a second time deviation function respectively, and the first time deviation function and the second time deviation function are both approximate expressions of the time deviation with respect to integral time; substituting the third power spectral density function and the fourth power spectral density function into the MTIE template respectively to obtain a first maximum time interval error function and a second maximum time interval error function respectively, and the first maximum time interval error function and the second maximum time interval error function are both approximate expressions of the maximum time interval error with respect to integral time; The acquisition time deviation corresponds to an approximate value when the integral time takes the extreme value, and is substituted into the first time deviation function, the second time deviation function, the first maximum time interval error function and the second maximum time interval error function respectively to obtain the gain coefficient and the slave clock bandwidth.

5. The method of claim 1-4, wherein, Further comprising the following steps: Stability simulation verification is performed on the noise generation time domain function.

6. A system for modeling internal noise of a slave clock in a master-slave synchronous network, the system comprising: The system performs the method for simulating the internal noise of the slave clock in the master-slave synchronization network according to any one of claims 1-5, and comprises a model construction unit, a function generation unit, a first calculation unit, a second calculation unit and a noise generation unit; The model construction unit is configured to establish a first equivalent model of the phase-locked loop introducing noise and a second equivalent model of the slave clock power spectrum noise, wherein the first equivalent model comprises a phase detector, a loop filter, a first adder, a voltage-controlled oscillator and a second adder, an output end of the phase detector is connected with an input end of the first adder, an output end of the first adder is connected with an input end of the loop filter, an output end of the loop filter is connected with an input end of the voltage-controlled oscillator, and an input end of the second adder is connected with an output end of the voltage-controlled oscillator; the second equivalent model comprises a first Gaussian noise generator, a first gain amplifier, a filter one, a filter two, a second Gaussian noise generator, a second gain amplifier and a filter three, the first Gaussian noise generator, the first gain amplifier, the filter one and the filter two are connected in series, the second Gaussian noise generator, the second gain amplifier and the filter three are connected in series, and output ends of the filter two and the filter three are connected in common. The function generation unit is configured to generate a first power spectrum density function corresponding to an output end of the first adder and a second power spectrum density function corresponding to an output end of the second adder based on the first equivalent model, generate a third power spectrum density function corresponding to an output end of the filter two and generate a fourth power spectrum density function corresponding to an output end of the filter three based on the second equivalent model. The first calculation unit is configured to perform equivalent association of the first power spectrum density function and the third power spectrum density function and equivalent association of the second power spectrum density function and the fourth power spectrum density function, obtain a loop bandwidth condition based on two sets of equivalent association solving conditions of the loop bandwidth, and obtain the loop bandwidth condition. The second calculation unit is configured to update the third power spectrum density function and the fourth power spectrum density function using the loop bandwidth condition, calculate a gain coefficient and a slave clock bandwidth of the second equivalent model using a TDEV template and an MTIE template, and update the third power spectrum density function and the fourth power spectrum density function twice using the gain coefficient and the slave clock bandwidth to obtain a noise generation time domain function. The noise generation unit is configured to input a noise source in the second equivalent model and output a slave clock internal noise time domain sequence based on the noise generation time domain function.

7. A computer storage medium, characterized in that The computer storage medium stores computer program instructions, and the computer program instructions are executed by the processor to implement the method for simulating the internal noise of the slave clock in the master-slave synchronization network according to any one of claims 1-5.

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