Heterogeneous analog-to-digital converter, signal processing device and electronic equipment

Abstract

The invention relates to a heterogeneous analog-to-digital converter, a signal processing device and electronic equipment. The heterogeneous analog-to-digital converter comprises a plurality of first analog-to-digital conversion modules, a plurality of second analog-to-digital conversion modules, a first input bus, a second input bus and a residual error bus, the input end of each first analog-to-digital conversion module is connected with a first input bus, and the input end of each second analog-to-digital conversion module is connected with a second input bus; the residual error bus is connected with the first analog-to-digital conversion module and the second analog-to-digital conversion module; each first analog-to-digital conversion module comprises a first multiplexer, a first SAR core and a first residual error signal processing circuit; each second analog-to-digital conversion module comprises a second multiplexer, a second SAR core and a second residual error signal processing circuit; and the digit of the digital signal output by the first SAR core is greater than that of the second SAR core. Therefore, the differential requirements of different analog-to-digital conversion scenes can be met, and the expansion capability and the stability of the heterogeneous analog-to-digital converter are improved.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and more particularly to a heterogeneous analog-to-digital converter, signal processing device, and electronic device. Background Technology

[0002] Analog-to-digital converters (ADCs) are indispensable key components in modern electronic systems, used to convert analog signals into digital signals for transmission to digital processing circuits. In recent years, with the increasing application scenarios such as wireless communication, the Internet of Things (IoT), artificial intelligence, and autonomous driving, electronic systems need to support signal acquisition tasks with varying bandwidths and resolutions. Therefore, single-specification ADCs can no longer meet the diverse signal acquisition requirements.

[0003] To address these challenges, researchers have proposed a reconfigurable analog-to-digital converter (ADC) architecture. By combining multiple ADC modules (also known as ADC channels), a single chip can simultaneously support multiple sampling modes, thereby reducing chip area, power consumption, and cost. For example, Chinese invention patent CN118783962A proposes an ADC that allows for flexible implementation of high-performance or multi-mode parallel sampling by combining multiple ADC modules. However, most currently disclosed reconfigurable ADC solutions employ a uniform module array structure, meaning that each ADC module has the same specifications and performance.

[0004] However, the aforementioned ADC solutions using a uniform module array structure are difficult to adapt to diverse architectural requirements. Specifically, since each module is of uniform specification, it is difficult to simultaneously meet the differentiated requirements of accuracy (such as signal-to-noise and distortion ratio (SNDR)) and power consumption in different scenarios, thus limiting the system's flexible switching between high-precision mode, high-speed mode, and low-power mode. Furthermore, the uniform module array structure typically adopts a fully interconnected input scheme (i.e., using the same input bus to connect multiple modules), resulting in longer signal transmission paths for some modules, making them susceptible to parasitic capacitance and resistance, which severely restricts the system's scalability and performance stability, especially when the chip area increases and the number of modules increases. Summary of the Invention

[0005] In view of this, this disclosure proposes a heterogeneous analog-to-digital converter, signal processing device, and electronic device that can meet the differentiated needs of different analog-to-digital conversion scenarios and improve the scalability and stability of the heterogeneous analog-to-digital converter.

[0006] According to one aspect of this disclosure, a heterogeneous analog-to-digital converter (ADC) is provided, comprising: a plurality of first ADC modules, a plurality of second ADC modules, a first input bus, a second input bus, and a residual bus; wherein the input terminal of each first ADC module is connected to the first input bus, and the input terminal of each second ADC module is connected to the second input bus; the residual bus is connected to each first ADC module and each second ADC module; wherein each first ADC module includes: a first multiplexer, a first SAR core, and a first residual signal processing circuit; the first multiplexer is used to acquire an analog signal from the first input bus, the first SAR core is used to convert the input analog signal into a digital signal; the first residual signal processing circuit includes a transconductance amplifier and a first transimpedance amplifier, the transconductance amplifier being used to convert the first SAR signal into a digital signal. The voltage-form residual signal generated by the AR core is converted into a current-form residual signal for transmission to the residual bus; the first transimpedance amplifier is used to convert the current-form residual signal obtained from the residual bus into a voltage-form residual signal for transmission to the first SAR core; wherein, each second analog-to-digital conversion module includes: a second multiplexer, a second SAR core, and a second residual signal processing circuit, the second multiplexer is used to obtain an analog signal from the second input bus; the second SAR core is used to convert the input analog signal into a digital signal; the second residual signal processing circuit includes a second transimpedance amplifier for converting the current-form residual signal obtained from the residual bus into a voltage-form residual signal for transmission to the second SAR core; wherein, the number of bits of the digital signal output by the first SAR core is greater than that of the second SAR core.

[0007] In one possible implementation, the heterogeneous analog-to-digital converter further includes: a jitter calibration module, used to inject voltage jitter signals into each analog-to-digital converter module and current jitter signals into the residual bus, so as to extract the gain deviation between different analog-to-digital converter modules and perform gain calibration based on the gain offset after injecting voltage jitter signals and current jitter signals; wherein, the jitter calibration module includes: a pseudo-random number generator and a current-mode digital-to-analog converter; the output terminal of the pseudo-random number generator is connected to the first SAR core in each first analog-to-digital converter module and / or the second SAR core in each second analog-to-digital converter module, the output terminal of the pseudo-random number generator is connected to the input terminal of the current-mode digital-to-analog converter, and the output terminal of the current-mode digital-to-analog converter is connected to the residual bus; the pseudo-random number generator is used to inject voltage jitter signals into the first SAR core in each first analog-to-digital converter module and / or the second SAR core in each second analog-to-digital converter module; the current-mode digital-to-analog converter is used to inject current jitter signals into the residual bus based on the voltage jitter signals generated by the pseudo-random number generator.

[0008] In one possible implementation, the heterogeneous analog-to-digital converter (ADC) operates in pipeline mode, comprising: a first multiplexer in a first ADC module receiving a first analog signal from a first input bus; a first SAR core in the first ADC module converting the first analog signal into a first digital signal and generating a first residual signal based on the first analog signal and the first digital signal; a first residual signal processing circuit in the first ADC module processing the first residual signal and sending the processed second residual signal to the residual bus; a second residual signal processing circuit in the second ADC module receiving a second residual signal from the residual bus, amplifying the second residual signal and converting it into a third residual signal; and a second SAR core in the second ADC module converting the third residual signal into a second digital signal.

[0009] In one possible implementation, the first residual signal processing circuit in each first analog-to-digital conversion module further includes: a switched capacitor circuit for feeding the residual signal input to the transconductance amplifier or output of the first transimpedance amplifier into the signal path; wherein the switched capacitor circuit includes: a first capacitor, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth switch, and a tenth switch; wherein the first terminal of the fifth switch is coupled to the output terminal of the first transimpedance amplifier, the second terminal of the fifth switch, the first terminal of the sixth switch, the first terminal of the seventh switch, and the first terminal of the first capacitor are coupled together, the second terminal of the sixth switch is coupled to the N terminal of the differential circuit in the first SAR core, the second terminal of the seventh switch is coupled to the P terminal of the differential circuit in the first SAR core, the second terminal of the first capacitor, the first terminal of the eighth switch, and the first terminal of the ninth switch are coupled together, the second terminal of the eighth switch is coupled to a preset voltage terminal, the second terminal of the ninth switch and the first terminal of the tenth switch are coupled to the input terminal of the transconductance amplifier, and the second terminal of the tenth switch is coupled to the P terminal of the differential circuit in the first SAR core.

[0010] In one possible implementation, the switched capacitor circuit has the following configuration states: residual sampling state, charge sharing state, capacitor stacking state, and pass-through state; in the residual sampling state, the fifth and eighth switches are closed, and the switches other than the fifth and eighth switches are open; in the charge sharing state, the sixth or seventh switch is closed, the eighth switch is closed, and the switches other than the sixth or seventh switch are open; in the capacitor stacking state, the sixth or seventh switch is closed, the ninth switch is closed, and the switches other than the sixth or seventh switch are open; in the pass-through state, the tenth switch is closed, and the switches other than the tenth switch are open.

[0011] In one possible implementation, the first residual signal processing circuit in each first analog-to-digital conversion module further includes: a receiver gating switch and an impedance cancellation circuit connected to the first transimpedance amplifier, and a transmitter gating switch connected to the transconductance amplifier; wherein the first transimpedance amplifier includes a floating current source, the floating current source being composed of an NMOS transistor and a PMOS transistor connected at their sources, wherein the source of the NMOS transistor and the PMOS transistor connected together serves as the first input terminal of the first transimpedance amplifier, the gate of the NMOS transistor serves as the second input terminal of the first transimpedance amplifier, and the gate of the PMOS transistor serves as the third input terminal of the first transimpedance amplifier; the first terminal of the receiver gating switch is coupled to the residual bus and the second terminal of the receiver gating switch is coupled to the first input terminal of the first transimpedance amplifier, for obtaining a current-form residual signal from the residual bus and The signal is transmitted to the first transimpedance amplifier; wherein, the impedance cancellation circuit is used to cancel the on-resistance of the receiving end gating switch and reduce the input resistance of the first transimpedance amplifier, the impedance cancellation circuit includes a replica switch, a first amplifier and a second amplifier; wherein, the first end of the replica switch is coupled to the first end of the receiving end gating switch, and the second end of the replica switch is coupled to the input ends of the first amplifier and the second amplifier respectively, the output end of the first amplifier is coupled to the second input end of the first transimpedance amplifier, and the output end of the second amplifier is coupled to the third input end of the first transimpedance amplifier; the first end of the transmitting end gating switch is coupled to the output end of the transconductance amplifier, and the second end of the transmitting end gating switch is coupled to the residual bus; the transmitting end gating switch is used to transmit the residual signal in the form of current output by the transconductance amplifier to the residual bus.

[0012] In one possible implementation, the first transimpedance amplifier further includes a first current mirror, a second current mirror, a first switch, a second switch, a third switch, a fourth switch, and a first resistor; wherein, the drain of the NMOS transistor in the floating current source is coupled in series with the first terminal of the first current mirror to the first switch, and the drain of the PMOS transistor in the floating current source is coupled in series with the first terminal of the second current mirror to the second switch; the second terminal of the first current mirror is coupled with the first terminal of the third switch, and the second terminal of the second current mirror is coupled with the first terminal of the fourth switch; the second terminal of the third switch, the second terminal of the fourth switch, and the first terminal of the first resistor are coupled together as the output terminal of the first transimpedance amplifier to output a residual signal in the form of a converted voltage; the second terminal of the first resistor is coupled with a preset voltage terminal.

[0013] In one possible implementation, each first analog-to-digital converter module and / or second analog-to-digital converter module further includes: a reset switch circuit for resetting the residual bus to a preset voltage; the residual bus includes multiple buses, the reset switch circuit includes multiple sub-switch circuits, each bus corresponds to one sub-switch circuit, the first terminal of the multiple sub-switch circuits is coupled to a preset voltage terminal, the second terminal of each sub-switch circuit is coupled to each bus in the residual bus, and when any sub-switch circuit is closed, the bus coupled to that sub-switch circuit is reset to the preset voltage.

[0014] According to another aspect of this disclosure, a signal processing apparatus is provided, the apparatus comprising: the heterogeneous analog-to-digital converter, and a digital signal processing circuit coupled to the heterogeneous analog-to-digital converter.

[0015] According to another aspect of this disclosure, an electronic device is provided, the electronic device comprising: a processor, and the aforementioned signal processing device.

[0016] According to various aspects of this disclosure, by providing two different types of analog-to-digital converter (ADC) modules—high-precision ADC modules and low-power ADC modules—flexible configuration among multiple precision, bandwidth, and power consumption targets on a single ADC chip can be achieved. This solves the structural limitation of existing ADC arrays that cannot simultaneously achieve high precision and low power consumption, supporting multiple performance coverage and flexible mode combinations. Furthermore, compared to existing fully interconnected methods, the interconnection method using two sets of input buses for grouped input, which selectively connects different input signals to ADC modules with appropriate performance, can significantly reduce the wiring complexity between modules and reduce the accumulation of parasitic capacitance caused by interconnection. In other words, it reduces the interconnection complexity between modules and the impact of parasitic capacitance on the bus, which is beneficial to improving the scalability and signal quality consistency of heterogeneous ADC array structures.

[0017] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0018] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0019] Figure 1 A schematic diagram of a reconfigurable analog-to-digital converter in the related art is shown.

[0020] Figure 2 A schematic diagram of another reusable analog-to-digital converter in the related technology is shown.

[0021] Figure 3A schematic diagram of a heterogeneous analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0022] Figure 4 A schematic diagram of the structure of a second analog-to-digital conversion module of the related technology is shown.

[0023] Figure 5 A schematic diagram of the structure of another heterogeneous analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0024] Figure 6 A schematic diagram illustrating the operating mode of a heterogeneous ADC according to an embodiment of the present disclosure is shown.

[0025] Figure 7 A schematic diagram of the structure of another heterogeneous analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0026] Figure 8 A schematic diagram of the structure of a first analog-to-digital conversion module according to an embodiment of the present disclosure is shown.

[0027] Figure 9 A schematic diagram showing various configuration states of a switched capacitor circuit according to an embodiment of the present disclosure is provided.

[0028] Figure 10 A schematic diagram of the structure of a transimpedance amplifier according to the related art is shown.

[0029] Figure 11 A schematic diagram of the structure of a transimpedance amplifier and impedance cancellation circuit according to an embodiment of the present disclosure is shown.

[0030] Figure 12 A schematic diagram of two common-source, common-gate amplifier structures according to an embodiment of the present disclosure is shown.

[0031] Figure 13 A schematic diagram of the structure of another first analog-to-digital conversion module according to an embodiment of the present disclosure is shown.

[0032] Figure 14 The diagram shows a schematic representation of the structure of each sub-switch circuit in a reset switch circuit according to an embodiment of the present disclosure. Detailed Implementation

[0033] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0034] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0035] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0036] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0037] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0038] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0039] To facilitate understanding of the technical solutions of the residual signal receiving circuit, transmission circuit, and processing circuit proposed in the embodiments of this disclosure, this article first provides a brief introduction to the analog-to-digital converter array structure and related content involved in the embodiments of this disclosure. For detailed information on the analog-to-digital converter array structure, please refer to the detailed description of the analog-to-digital converter in the aforementioned Chinese invention patent CN118783962A. In other words, the detailed description of the analog-to-digital converter in Chinese invention patent CN118783962A can be cited in this article.

[0040] For example, Figure 1 A schematic diagram of an analog-to-digital converter is shown, as follows: Figure 1As shown, the ADC includes: multiple analog-to-digital conversion modules, an input bus S1, and a residual bus S2 (also called an analog bus or residual bus). Each of the multiple analog-to-digital conversion modules includes a multiplexer 1, a successive approximation register (SAR) core 2, and a residual signal processing circuit 3. The output of the multiplexer 1 within the same module is connected to the SAR core 2, and the SAR core 2 is connected to the residual signal processing circuit 3. The residual signal processing circuits between different analog-to-digital conversion modules are connected via the residual bus S2, and the input bus S1 is connected to the multiplexer 1 of each analog-to-digital conversion module.

[0041] In each analog-to-digital converter module, the multiplexer 1 can receive analog signals from the input bus S1. Specifically, it can select one analog signal from the multiple analog signals transmitted on the input bus and output it to the corresponding SAR core 2. The SAR core 2 can convert the analog signals received by the multiplexer 1 into digital signals and generate a residual signal. The residual signal processing circuit 3 can process the residual signal generated by the SAR core 2 of the same module and transmit the processed residual signal to the residual bus S2, and obtain the residual signal from the residual bus S2 and transmit it to the SAR core 2. Specifically, the residual signal processing circuit 3 can amplify the residual signal, or amplify and shape the residual signal, and can also transmit the processed residual signal to the SAR core 2 of the same module, or transmit the processed residual signal to the residual signal processing circuit 3 of other modules through the residual bus S2, or obtain the residual signal from the residual bus S2, process it, and transmit it to the SAR core 2. The aforementioned residual signal can refer to the difference between the analog signal input to the SAR kernel and the converted digital signal.

[0042] The input bus S1 can be used to receive one or more analog signals and transmit them to the multiplexer 1 in the multiple analog-to-digital converter modules. In other words, the input bus S1 can be used to transmit the analog signal to be converted to each analog-to-digital converter module. The residual signal bus S2 can be used to transmit residual signals between the residual signal processing circuits 3 of the multiple analog-to-digital converter modules. For example, it can transmit the residual signal output from the residual signal processing circuit 3 of one module to the residual signal processing circuit 3 of another module. The residual signal bus S2 can include multiple buses to realize signal transmission between the residual signal processing circuits 3 of any two modules in the multiple analog-to-digital converter modules.

[0043] For example, Figure 2 A schematic diagram of another analog-to-digital converter is shown, such as... Figure 2As shown, each of the multiple analog-to-digital converter (ADC) modules may further include a multi-phase clock storage circuit 4 and an output buffer 5. Correspondingly, the ADC may also include a frame bus S3, an output bus S4, and a frame sequence generator 6 (also called a frame sequence generator). The aforementioned multi-phase clock storage circuit 4 is a programmable circuit, and therefore can also be called a programmable multi-phase clock storage circuit. Specifically, the residual signal processing circuit 3 in the same module is connected to the corresponding multi-phase clock storage circuit 4; the multi-phase clock storage circuit 4 is connected to the corresponding output buffer 5; and the SAR core 2 is connected to the corresponding output buffer 5. The frame bus S3 is connected to the multi-phase clock storage circuit 4 of the multiple ADC modules; and the output bus S4 is connected to the output buffer 5 of the multiple ADC modules.

[0044] The multiphase clock storage circuit 4 of each analog-to-digital converter (ADC) module provides control signals to the multiplexer 1, SAR core 2, and residual signal processing circuit 3 of that module. These control signals, also known as multiphase clock control signals, control the operation of each module. The output buffer 5 of each ADC module buffers the digital signal output by the SAR core 2. The frame bus S3 provides a clock signal to the multiphase clock storage circuit 4 of each ADC module, enabling the multiphase clock storage circuit 4 to generate a multiphase clock control signal. The output bus S4 outputs the digital signals buffered in the output buffers 5 of the multiple ADC modules; for example, the digital signals can be output to a digital signal processing circuit for processing.

[0045] The frame sequence generator 6 can be connected to the multiphase clock storage circuit 4 of each of the plurality of analog-to-digital conversion modules via the frame bus S3. The frame sequence generator 6 can provide a clock signal to the multiphase clock storage circuit 4 of each of the plurality of analog-to-digital conversion modules, and this clock signal can be generated based on the master clock. The SAR core 2 in the plurality of analog-to-digital conversion modules can also be used to receive the master clock.

[0046] like Figure 1 or Figure 2As shown, the analog-to-digital converters (ADCs) use uniform array structures of the same specifications for each ADC module. This makes it impossible to simultaneously cover performance requirements such as high precision, high speed, and low power consumption, resulting in insufficient flexibility for multi-mode tasks. Furthermore, the lack of differentiated signal processing capabilities prevents concurrent acquisition and hierarchical processing of signals of various specifications, limiting the parallelism and practicality of the ADC system. The system structure also exhibits poor scalability, especially as the number of modules increases. The complex signal paths and severe parasitic interference inherent in traditional fully interconnected structures negatively impact overall performance consistency and scalability. Therefore, it is evident that existing uniform module array structures are insufficient to effectively cover a wider range of performance specifications and cannot achieve more efficient multi-mode concurrent operation.

[0047] In view of this, embodiments of this disclosure propose an array-type heterogeneous programmable analog-to-digital converter (hereinafter referred to as heterogeneous ADC). By employing multiple types of analog-to-digital conversion modules with non-uniform construction, and through networking, programmable scheduling, and low parasitic signal transmission mechanisms, a flexible and scalable analog-to-digital conversion platform is constructed, which can meet the analog-to-digital conversion requirements of different precision and power consumption. Specifically, by introducing analog-to-digital conversion modules with different performance specifications, a single chip can be flexibly configured among multiple precision, bandwidth, and power consumption targets, solving the structural limitations of existing arrays that cannot simultaneously achieve high precision and low power consumption. By adopting a grouped connection input structure and a low parasitic interconnection method, the signal path complexity and parasitic capacitance problems caused by full interconnection are reduced, improving the scalability of the analog-to-digital converter. Furthermore, it can also support the concurrent operation and reconfigurable scheduling of multiple modules, enhancing the system's adaptability to multi-standard and multi-mode acquisition scenarios, and breaking through the bottleneck of limited concurrency capability under traditional uniform architecture.

[0048] Figure 3 A schematic diagram of a heterogeneous analog-to-digital converter according to an embodiment of the present disclosure is shown. Figure 3 As shown, the heterogeneous ADC includes:

[0049] The system comprises multiple first analog-to-digital converter (ADC) modules 100, multiple second ADC modules 200, a first input bus S11, a second input bus S12, and a residual bus S2; wherein the input terminal of each first ADC module 100 is connected to the first input bus S11, and the input terminal of each second ADC module 200 is connected to the second input bus S12; the residual bus S2 is connected to each first ADC module 100 and each second ADC module 200.

[0050] Each first analog-to-digital converter module 100 includes: a first multiplexer 101, a first SAR core 102, and a first residual signal processing circuit 103; the first multiplexer 101 is used to acquire an analog signal from the first input bus S11; the first SAR core 102 is used to convert the first analog signal acquired by the first multiplexer 101 into a first digital signal; the first residual signal processing circuit 101 includes a transconductance amplifier G. m With the first transimpedance amplifier TIA1, transconductance amplifier G m The first transimpedance amplifier TIA1 is used to convert the voltage-form residual signal generated by the first SAR core 102 into a current-form residual signal for transmission to the residual bus S2; the first transimpedance amplifier TIA1 is used to convert the current-form residual signal obtained from the residual bus S2 into a voltage-form residual signal for transmission to the first SAR core 102.

[0051] Each second analog-to-digital conversion module 200 includes: a second multiplexer 201, a second SAR core 202, and a second residual signal processing circuit 203. The second multiplexer 201 is used to acquire analog signals from the second input bus S12. The second SAR core is used to convert the second analog signal acquired by the second multiplexer 201 into a second digital signal. The second residual signal processing circuit 203 includes a second transimpedance amplifier TIA2 for converting the current-form residual signal acquired from the residual bus S2 into a voltage-form residual signal to be transmitted to the second SAR core 202.

[0052] In this embodiment, the first SAR core outputs a digital signal with a greater number of bits than the second SAR core. For example, the first SAR core may use a 13-bit successive approximation register (13bSAR) core, and the second SAR core may use an 11-bit successive approximation register (11bSAR) core. It should be understood that the aforementioned 13bSAR core and 11bSAR core are possible implementations proposed in this disclosure, and those skilled in the art do not limit the specific number of bits for the first and second SAR cores. It is known that the basic circuit structure of a single SAR core mainly includes a capacitive digital-to-analog converter (CDAC), a comparator (CMP), and successive approximation logic circuits (SAR Logic) or asynchronous SAR Logic, etc. It may also include other circuits, such as AND gates for receiving the master clock and SAM signal (i.e., the output signal of the sample-and-hold amplifier), and switches coupled to the AND gates, etc. This disclosure does not limit the inclusion of such circuits. The capacitive digital-to-analog converter (CDAC) is typically based on a differential binary capacitor array; therefore, SAR cores with different bit widths can be implemented by setting binary capacitor arrays with different bit widths. The specific circuit structure of a single SAR core can be found in existing art, and will not be described in detail in this disclosure.

[0053] The first analog-to-digital conversion module (referred to as the high-precision module) can be used for high-precision (i.e., high signal-to-noise ratio, such as greater than 70dB SNDR) and low-bandwidth analog-to-digital conversion scenarios. Internally, it can integrate a 13-bit SAR core, and be paired with a transconductance amplifier Gm and a first transimpedance amplifier TIA1 structure to improve low-noise capability and residual signal driving capability. It supports independent operation and can also be used as a pre-stage in pipelined operation mode. The second analog-to-digital conversion module (referred to as the low-power module) can be used for medium-precision (e.g., ~60dB SNDR), high-bandwidth or low-power analog-to-digital conversion scenarios. Internally, it can use a lightweight 11-bit SAR core, and can be paired with a smaller transimpedance amplifier TIA structure as a second transimpedance amplifier. It is suitable for forming the post-stage in pipelined operation mode or as a parallel sampling channel.

[0054] It should be understood, and referenced Figure 2 The illustrated analog-to-digital converter (ADC) structure may further include a multi-phase clock storage circuit, an output buffer, and other circuit structures in each first ADC module 100 and each second ADC module 200. The entire heterogeneous ADC may also include a frame sequence generator, a frame bus, an output bus, and other circuit structures. These circuit structures can be referenced for... Figure 2 The analog-to-digital converter shown is described in detail below. More specifically, the circuit structures described in the above-mentioned Chinese invention patent CN118783962A can be referred to in detail, and will not be elaborated here.

[0055] Optionally, the analog-to-digital conversion channel described in the aforementioned Chinese invention patent CN118783962A can be used as the first analog-to-digital conversion module 100 in this embodiment to achieve the high-precision, low-bandwidth analog-to-digital conversion requirements. Optionally, the second analog-to-digital conversion module 200 can, for example, adopt... Figure 4 This paper illustrates the circuit structure of an analog-to-digital conversion module in the related art to achieve low-power, high-bandwidth analog-to-digital conversion requirements, such as... Figure 4 As shown, the second residual signal processing circuit may also include a receiver selection switch RX MUX, which can be used to obtain the current-form residual signal I from the residual bus S2. RX The residual signal I in current form is processed by the second transimpedance amplifier TIA2. RX The residual signal V is amplified and converted into voltage form. RX V RX It can enter the second SAR core via a multiplexer, and the second SAR core can, for example, allow V... RX Converted to a digital signal. It should be understood that... Figure 4The specific circuit structure, function, and working process of the second multiplexer, CDAC, CMP, and heterogeneous SAR Logic shown herein can be referred to in the specific descriptions in related technologies. The embodiments disclosed herein will not be described in detail here.

[0056] It should be understood that the specific circuit structures of the first analog-to-digital conversion module 100 and the second analog-to-digital conversion module 200 are not limited in the embodiments disclosed herein. Overall, compared to the first analog-to-digital conversion module 100, the second SAR core of the second analog-to-digital conversion module 200 is more lightweight, and the second residual signal processing circuit is also simpler. Therefore, although the second analog-to-digital conversion module 200 has lower accuracy, it has lower power consumption and higher bandwidth, thus meeting the requirements for low-power, high-bandwidth analog-to-digital conversion. The first analog-to-digital conversion module 100 can achieve high-precision analog-to-digital conversion and can also implement more operating modes.

[0057] It is understood that those skilled in the art can customize and design other required circuit structures in each of the first analog-to-digital conversion modules 100 and the second module conversion module 200 according to actual needs. For example, the first module conversion module 100 may also be configured with... Figure 5 The auxiliary SAR (Aux.SAR) shown can be used to assist the first SAR core in performing some specific logic, but this disclosure does not limit the implementation of the embodiments.

[0058] In practical applications, each of the first analog-to-digital conversion modules 100 and each of the second analog-to-digital conversion modules 200 can independently complete analog-to-digital conversion to achieve multi-module input and output. Two or more modules can also work together through interleaving or collaboration to achieve higher speed or higher precision analog-to-digital conversion, for example... Figure 6As shown, based on the circuit structure of the first analog-to-digital converter (ADC) 100, the ADC 100 (i.e., Big Core) can implement multiple operating modes, including single-channel mode ①, noise shaping mode ②, and time-interleaving mode ③. Based on the circuit structure of the second ADC 200, the ADC 200 (i.e., Lite Core) can implement both single-channel mode ① and time-interleaving mode ③. Furthermore, the first ADC 100 and the second ADC 200 can cooperate to form a pipeline mode ④. When the heterogeneous ADC is in pipeline mode, the first ADC is used as the front-end stage in the pipeline, and the second ADC is used as the rear-end stage; that is, the signal can be processed first by the first ADC and then by the second ADC. The output of the reconfigurable RF front-end circuit is coupled to the input of the heterogeneous ADC to output an analog signal to the heterogeneous ADC. The output of the heterogeneous ADC is coupled to the input of the digital signal processing circuit to convert the analog signal into a digital signal and output it to the digital signal processing circuit. The digital signal processing circuit receives and processes the digital signal.

[0059] Unlike traditional uniform module array ADCs that employ a fully interconnected structure (i.e., using the same input bus to connect each analog-to-digital converter module), such as Figure 3 As shown, the heterogeneous ADC of this embodiment adopts a grouped input connection structure. That is, by connecting the first analog-to-digital converter module 100 and the second analog-to-digital converter module 200 respectively through the first input bus S11 and the second input bus S12, different input analog signals can be selectively connected to the analog-to-digital converter module with appropriate performance. For example, for high-precision analog signals, the first input bus S11 can be preferentially connected to the first analog-to-digital converter module 100 for processing; for high-bandwidth, low-power analog signals, the second input bus S12 can be preferentially connected to the second analog-to-digital converter module 200 for processing. All modules can participate in pipelined operation or parallel operation under the control of the multi-phase clock storage circuit.

[0060] For example, the following describes several possible implementations to illustrate different operating modes of the heterogeneous ADC.

[0061] In a first possible embodiment, when the heterogeneous ADC operates in single-channel mode (also known as independent SAR mode), each of the analog-to-digital conversion modules in the first analog-to-digital conversion module 100 and the second analog-to-digital conversion module 200 can be used to independently perform analog-to-digital conversion.

[0062] It should be understood that the operation of the first analog-to-digital converter module 100 in single-channel mode is similar to that of the second analog-to-digital converter module 200. This embodiment of the present disclosure uses the operation of the first analog-to-digital converter module 100 in single-channel mode as an example. Specifically, in this heterogeneous ADC, the first input bus S11 can be used to receive one or more first analog signals. Multiple first analog-to-digital converter modules 100 can be used to process one or more first analog signals respectively. For example, each first analog-to-digital converter module 100 can sample and perform analog-to-digital conversion on one analog signal. Specifically, the multiplexer of the first analog-to-digital converter module 100 can be used to select and receive one first analog signal from the multiple analog signals input from the first input bus S11. The first SAR core of the first analog-to-digital converter module 100 can be used to sample the first analog signal, convert the sampled first signal into a first digital signal, and output it to the digital signal processing circuit through the output bus. It should be understood that the first analog-to-digital converter module 100 can be any one of multiple first analog-to-digital converter modules 100. The working mode in which multiple first analog-to-digital converters 100 simultaneously perform independent analog-to-digital conversion processing on multiple analog channels can also be called the parallel working mode.

[0063] In a second possible embodiment, when the heterogeneous ADC operates in pipelined mode, the first analog-to-digital conversion module 100 and the second analog-to-digital conversion module 200 in the heterogeneous ADC can perform analog-to-digital conversion processing on the same input analog signal in a pipeline manner.

[0064] The following example, using the first analog-to-digital converter (ADC) module 100 and the second ADC module 200, illustrates the operation of the two-stage pipeline mode. Specifically, the first multiplexer 101 of the first ADC module 100 can receive a first analog signal from the first input bus S11; the first SAR core 102 of the first ADC module 100 can be used to sample the first analog signal, convert the sampled first signal into a first digital signal, and generate a first residual signal V based on the first analog signal and the first digital signal. RES (i.e., the residual signal in voltage form, or simply residual voltage); the first residual signal processing circuit of the first analog-to-digital conversion module 100 (specifically, a transconductance amplifier and a transmitting gating switch) processes the first residual signal V. RES The signal is amplified and converted, and the resulting second residual signal (i.e., the residual signal I in the form of current) is then processed. TX The residual signal is sent to the residual bus S2; the residual signal processing circuit of the second analog-to-digital converter module 200 (specifically the second transimpedance amplifier and the receiver selection switch) can be used to receive the second residual signal I from the residual bus S2. RX (that is, I) TX ), and for the second residual signal I RXAmplified and converted into a third residual signal V RX (i.e., the residual signal in voltage form); the second SAR core of the second analog-to-digital converter module 200 converts the third residual signal V... RX It is converted into a second digital signal.

[0065] It is understandable that this pipeline mode can include two-stage pipelines, as well as multi-stage pipeline modes such as three-stage and four-stage pipelines. In practical applications, the last stage of this multi-stage pipeline mode can use a second analog-to-digital converter (ADC) module 200, while all other stages of the pipeline can use a first ADC module 100. The module in the first stage pipeline can be used to sample and convert the input analog signal, while the modules in the second and subsequent stages pipelines can be used to convert the received signal. Compared to related technologies that use ADC modules of the same specifications to implement pipeline operation, by utilizing a high-precision and high-power first ADC module as the front-end of the pipeline and a low-precision and low-power second ADC module as the rear-end, a more energy-efficient pipeline operation can be achieved.

[0066] In a third possible embodiment, when the heterogeneous ADC operates in noise shaping mode, the noise shaping mode is implemented solely by the first analog-to-digital converter (ADC) module 100. This is because the first residual signal processing circuit in the first ADC module 100 provides noise shaping functionality. It should be understood that this noise shaping mode can also be used in conjunction with the operating modes provided above, for example, in conjunction with the single-channel mode and pipelined mode provided above. When the first ADC module 100 in the heterogeneous ADC operates in noise shaping mode, the first residual signal processing circuit in the first ADC module 100 can also perform shaping processing on the residual signal. Specifically, it can use the shaping function of the first residual signal processing circuit, combined with oversampling of the first SAR kernel, to form noise shaping.

[0067] In one possible example, when any first analog-to-digital converter (ADC) 100 operates in first-order noise shaping mode, its first multiplexer can be used to receive a first analog signal, its first SAR core can be used to sample and convert the first analog signal to obtain a first digital signal and generate a first residual signal, and its first residual signal processing circuit can be used to shape the first residual signal. It should be understood that when this noise shaping mode is used in conjunction with a pipelined mode, it can be referred to as the heterogeneous ADC operating in a multi-order noise shaping pipelined mode. This multi-order noise shaping pipelined mode can be referred to in the relevant description in the aforementioned Chinese invention patent CN118783962A, and will not be elaborated upon here.

[0068] In a third possible embodiment, when the heterogeneous ADC operates in time-interleaved mode, the multiple first analog-to-digital converter modules 100 and the multiple second analog-to-digital converter modules 200 can respectively implement time-interleaved mode, and the working process of time-interleaved mode is similar. Here, we take the working process of multiple second analog-to-digital converter modules 200 operating in time-interleaved mode as an example for a brief introduction. Specifically, the second multiplexers in the multiple second analog-to-digital converter modules 200 can be controlled to obtain the same analog signal from the second input bus S12 at different clock phases. The second SAR core in the multiple second analog-to-digital converter modules 200 can sample the same analog signal at different clock phases and convert it into a digital signal for transmission to the digital signal processing circuit. In this way, the subsequent digital signal processing circuit can use a high-frequency clock to determine the difference between the multiple digital signals output by the multiple second analog-to-digital converter modules 200 as the final digital signal according to the phase relationship at the time of sampling.

[0069] It should be understood that greater bandwidth can be obtained through time interleaving. Two-channel time interleaving can be achieved using two analog-to-digital converter modules, and three-channel time interleaving can be achieved using three conversion modules. Time interleaving can also be combined with pipelined techniques and noise shaping techniques. For example, two two-stage pipelined successive approximation register (ADC) converters can be interleaved to form a time-interleaved pipelined successive approximation register with doubled speed (doubled bandwidth). Another example is that the first stages of two pipelines can be interleaved and both passed to a second stage for conversion, forming a partially interleaved two-stage pipelined successive approximation register. Yet another example is that the two conversion modules in a noise-shaping mode can exchange filtered residual signals to form a time-interleaved noise-shaping successive approximation register; this disclosure does not limit the scope of the embodiments.

[0070] In some other embodiments, the above-described operating modes of this heterogeneous ADC can be combined with some general methods to form a hybrid architecture, improving performance or adding functionality. Optionally, these general methods may include, but are not limited to, multitasking, current summation, time-division multiplexing, and two-phase establishment. Detailed descriptions of these general methods can be found in relevant technical documents and will not be elaborated further here.

[0071] In practical applications, the operation of the multiplexer, SAR core, and residual signal processing circuit in any analog-to-digital converter module can be controlled by configuring the multiphase clock control signal provided by the multiphase clock storage circuit in different analog-to-digital converter modules. This allows the heterogeneous ADC to operate in different working modes, thus realizing a reconfigurable heterogeneous ADC.

[0072] According to the heterogeneous ADC of this disclosure, by providing two different types of analog-to-digital conversion modules—a high-precision analog-to-digital conversion module and a low-power analog-to-digital conversion module—flexible configuration among multiple precision, bandwidth, and power consumption targets on a single analog-to-digital converter chip can be achieved. This solves the structural limitation of existing analog-to-digital converter arrays that cannot simultaneously achieve high precision and low power consumption, and supports multiple performance coverage and flexible mode combinations. Furthermore, compared to the existing fully interconnected approach, the interconnection method using two sets of input buses for grouped input, which selectively connects different input signals to analog-to-digital conversion modules with appropriate performance, can significantly reduce the wiring complexity between modules and reduce the accumulation of parasitic capacitance caused by interconnection. In other words, it reduces the interconnection complexity between modules and the impact of parasitic capacitance on the bus, which is beneficial to improving the scalability and signal quality consistency of the heterogeneous ADC array structure.

[0073] It is known that gain offset inevitably exists between different analog-to-digital conversion modules in an ADC array. This may be due to different RC time constants caused by different residual signal transmission paths between different modules, resulting in different signal attenuation levels. Therefore, it is necessary to calibrate the gain between different analog-to-digital conversion modules in a heterogeneous ADC array. Related technologies, such as sine wave fitting calibration, are external front-end calibration methods that require external equipment and are costly. Therefore, this disclosure proposes a shared jitter calibration module to achieve low-cost internal gain deviation calibration, such as... Figure 7 As shown, the heterogeneous analog-to-digital converter further includes a jitter calibration module 30, used to inject voltage jitter signals into each analog-to-digital conversion module and current jitter signals into the residual bus, so as to extract the gain deviation between different analog-to-digital conversion modules after injecting voltage jitter signals and current jitter signals and perform gain calibration based on the gain offset. This jitter calibration module 30 is also known as... Figure 6 The Cal.Core shown in the image, such as Figure 6 As shown, a heterogeneous ADC may include N high-precision modules (i.e., Big Core), M low-power modules (i.e., Lite Core), and a shared jitter calibration module (i.e., Cal.Core).

[0074] like Figure 7As shown, the jitter calibration module 30 includes a pseudo-random number generator (PRNG) and a current-mode digital-to-analog converter (IDAC). The output of the PRNG is connected to the first SAR core in each of the first analog-to-digital converter modules and / or the second SAR core in each of the second analog-to-digital converter modules. The output of the PRNG is connected to the input of the IDAC, and the output of the IDAC is connected to the residual bus. The PRNG injects voltage jitter signals into the first SAR core in each of the first analog-to-digital converter modules and / or the second SAR core in each of the second analog-to-digital converter modules. The IDAC injects current jitter signals into the residual bus S2 based on the voltage jitter signals generated by the PRNG. Figure 7 As shown, the jitter calibration module 30 may further include a multi-phase clock storage circuit, which can be used to provide control signals to the PRNG to control the PRNG to generate jitter signals, which is equivalent to controlling the operation of the jitter calibration module 30.

[0075] As is known, the pseudo-random number generator (PRNG) can generate a binary pseudo-random sequence (commonly referred to as a jitter signal, which can be a digital signal in voltage form) to be injected into the SAR core in each module. The current-mode digital-to-analog converter (IDAC) can convert the binary pseudo-random sequence (i.e., the digital signal) into an analog current signal, obtaining a current jitter signal, which is injected into the residual bus S2 shared by each module. During the successive approximation conversion of the SAR core in the analog-to-digital converter module, this voltage jitter signal will, for example, slightly disturb the reference voltage of the CDAC, the comparator threshold, or the voltage on the sampling capacitor (the specific implementation depends on the circuit design). For example, this jitter signal can be superimposed on the low-order LSB capacitor of the CDAC. Thus, in each conversion cycle, the actual voltage input to the comparator in the SAR core is equal to the original input signal plus a small pseudo-random voltage disturbance determined by the pseudo-random sequence. The same pseudo-random sequence is also fed into the current-mode digital-to-analog converter (IDAC), which converts the pseudo-random sequence into an analog jitter current signal, which is directly injected into the residual bus. The residual bus is a shared resource. Residual signals generated by all modules during multi-step / pipeline conversions are transmitted to the next analog-to-digital converter (ADC) module via the residual bus. Injected current jitter slightly disturbs the residual signal on the residual bus. Under the combined influence of injected voltage jitter and injected current jitter on the residual bus, the output digital signal of each module contains information from the original input signal, the module's own gain error, and the injected jitter signal. Ideally, if all modules have identical gains and input signals, their responses to the same pseudo-random jitter signal should be strongly correlated. By calculating the cross-correlation between the module's output signal and the pseudo-random jitter signal, the response amplitude of each module to the same jitter signal can be accurately measured. The difference in response amplitude directly reflects the deviation of the actual gain of each module. This allows the extraction of gain offsets between different modules, and gain calibration can be performed based on these gain offsets. For example, based on the extracted gain offsets, the output signal of each module can be scaled in the digital domain to compensate for gain errors, ensuring that the effective gain of all modules is consistent. It should be noted that the above-described gain offset extraction process and gain calibration process are one possible implementation method provided by the embodiments of this disclosure. In fact, those skilled in the art can customize the gain offset extraction method and gain calibration method according to actual needs. The embodiments of this disclosure do not limit this. It should be understood that as long as the above-described jitter calibration module of the embodiments of this disclosure is used to inject voltage jitter and current jitter to realize gain offset extraction, it should be within the protection scope of the embodiments of this disclosure.

[0076] In this embodiment, the gain offset extraction method, which utilizes the voltage jitter signal injected by the jitter calibration module 30, enables background calibration during the normal operation of the array-type heterogeneous ADC (without affecting normal signal conversion). This eliminates the need for additional precision testing equipment and allows for low-cost calibration of gain deviations between analog-to-digital conversion modules, thereby improving the performance of the array-type heterogeneous ADC system. Furthermore, the heterogeneous ADC provided in this embodiment employs a non-uniform module array composed of high-precision modules, low-power modules, and a jitter calibration module, which differs from existing uniform module structures, supporting multiple performance coverages and flexible mode combinations.

[0077] As described above, the analog-to-digital conversion channel described in Chinese invention patent CN118783962A can be used as the first analog-to-digital conversion module in this disclosure embodiment. Optionally, this disclosure embodiment also provides Figure 8 Another schematic diagram of the structure of the first analog-to-digital converter module is shown, such as... Figure 8 As shown, the first residual signal processing circuit in each first analog-to-digital conversion module further includes: a switched capacitor circuit, used to convert the transconductance amplifier G... M The input or the output of the first transimpedance amplifier TIA1 is fed into the signal path to generate a new residual signal and achieve different operating modes.

[0078] like Figure 8 As shown, the switched capacitor circuit may include: a first capacitor C LF Fifth switch RS, sixth switch CS2, seventh switch CS1, eighth switch S CM Ninth switch S SER 10th switch S BYP Among them, the first terminal of the fifth switch RS is coupled to the output terminal of the first transimpedance amplifier TIA, and the second terminal of the fifth switch RS, the first terminal of the sixth switch CS2, the first terminal of the seventh switch CS1, and the first capacitor C are coupled together. LF The first terminal is coupled to the first terminal; the second terminal of the sixth switch CS2 is coupled to the N terminal of the differential circuit in the first SAR core; the second terminal of the seventh switch CS1 is coupled to the P terminal of the differential circuit in the first SAR core; the first capacitor C... LF The second terminal, the eighth switch S CM The first terminal and the ninth switch S SER The first end is coupled, the eighth switch S CM The second terminal is connected to the preset voltage terminal V CM Coupling, Ninth Switch S SER The second end and the tenth switch S BYP The first terminal is connected to the signal conversion circuit (as shown in the figure, the transconductance amplifier G). M The input terminal of ) is coupled, and the tenth switch S BYPThe second end is coupled to the P end of the differential circuit in the first SAR core.

[0079] As mentioned above, the basic circuit structure of a single SAR core mainly includes a capacitor-type digital-to-analog converter (CDAC), a comparator (CMP), and successive approximation logic (SAR Logic). It may also include other circuits, such as... Figure 8 A timing skew trimmer can be used to adjust timing skew, as well as an AND gate for receiving the master clock and SAM signal (i.e., the output signal of the sample-and-hold amplifier), and a switch coupled to the AND gate, etc., which are not limited in this embodiment. The capacitor-type digital-to-analog converter (CDAC) is typically based on a differential binary capacitor array. Therefore, in this embodiment, the differential circuit in the first SAR core can refer to a differential binary capacitor array. It is known that the differential binary capacitor array includes P-sides and N-sides. Therefore, in this embodiment, the P-terminal of the differential circuit in the first SAR core can refer to the P-side of the differential binary capacitor array, and the N-terminal of the differential circuit in the first SAR core can refer to the N-side of the differential binary capacitor array. It should be understood that the specific circuit structure of a single SAR core can be referenced from relevant existing art, and this embodiment does not elaborate on this in detail.

[0080] It should be understood that by controlling the opening and closing of different switches in the aforementioned switched capacitor circuit, the switched capacitor circuit can have multiple configuration states to achieve different operating modes of the analog-to-digital converter. Figure 9 As shown, the switched capacitor circuit can have the following configuration states: residual sampling state, charge sharing state, capacitor stacking state, and shoot-through state; in the residual sampling state, the fifth switch RS and the eighth switch S CM Closed, except for the fifth switch RS and the eighth switch S. CM Other switches are open; in the charge-sharing state, the sixth switch CS2 or the seventh switch CS1 is closed, and the eighth switch S CM Closed, except for the sixth switch CS2 or the seventh switch CS1, and the eighth switch S CM Other switches are open; in the capacitor stacking state, the sixth switch CS2 or the seventh switch CS1 is closed, and the ninth switch S SER Closed, except for the sixth switch CS2 or the seventh switch CS1, and the ninth switch S SER Other switches are open; in the through state, the tenth switch S BYP Closed, except for the tenth switch S BYP Other switches are off. Among them, V tp / n V represents the voltage at the P or N terminal of the differential circuit in the first SAR core. t This represents the residual voltage generated by the first SAR core as a whole.

[0081] For example, taking the non-interleaved first-order noise shaping mode and the multi-order pipeline mode as examples, we will introduce the possible configuration states of the switched capacitor circuit in different operating modes. In the non-interleaved first-order noise shaping mode, a residual error propagation process exists in a single first analog-to-digital converter module. This residual error propagation process alternates between residual error sampling and charge sharing. Specifically, the residual error voltage V generated by the first SAR core in the first analog-to-digital converter module... RES (i.e., the residual signal in voltage form) is amplified by transconductance amplifier G. M The signal is amplified and converted into a residual current (i.e., a residual signal in current form). This residual current can then be transmitted to the first transimpedance amplifier in the same module via the residual bus. The first transimpedance amplifier generates the amplified residual voltage V. RX At this point, the switched capacitor circuit enters the residual sampling state, that is, the fifth switch RS and the eighth switch S... CM With the switch closed and the other switches open, the residual voltage V... RX Sampled to the first capacitor C LF Then, the switched capacitor circuit enters a charge-sharing state, that is, the sixth switch CS2 or the seventh switch CS1 is closed, and the eighth switch S... CM With the switch closed and the other switches open, the first capacitor C... LF At least a portion of the capacitance at the P or N terminal of the differential circuit in the SAR core is connected in parallel, resulting in charge sharing; wherein, if the sixth switch CS2 is closed, it represents the first capacitor C LF The residual signal is fed in the reverse direction. If the seventh switch CS1 is closed, it means that the residual signal is fed in the forward direction. The closing of the sixth switch CS2 or the seventh switch CS1 can be determined according to the actual working mode configuration requirements. This disclosure embodiment does not limit this.

[0082] In the above process, assume that the transconductance amplifier G M Amplification factor A, first capacitor C LF If the ratio of the capacitor connected in parallel is appropriate, the loop filtering function in a noise-shaping ADC can be achieved. For example, if the first capacitor C... LF If the ratio of the capacitors connected in parallel is 1:(A-1), standard first-order noise shaping can be achieved. It should be understood that the specific values ​​of the above capacitors can be designed in many variations, and those skilled in the art can customize the specific values ​​of each capacitor according to actual needs; this disclosure does not limit such customization.

[0083] In the multi-stage pipeline mode, it is assumed that the first stage pipeline is the first analog-to-digital converter module 100A, the second stage pipeline is the first analog-to-digital converter module 110B, and the third stage pipeline is the second analog-to-digital converter module 200. In the first analog-to-digital converter module 100A, the first SAR core converts the first analog signal into a first digital signal and generates a first residual signal. The first residual signal processing circuit in the first analog-to-digital converter module 100A amplifies the first residual signal and converts it into a second residual signal. This second residual signal is then transmitted to the first analog-to-digital converter module 110B for processing via a residual bus. The first residual signal processing circuit in the first analog-to-digital converter module 110B converts the received second residual signal to obtain a third residual signal. The first SAR core in the first analog-to-digital converter module 110B converts the third residual signal into a second digital signal and generates a fourth residual signal. This fourth residual signal is then transmitted to the second analog-to-digital converter module 200 via a residual bus. The second analog-to-digital converter module 200 processes the fourth residual signal and converts it into a third digital signal. During the above process, the switched capacitor circuit in the first analog-to-digital conversion module 100A enters a shoot-through state, i.e., the tenth switch S... BYP When the switch is closed (the switched capacitor circuit is not working at this time), and the other switches are open, the first residual signal generated by the first SAR core in the first analog-to-digital converter module 100A is directly transmitted to the transconductance amplifier G. M via transconductance amplifier G M The signal is amplified and converted into a second residual signal, which is then sent to the first analog-to-digital converter (ADC) 110B via the residual bus. At this time, the switched-capacitor circuit of the first ADC 110B enters the aforementioned residual sampling state, causing the second residual signal to be sampled onto the first capacitor C. LF Then it enters the capacitor stacking state, that is, the sixth switch CS2 or the seventh switch CS1 is closed, and the ninth switch S SER With the switch closed and the other switches closed, the first capacitor C... LF The capacitor is connected in series with the capacitor at the P or N terminal of the differential circuit in the first SAR core, resulting in capacitor stacking, so as to feed the second residual signal into the first SAR core in the first analog-to-digital converter module 110B. Similarly, if the sixth switch CS2 is closed, it represents the first capacitor C LF The residual signal is fed in the reverse direction. If the seventh switch CS1 is closed, it means that the residual signal is fed in the forward direction. The sixth switch CS2 or the seventh switch CS1 can be closed according to the actual working mode configuration requirements. This disclosure embodiment does not limit this.

[0084] As described above, the multiphase clock storage circuit of each first analog-to-digital converter module can be used to provide control signals for the first multiplexer, the first SAR core and the first residual signal processing circuit of the module. The closing or opening of each switch in the above-mentioned switched capacitor circuit can be controlled by the control signals provided by the multiphase clock storage circuit to realize the circuit configuration requirements of different working modes of the first analog-to-digital converter module.

[0085] It should be understood that the configuration states of the switching circuit capacitors in the first-order noise shaping mode and pipeline mode provided in the above embodiments of this disclosure are some exemplary possible implementations provided in the embodiments of this disclosure. In fact, those skilled in the art can customize the configuration states of the switching capacitor circuit required for different operating modes (i.e., the opening and closing of different switches in the switching capacitor circuit) according to the circuit configuration requirements of different operating modes. This disclosure does not limit this.

[0086] like Figure 8 As shown, the first residual signal processing circuit in each first analog-to-digital conversion module further includes: a receiver gating switch RX MUX and an impedance cancellation circuit IC connected to the first transimpedance amplifier TIA1, and a transmitter gating switch TX MUX connected to the transconductance amplifier. The impedance cancellation circuit IC is used to cancel the on-resistance of the receiver gating switch RX MUX and reduce the input resistance of the first transimpedance amplifier TIA1.

[0087] Optionally, Figure 10 A schematic diagram of a transimpedance amplifier TIA is shown. This transimpedance amplifier TIA can be used as the first transimpedance amplifier TIA1 mentioned above, and of course, it can also be used as the second transimpedance amplifier TIA2. Figure 10 The specific circuit structure of the transimpedance amplifier shown can be found in the detailed description of the transimpedance amplifier TIA in the aforementioned Chinese invention patent CN118783962A. A brief introduction to this transimpedance amplifier is provided here, as follows: Figure 10 As shown, the first transimpedance amplifier may include: a floating current source IF, a first current mirror IM1, a transistor M1, a transistor M2, a second current mirror IM2, and a resistor R. OUT Resistance R LOAD and switch K HBW The floating current source IF is formed by an NMOS transistor M connected to its source. 10 and PMOS transistor M 20 The configuration includes an NMOS transistor and a PMOS transistor connected together, whose sources serve as the first input terminal of the first transimpedance amplifier, used to receive the residual signal I in the form of current. RX The gate of the NMOS transistor serves as the second input terminal of the first transimpedance amplifier, and the gate of the PMOS transistor serves as the third input terminal of the first transimpedance amplifier. Resistor R OUTThe other end and switch K HBW The other end is coupled as the output of the first transimpedance amplifier, which can be used to output the residual signal V in voltage form. RX The gate of transistor M1 receives the inverted enable signal / EN, and the gate of transistor M2 receives the enable signal EN. The two transistors controlled by the enable signals EN and / EN are switching transistors, which can turn off the transimpedance amplifier at different times to save power. In other words, the enable signal can control the switching on and off of the transimpedance amplifier. The floating current source IF provides DC bias current to each transistor in the transimpedance amplifier, allowing the current mirrors to reach their operating point. The first current mirror IM1 and the second current mirror IM2 can proportionally replicate the input residual current. For example, if the transistor ratio in the current mirrors is 1:4, the residual current can be amplified four times. The amplified residual current acts on resistor R. LOAD The output voltage is generated by amplifying the current-form residual signal and converting it into a voltage-form residual signal.

[0088] Optionally, embodiments of this disclosure also provide Figure 11 The diagram shows another transimpedance amplifier 53, which can be used as the first transimpedance amplifier TIA1 described above, such as... Figure 11 As shown, the transimpedance amplifier 53 may include a floating current source 531, a first current mirror 532, a second current mirror 533, a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, and a first resistor R1. The source of the NMOS transistor and the PMOS transistor connected together serves as the first input terminal of the first transimpedance amplifier and is connected to the receiver selection switch 51. The gate of the NMOS transistor serves as the second input terminal of the first transimpedance amplifier and is connected to the first amplifier 522. The gate of the PMOS transistor serves as the third input terminal of the first transimpedance amplifier and is connected to the second amplifier 523. In the floating current source 531, the drain of the NMOS transistor is connected in series with the first terminal of the first current mirror 532 via a first switch K1; the drain of the PMOS transistor in the floating current source 531 is connected in series with the first terminal of the second current mirror 533 via a second switch K2; the second terminal of the first current mirror 532 is coupled to the first terminal of the third switch K3; the second terminal of the second current mirror 533 is coupled to the first terminal of the fourth switch K4; the second terminals of the third switch K3, the fourth switch K4, and the first terminal of the first resistor R1 are coupled together to serve as the output terminal of the first transimpedance amplifier, outputting the residual signal in the form of a converted voltage; the second terminal of the first resistor R1 is connected to the preset voltage terminal V. CM coupling.

[0089] in, Figure 11 The floating current source 531, the first current mirror 532, the second current mirror 533, and the first resistor R1 shown in the figure have the same functions as described above. Figure 10 The floating current source IF, the first current mirror IM1, the second current mirror IM2, and R shown in the figure LOAD They serve the same purpose. The first switch K1 and the third switch K3 are used to receive the same enable signal EN. TIA (e.g., EN or / EN), the second switch K2 and the fourth switch K4 are used to receive the same enable signal EN. TIA (e.g., EN or / EN). It should be understood that the enable signals received by the first switch K1 and the third switch K3 can be inverse signals of the enable signals received by the second switch K2 and the fourth switch K4. Compared to Figure 10 Transistors M1 and M2 are used to receive enable signals EN and / EN to control the switching on and off of the transimpedance amplifier. Figure 11 The first switch K1, the second switch K2, the third switch K3, and the fourth switch K4 are used to receive the enable signal EN. TIA The implementation method of controlling the switching on and off of the transimpedance amplifier (using the EN or / EN signal) can enhance the isolation between different circuit parts of the transimpedance amplifier, thereby enhancing the isolation between different analog-to-digital converter modules and improving the stability of the entire analog-to-digital converter array structure.

[0090] It is understandable that the above Figure 11 The transimpedance amplifier shown can be used not only in the residual signal receiving circuit or the residual signal processing circuit, but also independently in other circuits. Alternatively, the transimpedance amplifier (TIA) can be a standalone solution and applied to any other circuit unrelated to the ADC or residual signal receiving circuit provided in this disclosure.

[0091] Back Figure 8In the configuration, the first terminal of the receiver gating switch is coupled to the residual bus, and the second terminal of the receiver gating switch is coupled to the first input terminal of the first transimpedance amplifier. This gating switch is used to acquire a current-form residual signal from the residual bus and transmit it to the first transimpedance amplifier. The residual bus S2 can have multiple buses, and the receiver gating switch can be coupled to multiple buses in the residual bus S2. Therefore, the receiver gating switch can determine which bus in the residual bus S2 to acquire the current-form residual signal from; or, in other words, the gating switch can be controlled to determine which bus to acquire the current-form residual signal from. Similarly, the first terminal of the transmitter gating switch is coupled to the output terminal of the transconductance amplifier, and the second terminal of the transmitter gating switch is coupled to the residual bus S2. The transmitter gating switch is used to transmit the current-form residual signal output by the transconductance amplifier to the residual bus. The transmitter gating switch can be coupled to multiple buses in the residual bus S2. Therefore, the transmitter gating switch can determine which bus in the residual bus S2 to transmit the current form of the residual signal. In other words, the transmitter gating switch can be controlled to close which bus to obtain the current form of the residual signal.

[0092] It should be noted that, Figure 8 The impedance cancellation circuit shown is only a simplified schematic structure. Figure 11 An impedance cancellation circuit 52 is shown in the figure, such as Figure 11 As shown, the impedance cancellation circuit 52 includes a replica switch 521, a first amplifier 522, and a second amplifier 523; wherein, the first end of the replica switch 521 is coupled to the first end of the receiver selection switch, and the second end of the replica switch 521 is coupled to the input end of the first amplifier 522 and the input end of the second amplifier 523 respectively; the output end of the first amplifier 522 is coupled to the second input end of the first transimpedance amplifier, and the output end of the second amplifier 523 is coupled to the third input end of the first transimpedance amplifier;

[0093] The first amplifier 522 and the second amplifier 523 can employ amplifier structures known in the art. Optionally, they can adopt a current-multiplexed common-gate amplifier structure, that is, the first amplifier 522 and the second amplifier 523 can be common-gate amplifiers, which can effectively receive and amplify high-speed current signals. The amplified current signal is input to the second and third input terminals corresponding to the first transimpedance amplifier. The specific structure of the first amplifier 522 and the second amplifier 523 should be matched with their respective connected NMOS and PMOS transistors. For example, considering that the input voltage of the NMOS transistor is high and the input voltage of the PMOS transistor is low, the first amplifier 522 connected to the gate of the NMOS transistor can be an amplifier with a high output potential, and the second amplifier 523 connected to the gate of the PMOS transistor can be an amplifier with a low output potential. For example... Figure 12 Image (a) shows a common-source, common-gate structure in a first amplifier 522. Figure 12 Figure (b) shows a common-source, common-gate structure in a second amplifier 523. It should be understood that... Figure 12 The two common source cascode structures shown are only one possible implementation provided by the embodiments of this disclosure. In fact, those skilled in the art can customize the common source cascode structure included in the amplifier according to actual needs, and the embodiments of this disclosure do not limit this.

[0094] Based on the above Figure 11 The impedance cancellation circuit shown is briefly described below. The operation of the residual signal processing circuit is as follows: The residual current is obtained from the residual bus through the receiving end selection switch and input to the first transimpedance amplifier. The floating current source (NMOS+PMOS source-connected point) in the first transimpedance amplifier serves as the first input terminal, directly receiving the residual current I. RX The NMOS gate is connected to the output of the first amplifier, and the PMOS gate is connected to the output of the second amplifier, forming a closed-loop control. The input of the second amplifier is connected to the input of the receiver's selector switch via a replica switch, forming a Kelvin connection. The on-resistance of the replica switch is precisely matched to that of the receiver switch to cancel out R. on The influence of the input residual current I. RX The current is converted into a voltage signal output through the TIA core (floating current source + current mirror). The first and second amplifiers force the input to virtual ground by adjusting the NMOS / PMOS gate voltage, which significantly reduces the input impedance.

[0095] It is understandable that the on-resistance R of the receiver's selection switch is... on Will be related to the input current I RXThis creates a voltage drop, causing the actual voltage reaching the TIA input to deviate from the expected value, resulting in gain error. The core idea of ​​a Kelvin connection is to avoid R... on Voltage drop affects detection accuracy. Therefore, the replica switch and the receiver's selector switch can be made to have identical manufacturing dimensions, so that the on-resistance R... on ≈ The resistance R of the replica switch on_rep The replica switch is connected between the input terminal of the second amplifier and the input terminal of the receiver switch 51 to form a Kelvin connection point. Based on this, the negative input terminal of the second amplifier detects the voltage V at the input terminal of the receiver selector switch. in_kelvin The second amplifier forces the voltage at its positive input terminal (i.e., the output terminal of the replica switch) to equal V by adjusting the PMOS gate voltage. in_kelvin Due to the R of the replica switch and the receiver selection switch. on The voltage drop I across the replica switch is the same, and the same current flows through it (due to the virtual short). RX ×R on_rep The voltage drop is synchronously copied to the output of the receiver's gating switch, thus canceling out the voltage drop. This means the voltage at the first input of the TIA is precisely stabilized at V. in_kelvin This eliminates the error introduced by Ron, thus offsetting the on-resistance of the receiver's gating switch. Simultaneously, the first amplifier can be used to drive the NMOS gate with its output, and its input detects the voltage at the first input terminal of TIA. The second amplifier can be used to drive the PMOS gate with its output, and its input detects the Kelvin point voltage V. in_kelvin The two amplifiers form a parallel voltage negative feedback loop, which forces the input voltage to equal the reference voltage (e.g., V). in_kelvin This forms a virtual ground, and the two amplifiers using a common source and common gate structure can provide higher open-loop gain and increase input transconductance. In short, gain enhancement technology is introduced into the residual signal receiving circuit to significantly reduce the input resistance of the TIA by increasing transconductance and using a negative feedback structure.

[0096] As is known, the input impedance of the entire residual signal receiver includes the on-resistance of the receiver gating switch and the input resistance of the transimpedance amplifier. In this embodiment, by setting a replica switch and related circuits, it is equivalent to using a Kelvin connection, which sets a replica path for the receiver gating switch. The replica path under this Kelvin connection can effectively cancel the on-resistance of the receiver gating switch 51. At the same time, by connecting the first amplifier 522 and the second amplifier 523 in the impedance cancellation circuit of this embodiment to the second input terminal and the third input terminal of the transimpedance amplifier 53 respectively, a common-source common-gate input structure with enhanced gain can be formed, thereby effectively reducing the transimpedance amplifier impedance. In short, the impedance cancellation circuit 52 described above can not only cancel the on-resistance of the receiver's selection switch, but also significantly reduce the input resistance of the transimpedance amplifier 53, thereby reducing the overall input impedance of the residual signal receiver. For example, it can reduce the input impedance of the entire residual signal receiver to below tens of ohms, which in turn can significantly reduce the RC time constant formed by the input impedance and parasitic capacitance on the residual bus, making the influence of the input impedance negligible. This is beneficial for improving the effective bandwidth of the residual signal transmission, suppressing signal attenuation and waveform distortion, ensuring the integrity of the residual signal at high frequencies, and also improving the consistency and stability of the residual signal transmission between different modules, which is significantly better than the existing residual signal transmission mode.

[0097] In this embodiment, the residual signal processing circuit employs a low-input-impedance current-receiving structure for current-mode residual signal interconnection at the residual signal receiving end. This structure is applicable to current-mode cross-module residual signal interconnection paths in reconfigurable analog-to-digital converters. Through a common-source, common-gate input structure of the first and second amplifiers with enhanced gain, the input resistance of the transimpedance amplifier is lower than that of conventional designs, and it possesses anti-parasitic performance. Furthermore, it features an impedance cancellation mechanism with Kelvin connections. Specifically, by setting a symmetrical replication path at the receiving end, the influence of the on-resistance of the receiving end's selection switch can be eliminated, improving the consistency and anti-interference capability of the residual signal during transmission between different modules. This is suitable for long-distance or multi-module cascade interconnection scenarios.

[0098] It is known that during the transmission of the residual signal along the shared residual bus between different analog-to-digital conversion modules, the parasitic capacitance on the residual bus may generate residual charge (i.e., the parasitic capacitance produces a "memory effect"). This residual charge can interfere with the subsequently transmitted residual signal. To prevent the "memory effect" caused by the parasitic capacitance of the residual bus, or to prevent the residual signal of the previous cycle from affecting the transmission of the residual signal of the current cycle, one possible implementation is to set multiple distributed reset switches along the residual bus to periodically clear the residual charge on the residual bus. For example, during the reset phase (i.e., the phase when no residual signal transmission is required), the residual bus can be set to a preset level (e.g., V). CM This ensures that the signal transmission path is quickly set, avoiding interference from residual charge from the previous cycle with the expected residual signal to be transmitted in the next cycle, which helps improve the accuracy and response speed of signal transmission in high-speed transmission scenarios.

[0099] Therefore, in one possible implementation, each first analog-to-digital converter module and / or second analog-to-digital converter module may further include: a reset switch circuit for setting the residual bus S2 to a preset voltage; the reset switch circuit is connected to the residual bus S2 and the multiphase clock storage circuit 4 respectively, so that the reset switch circuit can set the residual bus S2 under the control of the multiphase clock storage circuit 4.

[0100] As mentioned above, the residual bus includes multiple buses, and the reset switch circuit includes multiple sub-switch circuits. Taking the reset switch circuit in the first analog-to-digital conversion module as an example, such as... Figure 13 The reset switch circuit shown in the figure has one sub-switch circuit RST corresponding to each bus. bus The first terminal of multiple sub-switch circuits is connected to the preset voltage terminal V. CM Coupling, each sub-switch circuit RST bus The second terminal is coupled to each bus in the residual bus S2. When any sub-switch circuit is closed, the bus coupled to that sub-switch circuit is reset to a preset voltage V. CM .

[0101] In practical applications, each bus in a differential bus is typically a differential structure, meaning each bus includes a P-line and an N-line. Therefore, as... Figure 14 As shown, each sub-switch circuit RST bus It can contain three switches, namely the eleventh switch K. 11 12th switch K 12 And the thirteenth switch K 13 Among them, the eleventh switch K 11 The two ends are coupled to the P line and N line respectively, the twelfth switch K 12 One end is coupled to the P-line and the other end is coupled to the preset voltage terminal V. CM Coupling, the thirteenth switch K13 One end is coupled to the N-line and the other end is coupled to the preset voltage terminal V. CM Coupling, thus, any root bus in the residual bus entering the reset phase (i.e., the phase where residual signals are not transmitted) can be achieved by switching the eleventh switch K. 11 12th switch K 12 And the thirteenth switch K 13 When both switches are closed, the bus coupled to the sub-switch circuit is set to a preset voltage V. CM This method allows for the periodic clearing of residual charges on each bus in the residual bus by utilizing various sub-switching circuits. This prevents residual charges from the previous cycle from interfering with the residual signal expected to be transmitted in the next cycle, thereby improving the accuracy and response speed of signal transmission in high-speed transmission scenarios.

[0102] Based on the heterogeneous analog-to-digital converter proposed in the above embodiments of this disclosure, this disclosure also provides a signal processing device, which includes any of the heterogeneous ADCs provided above, and a digital signal processing circuit coupled to the output terminal of the heterogeneous ADC; wherein, the digital signal processing circuit can be used to process the digital signal output by the heterogeneous ADC.

[0103] Optionally, the signal processing device may further include a radio frequency (RF) front-end circuit. In one example, the signal processing device is a receiver, which includes a radio frequency front-end circuit, the ADC provided in this application, and a digital signal processing circuit coupled in sequence. The RF front-end circuit may be a reconfigurable RF front-end circuit, and the digital signal processing circuit may also be a reconfigurable digital signal processing circuit.

[0104] Based on the signal processing apparatus described above, embodiments of this disclosure also provide an electronic device, which may include a processor and the signal processing apparatus described above. In one example, the signal processing apparatus is a receiver, and the electronic device includes the receiver and may further include a transmitter, etc.

[0105] The above detailed description of the heterogeneous ADC can be applied to the corresponding embodiments of the signal processing device and electronic device, and will not be repeated here.

[0106] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A heterogeneous analog-to-digital converter, characterized in that, include: The system comprises multiple first analog-to-digital converter (ADC) modules, multiple second ADC modules, a first input bus, a second input bus, and a residual bus; wherein the input terminal of each first ADC module is connected to the first input bus, and the input terminal of each second ADC module is connected to the second input bus; the residual bus is connected to each first ADC module and each second ADC module. Each first analog-to-digital conversion module includes: a first multiplexer, a first SAR core, and a first residual signal processing circuit; the first multiplexer is used to acquire an analog signal from the first input bus, and the first SAR core is used to convert the input analog signal into a digital signal; the first residual signal processing circuit includes a transconductance amplifier and a first transimpedance amplifier, the transconductance amplifier is used to convert the voltage-form residual signal generated by the first SAR core into a current-form residual signal for transmission to the residual bus; the first transimpedance amplifier is used to convert the current-form residual signal acquired from the residual bus into a voltage-form residual signal for transmission to the first SAR core; Each second analog-to-digital conversion module includes: a second multiplexer, a second SAR core, and a second residual signal processing circuit. The second multiplexer is used to acquire analog signals from the second input bus; the second SAR core is used to convert the input analog signals into digital signals; the second residual signal processing circuit includes a second transimpedance amplifier, used to convert the current-form residual signal acquired from the residual bus into a voltage-form residual signal for transmission to the second SAR core. The first SAR core outputs a digital signal with a greater number of bits than the second SAR core.

2. The heterogeneous analog-to-digital converter according to claim 1, characterized in that, The heterogeneous analog-to-digital converter further includes a jitter calibration module, which is used to inject voltage jitter signals into each analog-to-digital conversion module and inject current jitter signals into the residual bus, so as to extract the gain deviation between different analog-to-digital conversion modules after injecting voltage jitter signals and current jitter signals and perform gain calibration based on gain offset; The jitter calibration module includes a pseudo-random number generator and a current-mode digital-to-analog converter. The output of the pseudo-random number generator is connected to the first SAR core in each first analog-to-digital converter module and / or the second SAR core in each second analog-to-digital converter module. The output of the pseudo-random number generator is connected to the input of the current-mode digital-to-analog converter, and the output of the current-mode digital-to-analog converter is connected to the residual bus. The pseudo-random number generator is used to inject voltage jitter signals into the first SAR core in each first analog-to-digital conversion module and / or the second SAR core in each second analog-to-digital conversion module; the current-mode digital-to-analog converter is used to inject current jitter signals into the residual bus based on the voltage jitter signals generated by the pseudo-random number generator.

3. The heterogeneous analog-to-digital converter according to claim 1, characterized in that, The operation of the heterogeneous analog-to-digital converter in pipeline mode includes: The first multiplexer in the first analog-to-digital converter module receives a first analog signal from the first input bus; The first SAR core of the first analog-to-digital conversion module converts the first analog signal into a first digital signal, and generates a first residual signal based on the first analog signal and the first digital signal; The first residual signal processing circuit of the first analog-to-digital conversion module processes the first residual signal and sends the processed second residual signal to the residual bus; The second residual signal processing circuit of the second analog-to-digital conversion module receives the second residual signal from the residual bus, amplifies the second residual signal, and converts it into a third residual signal; The second SAR core of the second analog-to-digital converter module converts the third residual signal into a second digital signal.

4. The heterogeneous analog-to-digital converter according to any one of claims 1 to 3, characterized in that, The first residual signal processing circuit in each first analog-to-digital conversion module further includes: a switched capacitor circuit, used to feed the residual signal input by the transconductance amplifier or output by the first transimpedance amplifier into the signal path; The switched capacitor circuit includes: a first capacitor, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth switch, and a tenth switch; Specifically, the first terminal of the fifth switch is coupled to the output terminal of the first transimpedance amplifier; the second terminal of the fifth switch, the first terminal of the sixth switch, the first terminal of the seventh switch, and the first terminal of the first capacitor are coupled together; the second terminal of the sixth switch is coupled to the N terminal of the differential circuit in the first SAR core; the second terminal of the seventh switch is coupled to the P terminal of the differential circuit in the first SAR core; the second terminal of the first capacitor, the first terminal of the eighth switch, and the first terminal of the ninth switch are coupled together; the second terminal of the eighth switch is coupled to a preset voltage terminal; the second terminal of the ninth switch and the first terminal of the tenth switch are coupled to the input terminal of the transconductance amplifier; and the second terminal of the tenth switch is coupled to the P terminal of the differential circuit in the first SAR core.

5. The heterogeneous analog-to-digital converter according to claim 4, characterized in that, The switched capacitor circuit has the following configuration states: residual sampling state, charge sharing state, capacitor stacking state, and pass-through state; In the residual sampling state, the fifth and eighth switches are closed, and all switches except the fifth and eighth switches are open. In the charge-sharing state, the sixth or seventh switch is closed, the eighth switch is closed, and all switches except the sixth or seventh switch are disconnected from the eighth switch. In the capacitor stacking state, the sixth or seventh switch is closed, the ninth switch is closed, and all switches except the sixth or seventh switch are disconnected from the ninth switch. In the straight-through state, the tenth switch is closed, and all other switches are open.

6. The heterogeneous analog-to-digital converter according to any one of claims 1 to 3, characterized in that, The first residual signal processing circuit in each first analog-to-digital conversion module further includes: a receiver gating switch and an impedance cancellation circuit connected to the first transimpedance amplifier, and a transmitter gating switch connected to the transconductance amplifier; The first transimpedance amplifier includes a floating current source, which is composed of an NMOS transistor and a PMOS transistor connected at their sources. The source of the NMOS transistor and the PMOS transistor is connected as the first input terminal of the first transimpedance amplifier, the gate of the NMOS transistor is connected as the second input terminal of the first transimpedance amplifier, and the gate of the PMOS transistor is connected as the third input terminal of the first transimpedance amplifier. The first end of the receiver gating switch is coupled to the residual bus and the second end of the receiver gating switch is coupled to the first input end of the first transimpedance amplifier, for obtaining the residual signal in the form of current from the residual bus and transmitting it to the first transimpedance amplifier. The impedance cancellation circuit is used to cancel the on-resistance of the receiver gating switch and reduce the input resistance of the first transimpedance amplifier. The impedance cancellation circuit includes a replica switch, a first amplifier, and a second amplifier. The first terminal of the replica switch is coupled to the first terminal of the receiver gating switch, and the second terminal of the replica switch is coupled to the input terminals of the first amplifier and the second amplifier, respectively. The output terminal of the first amplifier is coupled to the second input terminal of the first transimpedance amplifier, and the output terminal of the second amplifier is coupled to the third input terminal of the first transimpedance amplifier. The first terminal of the transmitting gating switch is coupled to the output terminal of the transconductance amplifier, and the second terminal of the transmitting gating switch is coupled to the residual bus; the transmitting gating switch is used to transmit the residual signal in the form of current output by the transconductance amplifier to the residual bus.

7. The heterogeneous analog-to-digital converter according to claim 6, characterized in that, The first transimpedance amplifier also includes a first current mirror, a second current mirror, a first switch, a second switch, a third switch, a fourth switch, and a first resistor; In this configuration, the drain of the NMOS transistor in the floating current source is connected in series with the first terminal of the first current mirror to the first switch; the drain of the PMOS transistor in the floating current source is connected in series with the first terminal of the second current mirror to the second switch; the second terminal of the first current mirror is coupled to the first terminal of the third switch; and the second terminal of the second current mirror is coupled to the first terminal of the fourth switch. The second end of the third switch, the second end of the fourth switch, and the first end of the first resistor are coupled together to serve as the output end of the first transimpedance amplifier, so as to output the residual signal in the form of the converted voltage; the second end of the first resistor is coupled to a preset voltage terminal.

8. The heterogeneous analog-to-digital converter according to any one of claims 1 to 3, characterized in that, Each first analog-to-digital converter module and / or second analog-to-digital converter module further includes: a reset switch circuit for resetting the residual bus to a preset voltage; The residual bus includes multiple buses, and the reset switch circuit includes multiple sub-switch circuits. Each bus corresponds to one sub-switch circuit. The first end of each sub-switch circuit is coupled to a preset voltage terminal, and the second end of each sub-switch circuit is coupled to each bus in the residual bus. When any sub-switch circuit is closed, the bus coupled to that sub-switch circuit is reset to the preset voltage.

9. A signal processing apparatus, characterized in that, The device includes: a heterogeneous analog-to-digital converter as described in any one of claims 1 to 8, and a digital signal processing circuit coupled to the heterogeneous analog-to-digital converter.

10. An electronic device, characterized in that, The electronic device includes: a processor, and a signal processing apparatus as described in claim 9.

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