Multi-channel code interleaving method, device, equipment and medium

Abstract

The invention discloses a multichannel code interleaving method, device and equipment and a medium, and relates to the technical field of integrated circuits. According to the scheme, a direct memory access and multi-channel technology is adopted in advance, a multi-channel coding interleaving circuit comprising a plurality of coding channels and a plurality of decoding channels is built to serve as a hardware basis of coding interleaving, multiple groups of to-be-coded data or to-be-decoded data are processed at the same time through multiple channels, coding and interleaving processing of complex scenes can be carried out, and the coding efficiency is improved. The data throughput and the data coding and interleaving processing speed are greatly improved; meanwhile, after the target coding / decoding channel is determined, configuration parameters corresponding to the coding / decoding interleaving submodules are determined according to the corresponding coding / decoding control descriptors, so that direct control over the target coding / decoding channel is achieved, flexible adjustment of interleaving parameters is supported, frame response delay is reduced, and configuration flexibility is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a multi-channel coding interleaving method, apparatus, device and medium. Background Technology

[0002] In data transmission, coding and interleaving techniques effectively address channel interference and sudden errors by adding redundant information and rearranging data order, thereby improving transmission reliability. These techniques are widely used in wireless communication and flash memory devices, such as USB flash drives and solid-state drives, to extend device lifespan and protect data integrity.

[0003] However, current interleaving coding circuit schemes face challenges when handling multiple data frames. The software first writes the data into the hardware circuitry and then processes it sequentially. However, when the business scenario involves large amounts of data and inconsistent encoding / decoding schemes, this approach suffers from low throughput and struggles to guarantee timely data transmission and response. Furthermore, while setting up dedicated circuits for different code types and interleaving depths is simple to implement, it suffers from low resource utilization and cannot adapt to scenarios requiring flexible adjustment of interleaving parameters.

[0004] In view of the above, how to solve the problems of low throughput, insufficient resource utilization, and difficulty in flexibly adjusting interleaving parameters faced by existing interleaving coding circuits when processing large amounts of data and diverse coding and decoding schemes is an urgent problem for technicians in this field. Summary of the Invention

[0005] This invention provides a multi-channel coding interleaving method, apparatus, device, and medium to at least solve the problems of low throughput, insufficient resource utilization, and difficulty in flexibly adjusting interleaving parameters faced by existing interleaving coding circuit schemes when processing large amounts of data and diverse coding and decoding schemes.

[0006] This invention provides a multi-channel coding interleaving method applied to a multi-channel coding interleaving circuit; the multi-channel coding interleaving circuit includes at least multiple coding channels and multiple decoding channels; each coding channel contains multiple coding interleaving sub-modules; each decoding channel contains multiple decoding interleaving sub-modules; the method includes:

[0007] Acquire the data to be encoded or decoded, and determine the priority of the data to be encoded or decoded;

[0008] Based on the priority of the data to be encoded or the priority of the data to be decoded, determine the target encoding channel in each encoding channel, or determine the target decoding channel in each decoding channel;

[0009] Obtain and parse the encoding control descriptor corresponding to the target encoding channel to determine the configuration parameters of each target encoding interleaving submodule, or obtain and parse the decoding control descriptor corresponding to the target decoding channel to determine the configuration parameters of each target decoding interleaving submodule;

[0010] The data to be encoded is input into the target encoding channel, and each target encoding interleaving submodule is controlled to encode the data according to the corresponding configuration parameters; or the data to be decoded is input into the target decoding channel, and each target decoding interleaving submodule is controlled to decode the data according to the corresponding configuration parameters.

[0011] The present invention also provides a multi-channel encoding interleaving device applied to a multi-channel encoding interleaving circuit; the multi-channel encoding interleaving circuit includes at least multiple encoding channels and multiple decoding channels; the encoding channels include multiple encoding interleaving sub-modules; the decoding channels include multiple decoding interleaving sub-modules; the device includes:

[0012] The acquisition module is used to acquire data to be encoded or data to be decoded, and to determine the priority of the data to be encoded or the priority of the data to be decoded.

[0013] The first determining module is used to determine the target encoding channel in each encoding channel or the target decoding channel in each decoding channel according to the priority of the data to be encoded or the priority of the data to be decoded.

[0014] The second determining module is used to obtain and parse the encoding control descriptor corresponding to the target encoding channel in order to determine the configuration parameters of each target encoding interleaving submodule, or to obtain and parse the decoding control descriptor corresponding to the target decoding channel in order to determine the configuration parameters of each target decoding interleaving submodule.

[0015] The encoding / decoding module is used to input the data to be encoded into the target encoding channel and control each target encoding interleaving submodule to encode the data according to the corresponding configuration parameters, or to input the data to be decoded into the target decoding channel and control each target decoding interleaving submodule to decode the data according to the corresponding configuration parameters.

[0016] The present invention also provides an electronic device, comprising: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the above-described multichannel coding interleaving methods.

[0017] The present invention also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described multichannel code interleaving methods.

[0018] The beneficial effects of this invention are as follows: by pre-emphasizing direct memory access and multi-channel technology, a multi-channel encoding and decoding interleaving circuit is constructed as the hardware foundation for encoding and interleaving. Utilizing multiple channels to simultaneously process multiple sets of data to be encoded or decoded enables encoding and interleaving processing in complex scenarios, significantly improving data throughput and the processing speed of data encoding and interleaving. Furthermore, after determining the target encoding / decoding channel, the configuration parameters of each corresponding encoding / decoding interleaving submodule are determined according to the corresponding encoding / decoding control descriptor, enabling direct control of the target encoding / decoding channel. This supports flexible adjustment of interleaving parameters, reduces frame response latency, and improves configuration flexibility.

[0019] In addition, the present invention also provides a multi-channel coding interleaving device, equipment and medium, with the same effect as above. Attached Figure Description

[0020] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a block diagram of a conventional coding interleaving circuit structure provided in an embodiment of the present invention;

[0022] Figure 2 A schematic diagram of a multi-channel coded interleaving circuit provided in an embodiment of the present invention;

[0023] Figure 3 A flowchart of a multi-channel coding interleaving method provided in an embodiment of the present invention;

[0024] Figure 4 A structural diagram of a ring descriptor provided in an embodiment of the present invention;

[0025] Figure 5 This is a diagram of the encoding control descriptor structure provided in an embodiment of the present invention;

[0026] Figure 6 This is a diagram of the decoding control descriptor structure provided in an embodiment of the present invention;

[0027] Figure 7 This is a schematic diagram of the write-back content of the encoding control descriptor provided in an embodiment of the present invention;

[0028] Figure 8 This is a schematic diagram of the decoding control descriptor write-back content provided in an embodiment of the present invention;

[0029] Figure 9This is a timing diagram of the encoding and interleaving process provided in an embodiment of the present invention;

[0030] Figure 10 This is a timing diagram of the deinterleaving and decoding process provided in an embodiment of the present invention;

[0031] Figure 11 This is a schematic diagram of a multi-channel coding interleaving device provided in an embodiment of the present invention. Detailed Implementation

[0032] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0033] It should be noted that, in the description of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0034] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] Figure 1 This is a block diagram of a conventional coded interleaving circuit structure provided in an embodiment of the present invention. Figure 1 As shown, the currently widely used interleaving coding circuit scheme involves the software first writing the data to be encoded into the hardware circuit, and then processing the data stream sequentially. Furthermore, if the business requires data frames with different code types, encoding methods, and interleaving depths, separate encoding and interleaving circuits are needed for each. Decoding is similar to encoding, requiring separate decoding and deinterleaving circuits. The decoded data frames are then read sequentially by the software. However, when the business scenario involves large amounts of data and inconsistent encoding / decoding schemes, this scheme suffers from low throughput, making it difficult to guarantee the timeliness of data transmission and response. In addition, while setting up dedicated circuits for different code types and interleaving depths is simple to implement, it has low resource utilization and cannot adapt to scenarios requiring flexible adjustment of interleaving parameters. Therefore, to solve the above problems, this invention provides a multi-channel encoding and interleaving circuit.

[0036] Figure 2This is a schematic diagram of a multi-channel coded interleaving circuit provided in an embodiment of the present invention. Figure 2 As shown, the multi-channel code-interleaving circuit includes at least multiple encoding channels and multiple decoding channels. Each encoding channel contains multiple encoding-interleaving submodules; each decoding channel contains multiple decoding-interleaving submodules. In this embodiment, the specific number of encoding channels / decoding channels is not limited, nor is the specific type of encoding-interleaving submodules / decoding-interleaving submodules; it depends on the specific implementation. It should be noted that the multi-channel code-interleaving method provided by this invention is applied to multi-channel code-interleaving circuits.

[0037] Figure 3 This is a flowchart illustrating a multi-channel coding interleaving method provided in an embodiment of the present invention. Figure 3 As shown, the method includes:

[0038] S10: Obtain the data to be encoded or the data to be decoded, and determine the priority of the data to be encoded or the priority of the data to be decoded.

[0039] Specifically, the process begins with acquiring either the data to be encoded or the data to be decoded. It's important to note that the data to be encoded and the data to be decoded originate from different sources. The data to be encoded typically comes from memory, i.e., the multi-channel encoding and interleaving circuit communicates with the memory; while the data to be decoded typically comes from other components, such as a network interface card (NIC), modulator, etc.

[0040] Subsequently, the priority of the data to be encoded or the priority of the data to be decoded is determined. It should be noted that the priority of the data to be encoded represents its importance or urgency in encoding, while the priority of the data to be decoded represents its importance or urgency in decoding. When there are multiple sets of data to be encoded or multiple sets of data to be decrypted, the encoding / decoding order of each set of data is set according to its corresponding priority. This embodiment does not limit the specific process for determining the priority of the data to be encoded or the priority of the data to be decoded; it depends on the specific implementation.

[0041] S11: Determine the target encoding channel in each encoding channel or the target decoding channel in each decoding channel according to the priority of the data to be encoded or the priority of the data to be decoded.

[0042] Depend on Figure 2 As can be seen, a multi-channel code-interleaving circuit contains multiple encoding channels and multiple decoding channels. It is important to note that the encoding methods of each encoding channel are different, and the decoding methods of each decoding channel are different, depending on the specific configuration of each channel, in order to adapt to different encoding and decoding requirements.

[0043] Therefore, after determining the priority of the data to be encoded or the priority of the data to be decoded, a target encoding channel is determined in each encoding channel, or a target decoding channel is determined in each decoding channel, based on the priority of the data to be encoded or the priority of the data to be decoded. It should be noted that the target encoding channel and the target decoding channel are respectively the channels applicable to the corresponding data to be encoded and the channels applicable to the corresponding data to be decoded. This embodiment does not limit the process of determining the target encoding channel and the target decoding channel; it depends on the specific implementation.

[0044] S12: Obtain and parse the encoding control descriptor corresponding to the target encoding channel to determine the configuration parameters of each target encoding interleaving submodule, or obtain and parse the decoding control descriptor corresponding to the target decoding channel to determine the configuration parameters of each target decoding interleaving submodule.

[0045] To enable individual configuration of encoding and decoding parameters for each frame of data, flexibly adjust the data encoding and decoding methods, improve the synergy between hardware and software, make information exchange between software programs and control circuits more efficient, improve the processing efficiency of different types of messages, and reduce response latency, this invention sets corresponding encoding control descriptors and decoding control descriptors for each encoding channel and decoding channel, which are stored in different areas of memory respectively.

[0046] Figure 4 This is a structural diagram of a ring descriptor provided in an embodiment of the present invention. It should be noted that, as... Figure 4 As shown, the encoding control descriptor is a ring descriptor, which contains configuration parameters for each encoding interleaving submodule within the corresponding channel, including at least interleaving parameters, enabling direct control of the encoding process for that channel. Similarly, the decoding control descriptor is a ring descriptor, which contains configuration parameters for each decoding interleaving submodule within the corresponding channel, enabling direct control of the decoding process for that channel. This embodiment does not limit the specific content of the encoding and decoding control descriptors, nor does it limit the specific process for obtaining them; it depends on the specific implementation.

[0047] Therefore, in this embodiment, in order to perform encoding of the data to be encoded or decoding of the data to be decoded, the encoding control descriptor corresponding to the target encoding channel is specifically obtained and parsed to determine the configuration parameters of each target encoding interleaving submodule, or the decoding control descriptor corresponding to the target decoding channel is obtained and parsed to determine the configuration parameters of each target decoding interleaving submodule.

[0048] S13: Input the data to be encoded into the target encoding channel and control each target encoding interleaving submodule to encode the data according to the corresponding configuration parameters, or input the data to be decoded into the target decoding channel and control each target decoding interleaving submodule to decode the data according to the corresponding configuration parameters.

[0049] Finally, the data to be encoded is input to the target encoding channel, and each target encoding interleaving submodule is controlled to encode the data according to the corresponding configuration parameters, or the data to be decoded is input to the target decoding channel, and each target decoding interleaving submodule is controlled to decode the data according to the corresponding configuration parameters, thereby realizing the encoding or decoding process.

[0050] In this embodiment, Direct Memory Access (DMA) and multi-channel technology are used to build a multi-channel encoding and decoding interleaving circuit as the hardware foundation for encoding and interleaving. By using multiple channels to process multiple sets of data to be encoded or decoded simultaneously, encoding and interleaving processing in complex scenarios can be performed, greatly improving data throughput and data encoding and interleaving processing speed. At the same time, after determining the target encoding / decoding channel, the configuration parameters of each encoding / decoding interleaving submodule are determined according to the corresponding encoding / decoding control descriptor, so as to realize direct control of the target encoding / decoding channel, support flexible adjustment of interleaving parameters, reduce frame response latency, and improve configuration flexibility.

[0051] Based on the above embodiments, in some embodiments, such as Figure 2 As shown, the multi-channel encoding and interleaving circuit also includes a Direct Memory Access Channel Arbiter (DMA arbiter); the DMA arbiter is connected to the memory via the AXI Master Interface. Simultaneously, the DMA arbiter is also connected to each encoding channel and each decoding channel. Furthermore, Figure 2 The AHB Slave Interface is connected to the processor for communication; the control register is connected to the AHB Slave Interface and also communicates with each submodule.

[0052] Furthermore, the encoding interleaving submodule includes a direct memory access control unit, a bit width conversion unit, an encoding timing control unit, an encoding unit, an interleaving unit, a transmission queue, and a transmission control unit, all connected in sequence. The decoding interleaving submodule includes a direct memory access control unit, a bit width conversion unit, a decoding unit, a decoding timing control unit, a deinterleaving unit, a receive queue, and a receive control unit, all connected in sequence. The operation process of each submodule is described below:

[0053] The function of the bit-width conversion unit is to convert the bus bit width to the encoding symbol bit width. For example, if DMA uses a 128-bit bus and employs RS(15,31) encoding, where each input symbol is 5 bits wide, then the 128-bit continuous data stream needs to be converted into a 5-bit data stream before being input into the encoder. The decoding direction is similar; the 5-bit continuous data stream needs to be converted into 128-bit data before being moved to memory via DMA. The bit-width conversion unit includes a temp register with a width equal to the least common multiple of the bit widths before and after conversion. It also controls the conversion from a high-bit-width continuous data stream to a low-bit-width data stream by reverse-pressure using the bus ready signal. Alternatively, asynchronous dual-port RAM can be used, allowing the read speed to be higher than the write speed, to achieve the conversion from a high-bit-width data stream to a low-bit-width data stream. In the decoding direction, the conversion of low-bit-width to high-bit-width data streams is simpler. Two sets of temp registers, each representing the least common multiple of the bit width before and after conversion, are used to process the input data stream in a "ping-pong" fashion. When one set of conversions is output, the input data is saved to the other set of temp registers. This alternating process achieves maximum conversion speed and uninterrupted bit-width conversion. No specific method is limited to the bit-width conversion method described here; the methods mentioned above are not excluded.

[0054] The encoding / decoding timing control unit is used to control the data flow and the generation and timing control of corresponding enable signals. In the encoding direction, due to the conversion time required by the preceding bit-width conversion circuit, the encoder input data may be discontinuous, necessitating the addition of enable signal control. After inputting a set of data to be encoded, a waiting period may be required until the encoder completes its encoding process before new data can be input. Furthermore, considering encoders with different encoding methods, some encodings are more complex, such as Low-Density Parity-Check (LDPC) encoding, which has a longer encoding time. To increase processing speed, multiple encoders can be used in a "ping-pong" manner to process the data to be encoded. In this case, the encoding timing control unit also needs to control the alternating writing of the data to be encoded to multiple encoders, while simultaneously generating the corresponding enable signals. Alternatively, a reverse-pressure method can be used. If encoding is not completed before encoding, the encoder pulls down the ready signal and outputs it to the encoding / decoding timing control unit, controlling the bit-width conversion circuit to temporarily delay the output of data to the encoder. This saves encoder resources but slows down the processing speed. The ping-pong or reverse-pressure method can be selected by configuring the encoding control register. In the decoding direction, the timing control unit receives the discontinuous data stream with enable signals from the deinterleaving unit, controls the data stream, groups the data stream into sets of decoding lengths, and then controls the data stream input to the decoder. If the decoder uses ping-pong processing, it also controls the deinterleaving unit's output data stream to flow to different decoders to achieve faster decoding data processing. If inverse pressure is used, if decoding is not complete, the decoder pulls down the ready signal to output to the deinterleaving unit, controlling the deinterleaving unit to temporarily delay outputting data to the decoder. The ping-pong processing or inverse pressure method can be selected by configuring the encoding control register.

[0055] The encoder / decoder can be specifically an LDPC encoder / decoder, RS encoder / decoder, etc. This embodiment does not restrict the specific encoding method or code type; selection is based on requirements. However, since the output of the preceding stage and the input of the following stage need to be considered, additional processing of the encoder / decoder input / output timing is required. In the encoding direction, the preceding stage is the output of the bit-width conversion circuit, and the data may be discontinuous. A valid signal is needed to mark valid data, and encoding begins once enough valid data is input. Since the encoding process may be lengthy, new data cannot be input during this period. This can be achieved by using multiple encoders to process the encoded data alternately, or by using an encoder with reverse pressure function, controlling the data input to be temporarily delayed by pulling down the ready signal. Since the next stage is an interleaver, the encoder needs to output data multiple times to accumulate enough for one interleaving block, so the encoder's output signal also needs to be marked with a valid signal. In the decoding direction, the decoding time is long, but since the speed at which the data to be decoded is input to the decoder is slow (limited by the receiving method, etc.), multiple decoders are no longer needed. Only the output data of the deinterleaver needs to be reverse-pressured using the ready signal to ensure that the deinterleaver does not input new data to the decoder during decoding.

[0056] The interleaving / deinterleaving units employ block interleaving, writing data row-by-row and reading it column-by-column. The interleaving depth and width of the interleaving units are parameterized, allowing them to be changed according to descriptor instructions. However, configuration should not be performed during interleaving / deinterleaving, as this may lead to errors. Larger interleaving blocks provide better dispersion of consecutive errors but also consume more resources. The width of a single data bit is consistent with the encoder / decoder. The deinterleaving unit supports output timing control, while the interleaving unit supports input timing control. The transmitting end can perform interleaving according to a fixed or variable interleaving scheme. If a change in the interleaving scheme of the transmitted frame is required, the interleaving method must be synchronized to the receiving end in advance using the content of the previous data frame. The receiving station saves the interleaving scheme information for different source stations according to the source station number. When receiving data, the receiving station selects the corresponding scheme based on the source station number and automatically configures the interleaving width and depth.

[0057] A transmit / receive queue is a first-in, first-out (FIFO) queue used to temporarily store data to be transmitted, ensuring that data is transmitted sequentially and stably. The transmit / receive control unit is responsible for managing and controlling the data transmission process, including data formatting, encoding, modulation, and scheduling of transmission timing, to ensure that data is transmitted according to predetermined requirements and protocols.

[0058] Furthermore, the direct memory access channel arbitration unit can perform channel arbitration, arbitrating DMA requests for the encoding and decoding channels, ensuring that only encoding or decoding can occur at any given time. Specifically, the weights of the read and write directions for each channel are configured through registers, allocating the number of burst transmissions of read data (data to be encoded) and write data (decoded data) within the arbitration cycle, thereby guaranteeing the orderliness and stability of the encoding and decoding process.

[0059] Meanwhile, to prevent clock drift, time synchronization is performed between the master and slave stations, and clock drift information is periodically corrected. It should be noted that during encoding, the multi-channel encoding interleaving circuit is located at the master station, and the target station for the encoded data is the slave station; during decoding, the source station of the data to be encoded is the master station, and the multi-channel encoding interleaving circuit is located at the slave station. Further, the slave station records the start encoding time T1 and the encoding-to-transmission duration T2, from which the transmission time T3 = T1 + T2 can be calculated and recorded locally. It is understandable that since the transmission time occurs after encoding, the transmission time data cannot be encoded before transmission; the encoding start time must be recorded before encoding, and the transmission time can be calculated based on the encoding duration. After receiving the data packet, the master station records the reception time T4 and returns the reception time T4, the fixed encoding duration T5, and the encoding start time T6 (transmission time T7 = T5 + T6) to the slave station via a data packet. The slave station then records the time it received the data, T8. The time deviation can be calculated from the four times T3, T4, T7, and T8 at the station. This allows for time synchronization between data transmission nodes without affecting encoding and decoding.

[0060] Based on the above embodiments, in some embodiments, determining the priority of the data to be encoded includes:

[0061] S101: Determine the data packet type of the data to be encoded; wherein the data packet type includes at least control data packets, normal data packets, and emergency data packets.

[0062] S102: Determine the priority of the data to be encoded according to the data packet type; wherein, the priority of urgent data packets is higher than that of control data packets, and the priority of control data packets is higher than that of ordinary data packets.

[0063] To determine the priority of the data to be encoded, the data packet type must first be identified. Specifically, data packets destined for different stations are categorized into control packets, normal packets, and urgent packets. Different types of data packets employ different encoding methods. Therefore, the priority of the data to be encoded is determined based on the data packet type, with urgent packets having a higher priority than control packets, and control packets having a higher priority than normal packets.

[0064] Correspondingly, the priority of the data to be decoded is determined, including:

[0065] S103: Determine the source station number to which the data to be decoded belongs, and determine the priority weight of the source station number; wherein, priority weights are pre-set for multiple stations that support the output of the data to be decoded, and the priority weights of each station are different.

[0066] S104: Determine the priority of the data to be decoded based on the priority weight of the source site number.

[0067] To determine the priority of the data to be decoded, the source station number of the data to be decoded is first determined. This source station number is simply the station number where decoding is required, and the corresponding data is the data to be decoded. Simultaneously, priority weights are pre-assigned to multiple source stations that support the output of the data to be decoded; each station has a different priority weight. Therefore, the priority weight of each source station corresponds to the priority of its respective data to be decoded, and the priority of the data to be decoded can be directly determined based on the priority weight of the source station number. It should also be noted that there is no priority distinction between data packets of the same type sent to different stations; they are encoded sequentially.

[0068] This allows for the determination of the priority of the data to be encoded or decoded, facilitating the subsequent selection of the corresponding target encoding or decoding channel.

[0069] Based on the above embodiments, in some embodiments, a target encoding channel is determined among each encoding channel according to the priority of the data to be encoded, including:

[0070] S111: Obtain the number of burst transmissions corresponding to each pre-configured encoding channel.

[0071] S112: Determine the target encoding channel among the encoding channels based on the priority of the data to be encoded and the number of burst transmissions corresponding to each encoding channel.

[0072] To determine the target encoding channel, this embodiment also requires encoding channel arbitration. Specifically, the DMA encoding channel register is pre-configured via software, setting weights for enabled encoding channels. Based on the set weights, corresponding burst transmission counts are allocated within the DMA arbitration cycle. The maximum number of burst transmissions per cycle is configured by software. When it is necessary to determine the target encoding channel, the pre-configured burst transmission counts for each encoding channel are directly obtained. Based on the priority of the data to be encoded and the burst transmission counts for each encoding channel, the target encoding channel is determined among the various encoding channels. For example, for urgent data packets to be encoded, the encoding channel with a high corresponding burst transmission count should be used; for ordinary data packets to be encoded, the encoding channel with a low corresponding burst transmission count can be used.

[0073] This increases the throughput of encoded data and prevents lower-priority data from remaining unprocessed for extended periods.

[0074] Correspondingly, based on the priority of the data to be decoded, the target decoding channel is determined in each decoding channel, including:

[0075] S113: Obtain the decoding channel specified by the source station number to which the data to be decoded belongs.

[0076] S114: Determine the target decoding channel among the decoding channels according to the priority of the data to be decoded and the specified decoding channel.

[0077] The selection method for decoding channels differs from that for encoding channels. Specifically, the decoding channel specified by the source station number of the data to be decoded is obtained. Based on the priority of the data to be decoded and the specified decoding channel, the target decoding channel is determined from among the various decoding channels. In other words, the target decoding channel is directly determined by the source station number, rather than by the data to be decoded.

[0078] Based on the above embodiments, in some embodiments, obtaining the encoding control descriptor includes:

[0079] S121: Determine the starting address of the encoding control descriptor based on the configuration bit information of the direct memory access control register.

[0080] S122: Read the encoding control descriptor based on the starting address of the encoding control descriptor.

[0081] The encoding control descriptor includes at least the source station number, destination station number, interleaving depth and width of different interleaving blocks in the current frame, data frame length, frame start address information, whether the interrupt flag is enabled, and whether the current descriptor has been processed by direct memory access.

[0082] In order to obtain the encoding control descriptor, in this embodiment, the starting address of the encoding control descriptor is determined according to the configuration bit information of the direct memory access control register, and the encoding control descriptor is read according to the starting address of the encoding control descriptor.

[0083] Figure 5 This is a structure diagram of the encoding control descriptor provided in an embodiment of the present invention. For example... Figure 5 As shown, the encoding control descriptor includes at least the source station number, destination station number, interleaving depth and width of different interleaving blocks in the current frame, data frame length, frame start address information, whether the interrupt flag is enabled, and whether the current descriptor has been processed by direct memory access.

[0084] Correspondingly, the decoding control descriptor is obtained, including:

[0085] S123: Determine the starting address of the decoding control descriptor based on the configuration bit information of the direct memory access control register.

[0086] S124: Read the decoding control descriptor based on the starting address of the decoding control descriptor.

[0087] The decoding control descriptor includes at least the starting memory address for receiving data, whether the interrupt flag is enabled, and whether the current descriptor has been processed by direct memory access.

[0088] In order to obtain the decoding control descriptor, in this embodiment, the starting address of the decoding control descriptor is determined according to the configuration bit information of the direct memory access control register, and the decoding control descriptor is read according to the starting address of the decoding control descriptor.

[0089] Figure 6 This is a structure diagram of the decoding control descriptor provided in an embodiment of the present invention. For example... Figure 6 As shown, the decoding control descriptor includes at least the starting memory address for receiving data (frame start address), whether to enable the interrupt flag, and whether the current descriptor has been processed by direct memory access.

[0090] This enables the accurate acquisition of encoding control descriptors / decoding control descriptors, facilitating precise control of the encoding / decoding processes executed by each submodule.

[0091] Based on the above embodiments, in some embodiments, each target coding interleaving submodule is controlled to encode the data to be encoded according to corresponding configuration parameters, including:

[0092] S131: Based on the source station number, destination station number, interleaving depth and width of different interleaving blocks in the current frame, data frame length, frame start address information, whether the interrupt flag is enabled, and whether the current descriptor has been processed by direct memory access, control each target encoding interleaving submodule to encode the data to be encoded.

[0093] In order to encode the data to be encoded, this embodiment specifically controls the operation of each target encoding and interleaving submodule based on the source station number, destination station number, interleaving depth and width of different interleaving blocks in the current frame, data frame length, frame start address information, whether the interrupt flag is enabled, and whether the current descriptor has been processed by direct memory access. That is, the above information is used to control the direct memory access control unit, bit width conversion unit, encoding timing control unit, encoding unit, interleaving unit, transmission queue and transmission control unit under the target encoding channel to encode the data to be encoded.

[0094] Correspondingly, each target decoding interleaving submodule is controlled to decode the data to be decoded according to the corresponding configuration parameters, including:

[0095] S132: Obtain the interleaving parameters output by the source station number to which the data to be decoded belongs.

[0096] S133: Based on the interleaving parameters output by the source station number to which the data to be decoded belongs, as well as the starting memory address of the received data, whether the interrupt flag is enabled, and whether the current descriptor has been directly accessed and processed flag in the decoding control descriptor, control each target decoding interleaving submodule to decode the data to be decoded.

[0097] Unlike the encoding process, the decoding process requires obtaining the interleaving parameters output by the source station number to which the data to be decoded belongs. Then, based on the interleaving parameters output by the source station number to which the data to be decoded belongs, as well as the starting memory address of the received data, whether the interrupt flag is enabled, and whether the current descriptor has been directly accessed and processed flag in the decoding control descriptor, the target decoding interleaving submodule is controlled to decode the data to be decoded.

[0098] Therefore, based on the encoding and decoding control descriptors, it is possible to perform encoding and interleaving processing in complex scenarios, which greatly improves the processing speed of data encoding and interleaving, reduces frame response latency, and makes the configuration more flexible.

[0099] It should also be noted that the length, number of interleavings, interleaving depth, and width of transmitted data packets of the same type are related to the destination station, while the length, number of deinterleavings, deinterleaving depth, and width of received data packets of the same type are related to the source station. Since each data frame requires multiple interleavings, but the interleaving block size is not always perfectly rounded, flexibly adjusting the width and depth of the interleaving block according to the actual transmission environment can reduce redundant zero-padding data.

[0100] Based on the above embodiments, in some embodiments, after controlling each target coding interleaving submodule to encode the data to be encoded according to the corresponding configuration parameters, the method further includes:

[0101] S141: Send the encoded data to the destination station and write the transmission status information back to the original address of the encoding control descriptor.

[0102] Figure 7 This is a schematic diagram illustrating the write-back content of the encoding control descriptor provided in an embodiment of the present invention. For example... Figure 7 As shown, after each target encoding interleaving submodule encodes the data to be encoded according to the corresponding configuration parameters, the encoded data is sent to the destination station, and the transmission status information is written back to the original address of the encoding control descriptor. The content written back includes the DMA processing flag, the transmission timeout flag, and the transmission time.

[0103] Correspondingly, after controlling each target decoding interleaving submodule to decode the data to be decoded according to the corresponding configuration parameters, the following is also included:

[0104] S142: Based on the starting memory address of the received data in the decoding control descriptor, the decoded data is transferred to memory, and the decoded information is written back to the decoding control descriptor.

[0105] Figure 8 This is a schematic diagram illustrating the write-back content of the decoding control descriptor provided in an embodiment of the present invention. Figure 8 As shown, after controlling each target decoding interleaving submodule to decode the data to be decoded according to the corresponding configuration parameters, the decoded data is transmitted to memory according to the starting memory address of the received data in the decoding control descriptor, and the decoding information is written back to the decoding control descriptor. Figure 8 As shown, the decoding information includes decoding status, destination station number, source station number, data frame reception time, and DMA-processed flag.

[0106] To enable those skilled in the art to better understand this solution, the execution process of this case is illustrated below with an example:

[0107] Taking master station 0 as an example, the control data packets use RS(19,31) encoding, and the ordinary data packets use RS(15,31) encoding. Master station 0 has data to send, including a 760-bit control data packet and a 2925-bit ordinary data packet to slave station 1, and a 1140-bit control data packet and a 3150-bit ordinary data packet to slave station 2. The bus width is 128 bits.

[0108] Prepare two descriptors in encoding channel 1 to describe data frames sent to slave station 1 and slave station 2 respectively. Set the frame length of the first descriptor to 760, the source station number to 0, and the destination station number to 1. Enable the transmit completion interrupt, set the descriptor flag to indicate that it has not been processed by DMA, and set the width of the first and second interleaving blocks to 31 and the depth to 4. Set the frame length of the second descriptor to 1140, the source station number to 0, and the destination station number to 2. Enable the transmit completion interrupt, set the descriptor flag to indicate that it has not been processed by DMA, and set the width of the first and second interleaving blocks to 31 and the depth to 6.

[0109] In encoding channel 2, two descriptors are prepared to describe the data frames sent to slave station 1 and slave station 2 respectively. The frame length of the first descriptor is set to 2925, the source station number is 0, and the destination station number is 1. A transmit completion interrupt is enabled, and the descriptor flag is set to indicate that it has not been processed by DMA. The width of interleaving blocks 1-3 is 31, and the depth is 10; the width of interleaving block 4 is 31, and the depth is 9. The frame length of the second descriptor is set to 3150, the source station number is 0, and the destination station number is 2. A transmit completion interrupt is enabled, and the descriptor flag is set to indicate that it has not been processed by DMA. The width of interleaving blocks 1-4 is 31, and the depth is 8; the width of interleaving block 5 is 31, and the depth is 10. Similarly, the starting address of each group of data to be encoded is filled into the corresponding descriptor.

[0110] Taking the descriptor sent from encoding channel 2 to station 2 as an example. After the descriptor content is configured, configure the control register, set the channel weight, specifically encoding channel 1: encoding channel = 4:1, read: write weight = 2:1, single burst length register (2 times), write the descriptor start address to the control register, finally configure the channel start register, start DMA encoding channel 2, and DMA starts working.

[0111] Figure 9 This is a timing diagram of the encoding and interleaving process provided in an embodiment of the present invention. Figure 9As shown, firstly, DMA requests from different channels are arbitrated according to the arbitration weight. After the DMA arbitrator allocates the burst length to encoding channel 2, the DMA reads an encoding control descriptor of encoding channel 2 according to the configured descriptor start address, parses the descriptor, and determines the parameters for each interleaving and whether to trigger an encoding completion interrupt. Then, according to the burst length allocated within the arbitration cycle, the data is moved to the bit-width conversion circuit, converting the 128-bit bus data into 5-bit width data, and written to the encoder. Timing control uses a ready signal reverse pressure method. When the encoder is encoding, the encoder pulls the ready signal low, controlling the bit-width conversion unit to prevent new data from being input to the encoder. The bit-width converted data is first written to the buffer, and new data is controlled to be input after encoding is completed. The encoded data consists of 39 segments with a bit width of 5 bits and a length of 31. According to the instructions of the encoding control descriptor, the interleaver controls the interleaving depth and width sequentially. First, it interleaves 3 times with an interleaving width of 31 and a depth of 10, then it interleaves once with an interleaving width of 31 and a depth of 9, thus completing the interleaving of all data. The encoded data length is 31 × 5 × 39 = 6045 bits. Each valid data segment is directly input into the interleaver using a valid signal. A ping-pong processing method is used between two interleavers: when interleaver 0 is outputting interleave data, the new encoded data is input into interleaver 1; when interleaver 1 is outputting interleave data, the new encoded data is input into interleaver 0. This maximizes the interleave output speed. The data output from the interleaver is then sent after adding the destination and source stations to the header.

[0112] Figure 10 This is a timing diagram of the deinterleaving and decoding process provided in an embodiment of the present invention. Figure 10 As shown, for the decoding direction, DMA also first acquires the decoding control descriptor. First, based on the source station information, it saves the initial interleaving scheme information through the configuration registers. After receiving the data packet, it first acquires the source station number, and then the deinterleaver performs deinterleaving according to the preset deinterleaving scheme. During deinterleaving output, after outputting enough data for one decoding operation, it pauses output to allow sufficient time for decoding. The deinterleaver resumes output only after the decoder has completed decoding. After decoding, DMA writes the decoded data to memory according to the address specified by the descriptor, and writes the decoding status (indicating whether there are uncorrectable errors in the decoded data), destination station number, source station number, and reception time information back to the decoding descriptor. It also sets the current descriptor occupancy flag to 1, indicating that the current descriptor has been processed by DMA. The written-back descriptor information is used by the software.

[0113] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0114] Figure 11 This is a schematic diagram of a multi-channel encoding interleaving device provided in an embodiment of the present invention. The device is applied to a multi-channel encoding interleaving circuit; the multi-channel encoding interleaving circuit includes at least multiple encoding channels and multiple decoding channels; each encoding channel contains multiple encoding interleaving sub-modules; each decoding channel contains multiple decoding interleaving sub-modules; as shown... Figure 11 As shown, the device includes:

[0115] The acquisition module 10 is used to acquire data to be encoded or data to be decoded, and to determine the priority of the data to be encoded or the priority of the data to be decoded.

[0116] The first determining module 11 is used to determine the target encoding channel in each encoding channel or the target decoding channel in each decoding channel according to the priority of the data to be encoded or the priority of the data to be decoded.

[0117] The second determining module 12 is used to obtain and parse the encoding control descriptor corresponding to the target encoding channel in order to determine the configuration parameters of each target encoding interleaving submodule, or to obtain and parse the decoding control descriptor corresponding to the target decoding channel in order to determine the configuration parameters of each target decoding interleaving submodule.

[0118] The encoding / decoding module 13 is used to input the data to be encoded into the target encoding channel and control each target encoding interleaving submodule to encode the data to be encoded according to the corresponding configuration parameters, or to input the data to be decoded into the target decoding channel and control each target decoding interleaving submodule to decode the data to be decoded according to the corresponding configuration parameters.

[0119] In some embodiments, the multi-channel encoding interleaving circuit further includes a direct memory access channel arbitration unit; the direct memory access channel arbitration unit is communicatively connected to memory; the direct memory access channel arbitration unit is communicatively connected to each encoding channel and each decoding channel; the encoding interleaving submodule includes a direct memory access control unit, a bit width conversion unit, an encoding timing control unit, an encoding unit, an interleaving unit, a transmission queue, and a transmission control unit that are communicatively connected in sequence; the decoding interleaving submodule includes a direct memory access control unit, a bit width conversion unit, a decoding unit, a decoding timing control unit, a deinterleaving unit, a reception queue, and a reception control unit that are communicatively connected in sequence.

[0120] In some embodiments, the acquisition module 10 includes:

[0121] The first determining submodule is used to determine the data packet type of the data to be encoded; wherein the data packet type includes at least control data packets, normal data packets, and emergency data packets;

[0122] The second determining submodule is used to determine the priority of the data to be encoded based on the data packet type; wherein, the priority of urgent data packets is higher than that of control data packets, and the priority of control data packets is higher than that of ordinary data packets.

[0123] The third determination submodule is used to determine the source station number to which the data to be decoded belongs, and to determine the priority weight of the source station number; among them, priority weights are pre-set for multiple stations that support the output of the data to be decoded, and the priority weights of each station are different;

[0124] The fourth determination submodule is used to determine the priority of the data to be decoded based on the priority weight of the source site number.

[0125] In some embodiments, the first determining module 11 includes:

[0126] The first acquisition submodule is used to acquire the number of burst transmissions corresponding to each pre-configured encoding channel;

[0127] The fifth determination submodule is used to determine the target encoding channel among the encoding channels based on the priority of the data to be encoded and the number of burst transmissions corresponding to each encoding channel;

[0128] The second acquisition submodule is used to acquire the decoding channel specified by the source station number to which the data to be decoded belongs;

[0129] The sixth determination submodule is used to determine the target decoding channel among the various decoding channels based on the priority of the data to be decoded and the specified decoding channel.

[0130] In some embodiments, the second determining module 12 includes:

[0131] The seventh determination submodule is used to determine the starting address of the encoding control descriptor based on the configuration bit information of the direct memory access control register;

[0132] The first reading submodule is used to read the encoding control descriptor according to the starting address of the encoding control descriptor;

[0133] The encoding control descriptor includes at least the source station number, destination station number, interleaving depth and width of different interleaving blocks in the current frame, data frame length, frame start address information, whether the interrupt flag is enabled, and whether the current descriptor has been processed by direct memory access.

[0134] The eighth determination submodule is used to determine the starting address of the decoding control descriptor based on the configuration bit information of the direct memory access control register;

[0135] The second reading submodule is used to read the decoding control descriptor according to the starting address of the decoding control descriptor;

[0136] The decoding control descriptor includes at least the starting memory address for receiving data, whether the interrupt flag is enabled, and whether the current descriptor has been processed by direct memory access.

[0137] In some embodiments, the encoding / decoding module 13 includes:

[0138] The encoding submodule is used to control each target encoding interleaving submodule to encode the data to be encoded based on the source station number, destination station number, interleaving depth and width of different interleaving blocks in the current frame, data frame length, frame start address information, whether the interrupt flag is enabled, and whether the current descriptor has been processed by direct memory access in the encoding control descriptor.

[0139] The interleaving parameter acquisition module is used to obtain the interleaving parameters output by the source station number to which the data to be decoded belongs;

[0140] The decoding submodule is used to control each target decoding interleaving submodule to decode the data to be decoded based on the interleaving parameters output by the source station number to which the data to be decoded belongs, as well as the starting memory address of the received data, whether the interrupt flag is enabled, and whether the current descriptor has been directly accessed and processed flags in the decoding control descriptor.

[0141] In some embodiments, it also includes:

[0142] The first sending submodule is used to send the encoded data to the destination station and write the sending status information back to the original address of the encoding control descriptor;

[0143] The second sending submodule is used to transmit the decoded data to memory according to the starting memory address of the received data in the decoding control descriptor, and write the decoded information back to the decoding control descriptor.

[0144] For a description of the features in the embodiments corresponding to the multi-channel coding interleaving apparatus, please refer to the relevant descriptions in the embodiments corresponding to the multi-channel coding interleaving method, which will not be repeated here.

[0145] Embodiments of the present invention also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above embodiments of the multichannel code interleaving method.

[0146] Embodiments of the present invention also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described multichannel coding interleaving method embodiments when running.

[0147] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0148] Embodiments of the present invention also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above embodiments of the multichannel coding interleaving method.

[0149] Embodiments of the present invention also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described multichannel code interleaving method embodiments.

[0150] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0151] The foregoing has provided a detailed description of a multi-channel coding interleaving method, apparatus, device, and medium provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. A multi-channel coding interleaving method, characterized in that, Applied to a multi-channel coding interleaving circuit; the multi-channel coding interleaving circuit includes at least multiple coding channels and multiple decoding channels; The encoding channel contains multiple encoding interleaving sub-modules; The decoding channel includes multiple decoding interleaving sub-modules; the method includes: Acquire the data to be encoded or the data to be decoded, and determine the priority of the data to be encoded or the priority of the data to be decoded; Based on the priority of the data to be encoded or the priority of the data to be decoded, a target encoding channel is determined in each of the encoding channels, or a target decoding channel is determined in each of the decoding channels; Obtain and parse the encoding control descriptor corresponding to the target encoding channel to determine the configuration parameters of each target encoding interleaving submodule, or obtain and parse the decoding control descriptor corresponding to the target decoding channel to determine the configuration parameters of each target decoding interleaving submodule; The data to be encoded is input to the target encoding channel, and each target encoding interleaving submodule is controlled to encode the data according to the corresponding configuration parameters; or the data to be decoded is input to the target decoding channel, and each target decoding interleaving submodule is controlled to decode the data according to the corresponding configuration parameters.

2. The multi-channel coding interleaving method according to claim 1, characterized in that, The multi-channel encoding interleaving circuit further includes a direct memory access channel arbitration unit; the direct memory access channel arbitration unit is communicatively connected to memory; the direct memory access channel arbitration unit is communicatively connected to each of the encoding channels and each of the decoding channels; The encoding interleaving submodule includes a direct memory access control unit, a bit width conversion unit, an encoding timing control unit, an encoding unit, an interleaving unit, a transmission queue, and a transmission control unit, which are connected in sequence via communication. The decoding interleaving submodule includes a direct memory access control unit, a bit width conversion unit, a decoding unit, a decoding timing control unit, a deinterleaving unit, a receive queue, and a receive control unit, which are connected in sequence.

3. The multi-channel coding interleaving method according to claim 1, characterized in that, Determining the priority of the data to be encoded includes: Determine the data packet type of the data to be encoded; wherein the data packet type includes at least control data packets, normal data packets, and emergency data packets; The priority of the data to be encoded is determined according to the data packet type; wherein, the priority of the emergency data packet is higher than the priority of the control data packet, and the priority of the control data packet is higher than the priority of the normal data packet; Correspondingly, determining the priority of the data to be decoded includes: The source station number to which the data to be decoded belongs is determined, and the priority weight of the source station number is determined; wherein, priority weights are pre-set for multiple stations that support the output of the data to be decoded, and the priority weights of each station are different; The priority of the data to be decoded is determined based on the priority weight of the source site number.

4. The multi-channel coding interleaving method according to claim 1, characterized in that, Based on the priority of the data to be encoded, a target encoding channel is determined from each of the encoding channels, including: Obtain the number of burst transmissions corresponding to each of the pre-configured encoding channels; The target encoding channel is determined from among the encoding channels based on the priority of the data to be encoded and the number of burst transmissions corresponding to each encoding channel; Correspondingly, based on the priority of the data to be decoded, a target decoding channel is determined among each of the decoding channels, including: Obtain the decoding channel specified by the source site number to which the data to be decoded belongs; The target decoding channel is determined among the decoding channels according to the priority of the data to be decoded and the specified decoding channel.

5. The multi-channel coding interleaving method according to claim 1, characterized in that, Obtaining the encoding control descriptor includes: The starting address of the encoding control descriptor is determined based on the configuration bit information of the direct memory access control register; The encoding control descriptor is read according to its starting address; The encoding control descriptor includes at least the source station number, destination station number, interleaving depth and width of different interleaving blocks in the current frame, data frame length, frame start address information, whether the interrupt flag is enabled, and whether the current descriptor has been processed by direct memory access. Correspondingly, obtaining the decoding control descriptor includes: The starting address of the decoding control descriptor is determined based on the configuration bit information of the direct memory access control register; The decoding control descriptor is read according to its starting address; The decoding control descriptor includes at least the starting memory address for receiving data, an interrupt flag, and a flag indicating whether the current descriptor has been processed by direct memory access.

6. The multi-channel coding interleaving method according to claim 5, characterized in that, According to the corresponding configuration parameters, each target encoding interleaving submodule is controlled to encode the data to be encoded, including: Based on the source station number, destination station number, interleaving depth and width of different interleaving blocks in the current frame, data frame length, frame start address information, whether the interrupt flag is enabled, and whether the current descriptor has been processed by direct memory access in the encoding control descriptor, each of the target encoding interleaving submodules is controlled to encode the data to be encoded. Correspondingly, each of the target decoding interleaving submodules is controlled to decode the data to be decoded according to the corresponding configuration parameters, including: Obtain the interleaving parameters output by the source station number to which the data to be decoded belongs; Based on the interleaving parameters output by the source station number to which the data to be decoded belongs, and the starting memory address of the received data, whether the interrupt flag is enabled, and whether the current descriptor has been directly accessed and processed flag in the decoding control descriptor, the target decoding interleaving submodules are controlled to decode the data to be decoded.

7. The multi-channel coding interleaving method according to claim 5, characterized in that, After controlling each target encoding interleaving submodule to encode the data to be encoded according to the corresponding configuration parameters, the method further includes: The encoded data is sent to the destination station, and the sending status information is written back to the original address of the encoding control descriptor; Correspondingly, after controlling each target decoding interleaving submodule to decode the data to be decoded according to the corresponding configuration parameters, the method further includes: Based on the starting memory address of the received data in the decoding control descriptor, the decoded data is transmitted to memory, and the decoded information is written back to the decoding control descriptor.

8. A multi-channel coding interleaving device, characterized in that, Applied to a multi-channel coding interleaving circuit; the multi-channel coding interleaving circuit includes at least multiple coding channels and multiple decoding channels; The encoding channel contains multiple encoding interleaving sub-modules; The decoding channel includes multiple decoding interleaving sub-modules; the device includes: An acquisition module is used to acquire data to be encoded or data to be decoded, and to determine the priority of the data to be encoded or the priority of the data to be decoded. The first determining module is used to determine a target encoding channel in each encoding channel or a target decoding channel in each decoding channel according to the priority of the data to be encoded or the priority of the data to be decoded. The second determining module is used to obtain and parse the encoding control descriptor corresponding to the target encoding channel to determine the configuration parameters of each target encoding interleaving submodule, or to obtain and parse the decoding control descriptor corresponding to the target decoding channel to determine the configuration parameters of each target decoding interleaving submodule. The encoding / decoding module is used to input the data to be encoded into the target encoding channel and control each of the target encoding interleaving submodules to encode the data to be encoded according to the corresponding configuration parameters, or to input the data to be decoded into the target decoding channel and control each of the target decoding interleaving submodules to decode the data to be decoded according to the corresponding configuration parameters.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the multichannel coded interleaving method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the multichannel coded interleaving method as described in any one of claims 1 to 7.

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