Circuit board circuit deposition method and circuit board circuit
By forming patterned ink on a copper-free substrate and catalytically depositing a thick copper layer, the circuit board manufacturing process is simplified, solving the problem of difficult cost reduction in existing technologies and achieving higher first-pass yield and lower production costs.
Patent Information
- Application Number
- CN202511113903.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-08
- Publication Date
- 2025-10-31
AI Technical Summary
Existing circuit board deposition processes are unlikely to further reduce manufacturing costs while meeting product quality requirements, especially as equipment and material demands have stabilized in the development of LED technology, resulting in limited profit margins.
Using a substrate without copper foil on its surface, a thick copper layer is directly deposited by forming patterned ink on the substrate surface and performing chemical copper deposition under catalysis, eliminating processes such as copper plating, grinding, pressing dry film, exposure and etching, thus optimizing the production process.
Simplify production processes, reduce equipment and copper material requirements, increase first-pass yield, significantly reduce manufacturing costs, and enhance product competitiveness.
Smart Images
Figure CN120881884A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of circuit board manufacturing technology, and in particular to a circuit board line deposition method and circuit board lines. Background Technology
[0002] Existing circuit board deposition processes mainly include: pretreatment of the substrate containing a double layer of copper foil, followed by copper plating, electroplating, grinding, dry film pressing, exposure, development, and etching to complete the circuit fabrication. Finally, post-processing is performed on the substrate. With the continuous development of LED (Light Emitting Diode) technology, existing processes have reached a bottleneck and cannot further reduce manufacturing costs. Therefore, how to reduce manufacturing costs while meeting product quality requirements is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention
[0003] The purpose of this application is to provide a circuit board line deposition method and circuit board lines. For substrates without copper foil on the surface, by combining line deposition process and thick copper deposition process, thick copper is directly deposited on the surface of the substrate without copper foil. This process is simpler, requires less production equipment, has a higher first-pass yield, less copper material loss, and is more cost-effective. As a result, the cost can be further reduced. Under the premise of meeting product quality, the development of new processes has greatly reduced the manufacturing cost.
[0004] To achieve the above objectives, this application provides a circuit board line deposition method, comprising:
[0005] A pretreatment is performed on a substrate whose surface does not contain copper foil to form through holes in the substrate;
[0006] A patterned ink is formed on the surface of the substrate after pretreatment;
[0007] The patterned substrate is placed in a chemical copper plating bath containing copper salt and reducing agent. Under catalysis, copper ions are reduced and deposited, adhering to the walls of the vias and the substrate surface not covered by the ink, to obtain a copper layer with the target thickness, thus completing the circuit layer fabrication. The thickness of the ink is greater than or equal to the thickness of the copper layer.
[0008] Optionally, the pretreatment of the substrate without copper foil on its surface to form through holes in the substrate includes:
[0009] The substrate without the copper foil on its surface is cut to obtain the substrate with the target size;
[0010] Drilling is performed on the substrate after the blanking process to form the through holes in the substrate;
[0011] The formed through-hole is inspected.
[0012] Optionally, forming patterned ink on the surface of the substrate after pretreatment includes:
[0013] A patterned nonpolar ink is formed on the surface of the substrate after pretreatment.
[0014] Optionally, forming patterned ink on the surface of the substrate after pretreatment includes:
[0015] A patterned polar ink is formed on the surface of the substrate after pretreatment;
[0016] Accordingly, after placing the patterned substrate into a chemical copper plating bath containing copper salt and a reducing agent, and under catalysis, reducing and depositing copper ions onto the walls of the vias and the substrate surface not covered by the ink to obtain a copper layer of the target thickness, the process further includes:
[0017] The ink and the copper layer adhering to the surface of the ink are removed by stripping.
[0018] Optionally, forming patterned ink on the surface of the substrate after pretreatment includes:
[0019] The patterned ink is applied to the pretreated substrate surface by screen printing or mold transfer; the ink contains a self-volatile diluent.
[0020] Allow the ink to self-level for a preset time after the transfer is completed;
[0021] The ink that has achieved self-leveling is then UV cured.
[0022] Optionally, the thickness of the copper layer is 15μm-20μm, including the values at both ends; the difference between the thickness of the ink and the thickness of the copper layer is greater than 5μm;
[0023] And / or, the ink is matte black.
[0024] Optionally, the step of placing the patterned substrate into a chemical copper plating bath containing copper salt and a reducing agent, and under catalysis, reducing and depositing copper ions onto the walls of the vias and the substrate surface not covered by the ink, to obtain a copper layer of the target thickness, thus completing the circuit layer fabrication, includes:
[0025] The patterned substrate is pre-impregnated;
[0026] The pre-impregnated substrate is activated to allow colloidal palladium to adhere to the walls of the through holes and the surface of the substrate not covered by the ink.
[0027] The colloidal palladium is accelerated to remove the colloidal portion of the outer layer of the colloidal palladium, exposing the palladium core;
[0028] The accelerated substrate is placed in the chemical copper plating bath containing the copper salt and the reducing agent. Under the action of the palladium nucleus, the copper ions are reduced and deposited, adhering to the hole walls of the vias and the substrate surface not covered by the ink, to obtain the copper layer with the target thickness, thus completing the fabrication of the circuit layer.
[0029] Optionally, the step of placing the patterned substrate into a chemical copper plating bath containing copper salt and a reducing agent, and under catalysis, reducing and depositing copper ions onto the walls of the vias and the substrate surface not covered by the ink, to obtain a copper layer of the target thickness, further includes the following after completing the circuit layer fabrication:
[0030] The substrate after the circuit layer fabrication is completed undergoes post-processing.
[0031] Optionally, the chemical copper plating tank includes a main tank and a secondary tank;
[0032] Accordingly, the patterned substrate is placed in a chemical copper plating bath containing copper salt and a reducing agent, and under catalysis, copper ions are reduced and deposited, adhering to the walls of the vias and the substrate surface not covered by the ink, to obtain a copper layer of the target thickness, thus completing the circuit layer fabrication, including:
[0033] Step 1: The patterned substrate is placed in the main tank containing the copper salt and the reducing agent, and under catalysis, the copper ions are reduced and precipitated, adhering to the hole walls of the through holes and the substrate surface not covered by the ink, and the reacted solution is obtained; copper powder is continuously added to the main tank throughout the deposition process.
[0034] Step 2: The solution after the catalytic reduction reaction is introduced into the auxiliary tank. Complexing ions are added to the auxiliary tank to form complex precipitates of substances that affect the catalytic reduction reaction. The solution is then filtered to obtain the filtered solution.
[0035] Step 3: After the filtered solution is introduced into the main tank, repeat steps 1 and 2 above until the copper layer with the target thickness is obtained, thus completing the fabrication of the circuit layer.
[0036] To achieve the above objectives, this application also provides a circuit board circuit, comprising: a circuit board circuit prepared by the circuit board circuit deposition method described above.
[0037] Clearly, the circuit board deposition method provided in this application breaks through the constraints of existing methods. It pre-treats a substrate without copper foil, forming patterned ink on the substrate surface. This ink is used to transfer patterns from non-circuit areas, completing the first step of pre-laying the circuit. Then, copper is deposited in the un-inked circuit areas and the walls of vias via a catalytic reduction reaction, forming thick copper and completing the circuit fabrication. Compared to existing circuit board deposition processes, this method eliminates the electroplating copper process, the grinding process, and the masking processes such as film drying, exposure, development, and etching. This significantly optimizes the process, greatly reducing the demand for equipment and copper materials, improving the first-pass yield (i.e., improving product quality), reducing manufacturing costs, completing a process transformation, and enhancing the product's core cost competitiveness. This application also provides a circuit board circuit with the aforementioned beneficial effects. Attached Figure Description
[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0039] Figure 1 A flowchart illustrating a circuit board deposition method provided in this application embodiment;
[0040] Figure 2 This is a schematic flowchart of a circuit board line deposition method provided in an embodiment of this application.
[0041] The annotations in the attached figures are explained as follows:
[0042] 1-FR4 core board (without copper foil on the surface); 2-through hole; 3-non-polar ink; 4-circuit layer; 5-PCB board. Detailed Implementation
[0043] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0044] Existing circuit board deposition processes are mainly for FR4 (epoxy fiberglass board) core boards with double-layer copper foil on the surface. The specific process flow includes: pretreatment (including: material cutting, drilling, hole inspection, and board grinding), copper plating, copper electroplating, circuit fabrication, and post-treatment.
[0045] The copper plating process mainly includes five steps: degreasing, micro-etching, acid treatment, catalysis, and copper plating. The specific principles are as follows:
[0046] Degreasing: Use alkaline cleaning agents to remove organic contaminants such as dust, fingerprints, and oil residue left on the surface of the FR4 core board (including the double-layer copper foil) during the drilling process to form through holes, ensuring that the surface of the FR4 core board (including the double-layer copper foil) is clean and creating good conditions for subsequent copper plating.
[0047] Micro-etching: The copper foil surface of the FR4 core board (including double-layer copper foil on the surface) is etched at the micron level using a solution such as sodium persulfate to form a uniform honeycomb rough surface, which enhances the adhesion of the plating layer;
[0048] Pickling: The oxide layer on the surface of copper foil is removed by dilute sulfuric acid solution, which at the same time activates the microstructure of the copper foil surface and provides catalytic sites for the electroplating reaction;
[0049] Catalysis: The catalyst is attached to the pore walls of the through holes and the non-copper foil surface that needs to conduct electricity;
[0050] Plating copper: Plating copper is performed on FR4 core boards (containing double-layer copper foil on the surface) that have undergone catalytic treatment. Specifically, a thin copper layer is formed on the wall of the through holes and on the non-copper foil surface that needs to conduct electricity. The thickness is generally 0.25μm-2.5μm.
[0051] Copper electroplating: This mainly aims to thicken the copper to meet current-carrying requirements, requiring a specialized electroplating line. Full-board copper electroplating: After chemical copper plating, which has already established conductive properties, electroplating is used to increase the copper thickness of the hole walls, typically to a certain thickness of 18μm. Simultaneously, a base copper layer is deposited on the FR4 core board (including the surface double-layer copper foil) to form a preliminary conductive network. Electroplating uses a copper sulfate / sulfuric acid electrolyte system. Under a DC electric field, copper ions are reduced to metallic copper at the cathode. Process parameters need precise control; the current density is typically set at 1A / dm³. 2 -3A / dm 2 At the same time, organic additives such as brighteners and leveling agents are added to optimize the crystal structure.
[0052] Circuit board fabrication mainly includes: pre-processing grinding, lamination, exposure, development, and etching. Required equipment includes: a horizontal pre-processing line, laminator, dry film press, exposure machine, developing line, and etching line. Working principle: A layer of photosensitive dry film is laminated onto the surface of an FR4 core board (including a double-layer copper foil). The image is transferred by the exposure machine, and the developing line removes the dry film from the exposed areas, leaving a layer of dry film that protects the copper layer on the FR4 core board (including the double-layer copper foil). The unprotected copper layer is then removed by the etching solution, thus fabricating the circuit.
[0053] The continuous advancement of LED technology has significantly improved the production efficiency of manufacturing equipment, while improvements in production processes have also reduced production costs. However, existing manufacturing processes have limited room for further cost reduction, and the demand for materials and equipment has stabilized. Compared to market costs, profit margins are low. Considering the industry trend towards large-pitch LEDs (0.15mm linewidth / pitch), overall demand is increasing, but current processes have reached a bottleneck, resulting in extremely low profit margins and a significant gap with the development of existing factories. Therefore, it is necessary to develop new technical solutions to reduce manufacturing costs and create a product advantage while meeting product quality requirements (i.e., ensuring a high yield rate).
[0054] Therefore, this application provides a circuit board line deposition method for substrates without copper foil on the surface. By combining line deposition process and thick copper deposition process, thick copper is directly deposited on the surface of the substrate without copper foil. This process is simpler, requires less production equipment, has a higher first-pass yield, less copper material loss, and is more cost-effective. As a result, the cost can be further reduced. Under the premise of meeting product quality requirements, the development of new processes has greatly reduced manufacturing costs.
[0055] Please refer to Figure 1 , Figure 1 A flowchart of a circuit board line deposition method provided in this application embodiment, the method may include:
[0056] S101: Pre-treat a substrate without copper foil on its surface to form through holes in the substrate.
[0057] This embodiment does not limit the specific type of substrate used; it can be any substrate without copper foil on its surface, such as an FR4 core board without copper foil on its surface.
[0058] This embodiment does not limit the specific method of pre-processing the substrate, as long as it ensures that through-holes can be formed in the substrate. For example, the following methods can be used:
[0059] The substrate without copper foil on its surface is cut to obtain a substrate with the target size;
[0060] Drill holes in the substrate after it has been cut to form through holes.
[0061] Inspect the formed through holes.
[0062] This includes, but is not limited to, using a drill bit to drill holes in the substrate after it has been cut.
[0063] It should be noted that, compared with existing circuit board deposition processes, this embodiment eliminates the post-drilling grinding step. Since this embodiment uses a substrate without copper foil on its surface, only a single material needs to be drilled, eliminating issues such as copper foil stringing, thus the post-drilling grinding step can be omitted.
[0064] S102: A patterned ink is formed on the surface of the pretreated substrate.
[0065] This embodiment does not limit the specific method of forming patterned ink, as long as it ensures that circuit patterns can be formed on the substrate surface by ink. For example, the following methods can be used:
[0066] The patterned ink is applied to the pretreated substrate surface by screen printing or mold transfer; the ink contains a self-volatile diluent.
[0067] Allow the transferred ink to self-level for a preset time;
[0068] The self-leveling ink is then UV (Ultraviolet) cured.
[0069] It should be noted that in this embodiment, screen printing or mold transfer can ensure that the patterned ink only covers the non-circuit areas on the substrate surface; while the uncovered areas correspond to the circuit areas on the substrate surface.
[0070] It should be noted that in this embodiment, self-leveling can eliminate microscopic edge jaggedness, and the self-volatile diluent can simultaneously increase the viscosity and hardness of the ink, allowing the ink to transition from a non-Newtonian state to a semi-cured state. UV curing then completes the curing process, achieving a hardness of up to 6H. This ink possesses sufficient strength characteristics while maintaining a certain level of hardness.
[0071] This embodiment does not limit the specific time of self-adjustment, which can be determined according to the actual situation. For example, the preset time can be 3min-5min, including the values at both ends.
[0072] This embodiment does not limit the specific type of ink. For example, the ink can be a non-polar ink; or, the ink can be a polar ink (i.e., a conventional ink).
[0073] In this embodiment, the ink thickness needs to be greater than or equal to the thickness of the copper layer to be deposited, so as to ensure that thick copper is deposited only in the circuit area defined by the ink. This embodiment does not limit the specific thickness of the ink, and it can be determined according to the actual thickness of the copper layer to be deposited. For example, the thickness of the copper layer can be 15μm-20μm, including the values at both ends; the difference between the ink thickness and the copper layer thickness can be greater than 5μm.
[0074] This embodiment does not limit the specific color of the ink; any color can be used, such as matte black. It should be noted that the ink color used in this embodiment is consistent with the solder resist screen printing ink color during post-processing, resulting in better consistency of the solder resist screen printing ink color and comprehensively improving the ink color consistency requirements of the display screen.
[0075] S103: The patterned substrate is placed in a chemical copper plating bath containing copper salt and reducing agent. Under catalysis, copper ions are reduced and deposited onto the walls of the vias and the substrate surface not covered by ink, resulting in a copper layer with the target thickness, thus completing the circuit layer fabrication. The thickness of the ink is greater than or equal to the thickness of the copper layer.
[0076] It should be noted that after step S103 is completed in this embodiment, the substrate with the circuit layer obtained is the PCB (Printed Circuit Board).
[0077] It should be noted that when the ink used in this embodiment is a non-polar ink, a patterned non-polar ink is formed on the surface of the substrate after pretreatment. In fact, non-polarization treatment is performed simultaneously with the patterning treatment of the substrate surface. Due to the inherent characteristics of non-polar ink, its surface free energy is low and it cannot be catalyzed. This prevents catalysts (such as palladium nuclei) from adsorbing on the surface of the non-polar ink, thus preventing copper ions from depositing on the surface of the non-polar ink. Consequently, the deposited copper can only adhere to the areas not covered by the non-polar ink, completing the selective deposition of the circuit.
[0078] It should be noted that when the ink used in this embodiment is a polar ink, although it is impossible to achieve non-polarity, the polar ink can still be removed after thick copper deposition by stripping, simultaneously carrying the copper layer deposited on the surface of the polar ink. That is, in this embodiment, after the patterned substrate is placed in a chemical copper plating bath containing copper salts and reducing agents, and under catalysis, copper ions are reduced and precipitated, adhering to the walls of the vias and the substrate surface not covered by ink, the following can be included:
[0079] The ink and the copper layer adhering to the ink surface are removed by stripping.
[0080] Furthermore, in this embodiment, the substrate after copper layer deposition can be placed in an organic stripping solution to remove the ink and the copper layer adhering to the ink surface.
[0081] It should be noted that, regardless of whether non-polar or polar ink is used, circuits can be formed in this embodiment, and there is no need to perform processes such as electroplating, grinding, pressing dry film, exposure, development, and etching.
[0082] In this embodiment, copper deposition is performed under catalysis, which requires pre-catalytic treatment. Therefore, step S103 in this embodiment may include:
[0083] Pre-impregnate the patterned substrate;
[0084] The pre-impregnated substrate is activated to allow colloidal palladium to adhere to the walls of the vias and the substrate surface not covered by ink.
[0085] The colloidal palladium is accelerated to remove the colloidal portion of the outer layer of the palladium, exposing the palladium core;
[0086] The accelerated substrate is placed in a chemical copper plating bath containing copper salt and reducing agent. Under the action of palladium nuclei, copper ions are reduced and deposited, adhering to the hole walls of the vias and the substrate surface not covered by ink, to obtain a copper layer with the target thickness, thus completing the fabrication of the circuit layer.
[0087] It should be noted that in this embodiment, the substrate is pre-impregnated first, which can prevent impurities from previous processes from being carried into the subsequent catalyst tank. At the same time, it can wet the walls of the through holes in the substrate and the substrate surface not covered by ink, thereby promoting the adsorption of catalyst by the substrate.
[0088] It should be noted that, in this embodiment, the pre-impregnated substrate is typically placed in a catalyst tank (such as a palladium tank) for activation.
[0089] In this embodiment, colloidal palladium is used as a catalyst. This embodiment does not limit the specific type of colloidal palladium. For example, colloidal palladium can be Pd / Sn colloidal palladium or Pd / Cu colloidal palladium. Among them, Pd / Sn colloidal palladium refers to stable colloidal particles formed by Pd (palladium) being surrounded by Sn (tin); Pd / Cu colloidal palladium refers to stable colloidal particles formed by Pd being surrounded by Cu (copper).
[0090] It should be noted that the substrate activation in this embodiment provides catalytic activation centers for subsequent copper plating. It should also be noted that the acceleration process in this embodiment, also known as desizing, is a process for removing colloids.
[0091] Furthermore, in order to increase the thickness of the deposited copper layer, the chemical copper plating tank in this embodiment may include a main tank and a secondary tank;
[0092] Accordingly, step S103 may include:
[0093] Step 1: The patterned substrate is placed in the main tank containing copper salt and reducing agent. Under the action of catalysis, copper ions are reduced and precipitated, adhering to the hole walls of the through holes and the substrate surface not covered by ink, and the reaction solution is obtained. Copper powder is continuously added to the main tank throughout the deposition process.
[0094] Step 2: The solution after the catalytic reduction reaction is introduced into the auxiliary tank. Complexing ions are added to the auxiliary tank to form complex precipitates of substances that affect the catalytic reduction reaction. The solution is then filtered to obtain the filtered solution.
[0095] Step 3: After the filtered solution is poured into the main tank, repeat steps 1 and 2 above until a copper layer with the target thickness is obtained, thus completing the circuit layer fabrication.
[0096] It should be noted that the catalytic reduction reaction in this embodiment is a reversible reaction. By continuously adding copper powder and a graded main and auxiliary tank, the chemical solution from the main tank after the catalytic reduction reaction is introduced into the auxiliary tank. Complexing ions are added to form complex precipitates of substances that affect the catalytic reduction reaction (such as sulfate ions or formaldehyde groups), and then filtered. This allows the forward reaction to proceed as a whole, thereby achieving the purpose of depositing thick copper.
[0097] Furthermore, to improve product quality, this embodiment may further include the following after step S103:
[0098] Post-processing is performed on the substrate after the circuit layer fabrication is completed.
[0099] This embodiment does not limit the specific method of post-processing, which can be determined according to the actual situation. For example, post-processing may include:
[0100] Outer layer AOI / line repair: AOI (Automatic Optical Inspection) is used to scan the line layer and compare it with design data to highlight abnormal points in the line layer; these abnormal points are then repaired.
[0101] Ultra-roughening / screen printing / pre-baking / exposure / development: Increase the surface roughness of the circuit layer by screen printing, coating the circuit layer with ink; pre-curing the ink by baking; forming a solder resist ink layer by exposure and development, exposing the solder pad area;
[0102] Visual inspection: Visually inspect the surface solder resist ink layer. If any abnormality is detected, perform oil touch-up (i.e., add ink) or rework (i.e., return to the previous step).
[0103] Character printing / baking: Printing character ink onto the solder resist ink layer and then baking the plate for curing;
[0104] CNC Milling Outline / Dimension Measurement: The PCB board after baking and curing is machined using a CNC (Computer Numerical Control) milling machine and milling cutter, and the dimensions required by the drawings are measured and monitored.
[0105] Electrical Testing / FQC: Perform electrical testing and FQC (Final Quality Control) on the PCB board after the shape processing is completed; electrical testing includes functional testing, and FQC includes visual inspection;
[0106] OSP: OSP (Organic Solderability Preservative) surface treatment process is applied to PCB boards after inspection to prevent pad oxidation.
[0107] Packaging: Pack the PCB boards after OSP surface treatment.
[0108] This application may be applied to, but is not limited to, displays, such as LED displays. Taking LED displays as an example, after post-processing the substrate following the fabrication of the circuit layers, the application may further include: module mounting and module testing, wherein:
[0109] (1) The film layer is applied using SMD (Surface Mount Device) mounting technology, which may include:
[0110] Circuit board preparation: Cleaning, drying, and anti-static treatment of the PCB board are carried out to remove oil, dust and other impurities from the PCB board surface to ensure the quality of subsequent solder paste printing and component mounting, while preventing static electricity from damaging the components.
[0111] Solder paste printing: Printing solder paste on the pads of the PCB board to provide a soldering medium for subsequent surface mount technology (SMT) assembly;
[0112] Surface mount technology (SMT): Using a surface mount machine to precisely mount the packaged LED light-emitting units onto the corresponding positions on the PCB board;
[0113] Reflow soldering: The PCB board with the LED light-emitting units mounted is placed in a reflow oven. After stages such as preheating, heating, holding and cooling, the solder paste melts and solidifies, completing the soldering connection between the LED light-emitting units and the PCB board.
[0114] Inspection: The assembled LED modules are inspected using equipment such as AOI and X-ray inspection to check the quality of solder joints, whether there are any missing or misaligned components, etc., to ensure that the electrical performance and reliability of the products meet the requirements.
[0115] Rework: For unqualified products or defective solder joints found during the inspection process, rework is carried out. During rework, it is usually necessary to first remove the defective components or solder joints, and then re-perform operations such as solder paste printing, surface mount technology (SMT) and reflow soldering to repair the defects.
[0116] (2) Module testing may include:
[0117] Functional testing: Perform functional tests on the assembled LED modules, including lighting tests, photoelectric parameter tests, etc., to check whether their emission color, brightness, wavelength, forward voltage, etc. meet the standards;
[0118] Aging test: LED modules are subjected to aging tests under certain conditions, usually including high temperature aging and constant current aging, to simulate the long-term working state in actual use, to discover potential quality problems in advance, and to screen out unqualified products.
[0119] Based on the above embodiments, this application breaks through the constraints of existing processes. By pre-treating a substrate without copper foil on its surface, patterned ink is formed on the surface of the pre-treated substrate. The ink is used to transfer patterns in non-circuit areas, completing the first step of pre-base layering for circuit fabrication. Then, copper is deposited in the circuit areas not covered by ink and on the walls of vias through a catalytic reduction reaction, forming thick copper and completing the circuit fabrication. Compared with existing circuit board deposition processes, this eliminates the electroplating copper process, the grinding process, and masking processes such as film drying, exposure, development, and etching. This greatly optimizes the process steps, significantly reduces the product's demand for equipment and copper materials, improves the product's first-pass yield (i.e., improves product quality), reduces manufacturing costs, completes the process transformation, and enhances the product's core cost competitiveness.
[0120] This application also provides a circuit board circuit, including: a circuit board circuit prepared by the circuit board circuit deposition method described above.
[0121] Based on the above embodiments, this application is prepared by the circuit board line deposition method described above, and also has the above-mentioned beneficial effects.
[0122] The circuit board deposition process described above is illustrated below with specific examples. Please refer to them. Figure 2 , Figure 2 The following is a flowchart illustrating a circuit board line deposition method provided in an embodiment of this application. The process is as follows:
[0123] Materials required: FR4 core board (without copper foil), ink, drill bit, milling cutter;
[0124] Process flow:
[0125] 1. Material cutting / drilling / hole inspection:
[0126] like Figure 2 As shown in (a), the FR4 core board (without copper foil on the surface) 1 is cut to obtain the FR4 core board (without copper foil on the surface) 1 with the target size;
[0127] like Figure 2 As shown in (b), holes are drilled in the FR4 core board (without copper foil on the surface) 1 after the cutting process to form through holes 2 in the FR4 core board (without copper foil on the surface) 1;
[0128] Inspect the formed through hole 2;
[0129] 2. Graphic transfer / UV curing: such as Figure 2 As shown in (c), non-polar ink 3 is transferred through a mold and coated onto the FR4 core board (without copper foil on the surface), and UV curing is performed after self-leveling for 3-5 minutes;
[0130] 3. Thick copper plating: such as Figure 2 As shown in (d), the FR4 core board 1 (without copper foil on the surface) that has undergone non-polarization treatment is placed in a chemical copper plating tank containing copper salt and reducing agent. Under the catalytic action of palladium nuclei, copper ions are reduced and precipitated, adhering to the hole walls of the through holes 2 and the open areas not covered by non-polar ink 3. At the same time, by continuously adding copper powder and using a graded main and auxiliary tank, the chemical solution from the main tank after the catalytic reduction reaction is introduced into the auxiliary tank. The addition of complex ions will form complex precipitates such as sulfate ions and formaldehyde groups that affect the catalytic reduction reaction. After filtration, the forward reaction can be promoted as a whole, thereby achieving the purpose of depositing thick copper and completing the fabrication of the circuit layer 4, resulting in the PCB board 5. The thickness of the copper layer deposited through the above steps can reach 15μm-20μm.
[0131] 4. Outer layer AOI / line repair;
[0132] 5. Ultra-roughening / screen printing / pre-baking / exposure / development;
[0133] 6. Visual inspection;
[0134] 7. Printing characters / baking plate;
[0135] 8. CNC milling of external shape / dimensional measurement;
[0136] 9. Electrical testing / FQC;
[0137] 10. OSP;
[0138] 11. Packaging.
[0139] This document uses specific examples to illustrate the principles and implementation methods of this application. The various embodiments are progressive, with each embodiment focusing on its differences from others. Similar or identical parts between embodiments can be referred to interchangeably. The descriptions of the embodiments above are merely illustrative of the method and core ideas of this application. For those skilled in the art, various improvements and modifications can be made to this application without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims of this application.
[0140] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.
Claims
1. A method for deposition of circuit board lines, characterized in that, include: A pretreatment is performed on a substrate whose surface does not contain copper foil to form through holes in the substrate; A patterned ink is formed on the surface of the substrate after pretreatment; The patterned substrate is placed in a chemical copper plating bath containing copper salt and reducing agent. Under catalysis, copper ions are reduced and deposited, adhering to the walls of the vias and the substrate surface not covered by the ink, to obtain a copper layer with the target thickness, thus completing the circuit layer fabrication. The thickness of the ink is greater than or equal to the thickness of the copper layer.
2. The circuit board line deposition method according to claim 1, characterized in that, The pretreatment of a substrate without copper foil on its surface to form through-holes in the substrate includes: The substrate without the copper foil on its surface is cut to obtain the substrate with the target size; Drilling is performed on the substrate after the material has been cut to form the through holes in the substrate; The formed through-hole is inspected.
3. The circuit board line deposition method according to claim 1, characterized in that, The process of forming patterned ink on the surface of the substrate after pretreatment includes: A patterned nonpolar ink is formed on the surface of the substrate after pretreatment.
4. The circuit board line deposition method according to claim 1, characterized in that, The process of forming patterned ink on the surface of the substrate after pretreatment includes: A patterned polar ink is formed on the surface of the substrate after pretreatment; Accordingly, after placing the patterned substrate into a chemical copper plating bath containing copper salt and a reducing agent, and under catalysis, reducing and depositing copper ions onto the walls of the vias and the substrate surface not covered by the ink to obtain a copper layer of the target thickness, the process further includes: The ink and the copper layer adhering to the surface of the ink are removed by stripping.
5. The circuit board line deposition method according to claim 1, characterized in that, The process of forming patterned ink on the surface of the substrate after pretreatment includes: The patterned ink is applied to the pretreated substrate surface by screen printing or mold transfer; the ink contains a self-volatile diluent. Allow the ink to self-level for a preset time after the transfer is completed; The ink that has achieved self-leveling is then UV cured.
6. The circuit board line deposition method according to claim 1, characterized in that, The thickness of the copper layer is 15μm-20μm, including the values at both ends; the difference between the thickness of the ink and the thickness of the copper layer is greater than 5μm. And / or, the ink is matte black.
7. The circuit board line deposition method according to claim 1, characterized in that, The process involves placing the patterned substrate into a chemical copper plating bath containing copper salt and a reducing agent. Under catalytic action, copper ions are reduced and deposited, adhering to the walls of the vias and the substrate surface not covered by the ink, to obtain a copper layer of the target thickness, thus completing the circuit layer fabrication. This includes: The patterned substrate is pre-impregnated; The pre-impregnated substrate is activated to allow colloidal palladium to adhere to the walls of the through holes and the substrate surface not covered by the ink. The colloidal palladium is accelerated to remove the colloidal portion of the outer layer of the colloidal palladium, exposing the palladium core; The accelerated substrate is placed in the chemical copper plating bath containing the copper salt and the reducing agent. Under the action of the palladium nucleus, the copper ions are reduced and deposited, adhering to the hole walls of the vias and the substrate surface not covered by the ink, to obtain the copper layer with the target thickness, thus completing the fabrication of the circuit layer.
8. The circuit board line deposition method according to claim 1, characterized in that, The process involves placing the patterned substrate into a chemical copper plating bath containing copper salt and a reducing agent, and under catalysis, reducing and depositing copper ions onto the walls of the vias and the substrate surface not covered by the ink, thereby obtaining a copper layer of the target thickness. After completing the circuit layer fabrication, the process further includes: The substrate after the circuit layer fabrication is completed undergoes post-processing.
9. The circuit board line deposition method according to any one of claims 1 to 8, characterized in that, The chemical copper plating tank includes a main tank and a secondary tank; Accordingly, the patterned substrate is placed in a chemical copper plating bath containing copper salt and a reducing agent, and under catalysis, copper ions are reduced and deposited, adhering to the walls of the vias and the substrate surface not covered by the ink, to obtain a copper layer of the target thickness, thus completing the circuit layer fabrication, including: Step 1: The patterned substrate is placed in the main tank containing the copper salt and the reducing agent, and under catalysis, the copper ions are reduced and precipitated, adhering to the hole walls of the through holes and the substrate surface not covered by the ink, and the reacted solution is obtained; copper powder is continuously added to the main tank throughout the deposition process. Step 2: The solution after the catalytic reduction reaction is introduced into the auxiliary tank. Complexing ions are added to the auxiliary tank to form complex precipitates of substances that affect the catalytic reduction reaction. The solution is then filtered to obtain the filtered solution. Step 3: After the filtered solution is introduced into the main tank, repeat steps 1 and 2 above until the copper layer with the target thickness is obtained, thus completing the fabrication of the circuit layer.
10. A circuit board circuit, characterized in that, include: The circuit board lines are prepared by the circuit board line deposition method according to any one of claims 1 to 9.