Preparation method of resistive random access memory and resistive random access memory
By selectively growing a bottom electrode composite layer and a top electrode on a substrate, the problem of low bottom electrode verticality in traditional resistive switching memory is solved, thus realizing a highly integrated and high-performance resistive switching memory.
Patent Information
- Application Number
- CN202511048613.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-29
- Publication Date
- 2025-10-31
AI Technical Summary
In traditional resistive switching memory fabrication methods, the bottom electrode has low verticality, which affects memory performance.
A selective growth process is used to form an N-layer bottom electrode composite layer on the substrate. A portion of the substrate or the previous bottom electrode composite layer is exposed through a patterned photoresist layer. The bottom electrode and insulating layer are then grown to avoid etching steps, forming a highly vertical bottom electrode composite layer. The top electrode is grown within the opening area of the top electrode photoresist layer to ensure its verticality.
This improves the verticality of each electrode layer in the resistive switching memory, forming a highly integrated memory, avoiding the limitations of etching technology, and enhancing the overall performance of the memory.
Smart Images
Figure CN120882005A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a resistive switching memory (RSM) and the RSM itself. Background Technology
[0002] Resistive Random Access Memory (RRAM) is a research field of non-volatile memory that has emerged in recent years. Due to its characteristics such as high storage density, low power consumption, high durability, high persistence, and CMOS process compatibility, it is widely used in computer architecture.
[0003] However, the traditional method for fabricating resistive switching memory (RSM) involves forming several initial bottom electrode composite layers on a substrate, followed by etching these layers to form a bottom electrode composite layer. This bottom electrode composite layer includes a bottom electrode and an insulating layer on top of it. However, this method is limited by etching techniques, resulting in low perpendicularity between the bottom electrodes in the RSM. The performance of the RSM is affected by the perpendicularity of the bottom electrodes within the RSM.
[0004] Therefore, how to improve the verticality of each bottom electrode layer in resistive switching memory has become a technical problem that urgently needs to be solved by existing technologies. Summary of the Invention
[0005] This invention provides a method for fabricating a resistive switching memory (RSM) and the RSM itself, which improves the perpendicularity of the bottom electrodes in the RSM.
[0006] According to a first aspect of the present invention, the technical solution of the present invention provides a method for fabricating a resistive random access memory (RRAM), the method comprising: Provide substrate; An N-layer bottom electrode composite layer is formed on the substrate. The extension direction of the N-layer bottom electrode composite layer is a first direction. The N-layer bottom electrode composite layer includes a middle region of the composite layer and edge regions of the composite layer located on both sides of the middle region of the composite layer. The i-th bottom electrode composite layer in the N-layer bottom electrode composite layer includes an i-th bottom electrode and an i-th insulating layer superimposed on the i-th bottom electrode. The length of the i-th bottom electrode composite layer in the first direction is less than the length of the (i-1)-th bottom electrode composite layer in the first direction, so as to expose a portion of the surface of the (i-1)-th insulating layer in the edge region of the composite layer. N ≥ i ≥ 1 and N and i are both integers. A method for forming an N-layer bottom electrode composite layer includes: forming a patterned i-th photoresist layer on the substrate, wherein when i=1, an opening region of the i-th photoresist layer exposes a portion of the substrate; when i>1, an opening region of the i-th photoresist layer exposes a portion of the (i-1)-th bottom electrode composite layer; and using a selective growth process, growing the i-th bottom electrode composite layer within the opening region of the i-th photoresist layer. After forming an N-layer bottom electrode composite layer, a patterned top electrode photoresist layer is formed on the surface of the N-layer bottom electrode composite layer and on the substrate. The opening region of the top electrode photoresist layer is located on a portion of the Nth insulating layer in the middle region of the composite layer and on a portion of the surface of the substrate surrounding the middle region of the composite layer. A selective growth process is used to grow the top electrode within the opening region of the top electrode photoresist layer; After growing the top electrode, the top electrode photoresist layer is removed to continue exposing a portion of the surface of the first insulating layer to the (n-1)th insulating layer in the edge region of the composite layer, and to expose the surface of the nth insulating layer in the edge region of the composite layer. Remove a portion of the surface of the first insulating layer to the (n-1)th insulating layer in the exposed edge region of the composite layer, as well as the surface of the nth insulating layer in the edge region of the composite layer.
[0007] Optionally, after forming the N-layer bottom electrode composite layer and before forming the top electrode photoresist layer, the process further includes: A patterned functional layer photoresist layer is formed on the surface of the Nth bottom electrode composite layer and the surface of the substrate. The opening region of the functional layer photoresist layer exposes at least a portion of the Nth bottom electrode composite layer in the middle region of the composite layer, as well as a portion of the substrate surrounding the middle region of the composite layer. The functional layer is grown by magnetron sputtering in the opening region of the photoresist layer of the functional layer. The size of the functional layer in the second direction is larger than the size of the N-layer bottom electrode composite layer in the middle region of the composite layer in the second direction. The second direction is perpendicular to the first direction.
[0008] Optionally, the material of the functional layer includes oxides, two-dimensional materials, organic materials, or perovskite materials.
[0009] Optionally, the thickness of the Nth insulating layer is 50nm-100nm.
[0010] Optionally, the top electrode includes a middle top electrode region and an edge top electrode region. The middle top electrode region is located on a portion of the middle region of the Nth bottom electrode composite layer. The edge top electrode region is located on both sides of the middle top electrode region in the direction perpendicular to the first direction. The length of the edge top electrode region in the first direction is greater than the length of the edge bottom electrode region in the first direction.
[0011] Optionally, the first width is smaller than the second width, where the first width is the width of the N-layer bottom electrode composite layer in the middle region of the composite layer along the second direction, and the second width is the width of the N-layer bottom electrode composite layer in the edge region of the composite layer along the second direction, the second direction being perpendicular to the first direction.
[0012] Optionally, the process for growing the i-th bottom electrode and the i-th insulating layer is magnetron sputtering growth, and the process for growing the top electrode is magnetron sputtering growth.
[0013] Optionally, the material of the i-th bottom electrode is a metal or a metal oxide.
[0014] Optionally, the material of the i-th insulating layer is a metal oxide.
[0015] According to a second aspect of the present invention, the present invention also provides a resistive switching memory, formed using the resistive switching memory fabrication method described above, comprising: Substrate; An N-layer bottom electrode composite layer extends in a first direction. The N-layer bottom electrode composite layer includes a middle region and edge regions located on both sides of the middle region. The i-th bottom electrode composite layer in the N-layer bottom electrode composite layer includes an i-th bottom electrode and an i-th insulating layer superimposed on the i-th bottom electrode. The length of the i-th bottom electrode composite layer in the first direction is less than the length of the (i-1)-th bottom electrode composite layer in the first direction. Part of the surface of the i-th bottom electrode to part of the (N-1)-th bottom electrode is exposed in the edge region of the composite layer. The surface of the N-th bottom electrode is exposed in the edge region of the composite layer. N ≥ i ≥ 1 and N and i are both integers. The top electrode is located on the middle region of the composite layer, on the side of the middle region of the composite layer perpendicular to the first direction, and on a portion of the substrate.
[0016] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects: In the resistive switching memory fabrication method and resistive switching memory of the present invention, since N bottom electrode composite layers are formed on the substrate, the i-th bottom electrode composite layer in the N-th bottom electrode composite layer includes an i-th bottom electrode and an i-th insulating layer superimposed on the i-th bottom electrode. The length of the i-th bottom electrode composite layer in the first direction is less than the length of the (i-1)-th bottom electrode composite layer in the first direction and exposes a portion of the surface of the (i-1)-th insulating layer in the edge region of the composite layer, the present invention can form multiple bottom electrode composite layers including bottom electrodes and insulating layers. Therefore, the present invention can form a resistive switching memory with high integration. On the one hand, since the method for forming the i-th bottom electrode composite layer includes: forming a patterned i-th photoresist layer on the substrate, when i=1, the opening region of the i-th photoresist layer exposes part of the substrate; when i>1, the opening region of the i-th photoresist layer exposes part of the (i-1)-th bottom electrode composite layer; using a selective growth process to grow the i-th bottom electrode composite layer in the opening region of the i-th photoresist layer; and using a method of growing N-layer bottom electrode composite layers in the opening region of the patterned photoresist, there is no need to etch the bottom electrode, therefore, the verticality of the formed bottom electrode composite layer is high. On the other hand, after forming the N-layer bottom electrode composite layer, a patterned top electrode photoresist layer is formed on the surface of the N-layer bottom electrode composite layer and on the substrate. The opening region of the top electrode photoresist layer is located on a portion of the Nth insulating layer in the middle region of the composite layer and on the surface of a portion of the substrate surrounding the middle region of the composite layer. A selective growth process is used to grow the top electrode within the opening region of the top electrode photoresist layer. Since the top electrode is grown in the opening region of the patterned top electrode photoresist, there is no need to etch the top electrode. Therefore, the verticality of the formed top electrode is high, thereby improving the verticality of each electrode layer in the resistive switching memory.
[0017] Furthermore, after forming the N-layer bottom electrode composite layer and before forming the top electrode photoresist layer, a functional layer is grown in the opening region of the photoresist layer of the patterned functional layer. This results in high verticality of the functional layer, and wet etching is not required in the process steps of forming the functional layer. Therefore, the material of the functional layer can be not only oxide, but also two-dimensional material, organic material or perovskite material. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figures 1-2This is a schematic diagram of the structure corresponding to each step in the fabrication method of a resistive switching memory; Figures 3-19 This is a schematic diagram of the structure corresponding to each step in a method for fabricating a resistive switching memory according to an embodiment of the present invention. Detailed Implementation
[0020] As described in the background section, the conventional method for fabricating resistive switching memory (RSM) involves forming several initial bottom electrode composite layers on a substrate, followed by etching these layers to form a bottom electrode composite layer. This bottom electrode composite layer includes a bottom electrode and an insulating layer located on top of the bottom electrode. However, this method is limited by etching techniques, resulting in low verticality of the bottom electrodes in the RSM. The following will describe in detail the fabrication method of prior art resistive switching memory with reference to the accompanying drawings.
[0021] Figures 1-2 This is a schematic diagram of the steps involved in the fabrication of resistive random access memory (RRAM).
[0022] Please refer to Figure 1 A substrate 10 is provided, on which N initial bottom electrode composite layers are formed. The i-th initial bottom electrode composite layer 20 in the N initial bottom electrode composite layers includes an initial i-th bottom electrode 21 and an initial i-th insulating layer 22 superimposed on the initial i-th bottom electrode 21; N≥i≥1 and N and i are both integers.
[0023] Please refer to Figure 2 The bottom electrode composite layer of the N layers is etched to form a plurality of initial N-layer bottom electrode composite layers. The i-th bottom electrode composite layer 30 in the N-layer bottom electrode composite layer includes an i-th bottom electrode 31 and an i-th insulating layer 32 superimposed on the i-th bottom electrode 31; N≥i≥1 and N and i are both integers.
[0024] Due to limitations in etching technology, the verticality of the etching process cannot be guaranteed during the etching of the N-layer initial bottom electrode composite layer. However, the low verticality of the bottom electrode composite layer obtained by etching the N-layer initial bottom electrode composite layer will lead to poor performance of the resulting resistive switching memory.
[0025] In view of this, the technical solution of the present invention provides a method for fabricating a resistive switching memory, by providing a substrate; forming an N-layer bottom electrode composite layer on the substrate, the N-layer bottom electrode composite layer extending in a first direction, the N-layer bottom electrode composite layer including a middle region of the composite layer and edge regions of the composite layer located on both sides of the middle region of the composite layer, the i-th bottom electrode composite layer in the N-layer bottom electrode composite layer including an i-th bottom electrode and an i-th insulating layer overlapping the i-th bottom electrode, the length of the i-th bottom electrode composite layer in the first direction is less than the length of the (i-1)-th bottom electrode composite layer in the first direction and exposes a portion of the surface of the (i-1)-th insulating layer in the edge region of the composite layer, N≥i≥1 and N and i are both integers; thus, the present invention can form a resistive switching memory with high integration. By forming a patterned i-th photoresist layer on the substrate, when i=1, the opening region of the i-th photoresist layer exposes a portion of the substrate; when i>1, the opening region of the i-th photoresist layer exposes a portion of the (i-1)-th bottom electrode composite layer. A selective growth process is used to grow the i-th bottom electrode composite layer within the opening region of the i-th photoresist layer, resulting in a high verticality of the formed bottom electrode composite layer. After forming N-layer bottom electrode composite layers, a patterned top electrode photoresist layer is formed on the surface of the N-layer bottom electrode composite layer and on the substrate. The opening region of the top electrode photoresist layer is located on a portion of the N-th insulating layer in the middle region of the composite layer and on the surface of a portion of the substrate surrounding the middle region of the composite layer, resulting in a high verticality of the formed top electrode. After growing the top electrode, the top electrode photoresist layer is removed to further expose a portion of the surface of the first insulating layer to the (n-1)th insulating layer in the edge region of the composite layer, and to expose the surface of the nth insulating layer in the edge region of the composite layer; the exposed portions of the surfaces of the first insulating layer to the (n-1)th insulating layer in the edge region of the composite layer, and the surface of the nth insulating layer in the edge region of the composite layer are then removed. Thus, this invention improves the verticality of the electrode layers in the resistive switching memory.
[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.
[0027] The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0028] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.
[0029] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0030] Figures 3-19 This is a schematic diagram of the structure corresponding to each step in a method for fabricating a resistive switching memory according to an embodiment of the present invention.
[0031] Please refer to Figure 3 Substrate 100 is provided.
[0032] As an example, substrate 100 may include semiconductor materials such as silicon, gallium arsenide, germanium, germanium silicon, or silicon-on-insulator.
[0033] Next, an N-layer bottom electrode composite layer is formed on the substrate 100. The N-layer bottom electrode composite layer extends in the first direction X. The N-layer bottom electrode composite layer includes a middle region of the composite layer and edge regions of the composite layer located on both sides of the middle region of the composite layer. The i-th bottom electrode composite layer in the N-layer bottom electrode composite layer includes an i-th bottom electrode and an i-th insulating layer superimposed on the i-th bottom electrode. The length of the i-th bottom electrode composite layer in the first direction X is less than the length of the (i-1)-th bottom electrode composite layer in the first direction X and exposes a portion of the surface of the (i-1)-th insulating layer in the edge region of the composite layer. N ≥ i ≥ 1 and N and i are both integers.
[0034] The method for forming an N-layer bottom electrode composite layer includes: forming a patterned i-th photoresist layer on a substrate 100, wherein when i=1, the opening region of the i-th photoresist layer exposes a portion of the substrate 100; when i>1, the opening region of the i-th photoresist layer exposes a portion of the (i-1)-th bottom electrode composite layer; and using a selective growth process, growing the i-th bottom electrode composite layer within the opening region of the i-th photoresist layer.
[0035] For example, the thickness of the i-th insulating layer is 50nm-100nm.
[0036] Setting the thickness of the i-th insulating layer to 50nm-100nm allows for a smaller thickness of the bottom electrode composite layer, which is beneficial for improving integration.
[0037] For example, the material of the i-th bottom electrode is a metal or a metal oxide.
[0038] For example, the material of the i-th insulating layer is a metal oxide.
[0039] After forming N low-electrode composite layers, the first photoresist layer to the Nth photoresist layer are removed.
[0040] Taking N=3 as an example, combined with the following appendix Figures 4 to 9 The specific steps for forming the N-layer bottom electrode composite layer are described in detail.
[0041] Please refer to Figure 4 A patterned first photoresist layer 200 is formed on the substrate 100, and the opening area of the first photoresist layer 200 exposes a portion of the substrate 100.
[0042] Please refer to Figure 5 A selective growth process is used to grow the first bottom electrode composite layer 300 in the opening area of the first photoresist layer 200.
[0043] Specifically, the step of growing the first bottom electrode composite layer 300 in the opening region of the first photoresist layer 200 using a selective growth process includes: growing the first bottom electrode 310 in the opening region of the first photoresist layer 200 using a selective growth process; and after growing the first bottom electrode 310, growing the first insulating layer 320 on the first bottom electrode 310 in the opening region of the first photoresist layer 200 using a selective growth process, wherein the first insulating layer 320 overlaps the first bottom electrode 310.
[0044] Please refer to Figure 6 A patterned second photoresist layer 400 is formed on the substrate 100, and the opening region of the second photoresist layer 400 exposes a portion of the first bottom electrode composite layer 300.
[0045] Please refer to Figure 7A selective growth process is used to grow a second bottom electrode composite layer 500 in the opening area of the second photoresist layer 400. The length of the second bottom electrode composite layer 500 in the first direction X is less than the length of the first bottom electrode composite layer 300 in the first direction X, so as to expose part of the surface of the first insulating layer 320 in the edge region of the composite layer.
[0046] Specifically, the step of growing the second bottom electrode composite layer 500 in the opening region of the second photoresist layer 400 using a selective growth process includes: growing a second bottom electrode 510 in the opening region of the second photoresist layer 400 using a selective growth process; and after growing the second bottom electrode 510, growing a second insulating layer 520 on the second bottom electrode 510 in the opening region of the second photoresist layer 400 using a selective growth process, wherein the second insulating layer 520 overlaps the second bottom electrode.
[0047] Please refer to Figure 8 A patterned third photoresist layer 600 is formed on the substrate 100, with an opening in the third photoresist layer 600 exposing a portion of the second bottom electrode composite layer 500. A third bottom electrode composite layer 700 is formed on the surface of the second bottom electrode composite layer 500, with the length of the third bottom electrode composite layer 700 in the first direction X being less than the length of the second bottom electrode composite layer 500 in the first direction. In the third bottom electrode composite layer, a third insulating layer 720 overlaps on the third bottom electrode 710. The specific method for growing the third bottom electrode composite layer is the same as the method for growing the second bottom electrode composite layer 500, and will not be described in detail here.
[0048] Please refer to Figure 9 as well as Figure 10 , Figure 9 and Figures 3 to 8 The view orientation is consistent, and, Figure 9 yes Figure 10 A schematic diagram of the cross-sectional structure along the A1-A2 direction. Figure 10 for Figure 9 The top view shows that after forming the N-layer bottom electrode composite layer, the first photoresist layer, the second photoresist layer 400, and the third photoresist layer 600 are removed.
[0049] In the above embodiments, by growing the bottom electrode composite layer in the opening area of the patterned photoresist layer, the verticality of each bottom electrode composite layer is well ensured.
[0050] In this embodiment, please continue to refer to Figure 10The first width d1 is smaller than the second width d2. The first width is the width of the N-layer bottom electrode composite layer along the second direction Y in the middle region of the composite layer, and the second width is the width of the N-layer bottom electrode composite layer along the second direction Y in the edge region of the composite layer. The second direction Y is perpendicular to the first direction. Setting the width of the N-layer bottom electrode composite layer along the second direction Y in the middle region of the composite layer to be narrower can make the area of the N-layer bottom electrode composite layer smaller.
[0051] Specifically, the length of the opening region of the i-th photoresist layer in the first direction X is less than the size of the opening region of the (i-1)-th photoresist layer in the first direction X, and the size of the opening region of the i-th photoresist layer in the second direction Y is equal to the size of the (i-1)-th photoresist layer in the second direction Y, where the second direction Y is perpendicular to the first direction. This ensures good perpendicularity between different bottom electrode composite layers in the second direction.
[0052] In one example, the process for growing the i-th bottom electrode and the i-th insulating layer is magnetron sputtering. The i-th bottom electrode and the i-th insulating layer grown using magnetron sputtering are more uniform, resulting in higher verticality of the i-th bottom electrode composite layer. Of course, this invention is not limited to this; the process for growing the i-th bottom electrode and the i-th insulating layer can also be chemical vapor deposition.
[0053] Next, please refer to Figure 11 A patterned functional layer photoresist layer 800 is formed on the surface of the N-layer bottom electrode composite layer and the surface of the substrate 100. The opening region of the functional layer photoresist layer 800 exposes at least a portion of the N-layer bottom electrode composite layer in the middle region of the composite layer, as well as a portion of the substrate 100 surrounding the middle region of the composite layer.
[0054] Please refer to Figure 12 as well as Figure 13 , Figure 12 and Figures 3 to 9 as well as Figure 11 The view orientation is consistent, and, Figure 12 yes Figure 13 A schematic diagram of the cross-sectional structure along the A1-A2 direction. Figure 13 for Figure 12 The top view shows that a functional layer 900 is grown in the opening area of the functional layer photoresist layer 800. The size of the functional layer 900 in the second direction Y is larger than the size of the N-layer bottom electrode composite layer in the middle region of the composite layer in the second direction Y. The second direction Y is perpendicular to the first direction X.
[0055] The present invention grows the functional layer 900 in the opening area of the photoresist layer of the patterned functional layer 900, which makes the verticality of the functional layer 900 high, and the process steps of forming the functional layer 900 do not require the use of wet etching, thereby allowing the material of the functional layer 900 to be other than oxides.
[0056] Specifically, the material of functional layer 900 may include oxides, two-dimensional materials, organic materials, or perovskite materials.
[0057] Next, please refer to Figure 14 A patterned top electrode photoresist layer 1000 is formed on the surface of the N-layer bottom electrode composite layer and on the substrate 100. The opening region of the top electrode photoresist layer 1000 is located on a portion of the Nth insulating layer in the middle region of the composite layer and on a portion of the surface of the substrate 100 surrounding the middle region of the composite layer.
[0058] Please refer to Figure 15 A selective growth process is used to grow the top electrode 1100 within the opening region of the top electrode photoresist layer 1000.
[0059] As an example, the top electrode 1100 is grown using magnetron sputtering. The top electrode 1100 grown using magnetron sputtering is more uniform and exhibits higher verticality. However, this invention is not limited to this method; the top electrode 1100 can also be grown using chemical vapor deposition.
[0060] Please refer to Figure 16 as well as Figure 17 , Figure 16 and Figures 3 to 9 , Figures 11 to 12 as well as Figures 14 to 15 The view orientation is consistent, and, Figure 16 yes Figure 17 A schematic diagram of the cross-sectional structure along the A1-A2 direction. Figure 17 for Figure 16 The top view shows that after the top electrode 1100 is grown, the top electrode photoresist layer 1000 is removed to continue exposing a portion of the surface of the first insulating layer 320 to a portion of the surface of the (n-1)th insulating layer in the edge region of the composite layer, and exposing the surface of the nth insulating layer in the edge region of the composite layer.
[0061] Please refer to Figure 18 as well as Figure 19 , Figure 18 and Figures 1 to 9 , Figures 11 to 12 as well as Figures 14 to 16 The view orientation of the views is consistent. Figure 18 for Figure 19 A schematic diagram of the cross-sectional structure along the A1-A2 direction. Figure 19 for Figure 18 The top view shows the partial surface of the first insulating layer 320 to the (n-1)th insulating layer in the exposed composite layer edge region, as well as the surface of the nth insulating layer in the composite layer edge region.
[0062] In this embodiment of the invention, since an N-layer bottom electrode composite layer is formed on the substrate 100, the i-th bottom electrode composite layer in the N-layer bottom electrode composite layer includes an i-th bottom electrode and an i-th insulating layer superimposed on the i-th bottom electrode. The length of the i-th bottom electrode composite layer in the first direction is less than the length of the (i-1)-th bottom electrode composite layer in the first direction and exposes a portion of the surface of the (i-1)-th insulating layer in the edge region of the composite layer, the present invention can form a multilayer bottom electrode composite layer including a bottom electrode and an insulating layer. Therefore, the present invention can form a resistive switching memory with a high degree of integration. On the one hand, since the method for forming the i-th bottom electrode composite layer includes: forming a patterned i-th photoresist layer on the substrate 100, when i=1, the opening region of the i-th photoresist layer exposes part of the substrate 100; when i>1, the opening region of the i-th photoresist layer exposes part of the (i-1)-th bottom electrode composite layer; using a selective growth process to grow the i-th bottom electrode composite layer in the opening region of the i-th photoresist layer; and using a method of growing N-layer bottom electrode composite layers in the opening region of the patterned photoresist, there is no need to etch the bottom electrode, therefore, the verticality of the formed bottom electrode composite layer is high. On the other hand, after forming the N-layer bottom electrode composite layer, a patterned top electrode photoresist layer 1000 is formed on the surface of the N-layer bottom electrode composite layer and on the substrate 100. The opening region of the top electrode photoresist layer 1000 is located on a portion of the Nth insulating layer in the middle region of the composite layer and on a portion of the surface of the substrate 100 surrounding the middle region of the composite layer. A selective growth process is used to grow the top electrode 1100 in the opening region of the top electrode photoresist layer 1000. Since the top electrode 1100 is grown in the opening region of the patterned top electrode 1100 photoresist, there is no need to etch the top electrode 1100. Therefore, the verticality of the formed top electrode 1100 is high, thereby improving the verticality of different layers in the resistive switching memory.
[0063] Accordingly, this invention also provides a resistive random access memory formed using the above-described forming method. Please refer to the following embodiments. Figure 18 as well as Figure 19 The resistive switching memory includes: a substrate 100, an N-layer bottom electrode composite layer, and a top electrode 1100.
[0064] The extension direction of the N-layer bottom electrode composite layer is the first direction. The N-layer bottom electrode composite layer includes a middle region of the composite layer and edge regions of the composite layer located on both sides of the middle region of the composite layer. The i-th bottom electrode composite layer in the N-layer bottom electrode composite layer includes the i-th bottom electrode and the i-th insulating layer superimposed on the i-th bottom electrode. The length of the i-th bottom electrode composite layer in the first direction is less than the length of the (i-1)-th bottom electrode composite layer in the first direction. Part of the surface of the i-th bottom electrode to part of the (N-1)-th bottom electrode is exposed in the edge region of the composite layer. The surface of the N-th bottom electrode in the edge region of the composite layer is exposed. N≥i≥1 and N and i are both integers. The top electrode 1100 is located on the middle region of the composite layer, on the side of the middle region of the composite layer perpendicular to the first direction, and on a portion of the substrate 100.
[0065] The materials, forming process, working principle, specific implementation method and beneficial effects of the resistive switching memory involved in this embodiment can be found in the preparation method of the resistive switching memory in the embodiment of the present invention, and will not be repeated here.
[0066] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for fabricating a resistive random access memory (RAD), characterized in that, The method includes: Provide substrate; An N-layer bottom electrode composite layer is formed on the substrate. The extension direction of the N-layer bottom electrode composite layer is a first direction. The N-layer bottom electrode composite layer includes a middle region of the composite layer and edge regions of the composite layer located on both sides of the middle region of the composite layer. The i-th bottom electrode composite layer in the N-layer bottom electrode composite layer includes an i-th bottom electrode and an i-th insulating layer superimposed on the i-th bottom electrode. The length of the i-th bottom electrode composite layer in the first direction is less than the length of the (i-1)-th bottom electrode composite layer in the first direction, so as to expose a portion of the surface of the (i-1)-th insulating layer in the edge region of the composite layer. N ≥ i ≥ 1 and N and i are both integers. A method for forming an N-layer bottom electrode composite layer includes: forming a patterned i-th photoresist layer on the substrate, wherein when i=1, an opening region of the i-th photoresist layer exposes a portion of the substrate; when i>1, an opening region of the i-th photoresist layer exposes a portion of the (i-1)-th bottom electrode composite layer; and using a selective growth process, growing the i-th bottom electrode composite layer within the opening region of the i-th photoresist layer. After forming an N-layer bottom electrode composite layer, a patterned top electrode photoresist layer is formed on the surface of the N-layer bottom electrode composite layer and on the substrate. The opening region of the top electrode photoresist layer is located on a portion of the Nth insulating layer in the middle region of the composite layer and on a portion of the surface of the substrate surrounding the middle region of the composite layer. A selective growth process is used to grow the top electrode within the opening region of the top electrode photoresist layer; After growing the top electrode, the top electrode photoresist layer is removed to continue exposing a portion of the surface of the first insulating layer to the (n-1)th insulating layer in the edge region of the composite layer, and to expose the surface of the nth insulating layer in the edge region of the composite layer. Remove a portion of the surface of the first insulating layer to the (n-1)th insulating layer in the exposed edge region of the composite layer, as well as the surface of the nth insulating layer in the edge region of the composite layer.
2. The method for fabricating a resistive random access memory as described in claim 1, characterized in that, After forming the N-layer bottom electrode composite layer and before forming the top electrode photoresist layer, the process also includes: A patterned functional layer photoresist layer is formed on the surface of the Nth bottom electrode composite layer and the surface of the substrate. The opening region of the functional layer photoresist layer exposes at least a portion of the Nth bottom electrode composite layer in the middle region of the composite layer, as well as a portion of the substrate surrounding the middle region of the composite layer. The functional layer is grown by magnetron sputtering in the opening region of the photoresist layer of the functional layer. The size of the functional layer in the second direction is larger than the size of the N-layer bottom electrode composite layer in the middle region of the composite layer in the second direction. The second direction is perpendicular to the first direction.
3. The method for fabricating a resistive random access memory as described in claim 2, characterized in that, The materials of the functional layer include oxides, two-dimensional materials, organic materials, or perovskite materials.
4. The method for fabricating a resistive random access memory as described in claim 1, characterized in that, The thickness of the Nth insulating layer is 50nm-100nm.
5. The method for fabricating a resistive random access memory as described in claim 1, characterized in that, The top electrode includes a middle top electrode region and an edge top electrode region. The middle top electrode region is located on a portion of the middle region of the Nth bottom electrode composite layer. The edge top electrode region is located on both sides of the middle top electrode region in the vertical direction of the first direction. The length of the edge top electrode region in the first direction is greater than the length of the edge bottom electrode region in the first direction.
6. The method for fabricating a resistive random access memory as described in claim 1, characterized in that, The first width is less than the second width. The first width is the width of the N-layer bottom electrode composite layer in the middle region of the composite layer along the second direction, and the second width is the width of the N-layer bottom electrode composite layer in the edge region of the composite layer along the second direction, which is perpendicular to the first direction.
7. The method for fabricating a resistive random access memory as described in claim 1, characterized in that, The process for growing the i-th bottom electrode and the i-th insulating layer is magnetron sputtering growth, and the process for growing the top electrode is magnetron sputtering growth.
8. The method for fabricating a resistive random access memory as described in claim 1, characterized in that, The material of the i-th bottom electrode is a metal or a metal oxide.
9. The method for fabricating a resistive random access memory as described in claim 1, characterized in that, The material of the i-th insulating layer is a metal oxide.
10. A resistive random access memory, characterized in that, The resistive switching memory is formed using the fabrication method of any one of claims 1-9, comprising: Substrate; An N-layer bottom electrode composite layer extends in a first direction. The N-layer bottom electrode composite layer includes a middle region and edge regions located on both sides of the middle region. The i-th bottom electrode composite layer in the N-layer bottom electrode composite layer includes an i-th bottom electrode and an i-th insulating layer superimposed on the i-th bottom electrode. The length of the i-th bottom electrode composite layer in the first direction is less than the length of the (i-1)-th bottom electrode composite layer in the first direction. Part of the surface of the i-th bottom electrode to part of the (N-1)-th bottom electrode is exposed in the edge region of the composite layer. The surface of the N-th bottom electrode is exposed in the edge region of the composite layer. N ≥ i ≥ 1 and N and i are both integers. The top electrode is located on the middle region of the composite layer, on the side of the middle region of the composite layer perpendicular to the first direction, and on a portion of the substrate.