MOS device and forming method thereof
By using SiCN material and PECVD process to adjust the tensile stress and dielectric constant of the etching stop layer, the parasitic capacitance problem caused by the high dielectric constant of SiN material was solved, thereby improving signal transmission speed and reducing power consumption.
Patent Information
- Application Number
- CN202510821487.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-19
- Publication Date
- 2025-10-31
AI Technical Summary
The high dielectric constant of the traditional SiN etch stop layer leads to an increase in the parasitic capacitance of the device, which affects the circuit operating speed.
SiCN material is used as the etching stop layer. Its tensile stress and dielectric constant are controlled by PECVD process, so that the target tensile stress is greater than the standard tensile stress and the target dielectric constant is less than the standard dielectric constant. The carbon content difference between the bulk region and the surface layer is controlled to form the stress difference between the bulk region and the surface layer.
It effectively reduces parasitic capacitance, improves signal transmission speed, reduces power consumption, and increases the operating frequency of integrated circuits.
Smart Images
Figure CN120882045A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a MOS device and a method for forming the same. Background Technology
[0002] In advanced semiconductor processes, the CESL (Contact Etch Stop Layer) typically uses SiN (Silicon Nitride). The SiN layer not only serves as an etch stop layer but also provides additional stress to the transistor to improve device performance. However, the dielectric constant of traditional SiN is as high as around 7, resulting in strong parasitic capacitance in the device. As process nodes continue to shrink, the impact of parasitic capacitance on device performance becomes more significant. When parasitic capacitance increases, signal delay on interconnects also increases, leading to a decrease in overall circuit operating speed. Summary of the Invention
[0003] The purpose of this invention is to provide a MOS device and its formation method to solve the problem that the large dielectric constant of the etch stop layer leads to strong parasitic capacitance in the device, which in turn causes a decrease in the operating speed of the entire circuit.
[0004] To solve the above-mentioned technical problems, the present invention provides a MOS device, comprising:
[0005] Substrate;
[0006] A gate, the gate being located on the substrate;
[0007] Sidewalls, the sidewalls being located on both sides of the gate and covering the two sidewalls of the gate;
[0008] An etch stop layer covers the top surface of the gate, sidewalls, and substrate between adjacent gates. The etch stop layer has a target tensile stress and a target dielectric constant, wherein the target tensile stress is greater than a standard tensile stress and the target dielectric constant is less than a standard dielectric constant. The etch stop layer includes a body region and a surface layer, and the tensile stress in the body region of the etch stop layer is less than the tensile stress in the surface layer of the etch stop layer.
[0009] Optionally, the material of the etch stop layer is SiCN, and the carbon content of the body region of the etch stop layer is less than the carbon content of the surface layer of the etch stop layer.
[0010] Optionally, the target tensile stress of the etching stop layer is 1.5 GPa to 2.5 GPa.
[0011] Optionally, the target dielectric constant of the etch stop layer is 3.8 to 5.
[0012] Based on the same inventive concept, the present invention also provides a method for forming a MOS device, comprising:
[0013] A substrate is provided on which a gate and sidewalls located on both sides of the gate are formed;
[0014] An etch stop layer is formed, the etch stop layer covering the top surface of the gate, the sidewalls and the substrate between adjacent gates, the etch stop layer having a target tensile stress and a target dielectric constant, the target tensile stress being greater than a standard tensile stress and the target dielectric constant being less than a standard dielectric constant, the etch stop layer comprising a body region and a surface layer, and the tensile stress of the body region of the etch stop layer being less than the tensile stress of the surface layer of the etch stop layer.
[0015] Optionally, the etching stop layer can be formed using a PECVD process.
[0016] Optionally, the PECVD process includes a first process stage and a second process stage. The first process stage is used to form the body region of the etch stop layer, and the second process stage is used to form the surface layer of the etch stop layer. The carbon content of the body region and the surface layer of the etch stop layer are different.
[0017] Optionally, the CH4 / N2 ratio in the process gases SiH4, CH4, and N2 of the first stage is less than the CH4 / N2 ratio in the process gases SiH4, CH4, and N2 of the second stage.
[0018] Optionally, the carbon content of the body region of the etch stop layer is less than the carbon content of the surface layer of the etch stop layer.
[0019] Optionally, after the step of forming the etch stop layer:
[0020] A dielectric layer is formed, which covers the etch stop layer;
[0021] Perform a chemical mechanical polishing process and stop on the etch stop layer on top of the gate so that the top surface of the dielectric layer on the substrate between adjacent gates is flush with the top surface of the etch stop layer on top of the gate;
[0022] An etching process is performed to etch the etch stop layer on top of the gate to expose the top surface of the gate.
[0023] In a MOS device provided by this invention, the MOS device includes a substrate and a gate located on the substrate. Sidewalls are formed on both sides of the gate. An etch stop layer is disposed on the top surface of the gate, the sidewalls, and the substrate between adjacent gates. The etch stop layer has a target tensile stress and a target dielectric constant, wherein the target tensile stress is greater than a standard tensile stress and the target dielectric constant is less than a standard dielectric constant. The etch stop layer includes a body region and a surface layer, and the tensile stress in the body region of the etch stop layer is less than the tensile stress in the surface layer of the etch stop layer. The etch stop layer in this invention has a target tensile stress and a target dielectric constant, wherein the target tensile stress is greater than a standard tensile stress and the target dielectric constant is less than a standard dielectric constant. The standard tensile stress and standard dielectric constant are the tensile stress and dielectric constant of etch stop layers in the prior art, that is, the tensile stress of the etch stop layer in this invention is greater than the tensile stress of the etch stop layer in the prior art, and the dielectric constant of the etch stop layer in this invention is less than the dielectric constant of the etch stop layer in the prior art. This invention can improve the stress characteristics of the etch stop layer while effectively reducing the dielectric constant and thus the parasitic capacitance of the device, thereby increasing the signal transmission speed of the device, increasing the operating frequency of the device and the entire integrated circuit, and reducing power consumption. Attached Figure Description
[0024] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:
[0025] Figure 1 This is a schematic diagram of the structure of a MOS device according to an embodiment of the present invention.
[0026] Figure 2 This is a flowchart of a method for forming a MOS device according to an embodiment of the present invention.
[0027] Figures 3 to 7 This is a schematic diagram of the structure corresponding to the steps of the method for forming a MOS device according to an embodiment of the present invention.
[0028] In the attached image:
[0029] 10-Substrate; 11-Shallow trench isolation structure; 12a-First well region; 12b-Second well region; 13-NMOS device; 13a-Gate dielectric layer; 13b-Gate; 13c-Isolation layer; 13d-Sidewall; 14-PMOS device; 15a-Source region; 15b-Germanium-silicon stress layer; 16-Etch stop layer; 17-Dielectric layer. Detailed Implementation
[0030] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.
[0031] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature. Additionally, as used in this invention, the placement of one element on another element generally only indicates a connection, coupling, cooperation, or transmission relationship between the two elements, which can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of the other element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0032] Figure 1 This is a schematic diagram of the structure of a MOS device according to an embodiment of the present invention. Figure 1As shown, this embodiment provides a MOS device, including a substrate 10, a first well region 12a and a second well region 12b within the substrate 10. The first well region 12a is P-type doped, i.e., a P-well, and is used to form an NMOS device 13. The second well region 12b is N-type doped, i.e., an N-well, and is used to form a PMOS device 14. Adjacent first well regions 12a and second well regions 12b are isolated by a shallow trench isolation structure 11. The NMOS device 13 includes a gate dielectric layer 13a, a gate 13b, an isolation layer 13c, and sidewalls 13d. The gate dielectric layer 13a is made of one or a combination of an oxide layer and a hafnium oxide layer. Hafnium oxide material, due to its high dielectric constant, can effectively improve gate leakage current. To prevent hafnium ions from entering the gate 13b from the hafnium oxide, a barrier layer (not shown) is usually formed on the gate dielectric layer 13a. The barrier layer is made of, for example, titanium nitride. An isolation layer 13c is also formed on the gate 13b, and the isolation layer 13c is made of silicon nitride and / or silicon oxide. Sidewalls 13d are formed on the sidewalls of the gate 13b. The structure of the NMOS device 13 is the same as that of the PMOS device 14. A germanium-silicon stress layer 15b is formed in the substrate 10 on both sides of the PMOS device 14, and a source region 15a and a drain region are formed in the substrate 10 on both sides of the NMOS device 13. An etch stop layer 16 is formed on the PMOS device 14 and the NMOS device 13. The etch stop layer 16 covers the top surface, sidewalls, and substrate 10 between adjacent PMOS devices 14 and NMOS devices 13. The material of the etch stop layer 16 is, for example, SiCN. The etch stop layer 16 has a target tensile stress and a target dielectric constant, wherein the target tensile stress is greater than the standard tensile stress and the target dielectric constant is less than the standard dielectric constant. The standard tensile stress and standard dielectric constant are those of SiN in the prior art. The target tensile stress of the etch stop layer 16 is, for example, 1.5 GPa to 2.5 GPa. The target dielectric constant of the etch stop layer 16 is, for example, 3.8 to 5. In this embodiment, the dielectric constant of SiCN can be controlled at around 4. In this embodiment, the material of the etch stop layer 16 is replaced from SiN to SiCN. SiCN reduces the dielectric constant from 7 (SiN) to 3.8 without losing tensile stress, which can significantly reduce parasitic capacitance. That is, this embodiment can effectively improve the signal transmission speed and reduce power consumption of the device without affecting the original functions of the device. The etch stop layer 16 includes a body region 16a and a surface layer 16b. The carbon content of the body region of the etch stop layer 16 is less than the carbon content of the surface layer of the etch stop layer. By controlling the carbon content of the body region and the surface layer of the etch stop layer, the tensile stress of the body region and the surface layer of the etch stop layer is controlled.Therefore, the tensile stress in the body region 16a of the etching stop layer is less than the tensile stress in the surface layer 16b of the etching stop layer, achieving high stress in the surface layer and stable stress in the body region, which can reduce the risk of interface delamination and reduce the density of interface defects.
[0033] Figure 2 This is a flowchart illustrating the method for forming a MOS device according to an embodiment of the present invention. Figure 2 As shown, this embodiment also provides a method for forming a MOS device, including:
[0034] Step S10: A substrate is provided, on which a gate and sidewalls located on both sides of the gate are formed;
[0035] Step S20: Forming an etch stop layer, the etch stop layer covering the top surface of the gate, the sidewalls and the substrate between adjacent gates, the etch stop layer having a target tensile stress and a target dielectric constant, the target tensile stress being greater than the standard tensile stress and the target dielectric constant being less than the standard dielectric constant, the etch stop layer comprising a body region and a surface layer, and the tensile stress of the body region of the etch stop layer being less than the tensile stress of the surface layer of the etch stop layer.
[0036] Figures 3 to 7 This is a schematic diagram corresponding to the structural steps of the method for forming a MOS device according to an embodiment of the present invention. To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, the following description is provided in conjunction with the appendix to the specification. Figures 3 to 7 Specific embodiments of the present invention will be described in detail below.
[0037] like Figure 3 As shown, a substrate 10 is provided. The substrate 10 provides an operating platform for subsequent processes. It can be any substrate known to those skilled in the art for supporting semiconductor integrated circuit components. It can be a bare die or a wafer processed by epitaxial growth. Specifically, the substrate 10 is, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium-silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate, etc. In this embodiment, the substrate 10 is a silicon substrate.
[0038] Please continue to refer to this. Figure 3The substrate 10 contains a first well region 12a and a second well region 12b. The first well region 12a is P-type doped, i.e., a P-well, and is used to form an NMOS device 13. The second well region 12b is N-type doped, i.e., an N-well, and is used to form a PMOS device 14. Adjacent first well regions 12a and second well regions 12b are isolated by a shallow trench isolation structure 11. The NMOS device 13 includes a gate dielectric layer 13a, a gate 13b, an isolation layer 13c, and sidewalls 13d. The gate dielectric layer 13a is made of one or a combination of an oxide layer and a hafnium oxide layer. Hafnium oxide material, due to its high dielectric constant, can effectively improve gate leakage current. The oxide layer can be formed by thermal oxidation or by atomic layer deposition. To prevent hafnium ions from entering the gate 13b, a barrier layer (not shown) is usually formed on the gate dielectric layer 13a. The barrier layer is made of, for example, titanium nitride. An isolation layer 13c is also formed on the gate 13b, and the isolation layer 13c is made of silicon nitride and / or silicon oxide. Sidewalls 13d are formed on the sidewalls of the gate 13b. The structure of the NMOS device 13 is the same as that of the PMOS device 14. A germanium-silicon stress layer 15b is formed in the substrate 10 on both sides of the PMOS device 14, and a source region 15a and a drain region are formed in the substrate 10 on both sides of the NMOS device 13.
[0039] like Figure 4As shown, an etch stop layer 16 is formed, which covers the top surface, sidewalls, and substrate 10 between adjacent PMOS devices 14 and NMOS devices 13. The etch stop layer 16 has a target tensile stress and a target dielectric constant, wherein the target tensile stress is greater than the standard tensile stress and the target dielectric constant is less than the standard dielectric constant. The material of the etch stop layer 16 is, for example, SiCN. The standard tensile stress and standard dielectric constant are those of SiN in the prior art. The target tensile stress of the etch stop layer 16 is 1.5 GPa to 2.5 GPa. The target dielectric constant of the etch stop layer 16 is 3.8 to 5; in this embodiment, the dielectric constant of SiCN can be controlled to around 4. In this embodiment, the material of the etch stop layer is replaced from SiN with SiCN. While maintaining tensile stress, SiCN reduces the dielectric constant from 7 (SiN) to 3.8, significantly reducing parasitic capacitance. This means that this embodiment can effectively improve signal transmission speed and reduce power consumption without affecting the original functions of the device. The etch stop layer 16 includes a body region 16a and a surface layer 16b. The tensile stress in the body region 16a is less than that in the surface layer 16b, achieving high stress in the surface layer and stable stress in the body region, reducing the risk of interface delamination and the density of interface defects. The carbon content in the body region of the etch stop layer 16 is less than that in the surface layer. By controlling the carbon content in the body and surface regions of the etch stop layer, the tensile stress in both regions can be controlled. Specifically, the etch stop layer 16 can be formed using a PECVD process. The PECVD process includes a first process stage and a second process stage. The first process stage is used to form the body region 16a of the etch stop layer, and the second process stage is used to form the surface layer 16b of the etch stop layer. The carbon content of the body region 16a and the surface layer 16b of the etch stop layer is different. The CH4 / N2 ratio in the process gases SiH4, CH4, and N2 of the first stage is less than the CH4 / N2 ratio in the process gases SiH4, CH4, and N2 of the second stage. The gas flow rates of SiH4 / CH4 / N2 in the first stage process gases are 10 sccm, 1 sccm, and 30 sccm, respectively, and the SiH4 / CH4 / N2 ratio is, for example, 10:1:30. The gas flow rates of SiH4 / CH4 / N2 in the second stage process gases are 10 sccm, 3 sccm, and 50 sccm, respectively, and the SiH4 / CH4 / N2 ratio is, for example, 10:3:50. Therefore, the carbon content of the body region 16a of the etch stop layer is less than the carbon content of the surface layer 16b of the etch stop layer.
[0040] like Figure 5As shown, a dielectric layer 17 is formed, which covers the etch stop layer 16. Since the height of the gate is higher than that of the substrate, the height of the dielectric layer 17 on the gate is also higher than that of the dielectric layer 17 on the substrate 10. The material of the dielectric layer 17 is, for example, silicon oxide, which can be formed by a chemical vapor deposition process.
[0041] like Figure 6 As shown, a chemical mechanical polishing (CMP) process is performed, stopping at the etch stop layer 16 on the gate, so that the top surface of the dielectric layer 17 on the substrate between adjacent gates is flush with the top surface of the etch stop layer 17 on the gate. That is, in the CMP process, the etch stop layer 16 serves as the stop layer for the CMP process.
[0042] like Figure 7 As shown, an etching process is performed to etch the etch stop layer 16 on the gate to expose the top surface of the gate. The etching process includes dry etching and wet etching. Specifically, a dry etching process is first used to remove most of the etch stop layer 16 on the gate. The etching gases include CF4, O2, and He. The etching gas ratio (CF4 / O2 / He) is, for example, 3:1:5, where CF4 is the main etching gas, O2 is used to improve the selectivity, and He dilutes the plasma density. In the dry etching process, the etch selectivity ratio of SiCN and SiO2 is greater than 15:1, which can protect the substrate 10 while removing 90% of the SiCN layer. After the dry etching process, a portion of the etch stop layer 16 will remain on the gate. A wet etching process is used to remove the remaining portion of the etch stop layer 16. The solution used in the wet etching process is a DHF solution, specifically including HF, H2O, and H2O2. The ratio of HF:H2O:H2O2 is, for example, 1:50:5. HF is used to etch SiCN, and H2O2 is used to oxidize and remove residual C and F-containing polymers. In the wet etching process, the etching selectivity ratio of SiCN and SiO2 is greater than 50:1 to protect the substrate 10 from being etched.
[0043] After removing the etch stop layer 16 on the gate, the isolation layer 13c and the gate 13b are removed to replace them with a metal gate. Those skilled in the art know how to replace the dummy gate with a metal gate, so it will not be described in detail here.
[0044] In summary, in the MOS device provided by this invention, the MOS device includes a substrate and a gate located on the substrate. Sidewalls are formed on both sides of the gate. An etch stop layer is disposed on the top surface of the gate, the sidewalls, and the substrate between adjacent gates. The etch stop layer has a target tensile stress and a target dielectric constant, wherein the target tensile stress is greater than the standard tensile stress and the target dielectric constant is less than the standard dielectric constant. The etch stop layer includes a body region and a surface layer, and the tensile stress in the body region of the etch stop layer is less than the tensile stress in the surface layer of the etch stop layer. The etch stop layer in this invention has a target tensile stress and a target dielectric constant, wherein the target tensile stress is greater than the standard tensile stress and the target dielectric constant is less than the standard dielectric constant. The standard tensile stress and standard dielectric constant are the tensile stress and dielectric constant of etch stop layers in the prior art; that is, the tensile stress of the etch stop layer in this invention is greater than the tensile stress of the etch stop layer in the prior art, and the dielectric constant of the etch stop layer in this invention is less than the dielectric constant of the etch stop layer in the prior art. This invention can improve the stress characteristics of the etch stop layer while effectively reducing the dielectric constant and thus the parasitic capacitance of the device, thereby increasing the signal transmission speed of the device, increasing the operating frequency of the device and the entire integrated circuit, and reducing power consumption.
[0045] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.
Claims
1. A MOS device, characterized in that, include: Substrate; A gate, the gate being located on the substrate; Sidewalls, the sidewalls being located on both sides of the gate and covering the two sidewalls of the gate; An etch stop layer covers the top surface of the gate, sidewalls, and substrate between adjacent gates. The etch stop layer has a target tensile stress and a target dielectric constant, wherein the target tensile stress is greater than a standard tensile stress and the target dielectric constant is less than a standard dielectric constant. The etch stop layer includes a body region and a surface layer, and the tensile stress in the body region of the etch stop layer is less than the tensile stress in the surface layer of the etch stop layer.
2. The MOS device according to claim 1, characterized in that, The etching stop layer is made of SiCN, and the carbon content in the body region of the etching stop layer is less than the carbon content in the surface layer of the etching stop layer.
3. The MOS device according to claim 1, characterized in that, The target tensile stress of the etching stop layer is 1.5 GPa to 2.5 GPa.
4. The MOS device according to claim 1, characterized in that, The target dielectric constant of the etch stop layer is 3.8 to 5.
5. A method for forming a MOS device, characterized in that, include: A substrate is provided on which a gate and sidewalls located on both sides of the gate are formed; An etch stop layer is formed, the etch stop layer covering the top surface of the gate, the sidewalls and the substrate between adjacent gates, the etch stop layer having a target tensile stress and a target dielectric constant, the target tensile stress being greater than a standard tensile stress and the target dielectric constant being less than a standard dielectric constant, the etch stop layer comprising a body region and a surface layer, and the tensile stress of the body region of the etch stop layer being less than the tensile stress of the surface layer of the etch stop layer.
6. The method for forming a MOS device according to claim 5, characterized in that, The etching stop layer is formed using a PECVD process.
7. The method for forming a MOS device according to claim 6, characterized in that, The PECVD process includes a first process stage and a second process stage. The first process stage is used to form the body region of the etch stop layer, and the second process stage is used to form the surface layer of the etch stop layer. The carbon content of the body region and the surface layer of the etch stop layer are different.
8. The method for forming a MOS device according to claim 7, characterized in that, The CH4 / N2 ratio in the process gases SiH4, CH4, and N2 of the first stage is less than the CH4 / N2 ratio in the process gases SiH4, CH4, and N2 of the second stage.
9. The method for forming a MOS device according to claim 7 or 8, characterized in that, The carbon content in the body region of the etch stop layer is less than the carbon content in the surface layer of the etch stop layer.
10. The method for forming a MOS device according to claim 5, characterized in that, After the step of forming the etch stop layer: A dielectric layer is formed, which covers the etch stop layer; Perform a chemical mechanical polishing process and stop on the etch stop layer on top of the gate so that the top surface of the dielectric layer on the substrate between adjacent gates is flush with the top surface of the etch stop layer on top of the gate; An etching process is performed to etch the etch stop layer on top of the gate to expose the top surface of the gate.