SiC power MOSFET device and preparation method thereof

Abstract

The invention provides a SiC power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a preparation method thereof, and relates to the technical field of wide bandgap semiconductor devices. When the SiC power MOSFET device bears off-state voltage, a large electric field can be generated at the gate oxide, after the P-type shielding cap is added, a PN junction can be formed by the P-type shielding cap and the N-type drift region, due to the fact that the PN junction is formed, most of power lines at the original gate oxide can be attracted to the interface of the P-type shielding cap and the N-type drift region by a space charge region of the P-type shielding cap, and therefore the shielding effectiveness is achieved, and the performance of the device is improved. And the gate-oxide reliability and the working life of the device are effectively improved. In order to prevent the potential floating of the P-type shielding cap from influencing the shielding performance of the P-type shielding cap, the P-type shielding cap is respectively connected with the first P-type base region and the second P-type base region, so that the good shielding effectiveness of the P-type shielding cap and the working performance of the SiC power MOSFET device are ensured.

Description

Technical Field

[0001] This application relates to the field of wide bandgap semiconductor device technology, and in particular to a SiC power MOSFET device and its fabrication method. Background Technology

[0002] Due to their excellent properties such as high breakdown field strength and high thermal conductivity, SiC power devices based on silicon carbide (chemical formula SiC) materials are widely used in electric vehicles and related fields.

[0003] Among various SiC power devices, SiC power MOSFETs (Metal / Oxide / Semiconductor Field Effect Transistors) are more suitable for high-density and high-power conversion applications due to their advantages of high switching speed and low specific on-resistance.

[0004] Furthermore, the carbon clusters introduced during the thermal oxidation process result in a high defect density in the gate oxide layer of SiC power MOSFET devices. Therefore, the gate oxide reliability of SiC power MOSFET devices significantly impacts their operational lifespan, making the improvement of gate oxide reliability a current research hotspot. Summary of the Invention

[0005] In view of the above problems, this application provides a SiC power MOSFET device and its fabrication method, thereby improving the gate oxide reliability of the SiC power MOSFET device. The specific solution is as follows:

[0006] A first aspect of this application provides a SiC power MOSFET device, the SiC power MOSFET device comprising:

[0007] The drain N-type region and the N-type drift region located on one side of the drain N-type region; wherein the N-type drift region includes a first region and a second region and a third region located on both sides of the first region respectively;

[0008] A P-type shielding cap located on the side of the first region away from the drain N-type region;

[0009] The first P-type base region is located in the second region;

[0010] The second P-type base region is located in the third region;

[0011] Wherein, the distance between the lower surface of the P-type shield cap and the upper surface of the drain N-type region is L1, and the distance between the upper surfaces of the first P-type base region and the second P-type base region and the upper surface of the drain N-type region is L2, where L1 > L2; the P-type shield cap is connected to the first P-type base region and the second P-type base region respectively.

[0012] Preferably, in the above-mentioned SiC power MOSFET device, the SiC power MOSFET device further includes:

[0013] The drain electrode located on the side of the N-type region away from the N-type drift region.

[0014] Preferably, in the above-mentioned SiC power MOSFET device, the SiC power MOSFET device further includes:

[0015] The first source N-type region is located in the first P-type base region;

[0016] The second source N-type region is located in the second P-type base region.

[0017] Preferably, in the above-mentioned SiC power MOSFET device, the SiC power MOSFET device further includes:

[0018] The source is connected to a portion of the first P-type base region and a portion of the first source N-type region, and is also connected to a portion of the second P-type base region and a portion of the second source N-type region.

[0019] Preferably, in the above-mentioned SiC power MOSFET device, the SiC power MOSFET device further includes:

[0020] A gate structure comprising a dielectric layer and a stacked gate oxide layer and a gate; a P-type shielding cap is located on the side of the gate oxide layer opposite to the gate; the dielectric layer covers the exposed surfaces of the gate oxide layer and the gate;

[0021] The gate structure covers the first region, a portion of the first P-type base region and a portion of the first source N-type region, and a portion of the second P-type base region and a portion of the second source N-type region.

[0022] Preferably, in the above-mentioned SiC power MOSFET device, the SiC power MOSFET device further includes:

[0023] The N-type drift region between the P-type shielding cap and the first P-type base region includes a first connection region, and the P-type shielding cap is connected to the first P-type base region through the first connection region.

[0024] The N-type drift region between the P-type shielding cap and the second P-type base region includes a second connection region, and the P-type shielding cap is connected to the second P-type base region through the second connection region.

[0025] Preferably, in the above-mentioned SiC power MOSFET device, the number of the first connection regions is N, N≥2, and N is a positive integer; there is a gap between two adjacent first connection regions;

[0026] The number of the second connected regions is M, M≥2, and M is a positive integer; there is a gap between two adjacent second connected regions.

[0027] Preferably, in the above-described SiC power MOSFET device, the gate structure includes a first groove that exposes a portion of the surface of the P-type shielding cap located in the first region;

[0028] The source electrode is connected to the P-type shielding cap through the first groove.

[0029] Preferably, in the above-mentioned SiC power MOSFET device, the first P-type base region includes a plurality of first sub-P-type base regions arranged at intervals, and there is a first interval region between two adjacent first sub-P-type base regions; the P-type shield and the gate structure extend to cover the first interval region; the gate structure includes a second groove, the second groove exposing a portion of the surface of the P-type shield located in the first interval region;

[0030] The second P-type base region includes a plurality of spaced-apart second sub-P-type base regions, with a second spacing region between two adjacent second sub-P-type base regions; the P-type shield and the gate structure extend to cover the second spacing region; the gate structure includes a third groove, the third groove exposing a portion of the surface of the P-type shield located in the second spacing region;

[0031] The source electrode is connected to the P-type shielding cap through the second groove and the third groove.

[0032] A second aspect of this application provides a method for fabricating a SiC power MOSFET device, the method comprising:

[0033] Provide a drain N-type region;

[0034] An N-type drift region is formed on one side of the drain N-type region; wherein the N-type drift region includes a first region, and a second region and a third region located on both sides of the first region respectively;

[0035] A P-type shielding cap is formed on the side of the first region away from the drain N-type region;

[0036] A first P-type base region is formed in the second region;

[0037] A second P-type base region is formed in the third region; wherein the distance between the lower surface of the P-type shield cap and the upper surface of the drain N-type region is L1, and the distance between the upper surfaces of the first P-type base region and the second P-type base region and the upper surface of the drain N-type region is L2, where L1 > L2; the P-type shield cap is connected to the first P-type base region and the second P-type base region respectively.

[0038] By employing the above technical solution, this application provides a SiC power MOSFET device and its fabrication method. When the SiC power MOSFET device is subjected to an off-state voltage, a large electric field is generated at the gate oxide. After adding a P-type shielding cap, the P-type shielding cap and the N-type drift region form a PN junction. The space charge region of this junction attracts most of the electric field lines from the original gate oxide to the interface between the P-type shielding cap and the N-type drift region, thereby achieving shielding effectiveness and effectively improving the gate oxide reliability and operating life of the SiC power MOSFET device. To prevent the floating potential of the P-type shielding cap from affecting its shielding performance, the P-type shielding cap is connected to the first P-type base region and the second P-type base region respectively, to ensure the operating performance of the SiC power MOSFET device. Attached Figure Description

[0039] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0040] Figure 1 A two-dimensional cross-sectional schematic diagram of a SiC power MOSFET device provided in an embodiment of the present invention;

[0041] Figure 2 A top view and a two-dimensional cross-sectional view along the AA' direction of a SiC power MOSFET device provided in an embodiment of the present invention;

[0042] Figure 3 A top view and a two-dimensional cross-sectional view along the BB' direction of a SiC power MOSFET device provided for an embodiment of the present invention;

[0043] Figure 4 A two-dimensional cross-sectional schematic diagram of another SiC power MOSFET device provided in an embodiment of the present invention;

[0044] Figure 5 A top view and a two-dimensional cross-sectional view along the CC' direction of a SiC power MOSFET device provided in an embodiment of the present invention;

[0045] Figure 6 A top view and a two-dimensional cross-sectional view along the DD' direction of a SiC power MOSFET device provided in an embodiment of the present invention;

[0046] Figure 7 A top view and a two-dimensional cross-sectional view along the EE' direction of a SiC power MOSFET device provided in an embodiment of the present invention;

[0047] Figure 8 This is a schematic flowchart illustrating a method for fabricating a SiC power MOSFET device according to an embodiment of the present invention. Detailed Implementation

[0048] The embodiments of this application are described below with reference to the accompanying drawings. The terminology used in the implementation section of this application is only for explaining specific embodiments and is not intended to limit the application. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0049] Based on the information described in the background art, reducing the electric field at the gate oxide is a feasible method to improve the gate oxide reliability of SiC power MOSFET devices.

[0050] Some existing technologies use two additional P-type epitaxial layers to partially surround the gate, successfully reducing the peak electric field at the oxide layer, increasing the device's breakdown voltage, reducing switching losses, and improving switching speed. However, this structure is limited by high manufacturing difficulty and has a turn-on knee voltage.

[0051] Based on this, the present application provides a SiC power MOSFET device and its fabrication method. The SiC power MOSFET device is a planar SiC power MOSFET device with a top P-type shielding cap structure. That is, a raised top P-type shielding cap is introduced into the SiC power MOSFET device and connected to the P-type base region. Under the condition of not affecting the resistance of the JFET region as much as possible, the shielding effect of the high electric field at the gate oxide is achieved.

[0052] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0053] It should be noted that the directional terms appearing in this invention are based on the relative positional relationships shown in the accompanying drawings and should not be taken as absolute limitations on this application.

[0054] refer to Figure 1 , Figure 1This is a two-dimensional cross-sectional schematic diagram of a SiC power MOSFET device provided in an embodiment of the present invention. The SiC power MOSFET device provided in this embodiment of the present invention includes:

[0055] The drain N-type region 11 and the N-type drift region 12 located on one side of the drain N-type region 11; wherein the N-type drift region 12 includes a first region and a second region and a third region located on both sides of the first region respectively.

[0056] A P-type shielding cap 13 located on the side of the first region away from the drain N-type region 11.

[0057] The first P-type base region 14 is located in the second region.

[0058] The second P-type base region 15 is located in the third region.

[0059] Wherein, the distance between the lower surface of the P-type shielding cap 13 and the upper surface of the drain N-type region 11 is L1, and the distance between the upper surfaces of the first P-type base region 14 and the second P-type base region 15 and the upper surface of the drain N-type region 11 is L2, where L1 > L2; the P-type shielding cap 13 is connected to the first P-type base region 14 and the second P-type base region 15 respectively.

[0060] Specifically, in the embodiments of the present invention, such as Figure 1 As shown, the SiC power MOSFET device further includes: a drain 16 located on the side of the drain N-type region 11 away from the N-type drift region 12; a first source N-type region 17 located on the first P-type base region 14; a second source N-type region 18 located on the second P-type base region 15; a source 19 connected to a portion of the first P-type base region 14 and a portion of the first source N-type region 17, and connected to a portion of the second P-type base region 15 and a portion of the second source N-type region 18; a gate structure including a dielectric layer 20 and a stacked gate oxide layer 21 and a gate 22; a P-type shielding cap 13 located on the side of the gate oxide layer 21 away from the gate 22; the dielectric layer 20 covering the exposed surfaces of the gate oxide layer 21 and the gate 22; wherein the gate structure covers the first region, a portion of the first P-type base region 14 and a portion of the first source N-type region 17, and a portion of the second P-type base region 15 and a portion of the second source N-type region 18.

[0061] As is understandable, source 19 is located on the top layer of the SiC power MOSFET device, and drain 16 is located on the back layer. Both source 19 and drain 16 are fabricated on their respective heavily doped regions using ohmic contact technology. Figure 1As shown, the drain 16 is in ohmic contact with the drain N-type region 11, and the source 19 is in ohmic contact with at least the source N-type region and the P-type base region.

[0062] The drain N-type region 11 is made of silicon carbide with a high concentration of N-type doping, which can be used as a substrate for SiC power MOSFET devices to form an ohmic contact with the drain 16.

[0063] The N-type drift region 12 is made of silicon carbide with a low concentration of N-type doping. It needs a certain thickness to meet the voltage withstand requirements and is used by SiC power MOSFET devices to withstand the off-state drain voltage in the off-state.

[0064] The first P-type base region 14 and the second P-type base region 15 are both P-type doped silicon carbide, used to form an electron inversion layer.

[0065] The first source N-type region 17 and the second source N-type region 18 are made of silicon carbide with a high concentration of N-type doping, which are used to form an ohmic contact with the source 19.

[0066] The P-type shielding cap 13 is P-type doped silicon carbide, used to shield the high electric field effect at the gate oxide; the P-type shielding cap 13 can be obtained by P-type doping and etching the N-type drift region 12.

[0067] The gate oxide layer 21 is fabricated on top of the P-type shielding cap 13. To ensure coverage of the entire active region of the channel, the gate oxide layer 21 should extend partially into the P-type base region and the source N-type region. In other words, the gate oxide layer 21 needs to fully cover the P-type base region of the channel region, while the source N-type region needs to be partially extended for coverage.

[0068] The gate 22 is fabricated on the gate oxide layer 21 and is made of polysilicon with a high concentration of N-type doping to form a MOS structure.

[0069] The dielectric layer 20 is used to isolate the gate 22 and the source 19, so it needs to cover the exposed surfaces of the gate oxide layer 21 and the gate 22 to prevent the gate 22 and the source 19 from short-circuiting.

[0070] Optionally, both the source electrode 19 and the drain electrode 16 are made of metallic materials.

[0071] As described above, the SiC power MOSFET device provided in this embodiment of the invention exhibits a large electric field at its gate oxide when subjected to an off-state voltage. After adding the P-type shielding cap 13, a PN junction is formed between the P-type shielding cap 13 and the N-type drift region 12. The space charge region of this junction attracts most of the electric field lines from the original gate oxide to the interface between the P-type shielding cap 13 and the N-type drift region 12, thereby enhancing the shielding effectiveness and significantly improving the gate oxide reliability and lifespan of the SiC power MOSFET device. To prevent the floating potential of the P-type shielding cap from affecting its shielding performance, the P-type shielding cap 13 is connected to the first P-type base region 14 and the second P-type base region 15, respectively, to ensure the operating performance of the SiC power MOSFET device.

[0072] In other words, compared with existing planar gate MOSFET devices, when a positive voltage is applied between the drain 16 and the source 19, the SiC power MOSFET device provided in this embodiment of the invention forms a PN junction between the P-type shield 13 and the N-type drift region 12. Its space charge region will transfer the electric field lines near the gate oxide layer 21 of the original planar gate MOSFET device to the P-type shield 13, thereby achieving the shielding effect of the high electric field of the gate oxide layer 21 and effectively improving the gate oxide reliability and operating life of the SiC power MOSFET device.

[0073] In an optional embodiment of the present invention, reference is made to... Figure 2 , Figure 2 This invention provides a top view and a two-dimensional cross-sectional view along the AA' direction of a SiC power MOSFET device, as shown in the following embodiment. Figure 3 , Figure 3 This invention provides a top view and a two-dimensional cross-sectional view along the BB' direction of a SiC power MOSFET device according to an embodiment of the invention. The SiC power MOSFET device provided in this embodiment of the invention also includes:

[0074] The N-type drift region 12 between the P-type shielding cap 13 and the first P-type base region 14 includes a first connection region 23, and the P-type shielding cap 13 is connected to the first P-type base region 14 through the first connection region 23.

[0075] The N-type drift region 12 between the P-type shielding cap 13 and the second P-type base region 15 includes a second connection region 24, and the P-type shielding cap 13 is connected to the second P-type base region 15 through the second connection region 24.

[0076] Specifically, in this embodiment of the invention, ion implantation is performed from the raised P-type shielding cap 13 and the exposed part of the N-type drift region 12 to the corresponding region of the P-type shielding cap 13 to form a first connection region 23 and a second connection region 24, so that the first connection region 23 is connected to the first P-type base region 14 and the second connection region 24 is connected to the second P-type base region 15, and finally the connection between the P-type shielding cap 13 and the P-type base region is completed simultaneously.

[0077] In other words, ion implantation is performed from the sidewall into the P-type shield 13 and the surrounding area until the P-type shield 13 is completely connected to the P-type base region. In other areas of the SiC power MOSFET device, the P-type shield 13 is not additionally connected to the P-type base region.

[0078] It should be noted that, Figure 2 and Figure 3 The top view shows the ion-implanted area. This is because, in the actual manufacturing process, the ion implantation coverage is relatively wide. The implanted area includes not only the first connection region 23 and the second connection region 24 located on the sidewall, but also parts of the first P-type base region 14, the first source N-type region 17, the second P-type base region 15, the second source N-type region 18, and the P-type shielding cap 13. In other words, when ion implantation is performed from the sidewall to the P-type shielding cap 13 and its vicinity, parts of the first P-type base region 14, the first source N-type region 17, the second P-type base region 15, the second source N-type region 18, and the P-type shielding cap 13 will all be ion-implanted.

[0079] Although some regions of the first P-type base region 14, the first source N-type region 17, the second P-type base region 15, the second source N-type region 18, and the P-type shielding cap 13 will be ion implanted, since the P-type base region and the P-type shielding cap are P-type doped and the source N-type region has a high N-type doping concentration, after the sidewall ion implantation is completed, the ion-implanted regions other than the first connection region 23 and the second connection region 24 on the sidewall will not be affected, and therefore will not affect the performance of the device.

[0080] Optionally, the number of the first connection regions 23 is N, where N≥2 and N is a positive integer; there is a gap between two adjacent first connection regions 23.

[0081] The number of the second connection regions 24 is M, M≥2, and M is a positive integer; there is a gap between two adjacent second connection regions 24.

[0082] Specifically, in this embodiment of the invention, since the semiconductor is not an ideal conductor and can be regarded as a resistor, for example, the P-type shield cap 13 is connected to the P-type base region in region one. However, in region two, due to the voltage drop inside the device caused by the resistance, the potential of the P-type shield cap 13 in region two may be different from that in region one. Therefore, in this application, multiple first connection regions 23 and multiple second connection regions 24 are arranged at intervals to realize the connection between the P-type shield cap 13 and multiple different positions of the first P-type base region 14, and the connection between the P-type shield cap 13 and multiple different positions of the second P-type base region 15, so as to ensure that the potential of the P-type shield cap 13 at different positions is equal to that of the P-type base region.

[0083] In other words, ion implantation should be performed from the sidewall at intervals to form a connection region, so as to ensure that the potential at different positions of the P-type shielding cap 13 is equal to that of the P-type base region.

[0084] It should be noted that the width of each connection area occupies only a small portion of the overall device width.

[0085] In an optional embodiment of the present invention, reference is made to... Figure 4 , Figure 4 This is a two-dimensional cross-sectional schematic diagram of another SiC power MOSFET device provided in an embodiment of the present invention. The gate structure of the SiC power MOSFET device provided in this embodiment includes a first groove 25, which exposes a portion of the surface of the P-type shielding cap 13 located in the first region.

[0086] The source electrode 19 is connected to the P-type shielding cap 13 through the first groove 25.

[0087] Specifically, in this embodiment of the invention, instead of ion implantation from the raised P-type shielding cap 13 and the exposed part of the N-type drift region 12 to the corresponding region of the P-type shielding cap 13 to form the first connection region 23 and the second connection region 24, the gate structure is slotted to form the first groove 25, exposing part of the surface of the P-type shielding cap 13 located in the first region, and then the source 19 is connected to the P-type shielding cap 13 through the first groove 25.

[0088] In other words, another way to achieve the connection between the P-type shielding cap 13 and the P-type base region is as follows: the P-type shielding cap 13 makes ohmic contact with the source electrode 19 through the first groove 25, and the P-type base region and the source electrode 19 also make ohmic contact, thereby achieving the connection between the P-type shielding cap 13 and the P-type base region.

[0089] It should be noted that, as Figure 4As shown, after the gate structure forms the first groove 25, the inner sidewall of the first groove 25 will expose part of the surface of the gate 22 and the gate oxide layer 21. In order to prevent the gate 22 and the source 19 from short-circuiting, this part of the exposed surface of the gate 22 and the gate oxide layer 21 also needs to be covered by the dielectric layer 20.

[0090] In an optional embodiment of the present invention, reference is made to... Figure 5 , Figure 5 This invention provides a top view and a two-dimensional cross-sectional view along the CC' direction of a SiC power MOSFET device, as shown in the following embodiment. Figure 6 , Figure 6 This invention provides a top view and a two-dimensional cross-sectional view along the DD' direction of a SiC power MOSFET device, as shown in the following embodiment. Figure 7 , Figure 7 This is a top view and a two-dimensional cross-sectional view along the EE' direction of a SiC power MOSFET device provided in an embodiment of the present invention. In the SiC power MOSFET device provided in this embodiment, the first P-type base region 14 includes a plurality of spaced-apart first sub-P-type base regions 141, with a first spacing region 26 between adjacent first sub-P-type base regions 141; the P-type shielding cap 13 and the gate structure extend to cover the first spacing region 26; the gate structure includes a second groove 27, the second groove 27 exposing a portion of the surface of the P-type shielding cap 13 located in the first spacing region 26.

[0091] The second P-type base region 15 includes a plurality of second sub-P-type base regions 151 spaced apart, with a second spacing region 28 between two adjacent second sub-P-type base regions 151; the P-type shield cap 13 and the gate structure extend to cover the second spacing region 28; the gate structure includes a third groove 29, the third groove 29 exposing a portion of the surface of the P-type shield cap 13 located in the second spacing region 28.

[0092] The source electrode 19 is connected to the P-type shielding cap 13 through the second groove 27 and the third groove 29.

[0093] Specifically, in the process of preparing the P-type shielding cap 13 in this embodiment of the invention, the P-type shielding cap 13 of the first spacing region 26 and the second spacing region 28 is retained, that is, the P-type shielding cap 13 of the first spacing region 26 and the second spacing region 28 is not etched, only the P-type shielding cap 13 of the first sub-P-type base region 141 and the second sub-P-type base region 142 is etched. After the gate oxide layer 21 and the gate 22 are formed, the preset contact position is etched to form the second groove 27 and the third groove 29. After the source 19 is formed, the source 19 can be connected to the P-type shielding cap 13 through the second groove 27 and the third groove 29.

[0094] In other words, another way to achieve the connection between the P-type shielding cap 13 and the P-type base region is as follows: the P-type shielding cap 13 makes ohmic contact with the source electrode 19 through the second groove 27 and the third groove 29, and the P-type base region and the source electrode 19 also make ohmic contact, thereby achieving the periodic connection between the P-type shielding cap 13 and the P-type base region.

[0095] It should be noted that, in order to prevent leakage current from the device, there is a certain gap between the boundary of the first source N-type region 17 and the first spacing region 26, and there is also a certain gap between the boundary of the second source N-type region 18 and the second spacing region 28.

[0096] Based on the above embodiments of the present invention, another embodiment of the present invention also provides a method for fabricating a SiC power MOSFET device, referencing... Figure 8 , Figure 8 This is a schematic flowchart illustrating a method for fabricating a SiC power MOSFET device according to an embodiment of the present invention. The method for fabricating a SiC power MOSFET device according to an embodiment of the present invention includes:

[0097] S101: Provides a drain N-type region 11.

[0098] S102: An N-type drift region 12 is formed on one side of the drain N-type region 11; wherein the N-type drift region 12 includes a first region, and a second region and a third region located on both sides of the first region respectively.

[0099] S103: A P-type shielding cap 13 is formed on the side of the first region away from the drain N-type region 11.

[0100] S104: A first P-type base region 14 is formed in the second region, and a second P-type base region 15 is formed in the third region; wherein, the distance between the lower surface of the P-type shielding cap 13 and the upper surface of the drain N-type region 11 is L1, and the distance between the upper surfaces of the first P-type base region 14 and the second P-type base region 15 and the upper surface of the drain N-type region 11 is L2, L1 > L2; the P-type shielding cap 13 is connected to the first P-type base region 14 and the second P-type base region 15 respectively.

[0101] Specifically, in this embodiment of the invention, providing a drain N-type region 11 is equivalent to providing an N-type doped silicon carbide substrate as the drain N-type region 11. Then, an intrinsic epitaxial layer is formed on the drain N-type region 11, and the intrinsic epitaxial layer is then subjected to low-concentration N-type doping via ion implantation to form an N-type drift region 12. Subsequently, P-type doping is performed on the surface of the N-type drift region 12 facing away from the drain N-type region 11 to form a full-surface P-type shielding cap 13.

[0102] for Figures 1-3 In the case of the SiC power MOSFET device shown, the P-type shield 13 of the second and third regions is completely etched away, forming a raised P-type shield 13 that retains only the first region.

[0103] At the corresponding position of the N-type drift region 12, a first P-type base region 14 and a second P-type base region 15 are formed by ion implantation using a self-aligned process.

[0104] An implantation window for the source N-type region is formed using a mask. A first source N-type region 17 is formed in the first P-type base region 14, and a second source N-type region 18 is formed in the second P-type base region 15.

[0105] Ion implantation is performed on the sidewalls of the raised P-type shielding cap 13 and the exposed part of the N-type drift region 12 to form a first connection region 23 and a second connection region 24, so that the first connection region 23 is connected to the first P-type base region 14 and the second connection region 24 is connected to the second P-type base region 15, and finally the connection between the P-type shielding cap 13 and the P-type base region is completed simultaneously.

[0106] Annealing is performed to activate the implanted ions.

[0107] The gate oxide layer 21 and gate 22 are then formed and patterned etching is performed.

[0108] A dielectric layer 20, such as silicon dioxide, is deposited to cover the exposed surfaces of the gate oxide layer 21 and the gate electrode 22, preventing the gate electrode 22 and the source electrode 19 from being short-circuited.

[0109] The dielectric layer 20 is etched to expose a portion of the surface of the first P-type base region 14, a portion of the surface of the second P-type base region 15, a portion of the surface of the first source N-type region 17, and a portion of the surface of the second source N-type region 18, forming a source ohmic contact hole.

[0110] A deposited metallic material forms an ohmic contact metal layer for forming a source 19; the source 19 is connected to the exposed portion of the first P-type base region 14 and the exposed portion of the first source N-type region 17, and is connected to the exposed portion of the second P-type base region 15 and the exposed portion of the second source N-type region 18.

[0111] An ohmic contact metal layer is formed by depositing a metallic material on the side of the drain N-type region 11 away from the N-type drift region 12, which is used to form the drain 16.

[0112] for Figure 4 In the case of the SiC power MOSFET device shown, the P-type shield 13 of the second and third regions is completely etched away, forming a raised P-type shield 13 that retains only the first region.

[0113] At the corresponding position of the N-type drift region 12, a first P-type base region 14 and a second P-type base region 15 are formed by ion implantation using a self-aligned process.

[0114] An implantation window for the source N-type region is formed using a mask. A first source N-type region 17 is formed in the first P-type base region 14, and a second source N-type region 18 is formed in the second P-type base region 15.

[0115] Annealing is performed to activate the implanted ions.

[0116] The gate oxide layer 21 and the gate 22 are formed and patterned etching is performed; the first groove 25 formed on the gate oxide layer 21 and the gate 22 exposes part of the surface of the P-type shield cap 13 located in the first region.

[0117] A dielectric layer 20, such as silicon dioxide, is deposited to cover the exposed surfaces of the gate oxide layer 21 and the gate electrode 22, preventing the gate electrode 22 and the source electrode 19 from being short-circuited.

[0118] The dielectric layer 20 is etched to expose a portion of the surface of the P-type shielding cap 13, a portion of the surface of the first P-type base region 14, a portion of the surface of the second P-type base region 15, a portion of the surface of the first source N-type region 17, and a portion of the surface of the second source N-type region 18, forming a source ohmic contact hole.

[0119] A deposited metallic material forms an ohmic contact metal layer for forming a source electrode 19; the source electrode 19 is connected to the exposed portion of the first P-type base region 14 and the exposed portion of the first source N-type region 17, and to the exposed portion of the second P-type base region 15 and the exposed portion of the second source N-type region 18, and is connected to the P-type shielding cap 13 through the first groove 25.

[0120] An ohmic contact metal layer is formed by depositing a metallic material on the side of the drain N-type region 11 away from the N-type drift region 12, which is used to form the drain 16.

[0121] for Figures 5-7 In the SiC power MOSFET device shown, the P-type shielding cap 13 in the region where the first sub-P-type base region 141 is located in the second region and the region where the second sub-P-type base region 151 is located in the third region is completely etched away, forming a raised P-type shielding cap 13 that retains only the first region, the first spacing region 26 and the second spacing region 28.

[0122] At the corresponding position of the N-type drift region 12, a first P-type base region 14 and a second P-type base region 15 are formed by ion implantation using a self-aligned process.

[0123] An implantation window for the source N-type region is formed using a mask. A first source N-type region 17 is formed in the first P-type base region 14, and a second source N-type region 18 is formed in the second P-type base region 15.

[0124] Annealing is performed to activate the implanted ions.

[0125] The gate oxide layer 21 and gate 22 are formed and patterned etching is performed. The second groove 27 formed on the gate oxide layer 21 and gate 22 exposes part of the surface of the P-type shield 13 located in the first spacing region 26, and the third groove 29 exposes part of the surface of the P-type shield 13 located in the second spacing region 28.

[0126] A dielectric layer 20, such as silicon dioxide, is deposited to cover the exposed surfaces of the gate oxide layer 21 and the gate electrode 22, preventing the gate electrode 22 and the source electrode 19 from being short-circuited.

[0127] The dielectric layer 20 is etched to expose a portion of the surface of the P-type shielding cap 13, a portion of the surface of the first P-type base region 14, a portion of the surface of the second P-type base region 15, a portion of the surface of the first source N-type region 17, and a portion of the surface of the second source N-type region 18, forming a source ohmic contact hole.

[0128] A deposited metallic material forms an ohmic contact metal layer for forming a source electrode 19; the source electrode 19 is connected to the exposed portion of the first P-type base region 14 and the exposed portion of the first source N-type region 17, and to the exposed portion of the second P-type base region 15 and the exposed portion of the second source N-type region 18, and is connected to the P-type shielding cap 13 through the second groove 27 and the third groove 29.

[0129] An ohmic contact metal layer is formed by depositing a metallic material on the side of the drain N-type region 11 away from the N-type drift region 12, which is used to form the drain 16.

[0130] The SiC power MOSFET device and its fabrication method provided by the present invention have been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

[0131] It should be noted that each embodiment in this specification focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to accordingly. As for the methods disclosed in the embodiments, since they correspond to the device structures disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the device structure section.

[0132] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that elements inherent to a process, method, article, or apparatus that comprises a list of elements, or elements inherent to such processes, methods, articles, or apparatus, are also included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0133] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A SiC power MOSFET device, characterized in that, The SiC power MOSFET device includes: The drain N-type region and the N-type drift region located on one side of the drain N-type region; wherein the N-type drift region includes a first region and a second region and a third region located on both sides of the first region respectively; A P-type shielding cap located on the side of the first region away from the drain N-type region; The first P-type base region is located in the second region; The second P-type base region is located in the third region; Wherein, the distance between the lower surface of the P-type shield cap and the upper surface of the drain N-type region is L1, and the distance between the upper surfaces of the first P-type base region and the second P-type base region and the upper surface of the drain N-type region is L2, where L1 > L2; the P-type shield cap is connected to the first P-type base region and the second P-type base region respectively.

2. The SiC power MOSFET device according to claim 1, characterized in that, The SiC power MOSFET device also includes: The drain electrode located on the side of the N-type region away from the N-type drift region.

3. The SiC power MOSFET device according to claim 1, characterized in that, The SiC power MOSFET device also includes: The first source N-type region is located in the first P-type base region; The second source N-type region is located in the second P-type base region.

4. The SiC power MOSFET device according to claim 3, characterized in that, The SiC power MOSFET device also includes: The source is connected to a portion of the first P-type base region and a portion of the first source N-type region, and is also connected to a portion of the second P-type base region and a portion of the second source N-type region.

5. The SiC power MOSFET device according to claim 4, characterized in that, The SiC power MOSFET device also includes: A gate structure comprising a dielectric layer and a stacked gate oxide layer and a gate; a P-type shielding cap is located on the side of the gate oxide layer opposite to the gate; the dielectric layer covers the exposed surfaces of the gate oxide layer and the gate; The gate structure covers the first region, a portion of the first P-type base region and a portion of the first source N-type region, and a portion of the second P-type base region and a portion of the second source N-type region.

6. The SiC power MOSFET device according to claim 5, characterized in that, The SiC power MOSFET device also includes: The N-type drift region between the P-type shielding cap and the first P-type base region includes a first connection region, and the P-type shielding cap is connected to the first P-type base region through the first connection region. The N-type drift region between the P-type shielding cap and the second P-type base region includes a second connection region, and the P-type shielding cap is connected to the second P-type base region through the second connection region.

7. The SiC power MOSFET device according to claim 6, characterized in that, The number of the first connection regions is N, N≥2, and N is a positive integer; there is a gap between two adjacent first connection regions; The number of the second connected regions is M, M≥2, and M is a positive integer; there is a gap between two adjacent second connected regions.

8. The SiC power MOSFET device according to claim 5, characterized in that, The gate structure includes a first groove that exposes a portion of the surface of the P-type shielding cap located in the first region; The source electrode is connected to the P-type shielding cap through the first groove.

9. The SiC power MOSFET device according to claim 5, characterized in that, The first P-type base region includes a plurality of first sub-P-type base regions arranged at intervals, with a first interval region between two adjacent first sub-P-type base regions; the P-type shielding cap and the gate structure extend to cover the first interval region; the gate structure includes a second groove, the second groove exposing a portion of the surface of the P-type shielding cap located in the first interval region; The second P-type base region includes a plurality of spaced-apart second sub-P-type base regions, with a second spacing region between two adjacent second sub-P-type base regions; the P-type shield and the gate structure extend to cover the second spacing region; the gate structure includes a third groove, the third groove exposing a portion of the surface of the P-type shield located in the second spacing region; The source electrode is connected to the P-type shielding cap through the second groove and the third groove.

10. A method for fabricating a SiC power MOSFET device, characterized in that, The method for fabricating the SiC power MOSFET device includes: Provide a drain N-type region; An N-type drift region is formed on one side of the drain N-type region; wherein the N-type drift region includes a first region, and a second region and a third region located on both sides of the first region respectively; A P-type shielding cap is formed on the side of the first region away from the drain N-type region; A first P-type base region is formed in the second region; A second P-type base region is formed in the third region; wherein the distance between the lower surface of the P-type shield cap and the upper surface of the drain N-type region is L1, and the distance between the upper surfaces of the first P-type base region and the second P-type base region and the upper surface of the drain N-type region is L2, where L1 > L2; the P-type shield cap is connected to the first P-type base region and the second P-type base region respectively.

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