Packaging method of photoelectric sealing structure and photoelectric sealing structure

Abstract

The invention provides a packaging method of a photoelectric sealing structure and the photoelectric sealing structure, and the method comprises the steps: forming a reconstructed wafer structure on the surface of a carrier plate, the reconstructed wafer structure is provided with a plurality of fan-out modules which are arranged at intervals, and each fan-out module comprises a plurality of electric chips which are arranged at intervals; an optical chip monomer is provided, the size of the optical chip monomer is smaller than that of each fan-out module, the first surface of the optical chip monomer is provided with a coupling structure, and an optical chip structure is installed on the surface of the rewiring layer of the reconstructed wafer structure; removing the carrier plate, and cutting the reconstructed wafer structure into a plurality of chip packaging structure monomers; and providing a substrate, and mounting the chip packaging structure monomer on the surface of the substrate. The photoelectric sealing structure is formed by using a packaging method. A plurality of electric chips form a fan-out module, an optical chip monomer is firstly mounted on the surface of the fan-out module with the electric chips, and then a chip packaging structure monomer is mounted on a substrate, so that the warping phenomenon and pseudo soldering problems generated when the optical chip monomer is mounted on the substrate are relieved.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging, and more particularly to a packaging method and an optoelectronic encapsulation structure. Background Technology

[0002] With the rapid development of information technology, emerging technologies and applications such as big data, artificial intelligence, cloud computing, and 5G communication are constantly emerging, placing unprecedented demands on the efficiency and quality of information transmission. In the field of optical communication, optical modules, as key transmission components, directly affect the operating efficiency of the entire communication system. To meet the ever-increasing demand for transmission rates and the stringent requirements for ultra-low latency, the co-packaged optical-electrical (CPO) structure has emerged and has received increasingly widespread attention and application. In traditional optical module packaging, the optical chip and the electrical chip are separate, and this discrete packaging method limits the improvement of optical module performance to some extent. The co-packaged optical-electrical (CPO) structure encapsulates the optical chip and the electrical chip in the same package, greatly shortening the conversion distance between light and electrical signals, reducing signal loss and interference during transmission, thereby significantly improving the transmission rate and reducing latency of the optical module. However, due to the specific characteristic dimensions of photonic structures, the area of ​​the optical chip in the co-packaged optical-electrical (CPO) structure is usually larger than that of the electrical chip. Given this situation, in the three-dimensional optoelectronic integrated packaging process, through-silicon vias (TSVs) are typically fabricated inside the optical chip unit. TSV technology, as an advanced semiconductor manufacturing process, can vertically create conductive channels within the optical chip unit, allowing electrical chips to be mounted on top of it. In this way, high-density interconnection can be achieved between the optical chip unit and the electrical chips, greatly improving the integration of the package and the efficiency of signal transmission. This provides strong technical support for building high-speed, high-efficiency, and low-latency optical communication systems, driving optical communication technology towards higher performance levels to better adapt to the wave of information technology development and meet the huge global demand for information transmission.

[0003] However, due to limitations in current through-silicon via (TSV) fabrication processes, optical chip units with internal TSV structures are typically relatively thin, usually not exceeding 200 micrometers. This thin design makes the optical chip unit more fragile during manufacturing and assembly. Once mounted on a substrate, the optical chip unit, due to its thinness and physical properties, is highly susceptible to warping due to substrate deformation. This warping not only affects the performance stability of the optical chip unit itself but also causes serious problems in subsequent electrical chip mounting processes. Precise alignment between the chip and the substrate is crucial in the electrical chip mounting process, and warping of the optical chip unit can lead to poor contact between them, easily causing cold solder joints. Cold solder joints not only reduce the quality of electrical connections between chips but can also cause signal instability or even interruption during device operation, significantly impacting the reliability and performance of the entire optical communication system. Even more seriously, warping of the optical chip unit can also cause deformation of internal photonic structures (such as gratings and waveguides) and coupling surfaces. Photonic structures such as gratings and waveguides require extremely high geometric precision. Even minute deformations can increase optical signal loss and cause mode distortion during transmission and coupling, leading to performance degradation of individual optical chips. Simultaneously, the coupling between optical fibers and individual optical chips requires high-precision alignment and a stable interface. Deformation of the optical chip itself can prevent precise matching between the coupling endface and the optical fiber endface, reducing coupling efficiency, compromising signal integrity, and lowering the overall performance and stability of the optical module, making it difficult to meet the demands of high-bandwidth, low-latency optical communication applications.

[0004] Therefore, providing a packaging process or structure to solve the problem of easy warping caused by the thinness of optical chip units and the resulting cold solder joint problem has become one of the key challenges in the development of current optoelectronic integrated packaging technology. Summary of the Invention

[0005] The problem this application aims to solve is to provide a packaging method and a photoelectric encapsulation structure to alleviate the warping problem of individual photoelectric chips in the photoelectric encapsulation structure and the resulting cold solder joint problem, thereby improving the fiber coupling efficiency, overall performance and stability of the photoelectric encapsulation structure.

[0006] To address the above problems, this application provides a packaging method for an optoelectronic encapsulation structure, comprising the following steps: Provide carrier board; A reconstructed wafer structure is formed on the surface of the carrier substrate. The reconstructed wafer structure has a plurality of spaced fan-out modules. Each fan-out module includes a plurality of spaced electrical chips. The active surface of the fan-out module is located on the side away from the carrier substrate. The active surface of the fan-out module has a redistribution layer. An optical chip structure is provided, the optical chip structure comprising a plurality of optical chip units, the size of each optical chip unit being smaller than the size of each fan-out module, each optical chip unit having a first surface and a second surface disposed opposite to each other, the first surface of the optical chip unit having a coupling structure, the optical chip structure being mounted on the surface of the redistribution layer, the first surface of the optical chip unit being in contact with the surface of the redistribution layer on the side away from the fan-out module; Remove the carrier board and cut the reconstructed wafer structure and optical chip structure into multiple chip package structure units. Each chip package structure unit has a fan-out module and a corresponding optical chip unit with a coupling structure. A substrate is provided, and the chip packaging structure is mounted onto the surface of the substrate, wherein the second surface of the optical chip of the chip packaging structure is disposed on the side close to the substrate.

[0007] By forming a fan-out module with multiple electrical chips, the optical chip is first mounted onto the surface of the fan-out module containing electrical chips. The optical chip is then connected to the electrical chips of the fan-out module to form a chip package structure. The chip package structure containing the optical chip is then mounted on a substrate. This alleviates the warping phenomenon that occurs when the optical chip is mounted on the substrate, as well as the cold solder joint problem caused by the warping of the optical chip. This is beneficial for maintaining the performance of the optical chip and the coupling of the fiber array.

[0008] Meanwhile, by first forming the electrical chip into a fan-out module and then connecting it to the optical chip unit, the process can avoid contamination of the coupling structure of the optical chip unit by the molding compound, further ensuring that the coupling structure of the optical chip unit is smoothly coupled to the optical fiber.

[0009] In one optional embodiment, the first surface of the optical chip unit has a first bump, the second surface of the chip has a second bump, and the radial dimension of the first bump is smaller than the radial dimension of the second bump. The optical chip unit is connected to the redistribution layer via a first bump; The optical chip unit is connected to the substrate via a second bump.

[0010] In an optional embodiment, the optical chip unit has a through-silicon via (TSV) that extends through the optical chip unit.

[0011] In an optional embodiment, the fan-out module further includes at least one dummy chip, which is spaced apart from the plurality of electrical chips.

[0012] In an optional embodiment, the specific steps for forming the reconstructed wafer structure include: A first carrier board is provided, the surface of the first carrier board having a first adhesive layer, and a plurality of electrical chips are mounted on the first adhesive layer, wherein the front side of the electrical chips is disposed on the side close to the first adhesive layer, and the front side of the electrical chips is the active side of the electrical chips. A molding compound is filled around the multiple electrical chips to form a fan-out module; A second carrier board is mounted on the back of the electrical chip. The surface of the second carrier board has a second adhesive layer, which is located on the side of the second carrier board near the back of the electrical chip. Remove the first carrier plate and the first adhesive layer to make the second carrier plate a carrier plate for reconstructing the wafer structure; A redistribution layer is formed on the active surface of the fan-out module.

[0013] In an optional embodiment, when forming the reconstructed wafer structure, a back gold layer is further formed on the back side of the fan-out module, the back gold layer being located between the second adhesive layer and the fan-out module.

[0014] The back gold layer can provide uniform heat dissipation and cooling for multiple electrical chips in the fan-out module. At the same time, the back gold layer and the fan-out module are formed together first. When the optical chip is connected to the surface of the electrical chip, it can also work with the fan-out module to suppress the warping problem of the optical chip.

[0015] In one optional embodiment, the back gold layer is a copper metal layer, an aluminum metal layer, a nickel metal layer, a titanium metal layer, or an alloy layer, wherein the alloy layer is an alloy layer formed of any two or more metals selected from copper, aluminum, nickel, and titanium.

[0016] In an optional embodiment, after filling the outer side of the plurality of electrical chips with molding compound to form a fan-out module, the molding compound is further thinned so that the back side of the electrical chips is exposed outside the molding compound. The gold backing layer is applied to the back of the thinned fan-out module.

[0017] In one alternative embodiment, the back sides of the plurality of electrical chips are located on the same plane, and the back sides of the plurality of electrical chips form the back side of the fan-out module.

[0018] In an optional embodiment, the redistribution layer has a first surface and a second surface disposed opposite to each other; The first surface has a first pad, which is used to connect to the active surface of the electrical chip; The second surface has a second pad for connecting to a first bump of the optical chip unit.

[0019] In one optional embodiment, the active surfaces of multiple electrical chips are located on the same plane, and the active surfaces of the multiple electrical chips form the active surfaces of the fan-out module.

[0020] In an optional embodiment, after forming the redistribution layer, a mounting groove is further formed on the reconstructed wafer structure for mounting optical fibers on the coupling structure of the optical chip unit.

[0021] In an optional embodiment, when the optical chip structure is mounted onto the surface of the redistribution layer, the coupling structure of the optical chip unit is configured to correspond to the mounting slot.

[0022] In an alternative embodiment, a mounting groove is formed on the reconstructed wafer structure using a laser cutting process.

[0023] In one optional embodiment, the mounting slot extends at least through the redistribution layer, the fan-out module, and the back gold layer.

[0024] In an optional embodiment, the radial dimension of the mounting groove is greater than or equal to the radial dimension of the coupling structure.

[0025] In one optional embodiment, the mounting groove is a closed mounting groove or an edge-opening mounting groove.

[0026] In an optional embodiment, when the mounting slot is a closed mounting slot, the coupling structure of the optical chip unit is a vertical grating coupling structure.

[0027] In an optional embodiment, when the mounting groove is an edge-opening mounting groove, the coupling structure of the optical chip unit is an edge grating coupling structure or a vertical grating coupling structure.

[0028] By forming mounting grooves on the reconstructed wafer structure before mounting the optical chip unit onto the fan-out module surface, and by controlling the structural form of the mounting grooves (closed mounting grooves or edge-opening mounting grooves), the packaging method of the optoelectronic encapsulation structure provided in this application can be applied to both optical chip units with edge grating coupling structures and optical chip units with vertical grating coupling structures.

[0029] In an optional embodiment, after the optical chip unit is mounted onto the substrate surface, the process further includes an optical fiber coupling step, the optical fiber coupling step comprising: Provide fiber optic cables; The optical fiber is installed onto the surface of the coupling structure through the mounting slot and forms an optical fiber coupling with the coupling structure.

[0030] In an optional embodiment, when the optical chip structure is mounted onto the surface of the redistribution layer, the first bump on the first surface of the optical chip unit contacts the second pad on the second surface of the redistribution layer. It also includes filling the space between the first surface of the optical chip unit and the second surface of the redistribution layer to form a first bottom fill layer.

[0031] In an optional embodiment, when the chip package structure is mounted onto the substrate surface, the second bump on the second surface of the optical chip unit contacts the substrate surface; It also includes filling the space between the second surface of the optical chip unit and the substrate with a bottom filler to form a second bottom filler layer.

[0032] In an optional embodiment, the size of the substrate is larger than the size of the chip package structure unit.

[0033] In one optional embodiment, after the chip packaging structure is mounted onto the surface of the substrate, a packaging cover is formed on the surface of the substrate, and the packaging cover is disposed on the back gold layer surface of the chip packaging structure.

[0034] In one optional embodiment, the encapsulation cover is a copper encapsulation cover, and the optoelectronic encapsulation structure can dissipate heat through the encapsulation cover.

[0035] In an alternative embodiment, the encapsulation cover has a notch corresponding to the mounting slot of the fan-out module.

[0036] In an optional embodiment, a thermal interface material layer is formed between the back gold layer and the encapsulation cover.

[0037] In one optional embodiment, the thermal interface material layer is a thermal grease thermal interface material layer.

[0038] This application also provides an optoelectronic sealing structure, including: substrate; An optical chip unit is disposed on the surface of the substrate, and the surface of the optical chip unit away from the substrate is the first surface of the optical chip unit, and the first surface of the optical chip unit has a coupling structure; A fan-out module, comprising a plurality of spaced electrical chips, wherein the fan-out module is disposed on the first surface of the optical chip unit via a redistribution layer, and the size of the fan-out module is larger than the size of the optical chip unit.

[0039] In an optional embodiment, an encapsulation cover is also included, wherein the size of the substrate is larger than the size of the fan-out module; The encapsulation cover is disposed on the surface of the substrate and covers the surface of the fan-out module.

[0040] In an optional embodiment, the fan-out module also has a back gold layer formed on the surface away from the optical chip unit, the back gold layer being adjacent to the back of the electrical chip.

[0041] In actual use, thermal interface material layers are respectively provided between the encapsulation cover and the back gold layer, and between the encapsulation cover and the substrate.

[0042] In an optional embodiment, the fan-out module has a mounting slot, which is correspondingly disposed to the coupling structure of the first surface of the optical chip unit, and the radial dimension of the mounting slot is greater than or equal to the radial dimension of the coupling structure; In an optional embodiment, an optical fiber is further included, which is located within the mounting groove and disposed on the surface of the coupling structure.

[0043] In one optional embodiment, the mounting groove is a closed mounting groove or an edge-opening mounting groove; When the mounting slot is a closed mounting slot, the coupling structure of the optical chip unit is a vertical grating coupling structure, and the optical fiber is arranged perpendicularly to the first surface of the optical chip unit. When the mounting slot is an edge-opening type mounting slot, the coupling structure of the optical chip unit is an edge grating coupling structure, and the optical fiber is arranged to coincide with or parallel to the first surface of the optical chip unit; or, the coupling structure of the optical chip unit is a vertical grating coupling structure, and the optical fiber is arranged perpendicular to the first surface of the optical chip unit.

[0044] In an optional embodiment, the fan-out module further includes at least one dummy chip, which is spaced apart from the plurality of electrical chips.

[0045] In one optional embodiment, the first surface of the optical chip unit has a first bump, the second surface of the chip has a second bump, and the radial dimension of the first bump is smaller than the radial dimension of the second bump. The optical chip unit is connected to the redistribution layer via a first bump; The optical chip unit is connected to the substrate via a second bump.

[0046] In an optional embodiment, the optical chip unit has a through-silicon via (TSV) that extends through the optical chip unit.

[0047] The advantages of the technical solution in this application are: This application first encapsulates multiple electrical chips to form a fan-out module. Then, an optical chip is mounted onto the surface of the fan-out module containing the electrical chips via a first bump with a small radial dimension. This connects the optical chip to the electrical chips in the fan-out module, forming a chip package structure. When the optical chip is mounted onto the surface of the fan-out module via the first bump, the fan-out module is fixed to the surface of the second substrate by a second adhesive layer, resulting in minimal warpage. This also minimizes the risk of cold solder joints during the soldering process due to the small diameter of the first bump. Finally, the chip package structure containing the optical chip is mounted onto the substrate, mitigating the warpage phenomenon caused when the optical chip is mounted onto the substrate, as well as the cold solder joint problems caused by the warpage of the optical chip. This is beneficial for maintaining the performance of the optical chip and the coupling of the fiber array.

[0048] Furthermore, the fan-out module is equipped with dummy chips. When the sum of the sizes of multiple electrical chips is also smaller than the size of a single optical chip, by adding dummy chips, the warping problem of the single optical chip can be suppressed by adjusting the warping of the fan-out module, while ensuring the stress parameters, bonding performance, and heat dissipation performance of the fan-out module.

[0049] Furthermore, the surface of the fan-out module has a back gold layer, which can evenly heat and dissipate heat for the multiple electrical chips in the fan-out module. At the same time, the back gold layer is formed together with the fan-out module. When the optical chip is connected to the surface of the electrical chip, it can also work with the fan-out module to suppress the warping problem of the optical chip.

[0050] Meanwhile, by first forming the electrical chip into a fan-out module and then connecting it to the optical chip unit, the molding compound can be used to avoid contaminating the coupling structure of the optical chip unit, thus ensuring that the coupling structure of the optical chip unit is successfully coupled to the optical fiber.

[0051] The packaging method for the optoelectronic co-packaging structure provided in this application can be applied to both edge grating coupled structure and vertical grating coupled structure optical chip units. Attached Figure Description

[0052] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In addition, in the following drawings, the components are not necessarily drawn to scale, and components with similar related characteristics or features may have the same or similar reference numerals.

[0053] Figure 1 This is a schematic diagram of the optical chip structure in one embodiment of this application; Figure 2This is a schematic diagram of the structure of the electronic chip and the dummy chip in one embodiment of this application; Figure 3 This is a schematic diagram of the structure in one embodiment of the present application, showing the electric chip and the dummy chip disposed on the first carrier board; Figure 4 This is a schematic diagram of a fan-out module formed by filling the outer side of the electronic chip and the dummy chip with molding compound in one embodiment of this application; Figure 5 This is a schematic diagram of a structure for thinning the molding compound in one embodiment of this application; Figure 6 This is a schematic diagram of the structure in one embodiment of the present application where a back gold layer is formed on the back of the fan-out module; Figure 7 This is a schematic diagram of a structure in which a second carrier plate is formed on the surface of the back gold layer in one embodiment of this application; Figure 8 This is a schematic diagram of the structure for removing the first carrier plate in one embodiment of this application; Figure 9 This is a schematic diagram of a redistribution layer formed on the active surface of a fan-out module in one embodiment of this application; Figure 10 This is a schematic diagram of the structure forming the mounting groove in one embodiment of this application; Figure 11 for Figure 10 A schematic diagram of the cross-sectional structure along the cutting line A1-A2; Figure 12 This is a schematic diagram of an optical chip structure formed on the surface of a redistribution layer in one embodiment of this application; Figure 13 This is a schematic diagram of the structure forming the first bottom filling layer in one embodiment of this application; Figure 14 This is a schematic diagram of the structure for removing the second carrier plate in one embodiment of this application; Figure 15 This is a schematic diagram of a chip packaging structure unit mounted on the surface of a substrate in one embodiment of this application; Figure 16 This is a schematic diagram of the structure forming the optical fiber and the encapsulation cover in one embodiment of this application; Figure 17 This is a schematic diagram of the structure forming the mounting groove in another embodiment of this application; Figure 18 for Figure 17 A schematic diagram of the cross-sectional structure along the cutting line B1-B2; Figure 19 This is a schematic diagram of a light chip structure formed on the surface of a redistribution layer in another embodiment of this application; Figure 20 This is a schematic diagram of the structure forming the first bottom filling layer in another embodiment of this application; Figure 21 This is a schematic diagram of the structure for removing the second carrier plate in another embodiment of this application; Figure 22 This is a schematic diagram of a chip packaging structure unit mounted on the surface of a substrate in another embodiment of this application; Figure 23 This is a schematic diagram of the structure forming the optical fiber and the encapsulation cover in another embodiment of this application; Figure 24 This is a schematic flowchart of a packaging method for an optoelectronic encapsulation structure in one embodiment of this application.

[0054] The labels for the attached figures are as follows: 100, Carrier board; 110, First carrier board; 120, First adhesive layer; 130, Second carrier board; 140, Second adhesive layer; 150, Thermal interface material layer; 200, Reconstructed wafer structure; 201, Mounting slot; 202, Active surface; 210, Fan-out module; 211, Electrical chip; 212, Molding compound; 213, Dummy chip; 220, Redistribution layer; 221, First pad; 222, Second pad; 230, Back gold layer; 300, Optical chip structure; 310, Optical chip unit; 311, Coupling structure; 312, First bump; 313, Second bump; 314, Through-Silicon via; 320, First bottom filler layer; 330, Second bottom filler layer; 400, Chip package structure unit; 500, Substrate; 600, Optical fiber; 700, Package cap; 701, Notch. Detailed Implementation

[0055] To make the technical problems, technical solutions and beneficial effects to be solved by this application clearer, the following describes this application in further detail with reference to the accompanying drawings and embodiments.

[0056] In the description of this application, it should be noted that the use of terms such as "first" and "second" to define objects (such as elements, components, regions, layers, doping types and / or parts) is merely for the purpose of distinguishing different objects and is not necessarily used to describe a specific order or sequence. Unless the context clearly indicates otherwise, it should be understood that such data can be used interchangeably where appropriate.

[0057] In the description of this application, it should be understood that the singular forms “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “compose” and / or “comprise” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0058] In the description of this application, it should also be noted that when a component is referred to as "on another component," "connected to another component," or "in contact with another component," it can mean not only that a component is directly on, directly connected to, or directly in contact with the other component, but also that an intermediate component can be inserted between the two components. Furthermore, "connection" includes not only fixed connections but also detachable connections or integral connections. Similarly, when an element is referred to as "electrically connected," "electrically contacted," "electrically coupled," or "electrically coupled to" another element, the two elements can be in direct electrical contact or electrical coupling, or they can be in electrical contact or electrical coupling through an intermediate component.

[0059] In the description of this application, it should also be noted that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0060] Furthermore, in the description of this application, spatial relation terms such as "below," "under," "below," "below," "below," "above," "on the upper surface of," "above," etc., can be used to describe the spatial positional relationship between one element or feature shown in the figures and other elements or features. It should be understood that spatial relation terms, in addition to the orientation shown in the figures, also include different orientations of elements or features in use and operation. For example, if an element or feature in the figures is flipped or inverted, an element or feature described as "below" or "below" other elements or features will be oriented "above" other elements or features. Furthermore, elements may also include other orientations (e.g., rotated by an angle or other orientations).

[0061] This application provides a packaging method and a photoelectric encapsulation structure for an optoelectronic encapsulation structure, in conjunction with reference to [reference]. Figures 1-24 ,in Figure 1 This is a schematic diagram of the optical chip structure in one embodiment of this application; Figure 2 This is a schematic diagram of the structure of the electronic chip and the dummy chip in one embodiment of this application; Figure 3 This is a schematic diagram of the structure in one embodiment of the present application, showing the electric chip and the dummy chip disposed on the first carrier board; Figure 4 This is a schematic diagram of a fan-out module formed by filling the outer side of the electronic chip and the dummy chip with molding compound in one embodiment of this application; Figure 5 This is a schematic diagram of a structure for thinning the molding compound in one embodiment of this application; Figure 6 This is a schematic diagram of the structure in one embodiment of the present application where a back gold layer is formed on the back of the fan-out module; Figure 7 This is a schematic diagram of a structure in which a second carrier plate is formed on the surface of the back gold layer in one embodiment of this application; Figure 8 This is a schematic diagram of the structure for removing the first carrier plate in one embodiment of this application; Figure 9 This is a schematic diagram of a redistribution layer formed on the active surface of a fan-out module in one embodiment of this application; Figure 10 This is a schematic diagram of the structure forming the mounting groove in one embodiment of this application; Figure 11 for Figure 10 A schematic diagram of the cross-sectional structure along the cutting line A1-A2; Figure 12 This is a schematic diagram of an optical chip structure formed on the surface of a redistribution layer in one embodiment of this application; Figure 13 This is a schematic diagram of the structure forming the first bottom filling layer in one embodiment of this application; Figure 14 This is a schematic diagram of the structure for removing the second carrier plate in one embodiment of this application; Figure 15 This is a schematic diagram of a chip packaging structure unit mounted on the surface of a substrate in one embodiment of this application; Figure 16 This is a schematic diagram of the structure forming the optical fiber and the encapsulation cover in one embodiment of this application; Figure 17 This is a schematic diagram of the structure forming the mounting groove in another embodiment of this application; Figure 18 for Figure 17 A schematic diagram of the cross-sectional structure along the cutting line B1-B2; Figure 19 This is a schematic diagram of a light chip structure formed on the surface of a redistribution layer in another embodiment of this application; Figure 20 This is a schematic diagram of the structure forming the first bottom filling layer in another embodiment of this application; Figure 21 This is a schematic diagram of the structure for removing the second carrier plate in another embodiment of this application; Figure 22 This is a schematic diagram of a chip packaging structure unit mounted on the surface of a substrate in another embodiment of this application; Figure 23 This is a schematic diagram of the structure forming the optical fiber and the encapsulation cover in another embodiment of this application; Figure 24This is a schematic flowchart illustrating the packaging method of the optoelectronic encapsulation structure in one embodiment of this application; please refer to... Figure 10 , Figures 13-15 as well as Figure 24 The packaging method for optoelectronic composite structures includes the following steps: S100. Provides carrier board 100; S200. A reconstructed wafer structure 200 is formed on the surface of the carrier 100. The reconstructed wafer structure 200 has a plurality of spaced fan-out modules 210. Each fan-out module 210 includes a plurality of spaced electrical chips 211. The active surface 202 of the fan-out module 210 is disposed on the side away from the carrier 100. The active surface 202 of the fan-out module 210 has a redistribution layer 220. S300. Provides an optical chip structure 300, which includes a plurality of optical chip units 310. The radial dimension of each optical chip unit 310 is smaller than the radial dimension of each fan-out module 210. Each optical chip unit 310 has a first surface and a second surface disposed opposite to each other. The first surface of the optical chip unit 310 has a coupling structure 311. The optical chip structure 300 is mounted on the surface of the redistribution layer 220. The first surface of the optical chip unit 310 is in contact with the surface of the redistribution layer 220 on the side away from the fan-out module 210. S400. Remove the carrier board 100 and cut the reconstructed wafer structure 200 and optical chip structure 300 into multiple chip package structure units 400. Each chip package structure unit 400 has a fan-out module 210 and a corresponding optical chip unit 310 with a coupling structure 311. S500. A substrate 500 is provided, and a chip packaging structure unit 400 is mounted on the surface of the substrate 500. The second surface of the optical chip unit 310 of the chip packaging structure unit 400 is disposed on the side close to the substrate 500.

[0062] A fan-out module 210 is formed by multiple electrical chips 211. First, an optical chip unit 310 is mounted on the surface of the fan-out module 210 with electrical chips 211. The optical chip unit 310 is then connected to the electrical chips 211 of the fan-out module 210 to form a chip package structure unit 400. Then, the chip package structure unit 400 with optical chip unit 310 is mounted on the substrate 500. This alleviates the warping phenomenon between the substrate 500 and the optical chip unit 310 after the optical chip unit 310 is mounted on the substrate 500, and also reduces the soldering problems caused by the warping of the surface of the optical chip unit 310 when the electrical chips 211 are subsequently packaged onto the surface of the optical chip unit 310. This is beneficial for maintaining the performance of the optical chip and the coupling of the fiber optic array 600.

[0063] Meanwhile, by first forming the electrical chip 211 into a fan-out module 210 and then connecting it to the optical chip unit 310, the molding compound 212 can be prevented from contaminating the coupling structure 311 of the optical chip unit 310, thus further ensuring the packaging quality.

[0064] Please refer to Figure 1 and Figure 12 In one embodiment, the first surface of the optical chip unit 310 has a first bump 312, and the second surface of the optical chip unit 310 has a second bump 313. The radial dimension of the first bump 312 is smaller than the radial dimension of the second bump 313. The optical chip unit 310 is connected to the redistribution layer 220 through the first bump 312; The optical chip unit 310 is connected to the substrate 500 through the second bump 313.

[0065] In actual use, the first bump 312 and the second bump 313 can be solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, etc.

[0066] In traditional packaging methods, the optical chip is first soldered onto the substrate. Due to the difference in thermal expansion coefficients between the optical chip and the substrate, the optical chip will warp along with the substrate (either towards the first bump 312 or towards the second bump 313). Since the diameter of the first bump 312 is small, the optical chip is more prone to cold solder joints on the side of the first bump 312 when soldering with the electrical chip. This application addresses this issue by first packaging the optical chip unit 310 and the fan-out module 210 together using the first bump 312 with a smaller radial dimension, and then connecting the optical chip unit 310 to the substrate 500 using the second bump 313 with a larger radial dimension. This further alleviates the cold solder joint problem on the side of the first bump 312 with a smaller radial dimension caused by the warping of the optical chip unit 310 along with the substrate 500 in the existing process.

[0067] In one embodiment, the optical chip unit 310 has a through silicon via 314, which is disposed through the optical chip unit 310.

[0068] In one specific embodiment, the first bump 312 and the second bump 313 can be respectively disposed at both ends of the through silicon via 314.

[0069] In another embodiment, the optical chip unit 310 has a first bump 312 or a second bump 313 on one side of the through silicon via 314, and a redistribution layer is provided on the other side of the through silicon via 314.

[0070] In another embodiment, the first and second surfaces of the optical chip unit 310 both have redistribution layers, and the first bump 312 and the second bump 313 are electrically connected by the redistribution layers and through silicon vias. The first bump 312 and the second bump 313 are asymmetrically arranged.

[0071] In one embodiment, the fan-out module 210 further includes at least one dummy chip 213, which is spaced apart from a plurality of electrical chips 211.

[0072] In practical applications, the size of existing electrical chips is smaller than that of the optical chip unit. Even when the size of multiple electrical chips is smaller than that of the optical chip unit, depending on the required number of electrical chips, if the remaining space in the fan-out module 210 is completely filled with molding compound, the difference in thermal expansion coefficients between the molding compound and the electrical chips will cause variations in the positions where electrical chips are present and those where they are not, resulting in warping of the fan-out module. When the size of multiple electrical chips is also smaller than that of the optical chip unit, by adding dummy chips 213, the warping of the optical chip unit 310 can be suppressed by controlling the warping of the fan-out module 210, while ensuring the stress parameters, bonding performance, and heat dissipation performance of the fan-out module 210.

[0073] In actual use, the electrical chip 211 is a transimpedance amplifier chip (TIA), a driver chip (DRV), or an application-specific integrated circuit chip (ASIC).

[0074] Please refer to Figures 1-11 In one embodiment, the specific steps for forming the reconstructed wafer structure 200 include: A first carrier board 110 is provided, and the surface of the first carrier board 110 has a first adhesive layer 120. A plurality of electrical chips 211 are attached to the first adhesive layer 120. The front side of the electrical chips 211 is disposed on the side close to the first adhesive layer 120, and the front side of the electrical chips 211 is the active surface 202 of the electrical chips 211. A molding compound 212 is filled on the outside of multiple electrical chips 211 to form a fan-out module 210. A second carrier plate 130 is mounted on the back of the electrical chip 211. The surface of the second carrier plate 130 has a second adhesive layer 140, which is located on the side of the second carrier plate 130 near the back of the electrical chip 211. Remove the first carrier 110 and the first adhesive layer 120, so that the second carrier 130 becomes the carrier 100 for reconstructing the wafer structure 200; A redistribution layer 220 is formed on the active surface 202 of the fan-out module 210.

[0075] In actual use, the surface of the first carrier board 110 also has a dummy chip 213, the size of which is larger than that of the electrical chip 211.

[0076] By first placing the electrical chip 211 on the first adhesive layer 120 of the first carrier board 110 to form the fan-out module 210, and then removing the first carrier board 110 and the first adhesive layer 120, it can be ensured that the active surface 202 of the electrical chip 211 is located on the same horizontal plane, so that the electrical chip 211 can be connected to the redistribution layer 220.

[0077] Please refer to Figure 6 In one embodiment, when forming the reconstructed wafer structure 200, a back gold layer 230 is also formed on the back side of the fan-out module 210, the back gold layer 230 being located between the second adhesive layer 140 and the fan-out module 210.

[0078] The back gold layer 230 can provide uniform heat dissipation and heat dissipation for the multiple electrical chips 211 of the fan-out module 210. At the same time, the back gold layer 230 and the fan-out module 210 are formed together. When the optical chip unit 310 is connected to the surface of the electrical chip 211, it can also work with the fan-out module 210 to suppress the warping problem of the optical chip unit 310.

[0079] In one embodiment, the back gold layer 230 is a copper metal layer, an aluminum metal layer, a nickel metal layer, a titanium metal layer, or an alloy layer, wherein the alloy layer is an alloy layer formed of any two or more metals selected from copper, aluminum, nickel, and titanium.

[0080] Please refer to Figure 5 In one embodiment, after filling the outer side of multiple electrical chips 211 with molding compound 212 to form a fan-out module 210, the molding compound 212 is further thinned so that the back side of the electrical chips 211 is exposed outside the molding compound 212. The back gold layer 230 is disposed on the back of the thinned fan-out module 210.

[0081] When the electrical chip 211 is actually installed, the back side of the electrical chip 211 may not be entirely on the same plane. Thinning the molding compound 212 can expose the back side of multiple electrical chips 211 outside the molding compound 212 and place them on the same horizontal plane, so that the formed back gold layer 230 can better heat the electrical chip 211.

[0082] In one embodiment, the back sides of a plurality of electrical chips 211 are located on the same plane, and the back sides of the plurality of electrical chips 211 form the back side of the fan-out module 210.

[0083] In one specific embodiment, the fan-out module 210 includes two spaced-apart electrical chips 211 and a dummy chip 213.

[0084] In one embodiment, the redistribution layer 220 has a first surface and a second surface disposed opposite to each other; The first surface has a first pad 221, which is used to connect to the active surface 202 of the electrical chip 211. The second surface has a second pad 222 for connection with the first bump 312 of the optical chip unit 310.

[0085] In one embodiment, the active surfaces 202 of a plurality of electrical chips 211 are located on the same plane, and the active surfaces 202 of the plurality of electrical chips 211 form the active surface 202 of the fan-out module 210.

[0086] Please refer to Figure 10 , Figure 11 , Figure 17 and Figure 18 In one embodiment, after forming the redistribution layer 220, a mounting groove 201 is formed on the reconstructed wafer structure 200. The mounting groove 201 is used to mount the optical fiber 600 on the coupling structure 311 of the optical chip unit 310.

[0087] In one embodiment, when the optical chip structure 300 is mounted onto the surface of the redistribution layer 220, the coupling structure 311 of the optical chip unit 310 is correspondingly set with the mounting groove 201.

[0088] In one embodiment, a mounting groove 201 is formed on the reconstructed wafer structure 200 using a laser cutting process.

[0089] In one embodiment, the mounting slot 201 is disposed through at least the redistribution layer 220, the fan-out module 210, and the back gold layer 230.

[0090] In actual use, the mounting slot 201 is located at the position of the molding compound 212 of the fan-out module 210.

[0091] In one embodiment, the size of the mounting slot 201 is greater than or equal to the size of the coupling structure 311.

[0092] Please refer to Figures 10-16 In one embodiment, the mounting groove 201 is a closed mounting groove 201; The coupling structure 311 of the optical chip unit 310 is a vertical grating coupling structure.

[0093] Please refer to Figures 17-23 In another embodiment, the mounting groove 201 is an edge-opening type mounting groove 201; The coupling structure 311 of the optical chip unit 310 is an edge grating coupling structure or a vertical grating coupling structure.

[0094] In another embodiment, the mounting groove 201 is an edge-opening type mounting groove 201; The coupling structure 311 of the optical chip unit 310 is a vertical grating coupling structure.

[0095] By forming a mounting groove 201 on the reconstructed wafer structure 200 before mounting the optical chip unit 310 onto the surface of the fan-out module 210, and by controlling the structural form of the mounting groove 201 (closed mounting groove 201 or edge-open mounting groove 201), the packaging method of the optoelectronic encapsulation structure provided in this application can be applied to both the optical chip unit 310 with the edge grating coupling structure and the optical chip unit 310 with the vertical grating coupling structure.

[0096] Please refer to Figure 16 and Figure 23 In one embodiment, after the optical chip unit 310 is mounted onto the surface of the substrate 500, the optical fiber coupling step is further included, which includes: Provides 600 fiber optic cable; The optical fiber 600 is installed onto the surface of the coupling structure 311 through the mounting slot 201 and forms an optical fiber coupling with the coupling structure 311.

[0097] Please refer to Figure 13 In one embodiment, when the optical chip structure 300 is mounted onto the surface of the redistribution layer 220, the first bump 312 on the first surface of the optical chip unit 310 contacts the second pad 222 on the second surface of the redistribution layer 220. It also includes filling the space between the first surface of the optical chip unit 310 and the second surface of the redistribution layer 220 with a bottom filler to form a first bottom filler layer 320.

[0098] Please refer to Figure 15 In one embodiment, when the chip package structure 400 is mounted onto the surface of the substrate 500, the second bump 313 on the second surface of the optical chip 310 contacts the surface of the substrate 500. It also includes filling the space between the second surface of the optical chip unit 310 and the substrate 500 with a bottom filler to form a second bottom filler layer 330.

[0099] In one specific embodiment, the first bottom filling layer is an epoxy resin filling layer or a phenolic curing agent filling layer, and the second bottom filling layer is an epoxy resin filling layer or a phenolic curing agent filling layer.

[0100] In one embodiment, the size of the substrate 500 is larger than the size of the chip package structure unit 400.

[0101] Please refer to Figure 16 and Figure 23In one embodiment, after the chip packaging structure 400 is mounted onto the surface of the substrate 500, a packaging cover 700 is formed on the surface of the substrate 500, and the packaging cover 700 covers the surface of the back gold layer 230 of the chip packaging structure 400.

[0102] In one embodiment, the encapsulation cover 700 is a copper encapsulation cover, and the optoelectronic encapsulation structure can dissipate heat through the encapsulation cover 700.

[0103] In one embodiment, the encapsulation cover 700 has a notch 701 corresponding to the mounting slot 201 of the fan-out module 210.

[0104] In one embodiment, a thermal interface material layer 150 is formed between the back gold layer 230 and the encapsulation cover 700.

[0105] In one specific embodiment, the thermal interface material layer 150 is a thermal grease thermal interface material layer.

[0106] Please refer to Figure 16 and Figure 23 This application also provides an optoelectronic sealing structure, comprising: substrate 500; The optical chip unit 310 is disposed on the surface of the substrate 500. The surface of the optical chip unit 310 away from the substrate 500 is the first surface of the optical chip unit 310. The first surface of the optical chip unit 310 has a coupling structure 311. Fan-out module 210 includes a plurality of spaced electrical chips 211. Fan-out module 210 is disposed on the first surface of optical chip unit 310 through redistribution layer 220. The size of fan-out module 210 is larger than the size of optical chip unit 310.

[0107] In one embodiment, it also includes an encapsulation cover 700, and the size of the substrate 500 is larger than the size of the fan-out module 210; The encapsulation cover 700 is disposed on the surface of the substrate 500 and covers the surface of the fan-out module 210.

[0108] In one embodiment, the fan-out module 210 also has a back gold layer 230 formed on the surface away from the optical chip unit 310, and the back gold layer 230 is the back side of the electrical chip 211.

[0109] In actual use, thermal interface material layers 150 are respectively provided between the encapsulation cover 700 and the back gold layer 230, and between the encapsulation cover 700 and the substrate 500.

[0110] In one embodiment, the fan-out module 210 has a mounting groove 201, which is correspondingly disposed to the coupling structure 311 on the first surface of the optical chip unit 310, and the size of the mounting groove 201 is greater than or equal to the size of the coupling structure 311. In one embodiment, an optical fiber 600 is also included, which is located in the mounting groove 201 and disposed on the surface of the coupling structure 311.

[0111] Please refer to Figures 10-16 In one embodiment, the mounting groove 201 is a closed mounting groove 201; The coupling structure 311 of the optical chip unit 310 is a vertical grating coupling structure, and the optical fiber 600 is set perpendicular to the first surface of the optical chip unit 310.

[0112] Please refer to Figures 17-23 In another embodiment, the mounting groove 201 is an edge-opening type mounting groove 201; The coupling structure 311 of the optical chip unit 310 is an edge grating coupling structure, and the optical fiber 600 is arranged to coincide with or parallel to the first surface of the optical chip unit 310.

[0113] In another embodiment, the mounting groove 201 is an edge-opening mounting groove 201, the coupling structure 311 of the optical chip unit 310 is a vertical grating coupling structure, and the optical fiber 600 is perpendicular to the first surface of the optical chip unit 310.

[0114] In one embodiment, the fan-out module 210 further includes at least one dummy chip 213, which is spaced apart from a plurality of electrical chips 211.

[0115] In one specific embodiment, the fan-out module 210 includes two spaced-apart electrical chips 211 and a dummy chip 213.

[0116] In one embodiment, the first surface of the optical chip unit 310 has a first bump 312, and the second surface of the chip has a second bump 313, wherein the radial dimension of the first bump 312 is smaller than the radial dimension of the second bump 313. The optical chip unit 310 is connected to the redistribution layer 220 through the first bump 312; The optical chip unit 310 is connected to the substrate 500 through the second bump 313.

[0117] In one embodiment, the optical chip unit 310 has a through silicon via 314, which is disposed through the optical chip unit 310.

[0118] In one specific embodiment, the first bump 312 and the second bump 313 can be respectively disposed at both ends of the through silicon via 314 and directly electrically connected to the through silicon via 314.

[0119] In other embodiments, the first surface and / or the second surface of the optical chip unit 310 have redistribution layers, and the first bump 312 and / or the second bump 313 are electrically connected to the through-silicon via 314 through the redistribution layers. The first bump 312 and the second bump 313 may be asymmetrically arranged.

[0120] In this application, the size of the optical chip unit refers to the size of the optical chip unit along the cross-sectional direction (radial dimension); the size of the fan-out module refers to the size of the fan-out module along the cross-sectional direction (radial dimension); the size of the substrate refers to the size of the substrate along the cross-sectional direction (radial dimension); the size of the dummy chip refers to the size of the dummy chip along the cross-sectional direction (radial dimension); the size of the electrical chip refers to the size of the electrical chip along the cross-sectional direction (radial dimension); and the size of the mounting groove refers to the width of the mounting groove.

[0121] It should be noted that, where there is no conflict, the features in the different embodiments of this application described above can be combined with each other. Furthermore, in each of the above embodiments, the focus is on describing the differences from other embodiments; other specific descriptions of the same / similar parts between the embodiments can be referred to (or referenced) interchangeably. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this application.

[0122] Although this application has been disclosed above with reference to preferred embodiments, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.

Claims

1. A packaging method for an optoelectronic encapsulation structure, characterized in that, Includes the following steps: Provide carrier board; A reconstructed wafer structure is formed on the surface of the carrier substrate. The reconstructed wafer structure has a plurality of spaced fan-out modules. Each fan-out module includes a plurality of spaced electrical chips. The active surface of the fan-out module is located on the side away from the carrier substrate. The active surface of the fan-out module has a redistribution layer. An optical chip structure is provided, the optical chip structure comprising a plurality of optical chip units, the size of each optical chip unit being smaller than the size of each fan-out module, each optical chip unit having a first surface and a second surface disposed opposite to each other, the first surface of the optical chip unit having a coupling structure, the optical chip structure being mounted on the surface of the redistribution layer, the first surface of the optical chip unit being in contact with the surface of the redistribution layer on the side away from the fan-out module; Remove the carrier board and cut the reconstructed wafer structure and optical chip structure into multiple chip package structure units. Each chip package structure unit has a fan-out module and a corresponding optical chip unit with a coupling structure. A substrate is provided, and the chip packaging structure is mounted onto the surface of the substrate, wherein the second surface of the optical chip of the chip packaging structure is disposed on the side close to the substrate.

2. The packaging method for an optoelectronic encapsulation structure as described in claim 1, characterized in that, The first surface of the optical chip unit has a first bump, and the second surface of the chip has a second bump, wherein the radial dimension of the first bump is smaller than the radial dimension of the second bump. The optical chip unit is connected to the redistribution layer via a first bump; The optical chip unit is connected to the substrate via a second bump.

3. The packaging method for an optoelectronic encapsulation structure as described in claim 2, characterized in that, The optical chip unit has a through-silicon via (TSV), which is disposed through the optical chip unit.

4. The packaging method for an optoelectronic encapsulation structure as described in claim 1, characterized in that, The fan-out module also includes at least one dummy chip, which is spaced apart from the plurality of electrical chips.

5. The packaging method for an optoelectronic encapsulation structure as described in claim 1, characterized in that, The specific steps for forming the reconstructed wafer structure include: A first carrier board is provided, the surface of the first carrier board having a first adhesive layer, and a plurality of electrical chips are mounted on the first adhesive layer, wherein the front side of the electrical chips is disposed on the side close to the first adhesive layer, and the front side of the electrical chips is the active side of the electrical chips. A molding compound is filled around the multiple electrical chips to form a fan-out module; A second carrier board is mounted on the back of the electrical chip. The surface of the second carrier board has a second adhesive layer, which is located on the side of the second carrier board near the back of the electrical chip. Remove the first carrier plate and the first adhesive layer to make the second carrier plate a carrier plate for reconstructing the wafer structure; A redistribution layer is formed on the active surface of the fan-out module.

6. The packaging method for an optoelectronic encapsulation structure as described in claim 5, characterized in that, When forming the reconstructed wafer structure, the method further includes forming a back gold layer on the back side of the fan-out module, the back gold layer being located between the second adhesive layer and the fan-out module.

7. The packaging method for an optoelectronic encapsulation structure as described in claim 6, characterized in that, The back gold layer is a copper metal layer, an aluminum metal layer, a nickel metal layer, a titanium metal layer, or an alloy layer, wherein the alloy layer is an alloy layer formed of any two or more metals selected from copper, aluminum, nickel, and titanium.

8. The packaging method for an optoelectronic encapsulation structure as described in claim 6, characterized in that, After filling the outer side of multiple electrical chips with molding compound to form a fan-out module, the process further includes thinning the molding compound so that the back side of the electrical chips is exposed outside the molding compound. The gold backing layer is applied to the back of the thinned fan-out module.

9. The packaging method for an optoelectronic encapsulation structure as described in claim 8, characterized in that, The back sides of multiple electrical chips are located on the same plane, and the back sides of multiple electrical chips form the back side of the fan-out module.

10. The packaging method for an optoelectronic encapsulation structure as described in claim 6, characterized in that, The rewiring layer has a first surface and a second surface disposed opposite to each other; The first surface has a first pad, which is used to connect to the active surface of the electrical chip; The second surface has a second pad for connecting to a first bump of the optical chip unit.

11. The packaging method for an optoelectronic encapsulation structure as described in claim 5, characterized in that, The active surfaces of multiple electrical chips are located on the same plane, and the active surfaces of the multiple electrical chips form the active surface of the fan-out module.

12. The packaging method for an optoelectronic encapsulation structure as described in claim 5, characterized in that, After forming the redistribution layer, the method further includes forming a mounting groove on the reconstructed wafer structure, the mounting groove being used to mount optical fibers on the coupling structure of the optical chip unit.

13. The packaging method for an optoelectronic encapsulation structure as described in claim 12, characterized in that, When the optical chip structure is mounted onto the surface of the redistribution layer, the coupling structure of the optical chip unit is configured to correspond to the mounting slot.

14. The packaging method for an optoelectronic encapsulation structure as described in claim 12, characterized in that, Mounting grooves are formed on the reconstructed wafer structure using a laser cutting process.

15. The packaging method for an optoelectronic encapsulation structure as described in claim 12, characterized in that, The mounting slot extends at least through the redistribution layer, the fan-out module, and the back gold layer.

16. The packaging method for an optoelectronic encapsulation structure as described in claim 12, characterized in that, The radial dimension of the mounting groove is greater than or equal to the radial dimension of the coupling structure.

17. The packaging method for an optoelectronic encapsulation structure as described in claim 12, characterized in that, The mounting slot is either a closed mounting slot or an edge-open mounting slot.

18. The packaging method for an optoelectronic encapsulation structure as described in claim 17, characterized in that, When the mounting slot is a closed mounting slot, the coupling structure of the optical chip unit is a vertical grating coupling structure.

19. The packaging method for an optoelectronic encapsulation structure as described in claim 17, characterized in that, When the mounting slot is an edge-opening mounting slot, the coupling structure of the optical chip unit is an edge grating coupling structure or a vertical grating coupling structure.

20. The packaging method for an optoelectronic encapsulation structure as described in claim 12, characterized in that, After the optical chip unit is mounted onto the substrate surface, the process further includes an optical fiber coupling step, which includes: Provide fiber optic cables; The optical fiber is installed onto the surface of the coupling structure through the mounting slot and forms an optical fiber coupling with the coupling structure.

21. The packaging method for an optoelectronic encapsulation structure as described in claim 1, characterized in that, When the optical chip structure is mounted onto the surface of the redistribution layer, the first bump on the first surface of the optical chip unit contacts the second pad on the second surface of the redistribution layer. It also includes filling the space between the first surface of the optical chip unit and the second surface of the redistribution layer with a bottom filler to form a first bottom filler layer.

22. The packaging method for an optoelectronic encapsulation structure as described in claim 1, characterized in that, When the chip packaging structure is mounted onto the substrate surface, the second protrusion on the second surface of the optical chip unit contacts the substrate surface. It also includes filling the space between the second surface of the optical chip unit and the substrate with a bottom filler to form a second bottom filler layer.

23. The packaging method for an optoelectronic encapsulation structure as described in claim 1, characterized in that, The size of the substrate is larger than the size of the chip packaging structure unit.

24. The packaging method for an optoelectronic encapsulation structure as described in claim 1, characterized in that, After the chip packaging structure is mounted onto the surface of the substrate, the assembly further includes forming a packaging cover on the surface of the substrate, the packaging cover being disposed on the back gold layer surface of the chip packaging structure.

25. The packaging method for an optoelectronic encapsulation structure as described in claim 24, characterized in that, The encapsulation cover is a copper encapsulation cover.

26. The packaging method for an optoelectronic encapsulation structure as described in claim 24, characterized in that, The encapsulation cover has a notch corresponding to the mounting slot of the fan-out module.

27. The packaging method for an optoelectronic encapsulation structure as described in claim 24, characterized in that, A thermal interface material layer is formed between the back gold layer and the encapsulation cover.

28. A photoelectric sealing structure, characterized in that, include: substrate; An optical chip unit is disposed on the surface of the substrate, and the surface of the optical chip unit away from the substrate is the first surface of the optical chip unit, and the first surface of the optical chip unit has a coupling structure; A fan-out module, comprising a plurality of spaced electrical chips, wherein the fan-out module is disposed on the first surface of the optical chip unit via a redistribution layer, and the size of the fan-out module is larger than the size of the optical chip unit.

29. The photoelectric sealing structure as described in claim 28, characterized in that, It also includes a packaging cover, wherein the size of the substrate is larger than the size of the fan-out module; The encapsulation cover is disposed on the surface of the substrate and covers the surface of the fan-out module.

30. The photoelectric sealing structure as described in claim 28, characterized in that, The fan-out module also has a back gold layer formed on the surface away from the optical chip unit, and the back gold layer is in contact with the back of the electrical chip.

31. The photoelectric sealing structure as described in claim 28, characterized in that, The fan-out module has a mounting slot, which is correspondingly set with the coupling structure of the first surface of the optical chip unit, and the size of the mounting slot is greater than or equal to the size of the coupling structure.

32. The photoelectric sealing structure as described in claim 31, characterized in that, It also includes an optical fiber, which is located within the mounting groove and disposed on the surface of the coupling structure.

33. The photoelectric sealing structure as described in claim 31, characterized in that, The mounting groove is either a closed mounting groove or an edge-open mounting groove; When the mounting slot is a closed mounting slot, the coupling structure of the optical chip unit is a vertical grating coupling structure, and the optical fiber is arranged perpendicularly to the first surface of the optical chip unit. When the mounting slot is an edge-opening type mounting slot, the coupling structure of the optical chip unit is an edge grating coupling structure, and the optical fiber is arranged to coincide with or parallel to the first surface of the optical chip unit; or, the coupling structure of the optical chip unit is a vertical grating coupling structure, and the optical fiber is arranged perpendicular to the first surface of the optical chip unit.

34. The photoelectric sealing structure as described in claim 31, characterized in that, The fan-out module also includes at least one dummy chip, which is spaced apart from the plurality of electrical chips.

35. The photoelectric sealing structure as described in claim 28, characterized in that, The first surface of the optical chip unit has a first bump, and the second surface of the chip has a second bump, wherein the radial dimension of the first bump is smaller than the radial dimension of the second bump. The optical chip unit is connected to the redistribution layer via a first bump; The optical chip unit is connected to the substrate via a second bump.

36. The photoelectric sealing structure as described in claim 35, characterized in that, The optical chip unit has a through-silicon via (TSV), which is disposed through the optical chip unit.

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