Online dynamic resolution for time-based temperature estimation

Abstract

The invention discloses a measuring method for estimating the junction temperature of a power semiconductor module. The method comprises the following steps: a, copying pulse current; b. Injecting a first replica pulse current into a control electrode of a power transistor of the power semiconductor module while injecting a second replica pulse current into an emulator circuit comprising a resistor connected in series with a capacitor; c. Comparing the voltage signal of the power transistor with the voltage signal of the emulator circuit to generate a comparison signal; d. Measuring the duration ([delta] t) of the voltage signal of the power transistor reaching the same value as the voltage signal of the emulator circuit according to the comparison signal; e. Converting the measured duration ([Delta] t) into an estimated value of the junction temperature (TJ).

Description

Technical Field

[0001] This disclosure relates to the field of power semiconductor monitoring and related calibration methods applicable throughout the lifespan of such components. This application claims priority to European Patent Application No. EP23305442.8, filed on March 29, 2023, the contents of which are incorporated herein by reference. Background Technology

[0002] As is well known, monitoring the temperature of power semiconductor devices / modules (such as multi-chip power modules) is essential for protection, status, and health monitoring, as temperature is one of the primary sources of failure. Power semiconductor datasheets provide the highest junction temperature at which the device can operate without thermal runaway and the ensuing catastrophic failure. Therefore, junction temperature monitoring, or at least the measurement of the highest junction temperature, is crucial for ensuring the safe operation of the device.

[0003] Typically, the free surface area of ​​a chip is very small. Mounting a sensor on it is very difficult, and in some cases, impossible. The number of external connections is numerous, and the acquisition system is complex. Performing this work under laboratory conditions is extremely challenging. In real-world industrial and operational situations, using a standalone PN junction sensor is impractical. Furthermore, the sensor must be integrated within the power module package, meaning its presence must be planned in advance during the module design phase, and it cannot be retrofitted into existing power modules.

[0004] As is well known, many methods based on temperature-sensitive electrical parameters (TSEP) and on-chip sensors can be used to estimate the junction temperature of power semiconductors online. This allows for direct acquisition of the junction temperature without the need for external sensors. Typically, TSEP measurements of transistors are performed using an analog-to-digital converter (ADC). For low-cost systems, the use of an ADC can be a limitation because the resolution and sampling rate of the ADC are directly related to the quality of the temperature estimation. The TSEP of a transistor can be time. More specifically, the TSEP of a transistor can be measured as the duration relative to a detection threshold. Time measurements can be problematic due to the low sensitivity of temperature to time. The simplest method is to monitor whether the temperature exceeds a safety-related critical temperature value. This can be achieved by comparing the TSEP value with a threshold using an analog comparator. This technique is described in EP3855145A1. This method does not require an ADC but limits the measurement to a specific temperature value. This specific temperature value is adjusted to correspond to an over-temperature condition of a particular power transistor. However, this method has the following limitations:

[0005] - Only one temperature is monitored. Typically, a predetermined temperature threshold is selected based on the datasheet provided by the manufacturer.

[0006] It's possible to monitor multiple temperature values, but this directly impacts the complexity of the circuitry and calibration. In practice, multiple temperatures can be monitored by replicating the monitoring circuitry. This, in turn, multiplies the number of simulator components and the calibration workload.

[0007] - Over-temperature detection (OTD) circuit hardware needs to be customized for each monitored device. Each device has different TSEP characteristics, requiring each OTD circuit to be calibrated. This limits the functionality of the OTD for specific transistors.

[0008] The OTD circuit is unmodifiable and cannot be adjusted during operation. Deviations in the TSEP (Total Temperature Equivalent) during task execution cannot be ruled out, which may alter the OTD's operation, for example, by modifying the measured temperature value.

[0009] When the TSEP of a power transistor is time, the time-temperature sensitivity is low. This will result in lower accuracy and / or the need for expensive signal conditioning circuitry. Summary of the Invention

[0010] This disclosure improves upon this situation.

[0011] A measurement method for estimating the junction temperature of a power semiconductor module is proposed, the method comprising:

[0012] a. To duplicate a single pulse current into two duplicate pulse currents;

[0013] b.

[0014] - Injecting the first replicated pulse current into the control electrode of the power transistor in the power semiconductor module, simultaneously

[0015] - Inject the second replicated pulse current into the simulator circuit, which includes a resistor connected in series with a capacitor;

[0016] c. Compare the voltage signal of the power transistor with the voltage signal of the simulator circuit to generate a comparison signal;

[0017] d. Based on the comparison signal, measure the duration for which the voltage signal of the power transistor reaches the same value as the voltage signal of the simulator circuit;

[0018] e. Convert the duration of the measurement into an estimate of the junction temperature.

[0019] On the other hand, a power semiconductor module is proposed, the power semiconductor module comprising:

[0020] - At least one power transistor;

[0021] - A current pulse source, which is provided through the control electrode of the power transistor;

[0022] - A current replicator, which is arranged to replicate the current provided by the current pulse source;

[0023] -A simulator circuit, which includes a resistor connected in series with a capacitor;

[0024] - A comparator configured to compare the voltage signal of the power transistor with the voltage signal of the simulator circuit to generate a comparison signal.

[0025] On the other hand, a computer software comprising instructions is proposed, wherein when the software is executed by a processor, the instructions implement the methods defined in this specification. On the other hand, a computer-readable non-transitory recording medium is proposed, wherein software is registered on the computer-readable non-transitory recording medium, which, when executed by a processor, implements the methods defined in this specification.

[0026] The following features can be implemented individually or in combination:

[0027] The resistor in the simulator circuit is tunable. The value of the resistor is set to select the range of temperature estimation. The capacitor in the simulator circuit is tunable. The value of the capacitor is set to select the position within the temperature estimation range.

[0028] The method further includes:

[0029] f. Modify the value of the resistor in the simulator circuit so that the corresponding temperature estimation range is modified and the estimated value of the junction temperature is closer to the middle of the modified temperature estimation range;

[0030] g1. If the estimated value of the junction temperature is sufficiently within the middle of the modified temperature estimation range according to a predetermined standard, then modify the value of the capacitor in the simulator circuit to improve sensitivity;

[0031] g2. If the estimated junction temperature is not sufficiently within the middle of the modified temperature estimation range according to the predetermined standard, then the value of the capacitor in the simulator circuit is modified to reduce the sensitivity.

[0032] The method further includes iteratively modifying the value of the resistor while the duration t is fixed to a value close to zero, until the generated comparison signal corresponds to the case where the voltage signal of the power transistor is equal to the voltage signal of the simulator circuit.

[0033] The module also includes:

[0034] - A controller configured to tune the resistor and / or the capacitor. Attached Figure Description

[0035] Other features, details and advantages will be shown in the following detailed description and accompanying drawings.

[0036] Figure 1 This is a schematic diagram of a module according to some implementation methods.

[0037] Figure 2 It is a graphical representation of the output voltage measured during the current pulse and the corresponding comparison signal.

[0038] Figure 3 It is a graphical representation of the output voltage measured during the current pulse and the corresponding comparison signal.

[0039] Figure 4 Through with Figure 2 and Figure 3 A similar comparison yields a graphical representation of the linear relationship between the signal duration as a function of temperature.

[0040] Figure 5 In C g >C emu In the case of Figure 2 or Figure 3 similar.

[0041] Figure 6 In C g <C emu In the case of Figure 2 or Figure 3 similar.

[0042] Figure 7 It is a temperature-time resolution graphical view as a function of the simulator's capacitance.

[0043] Figure 8 It is a schematic representation of the controller layout used in a tuning simulator circuit.

[0044] Figure 9 It is a flowchart of an algorithm that can be executed in the implementation.

[0045] Figure 10 It is a flowchart of an algorithm that can be executed in the implementation.

[0046] Figure 11 It is a flowchart of an algorithm that can be executed in the implementation.

[0047] Figure 12 It is a dynamic adaptive graphical representation of the simulator circuit.

[0048] Figure 13 It is a flowchart of an algorithm that can be executed in the implementation.

[0049] Figure 14 It is a flowchart of an algorithm that can be executed in the implementation.

[0050] Figure 15 This is a schematic representation of a dynamic adaptive implementation of a simulator circuit. Detailed Implementation

[0051] Here, the term "power" is used in a broad sense within the field of energy conversion (power electronics) technology. Furthermore, the solution described below is designed to be used within the lifespan of a semiconductor module under "normal" conditions, meaning it is not limited to ideal and controlled environments such as laboratory or test bench environments (e.g., post-production quality control phases).

[0052] Now refer to Figure 1 The diagram shows a power semiconductor module 1. The power semiconductor module 1 includes:

[0053] -At least one power transistor TR;

[0054] - Current pulse source CPS, which is provided through the control electrode G of the aforementioned power transistor TR;

[0055] - Current replicator CC, which is configured to replicate the current provided by the aforementioned current pulse source;

[0056] - The simulator circuit EMU, which includes capacitor C emu series resistor R emu ;as well as

[0057] - Comparator COMP, which is configured to compare the voltage signal V of the aforementioned power transistor TR. ge The voltage signal V of the aforementioned simulator circuit EMU emu To generate comparison signal V CMP .

[0058] exist Figure 1 Module 1 also includes a time detector CHR. The time detector CHR is configured to measure the comparison signal V. CMP The duration of the time detector (CHR). Structurally, the time detector (CHR) can be a separate module or a submodule functionally integrated into the comparator (COMP).

[0059] The method used for estimating, as will now be described. Figure 1 An example of a method for measuring the junction temperature of a power semiconductor module is shown.

[0060] In the first operation, a pulse current is copied into two identical pulse currents. Figure 1In the example, the pulsed current from the current pulse source CPS is replicated by the current replicator CC (e.g., a "current mirror circuit"). The goal is to inject the same current pulse into both the transistor TR and the simulator circuit EMU simultaneously.

[0061] In the second operation, the first and second replicated pulse currents are simultaneously injected into the control electrode of the power transistor TR and the simulator circuit EMU. Figure 1 In the example, the control electrode is the gate G of the transistor TR. For this purpose, the internal gate resistance of the transistor (existing within the transistor structure) is used as TSEP.

[0062] In the third operation, the obtained voltage V ge and V emu Comparison. In Figure 1 In the example, the gate-emitter voltage V of transistor TR is compared using comparator COMP. ge and the output voltage V of the simulator circuit EMU emu .

[0063] The obtained voltage V ge and V emu It can be described by the following formulas ([Mathematical Formula 1] and [Mathematical Formula 2]).

[0064] [Mathematical Expression 1]

[0065]

[0066] [Mathematical Expression 2]

[0067]

[0068] Where I is current, t is time, and R g (T j ) is the gate resistor.

[0069] Gate resistor R g It is linearly related to temperature and can be described by the following formula ([Mathematical Formula 3]).

[0070] [Mathematical Expression 3]

[0071] R g (T j )=(δR g ·T j +1)R g0

[0072] In this example, the comparison is performed in binary form: when the transistor voltage is higher than or equal to the emulator circuit voltage (V... ge ≥V emu When ), the output signal V CMPIt equals "1"; in other cases (V) ge <V emu Under these conditions, the output signal V CMP The value is "0". Therefore, the transistor voltage is higher than or equal to the simulator circuit voltage (V). CMP The duration of case =1) can be measured using formulas ([Mathematical Formula 1] and [Mathematical Formula 2]) according to the following formula ([Mathematical Formula 4]).

[0073] [Mathematical Expression 4]

[0074]

[0075] Here, binary values ​​("1" or "0") are used to analyze the difference because the difference itself is not important. Only the duration of the difference sign matters. In various implementations, the two voltages can be compared in different ways; for example, the comparison can be analog.

[0076] The relationship between time and temperature is independent of the current injection value. Therefore, this method is robust to the limitations of current pulse source CPS and achieves good accuracy and low drift even with low-cost current injection circuitry. Temperature can be measured without an additional ADC, thus significantly reducing the junction temperature To. j The cost of measurement. A time-to-digital converter (TDC) can be used, or the time-to-digital conversion can even be implemented in an FPGA, ultimately in the same FPGA that generates the switch control signals and other functions of Module 1.

[0077] V ge and V emu The comparison is shown graphically. Figure 2 , Figure 3 and Figure 4 . Figure 2 The implementation corresponding to the first temperature T1, and Figure 3 This corresponds to the implementation at the second temperature T2.

[0078] In the fourth operation, due to the linear relationship between the duration Δt and temperature T, the measured duration Δt is converted into the junction temperature T. For example... Figure 4 As shown, this relationship can be established by considering different temperatures T. n It was derived through multiple measurements.

[0079] The conversion can be achieved using a time-to-digital converter (TDC), including known TDCs. Some TDCs have a resolution better than 1 ns. For example, the component with the commercial reference model "TDC7401ZAXRé" has a resolution of 55 ps. The temperature resolution can be expressed as a function of the TDC resolution using the following formula ([Mathematical Formula 5]).

[0080] [Mathematical Expression 5]

[0081]

[0082] Temperature-time resolution can easily fall below 1°C / ns, meaning a 55ps TDC can achieve a temperature resolution below 0.055°C. To demonstrate the high resolution achievable with this method, we compare it to a known resistance-temperature resolution of 0.013Ω / °C with a 100mA current injection: in this case, using a known 14-bit ADC and ±5V rails, the temperature resolution is on the order of 0.5°C.

[0083] Temperature resolution, and subsequently accuracy and precision, may be far lower than that of state-of-the-art methods.

[0084] In the proposed example, the output signal value of the comparator COMP can be either 0 or 1. According to R... emu and C emu The value of can be considered in two cases. These two cases are as follows: Figure 5 and Figure 6 As shown. In the first case ( Figure 5 ), C g and R g Higher than C emu and R emu The output signal V of comparator COMP CMP When the value is "1", the signal length (duration) will be related to the temperature T. j Proportional. In the second case ( Figure 6 ), C g and R g Each is lower than C emu and R emu The output signal V of comparator COMP CMP When the value is "0", the signal length (duration) will be related to the temperature T. j Proportional.

[0085] In the example, the simulator circuit EMU is tunable, and the resistor R can be set. emu The value of capacitor C can be set. emu The values ​​of the two are independent of each other. In various implementations, only the resistors or only the capacitors are tunable. In other implementations, the emulator circuit EMU is non-tunable.

[0086] When the capacitor value C emu When configurable, only by setting C emu Temperature can be estimated without considering R. emu The value of R. emu <Rg (See [ Figure 5 ]) and R emu >R g (See [ Figure 6 When ]), they correspond to C respectively. emu <C g And C emu >C g Therefore, for example, at the end of the manufacturing of module 1, T will be... j After the circuit is connected to transistor TR, it is estimated that only C can be used. emu Perform calibration.

[0087] For R emu Given value:

[0088] - If no signal ("0") is detected at the output of comparator COMP, then C must be increased. emu ;

[0089] - If only a positive signal ("1") is detected at the output of comparator COMP, then C must be reduced. emu .

[0090] When the capacitance value C emu When configurable, it can be done by setting C emu Set close to C g To improve temperature-time resolution. According to formula ([Mathematical Formula 5]), the closer to C... emu The higher the temperature-time resolution, the better. Figure 7 As shown, the diagram is drawn as C. emu -C g The temperature-time resolution of the function. It can be seen that for C... emu The closer to C g The resolution has increased.

[0091] Reduce capacitance C emu (During the lifespan of Module 1) this can be achieved using a laser-tunable chip capacitor, which consists of a multilayer plate capacitor. Vaporizing the top layer with a laser reduces the capacitance by decreasing the area of ​​the top electrode. Depending on the industrial environment, capacitor tuning can be used instead of resistor tuning where more convenient.

[0092] calibration

[0093] In some implementations, if the emulator circuit EMU has a tunable resistor R emu and tunable capacitor C emu This allows for further calibration operations. In this case, module 1 may also include a controller CONT.

[0094] As an example, tunable capacitors and resistors can be digital potentiometers controlled by a controller CONT (such as an FPGA). For example only, a component with the commercial reference model "NCD2400MTR" can be used, with a range of 200pF and 512 discrete 355fF steps. If this range is insufficient to cover the full range of capacitance for different devices, the range can be extended by connecting several larger capacitors in parallel with an "NCD2400MTR," controlled by an FPGA, such as... Figure 8 As shown.

[0095] As a second example, an n-bit R-2R resistor ladder network controlled by an FPGA can be used. This provides 2n resistor steps that can be directly tuned by the FPGA. As a third example, a digital potentiometer, such as the commercial reference model "AD5258" with 64 resistor steps, can be used.

[0096] Those skilled in the art will select an emulator circuit EMU, including a controller CONT, which adapts to the capacitance range based on the transistor to be driven and operating conditions. By using tunable capacitors and resistors, the TSEP of the transistor can be automatically calibrated using different algorithms. This allows for (only) transistor modification while maintaining temperature measurement operation. Furthermore, throughout the transistor's lifespan (not just under laboratory conditions on a test bench), a periodic calibration procedure can be performed to balance any TSEP parameter variations.

[0097] Figure 9 , Figure 10 and Figure 11 These are three examples of calibration algorithms that can be used.

[0098] exist Figure 9 In the example, the transistor is exposed to two different temperatures, T1 and T2. Capacitor C emu and resistor R emu It is initially set to a lower value to obtain different output voltages between the transistor and the emulator circuit. If this calibration algorithm is used in conjunction with the aforementioned comparator COMP, this corresponds to V. CMP =1. The component is set at a first fixed temperature T1, and time detection is set at a time t1. Resistance R emu Gradually increase the voltage until the same output voltage (V) is achieved between the transistor and the emulator circuit. CMP =0). Then, at another time t2, a time detection is set, and the capacitor C is gradually increased. emu Until a different output voltage (V) is obtained between the transistor and the emulator circuit. CMP=1). This sets the time detection sensitivity. Finally, the temperature is fixed at the second temperature T2, and a time scan is performed until the same output voltage (V) is obtained between the transistor and the simulator circuit. CMP =0).

[0099] Figure 9 The example can reduce the amount of calibration work because module 1 only needs to be exposed to two different temperatures, T1 and T2. A typical (inexpensive) FPGA is sufficient to do this.

[0100] exist Figure 10 In the example, only capacitor C was modified. emu The value of the time detection is gradually increased to set the time detection corresponding to the first temperature T1. Then, the capacitor C is gradually increased. emu The detector resolution is fixed. Finally, the temperature is fixed at a second temperature T2, and the detection time is gradually increased until a different output voltage (V) is obtained between the transistor and the emulator circuit. CMP =1).

[0101] Figure 10 The example allows the use of a fixed (non-tunable) resistor R. emu .

[0102] Figure 11 The example applies to the two cases described above: when the transistor's resistance R... g The resistance R of the simulator circuit is greater than that of the simulator circuit. emu (R g >R emu See Figure 5 When, and when the transistor's resistance R g Less than the resistor R of the simulator circuit emu (R g <R emu See Figure 6 At that time, initially, the capacitance C... emu The temperature is fixed at a midpoint (e.g., the middle of a known range), and the temperature is fixed at a known first temperature T1. The time is gradually increased. If the output voltages between the transistor and the simulator circuit were initially different, they later become equal (V... CMP (If it changes from 1 to 0), then it means R g >R emu ,Right now, Figure 5 The situation shown is different. Conversely, if the output voltages between the transistor and the emulator circuit were originally equal but later became different (V... CMP (From 0 to 1) means that R g <R emu ,Right now, Figure 6 The situation is shown. Then, in the first case (R) g >Remu ), capacitor C emu Decrease, and in the second case (R) g <R emu ), capacitor C emu Increase the time sensitivity to set the sensitivity. Then, fix the temperature at a known second temperature T2 and gradually increase the detection time until the first case (R) is reached. g >R emu To achieve the same output voltage (V) between the transistor and the emulator circuit. CMP =0), or in the second case (R g <R emu Different output voltages (V) are obtained between the transistor and the simulator circuit. CMP =1).

[0103] exist Figure 11 In the example, the resistor R of the simulator circuit emu Relative to the transistor's resistance R g The value of R is not very important, and emu It can be a fixed resistor value, rather than a tunable value.

[0104] One way to expose a transistor to a known temperature (T1 or T2) is to consider the ambient (heatsink) temperature when the transistor is off for several minutes. Another way to expose a transistor to a known temperature is to consider the base plate temperature when the transistor is off for several seconds. By considering the temperatures at two different times, temperature exposure can be performed in situ and / or in situ (i.e., outside the module) using a heated plate.

[0105] T based on time J Estimated dynamic resolution

[0106] As described above, it has a tunable resistor R emu and tunable capacitor C emu The emulator circuit EMU can be calibrated based on transistors, for example, calibrated only once after manufacturing / assembly processing, periodically calibrated during the module's lifespan (e.g., during maintenance operations), or even calibrated during the module's "normal" operation. The following section highlights a solution specifically designed for dynamic implementation throughout the module's lifespan, enabling the embedded controller to dynamically adapt the resolution of temperature estimates as temperatures change.

[0107] The estimable temperature range is related to the resistance R of the simulator circuit EMU. emu The temperature amplitude (sensitivity) that can be inferred from time t is related to the conductance C of the simulator circuit EMU. emuIn other words, unlike existing technological solutions that must ultimately compromise between large amplitude and high resolution, the solution proposed here is able to automatically and dynamically optimize the range and resolution of each transistor as well as the range and resolution of each lifetime state (variation characteristic) of each transistor.

[0108] As an example, one calibration objective could be to cover a temperature range between 125°C and 200°C (i.e., for protection). Alternatively, the objective could be to cover a range between -40°C and 200°C (i.e., for counting temperature cycles). For a specific temperature range, sensitivity can be optimized to the highest level. The junction temperature T0 can be optimized. J Estimate the circuit's performance to achieve optimal accuracy across each temperature range.

[0109] Since the junction temperature T has already been estimated J Therefore, the following operations can be performed:

[0110] f. Modify the resistor R in the above-mentioned simulator circuit EMU. emu The value of causes the corresponding temperature estimation range to be modified, and the junction temperature T J The estimated value is closer to the middle of the revised temperature estimation range;

[0111] g1. If the junction temperature T J If the above estimated value is sufficiently within the middle of the modified temperature estimation range according to the predetermined standard, then the capacitor C of the simulator circuit EMU is modified. emu The value of increases sensitivity (and narrows the range);

[0112] g2. If the junction temperature T J If the above-mentioned estimated value does not fall sufficiently within the middle of the modified temperature estimation range according to the aforementioned predetermined standard, then the capacitor C of the simulator circuit EMU will be modified. emu The value of results in decreased sensitivity (and increased range).

[0113] The above operations are illustrated graphically in... Figure 12 In the first case ( Figure 12 (Left side), junction temperature T J Estimated as T J1 Value T J1 It is positioned precisely at the center of the measurement range (curve "A"). Then, the time-temperature sensitivity improves, T J1 The value remains centered within the measurement range (curve "B"). Time-temperature sensitivity improves again, T J1 The value remains centered within the measurement range (curve "C"). In the second case ( Figure 12 (Right side), junction temperature T JThe change (in the example, an increase) is estimated as T. J2 Junction temperature T J =T J2 No longer within the measurement range (curve "C"). (By modifying capacitor C in the simulator circuit) emu The value (T) reduces time-temperature sensitivity: temperature T J2 Within the measurement range, but not reaching the center value (curve "D"). (By modifying the resistor R in the simulator circuit) emu (Value) shift the temperature range to the estimated temperature T J2 The center (curve "E"), and (by modifying the capacitor C of the simulator circuit) emu Increase sensitivity (curve "F").

[0114] exist Figure 12 In the example, the temperature range is maximized to understand the approximate temperature range of the transistor. Once the temperature range is known, the controller applies an algorithm to set R. emu The value is adjusted to monitor temperature and C. emu To optimize resolution. The algorithm readjusts R when transistor temperature changes. emu and C emu To focus on the measurement of new temperatures.

[0115] In summary, by making C emu Approaching C g This can improve time sensitivity. This allows for more accurate measurement over a wider temperature range by using different algorithms, overcoming the trade-off between range and sensitivity. The simulator circuit (R) is set up through dynamic iteration. emu and C emu This involves balancing range and sensitivity. In other words, by using multiple iterations, it is possible to achieve both high measurement range and high sensitivity simultaneously.

[0116] For example only, Figure 13 and Figure 14 An example of an implementation of the dynamic estimation / calibration algorithm is shown. Figure 13 The example is universal, while Figure 14 The example is more detailed and takes into account the above. Figure 5 , Figure 6 and Figure 11 The two situations described in the text.

[0117] In various implementations, the duration t can also be fixed close to "0" (to obtain R). g (T), see [Mathematical Formula 1]), to use a tunable R emu and C emu The parameters are used for dynamic temperature estimation. This method is as follows: Figure 15 As shown, where Cemu R is a constant. emu Tuning was performed until a different output voltage (V) was obtained between the transistor and the emulator circuit. CMP =1). This allows for the use of regulators, such as proportional-integral regulators (e.g., Figure 15 The "PI" in the figure determines the temperature and the gate resistance R. g The value of (T) can be estimated without measuring the duration of the comparator COMP's output signal. g Value and temperature T J .

[0118] Industrial practicality

[0119] The previously described objective was to utilize the internal gate resistance R g As a TSEP (Transformer Electron Precipitator) for measuring the junction temperature of power transistors, this measurement method offers high resolution, low circuit cost, low calibration workload, and high circuit versatility. Optionally, calibration can be performed. Two equal currents are simultaneously injected through the transistor's control electrode (typically the gate) and an equivalent RC circuit called an "emulator circuit." In implementations where more measurements / estimations of a specific transistor are desired, a tunable emulator circuit (with resistor R...) can be used. emu and / or capacitor C emu Tuning to R of the transistor respectively g and C g Within the same range, further calibration steps are performed. An analog comparator is used to compare voltage V. ge and V emu The duration (not the amplitude itself) of the comparator's output signal is linearly proportional to the transistor's temperature. This allows for the measurement of the transistor's junction temperature without an ADC. Furthermore, in-situ calibration for different component characteristics can be performed using tunable resistors and capacitors controlled by a controller (e.g., an FPGA), and repeated calibration can be performed throughout the module's lifespan to compensate for deviations.

[0120] The modules described above can be used as power modules and inverters in fields such as automotive and powertrain technology, factory automation, air conditioning systems, HVDC and renewable energy, but are not limited thereto.

[0121] This disclosure is not limited to the methods, modules, components, and computer software described herein, which are merely examples. The invention encompasses all alternatives that may arise to those skilled in the art upon reading this specification.

[0122] Explanation of reference numerals in the attached figures

[0123] -1: Module

[0124] -CPS: Current Pulse Source

[0125] -CC: Current Replicator

[0126] -TR: Transistor

[0127] -EMU: Emulator Circuit

[0128] -COMP: Comparator

[0129] -CHR: Time Detector

[0130] -CONT: Controller

Claims

1. A measurement method for estimating the junction temperature of a power semiconductor module (1), the method comprising the following steps: a. To duplicate a single pulse current into two duplicate pulse currents; b. - Inject the first replicated pulse current into the control electrode (G) of the power transistor (TR) of the power semiconductor module (1), while - Inject the second replicated pulse current into the capacitor (C) emu series resistors (R) emu The emulator circuit (EMU) of ) c. The voltage signal (V) of the power transistor (TR) ge The voltage signal (V) of the simulator circuit (EMU) emu ) are compared to generate a comparison signal (V) CMP ); d. Based on the comparison signal (V) CMP ), measuring the voltage signal (V) of the power transistor (TR). ge ) to achieve the voltage signal (V) of the simulator circuit (EMU). emu The duration (Δt) of the same value; e. Convert the measured duration (Δt) to junction temperature (T). J The estimated value of ).

2. The method according to the preceding claim, wherein, The resistor (R) of the simulator circuit (EMU) emu It is tunable. The resistor (R) is set by selecting the range of temperature estimation. emu The value of ) and Among them, the capacitor (C) of the simulator circuit (EMU) emu The capacitor (C) is tunable, and wherein the capacitor (C) is set in a manner that selects the location of the temperature estimation range. emu The value of ).

3. The method according to any one of the preceding claims, further comprising the step of: f. Modify the resistor (R) of the simulator circuit (EMU). emu The value of ) causes the corresponding temperature estimation range to be modified, and the junction temperature (T) J The estimated value is closer to the middle of the revised temperature estimation range; g1. If the junction temperature (T) J If the estimated value of the temperature is sufficiently within the middle of the modified temperature estimation range according to a predetermined standard, then the capacitor (C) of the simulator circuit (EMU) is modified. emu The value of ) increases sensitivity; g2. If the junction temperature (T) J If the estimated value of the temperature is not sufficiently within the middle of the modified temperature estimation range according to the predetermined standard, then the capacitor (C) of the simulator circuit (EMU) is modified. emu The value of ) reduces the sensitivity.

4. The method according to any one of claims 1 and 2, further comprising the step of: While fixing the duration t to a value close to zero, the resistance (R) is iteratively modified. emu The value of ) until the generated comparison signal (V) is obtained. CMP ) corresponds to the voltage signal (V) of the power transistor (TR). ge The voltage signal (V) of the simulator circuit (EMU) is equal to that of the simulator circuit (EMU). emu (The situation is as follows.) 5. A power semiconductor module (1), the power semiconductor module comprising: - At least one power transistor (TR); - A current pulse source (CPS), which is provided through the control electrode (G) of the power transistor (TR); - Current replicator (CC), the current replicator being configured to replicate the current provided by the current pulse source; - Emulator circuit (EMU), the emulator circuit including capacitor (C) emu series resistors (R) emu );as well as - A comparator (COMP) configured to compare the voltage signal (V) of the power transistor (TR). ge The voltage signal (V) of the simulator circuit (EMU) emu ), to generate a comparison signal (V) CMP ).

6. The power semiconductor module (1) according to the preceding claim, further comprising: - Controller (CONT), the controller being configured to tune the resistor (R) emu ) and / or the capacitor (C emu ).

7. Computer software including instructions that, when executed by a processor, cause the power semiconductor module (1) according to claim 5 or 6 to implement the method according to any one of claims 1 to 4.

8. A computer-readable non-transitory recording medium having software registered thereon, which, when executed by a processor, implements the method according to any one of claims 1 to 4.

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