Display panel and display terminal

Abstract

The invention relates to a display panel and a display terminal. The display panel is provided with a display area and a non-display area, the display panel comprises a substrate, a first transistor and a second transistor, the first transistor is located in the display area, the second transistor is located in the non-display area, the first transistor comprises a first active part, the second transistor comprises a second active part, and the first active part and the second active part are made of different materials; the pixel electrode is arranged on the side, away from the substrate, of the first transistor, and the pixel electrode penetrates through the first via hole to make contact with the first active part. According to the display panel, the pixel electrode penetrates through the first via hole to be in contact with the first active part, a drain electrode of the first transistor can be omitted, the manufacturing process of the display panel is simplified, the manufacturing cost is reduced, meanwhile, compared with a light-proof drain electrode, the pixel electrode does not block light, the aperture opening ratio of the display panel can be increased, and the display effect is improved. And the brightness of the display panel is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and a display terminal. Background Technology

[0002] With the development of display technology, consumers have increasingly higher demands for display products. They require both high display brightness and low product prices.

[0003] To improve product brightness, the aperture ratio of the display panel needs to be increased. Related technologies use transparent materials to fabricate the electrodes of the thin-film transistors in the display area, thereby increasing the aperture ratio. However, using transparent materials for the electrodes requires increasing the number of film layers, which in turn increases the number of photomasks and the complexity of the process, thus raising manufacturing costs. Summary of the Invention

[0004] This application provides a display panel and a display terminal, which improves the technical problem that in order to improve the brightness of the product, it is necessary to increase the aperture ratio of the display panel. However, increasing the aperture ratio of the display panel will increase the number of photomasks and the complexity of the process, thus increasing the manufacturing cost.

[0005] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, having a display area and a non-display area located on at least one side of the display area, the display panel comprising:

[0006] substrate;

[0007] The first transistor and the second transistor are both disposed on one side of the substrate. The first transistor is located in the display area and the second transistor is located in the non-display area. The first transistor includes a first active portion and the second transistor includes a second active portion. The first active portion and the second active portion are made of different materials.

[0008] A pixel electrode is disposed on the side of the first transistor away from the substrate, and the pixel electrode passes through a first via and contacts the first active portion.

[0009] Optionally, the display panel includes:

[0010] An interlayer insulating layer is disposed between the first active portion and the pixel electrode;

[0011] A planarization layer is disposed between the interlayer insulating layer and the pixel electrode;

[0012] The first via penetrates the planarization layer and the interlayer insulation layer.

[0013] Optionally, the display panel further includes:

[0014] A common electrode is disposed on the side of the planarization layer opposite to the substrate;

[0015] A first passivation layer is disposed between the common electrode and the pixel electrode;

[0016] The common electrode is disposed on the side of the pixel electrode away from the substrate, or the common electrode is disposed on the side of the pixel electrode close to the substrate.

[0017] Optionally, the common electrode is disposed on the side of the pixel electrode opposite to the substrate, and the orthographic projection of the common electrode on the substrate covers the orthographic projection of the pattern of the first via on the substrate.

[0018] Optionally, the common electrode is disposed on the side of the pixel electrode closer to the substrate;

[0019] The display panel includes a second passivation layer disposed on the side of the pixel electrode opposite to the substrate, and the second passivation layer at least covers the first via.

[0020] Optionally, the display panel further includes:

[0021] A source-drain layer is disposed between the interlayer insulating layer and the planarization layer, and the source-drain layer includes a first source of the first transistor, a second drain of the second transistor, and a second source of the second transistor.

[0022] A trace section is disposed in the non-display area, and the trace section is disposed on the same layer as the common electrode;

[0023] The parallel connection section is disposed in the non-display area, and the parallel connection section is disposed on the same layer as the first source electrode;

[0024] The wiring section passes through the third via and is electrically connected to the parallel section.

[0025] Optionally, the first via includes a first sub-via and a second sub-via that are connected, the first sub-via penetrating the planarization layer and the second sub-via penetrating the interlayer insulation layer;

[0026] Wherein, at the interface between the planarization layer and the interlayer insulation layer, the difference between the aperture of the first sub-hole and the aperture of the second sub-hole is greater than or equal to zero and less than or equal to 4 micrometers.

[0027] Optionally, the display panel includes multiple data lines extending along a first direction and multiple scan lines extending along a second direction, the first direction and the second direction intersect, and two adjacent data lines and two adjacent scan lines enclose a pixel opening;

[0028] The first via is located within the pixel opening, and the minimum distance between the first via and the scan line is less than the minimum distance between the first via and the data line.

[0029] Optionally, the interlayer insulating layer is provided with a second via, the first source electrode passes through the second via and contacts the first active portion, the orthographic projection of the pattern of the second via on the substrate overlaps with the orthographic projection of the data line on the substrate, the second active portion is disposed between the first active portion and the substrate, and the second source electrode and the second drain electrode are disposed between the interlayer insulating layer and the planarization layer.

[0030] According to a second aspect of this application, a display terminal is provided, including the display panel described above.

[0031] In the display panel of this application embodiment, by passing the pixel electrode through the first via and contacting the first active part, the drain of the first transistor can be omitted, thereby simplifying the manufacturing process of the display panel and reducing the manufacturing cost. At the same time, compared with the opaque drain, the pixel electrode does not block light, which can increase the aperture ratio of the display panel and improve the brightness of the display panel.

[0032] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0035] Figure 1 This is a top view of a display panel provided in an exemplary embodiment of this disclosure;

[0036] Figure 2 yes Figure 1 A schematic diagram of a cross-sectional structure at point CC;

[0037] Figure 3 yes Figure 1 Another cross-sectional structural diagram at the CC section;

[0038] Figure 4 yes Figure 1 Another cross-sectional structural diagram at the CC section;

[0039] Figure 5 yes Figure 1 A magnified schematic diagram of the local structure at a sub-pixel;

[0040] Figures 6A to 6D This is a process flow diagram of a first transistor provided in an exemplary embodiment of this disclosure;

[0041] Figure 7 This is a schematic diagram of the structure of a display terminal provided in an exemplary embodiment of this disclosure.

[0042] Explanation of reference numerals in the attached figures:

[0043] 1-Display panel; AA-Display area; NA-Non-display area; 11-Subpixel;

[0044] 10-Substrate; 12-Buffer layer; 13-First gate insulating layer; 14-Second gate insulating layer; 15-Third gate insulating layer; 16-Interlayer insulating layer; 17-Planarization layer; 18-First passivation layer; 19-Second passivation layer;

[0045] 20 - First transistor; 21 - First active part; 22 - First source; 23a - First via; 231a - First sub-via; 232a - Second sub-via; 24a - Second via; 25 - First gate; 26 - Third gate;

[0046] 30 - Second transistor; 31 - Second active part; 32 - Second source; 33 - Second drain; 34 - Second gate;

[0047] 41-Pixel electrode; 42-Common electrode; 43-Source / drain layer; 44-Trace section; 44a-Third via; 46-Parallel section;

[0048] 61-Data cable; 62-Scan line; 60a-Pixel aperture; 63-Light-shielding layer;

[0049] d1 - Diameter of the first sub-hole; d2 - Diameter of the second sub-hole;

[0050] s1 - Minimum spacing between the first via and the scan line; s2 - Minimum spacing between the first via and the data line;

[0051] D1 - First direction; D2 - Second direction;

[0052] 2-Display terminal; 3-Terminal body. Detailed Implementation

[0053] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0054] According to a first aspect of this application, a display panel 1 is provided, such as... Figures 1 to 4 As shown, the display panel 1 includes a display area AA and a non-display area NA located on at least one side of the display area AA. The display panel 1 includes a substrate 10, a first transistor 20, and a second transistor 30. Both the first transistor 20 and the second transistor 30 are disposed on one side of the substrate 10. The first transistor 20 is located in the display area AA, and the second transistor 30 is located in the non-display area NA. The first transistor 20 includes a first active portion 21, and the second transistor 30 includes a second active portion 31. The first active portion 21 and the second active portion 31 are made of different materials. A pixel electrode 41 is disposed on the side of the first transistor 20 away from the substrate 10. The pixel electrode 41 passes through a first via 23a and is connected to the first active portion 21.

[0055] Display panel 1 can be an LCD panel, etc. The LCD panel is a non-self-emissive panel and requires a backlight module to provide a backlight source.

[0056] like Figure 1 As shown, the display panel 1 has a display area AA and a non-display area NA disposed around the display area AA. The display area AA can be provided with multiple sub-pixels 11, which can include red sub-pixels, green sub-pixels, and blue sub-pixels, thereby realizing color display. A pixel driving circuit can be disposed within the display area AA to control the display of the sub-pixels 11. The non-display area NA can be provided with a gate driving circuit, etc., which can provide scanning signals to the sub-pixels 11.

[0057] The substrate 10 can be a rigid material or a flexible material. The rigid material can be glass, quartz, or silicon wafer. The flexible material can be one of polyimide (PI), polycarbonate (PC), polynorbornene (PNB), and polyethylene terephthalate (PET).

[0058] like Figures 2 to 4 As shown, the first transistor 20 and the second transistor 30 are disposed on the same side of the substrate 10. Both the first transistor 20 and the second transistor 30 can be thin-film transistors. The first transistor 20 is located within the display area AA and can be a transistor in a pixel driving circuit. The second transistor 30 is located within the non-display area NA and can be a transistor in a gate driving circuit.

[0059] The first active portion 21 and the second active portion 31 are made of different materials. For example, the first active portion 21 can be made of metal-oxide semiconductor, such as IGZO (indium gallium zinc oxide), ZnO (zinc oxide), IZO (indium zinc oxide), IGTO (indium gallium tin oxide), IZTO (indium zinc tin oxide), etc. Metal-oxide transistors have the characteristic of low leakage current and are used in pixel driving circuits, resulting in low power consumption.

[0060] The material of the second active part 31 can be cryogenic polysilicon, etc. Because cryogenic polysilicon transistors have high electron mobility, they are suitable for high-speed switching and high-resolution displays. When applied in gate drive circuits, cryogenic polysilicon transistors can achieve high refresh rates and provide smooth display images.

[0061] Therefore, by using different materials for the first active part 21 and the second active part 31, the characteristics of the two materials can be combined to realize LTPO (Low-Temperature Polycrystalline Oxide) technology. This allows the display panel 1 to reduce the refresh rate to save power when displaying static images, while providing a smooth visual experience in scenarios requiring a high refresh rate. The display panel 1 using LTPO technology can be applied to various application scenarios such as VR (Virtual Reality), dedicated displays, and consumer products.

[0062] like Figures 2 to 4 As shown, the pixel electrode 41 is disposed on the side of the first transistor 20 facing away from the substrate 10. The pixel electrode 41 is made of a transparent conductive material, such as ITO (indium tin oxide), IZO (indium zinc oxide), IZTO (indium zinc tin oxide), IAZO (indium aluminum zinc oxide), IGZO (indium gallium zinc oxide), IGTO (indium gallium tin oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), IGZTO (indium gallium zinc tin oxide), IGO (indium gallium oxide), InO (indium oxide), etc.

[0063] In the liquid crystal panel, the display panel 1 also includes a liquid crystal layer (not shown in the figure). The liquid crystal molecules in the liquid crystal layer are deflected under the influence of an electric field, and different deflection angles correspond to different light transmittances. By controlling the magnitude of the electric field, the light transmittance of the display panel 1 can be adjusted. Pixel electrodes 41 are used to provide an electric field to the liquid crystal molecules.

[0064] like Figures 2 to 4As shown, the pixel electrode 41 passes through the first via 23a and connects to the first active portion 21. An insulating layer is provided between the pixel electrode 41 and the first active portion 21 to achieve insulation between adjacent conductive materials. The first via 23a penetrates the insulating layer between the pixel electrode 41 and the first active portion 21, exposing the first active portion 21 located at the bottom of the first via 23a. The pixel electrode 41 is deposited in the first via 23a and contacts the first active portion 21, thereby connecting the pixel electrode 41 to the first active portion 21. By connecting the pixel electrode 41 to the first active portion 21 through the first via 23a, the drain of the first transistor 20 can be omitted, thereby simplifying the manufacturing process of the display panel 1 and reducing manufacturing costs. At the same time, compared with an opaque drain, the pixel electrode 41 does not block light, which can increase the aperture ratio of the display panel 1 and improve the brightness of the display panel 1.

[0065] Optionally, such as Figures 2 to 4 As shown, the display panel 1 includes an interlayer insulating layer 16 and a planarization layer 17. The interlayer insulating layer 16 is disposed between the first active portion 21 and the pixel electrode 41; the planarization layer 17 is disposed between the interlayer insulating layer 16 and the pixel electrode 41; wherein, the first via 23a penetrates the planarization layer 17 and the interlayer insulating layer 16.

[0066] The interlayer insulation layer 16 can be an inorganic material, such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0067] The planarization layer 17 can be an organic material, such as acrylic resin, epoxy resin, or perfluoroalkoxy resin (PFA). Organic materials have leveling properties, which can provide a smoother surface for the pixel electrode 41 and improve the display effect.

[0068] like Figures 2 to 4 As shown, the first via 23a penetrates the planarization layer 17 and the interlayer insulating layer 16. That is to say, the first via 23a passes through the planarization layer 17 and the interlayer insulating layer 16 located between the pixel electrode 41 and the first active portion 21.

[0069] In related technologies, to increase the light transmittance of the display panel 1, a transparent metal is used to form the drain of the first transistor 20. This requires two photomasks, one for forming the drain and the other for forming the via connecting the drain to the first active part 21. Adding photomasks not only increases the complexity of the process but also increases the manufacturing cost of the display panel 1. However, in the embodiment of this application, the first via 23a can be formed using a single photomask, thus eliminating the need for the two photomasks used in related technologies to form the drain and the via connecting the drain to the first active part 21. This simplifies the manufacturing process of the display panel 1 and reduces its manufacturing cost.

[0070] Optionally, such as Figures 2 to 4As shown, the display panel 1 also includes a common electrode 42 and a first passivation layer 18. The common electrode 42 is disposed on the side of the planarization layer 17 away from the substrate 10. The first passivation layer 18 is disposed between the common electrode 42 and the pixel electrode 41. The common electrode 42 is disposed on the side of the pixel electrode 41 away from the substrate 10, or the common electrode 42 is disposed on the side of the pixel electrode 41 close to the substrate 10.

[0071] The material of the common electrode 42 can be a transparent conductive material, such as ITO (indium tin oxide), IZO (indium zinc oxide), IZTO (indium zinc tin oxide), IAZO (indium aluminum zinc oxide), IGZO (indium gallium zinc oxide), IGTO (indium gallium tin oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), IGZTO (indium gallium zinc tin oxide), IGO (indium gallium oxide), InO (indium oxide), etc.

[0072] In some embodiments, such as Figure 2 As shown, the common electrode 42 is disposed on the side of the pixel electrode 41 facing away from the substrate 10. Both the common electrode 42 and the pixel electrode 41 can be located on the substrate 10, with the common electrode 42 located on the side of the pixel electrode 41 furthest from the substrate 10. This means that the common electrode 42 and the pixel electrode 41 are located on the same side of the liquid crystal layer near the substrate 10. Alternatively, the common electrode 42 can be located on a counter substrate 10 opposite to the substrate 10, i.e., the common electrode 42 and the pixel electrode 41 are located on different sides of the liquid crystal layer.

[0073] In some embodiments, such as Figure 3 and Figure 4 As shown, the common electrode 42 is disposed on the side of the pixel electrode 41 closest to the substrate 10, meaning that the common electrode 42 is located between the pixel electrode 41 and the substrate 10. At this time, the liquid crystal layer is located on the side of the pixel electrode 41 furthest from the substrate 10.

[0074] It should be noted that when the common electrode 42 is disposed on the side of the pixel electrode 41 close to the substrate 10, the first via 23a penetrates the first passivation layer 18, the planarization layer 17, and the interlayer insulating layer 16. In this case, a common photomask can be used to form the first via 23a. Compared with a halftone photomask, the cost of a common photomask is reduced, and the process difficulty is reduced, which can save manufacturing costs and photomask costs, and further reduce the manufacturing cost of the display panel 1.

[0075] Liquid crystal molecules in the liquid crystal layer are deflected in the electric field formed by the pixel electrode 41 and the common electrode 42, achieving different transmittance, thereby realizing the brightness control of the display panel 1.

[0076] The first passivation layer 18 can be made of inorganic materials, such as silicon oxide, silicon nitride, silicon oxynitride, etc. The first passivation layer 18 can be used to achieve insulation between the pixel electrode 41 and the common electrode 42. The first passivation layer 18 can also protect the underlying conductive layer to prevent moisture and other substances from entering the first transistor 20 and affecting the performance of the first transistor 20.

[0077] Optionally, such as Figure 2 As shown, the common electrode 42 is disposed on the side of the pixel electrode 41 facing away from the substrate 10. The orthographic projection of the common electrode 42 on the substrate 10 covers the orthographic projection of the pattern of the first via 23a on the substrate 10. That is to say, the common electrode 42 and the first via 23a are directly aligned. With the above arrangement, the common electrode 42 and the pixel electrode 41 can form an electric field directly above the first via 23a, thereby controlling the deflection of liquid crystal molecules in the liquid crystal layer. That is, the first via 23a will not affect the aperture ratio of the display panel 1, thereby improving the brightness of the display panel 1.

[0078] Optionally, such as Figure 4 As shown, the common electrode 42 is disposed on the side of the pixel electrode 41 close to the substrate 10; wherein, the display panel 1 includes a second passivation layer 19 disposed on the side of the pixel electrode 41 away from the substrate 10, and the second passivation layer 19 at least covers the first via 23a.

[0079] The material of the second passivation layer 19 can be the same as that of the first passivation layer 18. For example, the material of the second passivation layer 19 can be silicon oxide, silicon nitride, silicon oxynitride, etc.

[0080] The second passivation layer 19 covers the first via 23a, thereby protecting the first via 23a from moisture and other contaminants that could invade the first active part 21 and affect the performance of the first transistor 20. Specifically, the second passivation layer 19 may cover the material of the pixel electrode 41 located within the first via 23a.

[0081] Optionally, such as Figures 2 to 4 As shown, the display panel 1 also includes a source-drain layer 43, a trace portion 44, and a parallel portion 46. The source-drain layer 43 is disposed between the interlayer insulating layer 16 and the planarization layer 17. The source-drain layer 43 includes a first source 22 of the first transistor 20, a second drain 33 of the second transistor 30, and a second source 32. The trace portion 44 is disposed in the non-display area NA and is disposed on the same layer as the common electrode 42. The parallel portion 46 is disposed in the non-display area NA and is disposed on the same layer as the first source 22. The trace portion 44 passes through a third via 44a and is electrically connected to the parallel portion 46.

[0082] In some embodiments, the trace portion 44 passes through the third via 44a and is electrically connected to the parallel portion 46, thereby reducing the resistance of the trace portion 44.

[0083] In some embodiments, such as Figures 2 to 4 As shown, the first source 22, the second source 32, and the second drain 33 are arranged on the same layer, so that the first source 22, the second source 32, and the second drain 33 can be formed using the same photomask, simplifying the manufacturing process of the display panel 1 and reducing the manufacturing cost.

[0084] In some embodiments, the materials of the first source 22, the second source 32, and the second drain 33 may be any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or their alloys.

[0085] like Figures 2 to 4 As shown, the trace portion 44 is located in the non-display area NA. For example, the trace portion 44 can be a trace in the gate drive circuit, but it is not limited to this. The trace portion 44 is disposed on the same layer as the common electrode 42, which means that the trace portion 44 and the common electrode 42 are made of the same material and are formed using the same photomask.

[0086] Optionally, Figures 6A to 6D This is a process flow diagram of a first transistor 20 provided in an exemplary embodiment of this disclosure. For example... Figures 6A to 6D It shows Figures 2 to 4 A process flow diagram of the film layer at the first transistor 20. (See diagram below.) Figures 6A to 6D As shown, the first via 23a includes a first sub-via 231a and a second sub-via 232a that are connected. The first sub-via 231a penetrates the planarization layer 17, and the second sub-via 232a penetrates the interlayer insulating layer 16. At the interface between the planarization layer 17 and the interlayer insulating layer 16, the difference between the aperture d1 of the first sub-via and the aperture d2 of the second sub-via is greater than or equal to zero and less than or equal to 4 micrometers. For example, the difference between the aperture d1 of the first sub-via and the aperture d2 of the second sub-via can be 0, 0.5, 1 micrometer, 1.5 micrometers, 2 micrometers, 2.5 micrometers, 3 micrometers, 3.5 micrometers, 4 micrometers, etc.

[0087] The interface between the planarization layer 17 and the interlayer insulation layer 16 refers to the surface of the planarization layer 17 that is close to the interlayer insulation layer 16, and also refers to the surface of the interlayer insulation layer 16 that is close to the planarization layer 17. The surface of the planarization layer 17 that is close to the interlayer insulation layer 16 coincides with the surface of the interlayer insulation layer 16 that is close to the planarization layer 17.

[0088] In some embodiments, the first sub-hole 231a and the second sub-hole 232a are coaxially arranged.

[0089] Specifically, such as Figure 6A As shown, the first source electrode 22 is formed.

[0090] Combination Figure 2 and Figure 6B A planarization layer 17 is formed on the first source electrode 22. A halftone mask is used to expose the planarization layer 17 to form a third via 44a and a first sub-via 231a of different depths.

[0091] like Figure 6C As shown, the first sub-hole 231a is self-aligned, and the interlayer insulating layer 16 is penetrated by etching process to form a second sub-hole 232a that communicates with the first sub-hole 231a, thereby forming the first via 23a.

[0092] like Figure 6D As shown, a pixel electrode 41 is formed on the planarization layer 17, and the pixel electrode 41 is connected to the first active part 21 through the first via 23a.

[0093] Since the first sub-hole 231a and the second sub-hole 232a are formed using the same photomask, the first sub-hole 231a and the second sub-hole 232a are coaxially arranged.

[0094] In some embodiments, such as Figure 6C As shown, at the interface between the planarization layer 17 and the interlayer insulation layer 16, the difference between the aperture d1 of the first sub-hole and the aperture d2 of the second sub-hole is zero. This means that the aperture d2 of the first sub-hole 231a and the second sub-hole are smoothly transitioned, and there is no step surface between the sidewall of the first sub-hole 231a and the sidewall of the second sub-hole 232a.

[0095] In some embodiments, at the interface between the planarization layer 17 and the interlayer insulating layer 16, the difference between the aperture d1 of the first sub-via and the aperture d2 of the second sub-via is greater than zero and less than or equal to 4 micrometers. That is, the aperture d1 of the first sub-via is greater than the aperture d2 of the second sub-via, and at the interface between the planarization layer 17 and the interlayer insulating layer 16, the difference between the aperture d1 of the first sub-via and the aperture d2 of the second sub-via is less than 4 micrometers.

[0096] It should be noted that due to process reasons, such as Figures 6A to 6D As shown, in the thickness direction of the display panel 1, the first via 23a is a hole with a larger diameter at the top and a smaller diameter at the bottom, that is, the diameter of the first via 23a near the end of the substrate 10 is smaller than the diameter of the first via 23a away from the substrate 10. In order to ensure good contact between the pixel electrode 41 and the first active part 21 in the first via 23a, the diameter of the second sub-hole 232a near the end of the first active part 21 cannot be too small. In order to avoid the first sub-hole having an excessively large diameter d1, which would occupy too much space, the difference between the first sub-hole 231a and the second sub-hole 232a at the interface between the planarization layer 17 and the interlayer insulating layer 16 can be less than 4 micrometers.

[0097] Optionally, combined Figure 1 and Figure 5The display panel 1 includes multiple data lines 61 extending along a first direction D1 and multiple scan lines 62 extending along a second direction D2. The first direction D1 and the second direction D2 intersect. It should be noted that... Figure 5 Only two scan lines 62 and two data lines 61 are shown. The two adjacent data lines 61 and the two adjacent scan lines 62 form a pixel opening 60a; wherein, the first via 23a is located within the pixel opening 60a, and the minimum distance s1 between the first via 23a and the scan line 62 is less than the minimum distance s2 between the first via 23a and the data line 61.

[0098] In some embodiments, the angle between the first direction D1 and the second direction D2 can be a right angle, an acute angle, or an obtuse angle.

[0099] Data line 61 is used to provide data signals to sub-pixel 11, and data line 61 is electrically connected to the first transistor 20. Scan line 62 is used to provide scan signals to sub-pixel 11, and scan line 62 is electrically connected to the first transistor 20.

[0100] In some embodiments, the scan line 62 and data line 61 may be made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. The scan line 62 and data line 61 are made of opaque materials.

[0101] In some embodiments, such as Figure 5 As shown, the display panel 1 also includes a light-shielding layer 63. The material of the light-shielding layer 63 is a light-shielding material, such as a black matrix. The light-shielding layer 63 covers the scan lines 62 to prevent light crosstalk between two adjacent sub-pixels 11.

[0102] Two adjacent data lines 61 and two adjacent scan lines 62 together form a pixel opening 60a, with one pixel opening 60a corresponding to one sub-pixel 11. Light emitted from the backlight module can pass through the pixel opening 60a for display. This means that the pixel opening 60a is a light-transmitting area, and the area between two adjacent pixel openings 60a is a non-light-transmitting area. When the proportion of the light-transmitting area to the total display area AA increases, the aperture ratio of the display panel 1 increases, which can improve the brightness of the display panel 1.

[0103] In some embodiments, such as Figure 5As shown, the first via 23a is located within the pixel opening 60a. Since both the first active portion 21 and the pixel electrode 41 are made of transparent materials, placing the first via 23a within the pixel opening 60a does not block the light from the backlight module. Therefore, the first via 23a does not reduce the aperture ratio of the display panel 1. In related technologies, the orthographic projection of the first via 23a onto the substrate 10 overlaps with the orthographic projection of the light-shielding layer 63 onto the substrate 10, which increases the area of ​​the light-shielding layer 63, i.e., increases the area of ​​the non-transparent region, resulting in a decrease in the aperture ratio of the display panel 1. Therefore, relatively speaking, the embodiment of this application can increase the aperture ratio of the display panel 1.

[0104] In some embodiments, such as Figure 5 As shown, the minimum distance s1 between the first via 23a and the scan line 62 is less than the minimum distance s2 between the first via 23a and the data line 61. This means that, relatively speaking, the distance between the first via 23a and the scan line 62 is smaller, while the distance between the first via 23a and the data line 61 is larger; that is, the first via 23a is positioned closer to the scan line 62. This arrangement allows the first via 23a to be positioned closer to the edge of the pixel opening 60a, thereby reducing the amount of liquid crystal molecules above the first via 23a entering the first via 23a and affecting the degree of deflection of the liquid crystal molecules.

[0105] Optionally, such as Figures 2 to 5 As shown, the interlayer insulating layer 16 is provided with a second via 24a. The first source electrode 22 passes through the second via 24a and contacts the first active part 21. The orthographic projection of the pattern of the second via 24a on the substrate 10 overlaps with the orthographic projection of the data line 61 on the substrate 10. The second active part 31 is disposed between the first active part 21 and the substrate 10. The second source electrode 32 and the second drain electrode 33 are disposed between the interlayer insulating layer 16 and the planarization layer 17.

[0106] It should be noted that the orthographic projection of the pattern of the first via 23a onto the substrate 10 is larger than that of the pattern of the second via 24a onto the substrate 10. This ensures that the contact area between the first via 23a and the second active part 31 is sufficiently large to meet the reliability of the electrical connection. This is because the thickness of the film layer penetrated by the first via 23a is greater than the thickness of the film layer penetrated by the second via 24a, meaning the depth of the first via 23a is greater than the depth of the second via 24a. Due to manufacturing processes, the sidewalls of the first via 23a and the second via 24a are formed with inclined surfaces, meaning the aperture of the via near the substrate 10 is smaller than the aperture of the via away from the substrate 10. When the orthographic projection patterns of the first via 23a and the second via 24a are the same size, the contact area between the first via 23a and the second active part 31 will be too small, affecting the reliability of the electrical connection.

[0107] In some embodiments, such as Figures 2 to 5As shown, the first source 22 and the first active part 21 are connected through a second via 24a. The orthographic projection of the pattern of the second via 24a on the substrate 10 overlaps with the orthographic projection of the data line 61 on the substrate 10. This means that the data line 61 passes through the second via 24a and connects to the first active part 21. With this configuration, a portion of the material of the data line 61 can be used as the first source 22. This configuration simplifies the manufacturing process of the display panel 1 and avoids reducing the aperture ratio of the display panel 1 by occupying a non-transparent area when additionally fabricating the source of the first transistor 20.

[0108] In some embodiments, such as Figure 5 As shown, one end of the second active portion 31 overlaps with the data line 61, the other end of the second active portion 31 overlaps with the pixel electrode 41, and the middle region of the second active portion 31 overlaps with the first gate 25 and the third gate 26.

[0109] In some embodiments, in order to increase the overlap area between the second active portion 31 and the data line 61 so as to facilitate the provision of the second via 24a, the end of the second active portion 31 that overlaps with the data line 61 may extend in the same direction as the data line 61.

[0110] In some embodiments, the extension direction of the middle region of the second active portion 31 is perpendicular to the extension direction of the first gate 25, and the portion of the middle region of the second active portion 31 that overlaps with the first gate 25 forms a channel region, which is used to form a carrier flow channel. When the extension direction of the middle region of the second active portion 31 is perpendicular to the extension direction of the first gate 25, Figure 5 The vertical direction is the length direction of the channel, and the horizontal direction is the width direction of the channel. In this case, the length of the channel is defined by the width of the first gate 25 or the third gate 26, resulting in the shortest channel length. Compared to when the middle region of the second active portion 31 forms an acute or obtuse angle with the extension direction of the first gate 25, the second active portion 31 does not need to occupy additional horizontal space, thus significantly reducing the overall area of ​​the second transistor 30.

[0111] In some embodiments, such as Figures 2 to 4 As shown, the second source 32 and the second drain 33 are located between the interlayer insulating layer 16 and the planarization layer 17.

[0112] In some embodiments, such as Figures 2 to 4 As shown, the second source 32, the second drain 33, and the data line 61 are all arranged on the same layer, so that the second source 32, the second drain 33, and the data line 61 can be formed using the same photomask, which simplifies the manufacturing process of the display panel 1 and reduces the manufacturing cost.

[0113] In some embodiments, such as Figures 2 to 4As shown, the first transistor 20 further includes a first gate 25, and the second transistor 30 further includes a second gate 34. The first gate 25 and the second gate 34 can be disposed on the same layer. Specifically, the first gate 25 can be disposed on the side of the first active portion 21 close to the substrate 10. The second gate 34 can be disposed on the side of the second active portion 31 opposite to the substrate 10.

[0114] In some embodiments, such as Figures 2 to 4 As shown, the first transistor 20 also includes a third gate 26, which is disposed on the side of the first active portion 21 away from the substrate 10, that is, the first transistor 20 can be a dual-gate transistor.

[0115] In some embodiments, the first gate 25, the second gate 34, and the third gate 26 may be formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof. The scan line 62 may be disposed with the first gate 25, or the scan line 62 may be disposed in the same layer as the third gate 26.

[0116] In some embodiments, such as Figures 2 to 4 As shown, the display panel 1 also includes a buffer layer 12, which can be made of silicon oxide, silicon nitride, silicon oxynitride, etc.

[0117] In some embodiments, such as Figures 2 to 4 As shown, the display panel 1 also includes a first gate insulating layer 13 disposed between the second gate 34 and the second active portion 31, and a second gate insulating layer 14 disposed between the first gate 25 and the first active portion 21.

[0118] In some embodiments, the display panel 1 further includes a third gate insulating layer 15 disposed between the third gate 26 and the first active portion 21. When the display panel 1 includes the third gate insulating layer 15, the first via 23a penetrates the planarization layer 17, the interlayer insulating layer 16, and the third gate insulating layer 15.

[0119] Figure 2 and Figure 3 The display panel 1 shown only requires 11 photomasks to form, which saves 2 photomasks compared to the 13 photomasks in related technologies, reducing the complexity of the process and the manufacturing cost.

[0120] Figure 4 The display panel 1 shown only requires 12 photomasks to form, which saves 1 photomask compared to 13 photomasks in related technologies, reducing the complexity of the process and the manufacturing cost.

[0121] According to the second aspect of this application, such as Figure 7 As shown, a display terminal 2 is provided, including the display panel 1 described above.

[0122] In this embodiment, as Figure 7 As shown, the display terminal 2 includes a display panel 1 and a terminal body 3, which are combined into one unit.

[0123] In this embodiment, the display terminal 2 can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0124] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0125] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0126] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0127] The above description is merely a preferred embodiment of this application and does not constitute any limitation on this application. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area located on at least one side of the display area. substrate; The first transistor and the second transistor are both disposed on one side of the substrate. The first transistor is located in the display area and the second transistor is located in the non-display area. The first transistor includes a first active portion and the second transistor includes a second active portion. The first active portion and the second active portion are made of different materials. A pixel electrode is disposed on the side of the first transistor away from the substrate, and the pixel electrode passes through a first via and contacts the first active portion.

2. The display panel according to claim 1, characterized in that, The display panel includes: An interlayer insulating layer is disposed between the first active portion and the pixel electrode; A planarization layer is disposed between the interlayer insulating layer and the pixel electrode; The first via penetrates the planarization layer and the interlayer insulation layer.

3. The display panel according to claim 2, characterized in that, The display panel also includes: A common electrode is disposed on the side of the planarization layer opposite to the substrate; A first passivation layer is disposed between the common electrode and the pixel electrode; The common electrode is disposed on the side of the pixel electrode away from the substrate, or the common electrode is disposed on the side of the pixel electrode close to the substrate.

4. The display panel according to claim 3, characterized in that, The common electrode is disposed on the side of the pixel electrode opposite to the substrate, and the orthogonal projection of the common electrode on the substrate covers the orthogonal projection of the pattern of the first via on the substrate.

5. The display panel according to claim 3, characterized in that, The common electrode is disposed on the side of the pixel electrode close to the substrate; The display panel includes a second passivation layer disposed on the side of the pixel electrode opposite to the substrate, and the second passivation layer at least covers the first via.

6. The display panel according to claim 3, characterized in that, The display panel also includes: A source-drain layer is disposed between the interlayer insulating layer and the planarization layer, and the source-drain layer includes a first source of the first transistor, a second drain of the second transistor, and a second source of the second transistor. A trace section is disposed in the non-display area, and the trace section is disposed on the same layer as the common electrode; The parallel connection section is disposed in the non-display area, and the parallel connection section is disposed on the same layer as the first source electrode; The wiring section passes through the third via and is electrically connected to the parallel section.

7. The display panel according to claim 6, characterized in that, The display panel includes multiple data lines extending along a first direction and multiple scan lines extending along a second direction. The first direction and the second direction intersect, and two adjacent data lines and two adjacent scan lines form a pixel opening. The first via is located within the pixel opening, and the minimum distance between the first via and the scan line is less than the minimum distance between the first via and the data line.

8. The display panel according to claim 7, characterized in that, The interlayer insulating layer is provided with a second via, the first source electrode passes through the second via and contacts the first active part, the orthographic projection of the pattern of the second via on the substrate overlaps with the orthographic projection of the data line on the substrate, the second active part is disposed between the first active part and the substrate, and the second source electrode and the second drain electrode are disposed between the interlayer insulating layer and the planarization layer.

9. The display panel according to any one of claims 2 to 8, characterized in that, The first via includes a first sub-via and a second sub-via that are connected, the first sub-via penetrating the planarization layer and the second via penetrating the interlayer insulation layer; Wherein, at the interface between the planarization layer and the interlayer insulating layer, the difference between the aperture of the first sub-hole and the aperture of the second sub-hole is greater than or equal to zero and less than or equal to 4 micrometers.

10. A display terminal, characterized in that, Includes the display panel as described in any one of claims 1 to 9.

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