Cache error correction method, error correction device, cache controller and computer equipment

Abstract

The invention provides a cache error correction method, an error correction device, a cache controller and computer equipment, the method is applied to a processor cache, and the method comprises the following steps: when the cache detects error data in the process of processing a read-write request, pausing a new read-write request to enter the cache; an error correction step is added in the cache assembly line, wherein the error correction step is used for correcting error data; generating an error correction request, wherein the error correction request is used for modifying the error data in the cache into correct data; and executing the error correction request to read the error data from the cache, modifying the error data into correct data, and writing the correct data into the cache. According to the method, efficient error correction processing on the cached data can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the computer technical field, and in particular to a cache error correction method, an error correction device, a cache controller and a computer device. BACKGROUND

[0002] A cache pipeline is arranged in the cache of the processor. When the processor needs to read and write data, a read-write request is sent to the cache. After the read-write request enters the cache pipeline, the cache processes in sequence according to each processing step of the pipeline, and finally the processor obtains the data to be read and written.

[0003] Due to the existence of interference, the data in the cache may be erroneous, which may cause the processor to obtain erroneous data when reading and writing data from the cache. Therefore, the erroneous data should be discovered in time and repaired during the running of the cache pipeline, so as to ensure that the processor obtains correct data from the cache without affecting the running of the cache as much as possible. SUMMARY

[0004] In view of the above technical status, the present application provides a cache error correction method, an error correction device, a cache controller and a computer device, which can realize efficient error correction processing of cache data.

[0005] The first aspect of the present application provides a cache error correction method applied to a processor cache, and the method comprises the following steps.

[0006] When the cache detects erroneous data during processing of a read-write request, a new read-write request is paused from entering the cache.

[0007] An error correction step is added in the pipeline of the cache, and the error correction step is used for error correction of the erroneous data.

[0008] An error correction request is generated, and the error correction request is used for modifying the erroneous data in the cache to correct data.

[0009] The error correction request is executed to read out the erroneous data from the cache, modify the erroneous data to correct data, and then write the correct data into the cache.

[0010] In some implementations, when the cache detects erroneous data during processing of a read-write request, the method further comprises the following steps.

[0011] The read-write request is stored in a buffer.

[0012] In addition,

[0013] After the error correction step is added in the pipeline of the cache, the read-write request is taken out from the buffer and reenters the pipeline of the cache.

[0014] In some implementations, the method further includes:

[0015] After the correct data is written into the cache, a new read-write request is initiated to enter the cache, and a timer is started to begin timing;

[0016] If the cache does not detect error data within a set time period, the error correction step in the pipeline of the cache is removed.

[0017] In some implementations, the cache includes a first sub-cache and a second sub-cache;

[0018] The adding of the error correction step in the pipeline of the cache includes adding the error correction step in the pipeline of the first sub-cache;

[0019] After the correct data is written into the cache, the method further includes:

[0020] The adding of the error correction step in the pipeline of the second sub-cache.

[0021] In some implementations, the method further includes:

[0022] A new read-write request is initiated to enter the cache, and a timer is started to begin timing;

[0023] In a case where the first sub-cache and the second sub-cache do not detect error data within a set time period, the error correction steps in the pipelines of the first sub-cache and the second sub-cache are synchronously removed.

[0024] In some implementations, the flag storage body and the data storage body in the cache share the same storage body; or, the flag storage body and the data storage body in the cache occupy different storage bodies respectively;

[0025] In a case where the flag storage body and the data storage body in the cache occupy different storage bodies respectively, the cache detecting error data in processing a read-write request includes:

[0026] The cache detects error data in the flag storage body in processing the read-write request; or, the cache detects error data in the data storage body in processing the read-write request.

[0027] In some implementations, in a case where the flag storage body and the data storage body in the cache occupy different storage bodies respectively, the cache detecting error data in processing a read-write request includes: the cache detects error data in the flag storage body in processing the read-write request;

[0028] The method further comprises:

[0029] In the case that the error data is detected in the data storage body in the process of processing the read-write request, the cache returns the data read from the data storage body to the request source sending the read-write request, and sends error data prompt information, and modifies the error data in the data storage body to correct data.

[0030] The error data prompt information is used to instruct the request source to resend the read-write request.

[0031] The second aspect of the application provides an error correction device applied to a processor cache, the error correction device comprising:

[0032] The first control unit is configured to pause new read-write requests from entering the cache when the cache detects error data in the process of processing the read-write request.

[0033] The first processing unit is configured to add an error correction step in the pipeline of the cache, and the error correction step is used to correct error data.

[0034] The second processing unit is configured to generate an error correction request, and the error correction request is used to modify error data in the cache to correct data.

[0035] The second control unit is configured to execute the error correction request to read out the error data from the cache, modify the error data to correct data, and write the correct data into the cache.

[0036] The third aspect of the application provides a cache controller applied to a processor cache, and the cache controller is configured to execute the cache error correction method described above.

[0037] The fourth aspect of the application provides a computer device comprising the error correction device described above or the cache controller described above.

[0038] The cache error correction method provided by the application can find error data in the cache, add an error correction step in the cache pipeline, so that subsequent read-write requests that have entered the cache pipeline can obtain correct data, so that these read-write requests can be successfully processed. The method not only can realize effective cache data error detection and correction processing, but also can ensure that the processor obtains correct data from the cache in time without affecting the operation of the cache as much as possible, and avoid increasing data reading delay due to data errors. On the other hand, the method also modifies the error data stored in the cache storage body to correct data, which fundamentally solves the problem of data errors. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only belong to the embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of the provided drawings.

[0040] Figure 1 A schematic diagram of a multi-level cache processor architecture provided by an embodiment of the present application.

[0041] Figure 2 And Figure 3 Schematic diagrams of two cache pipelines provided by an embodiment of the present application.

[0042] Figure 4 A flowchart of a cache error correction method provided by an embodiment of the present application.

[0043] Figures 5-7 Schematic diagrams of several other cache pipelines provided by an embodiment of the present application.

[0044] Figure 8 A flowchart of another cache error correction method provided by an embodiment of the present application. DETAILED DESCRIPTION

[0045] The technical solutions of the embodiments of the present application are applicable to the application scenarios of data error detection and correction in the process of requesting data from the cache. By using the technical solutions of the embodiments of the present application, efficient data error detection and correction processing can be achieved during the operation of the cache, and the problem of resource conflict between different sub-cache pipelines caused by data error detection and correction processing can be avoided.

[0046] In the hierarchy of computer storage systems, the cache is a high-speed small-capacity memory between the central processing unit and the main memory, which is composed of static storage chips (SRAM) and has a relatively small capacity but a faster speed than the main memory, close to the speed of the CPU.

[0047] The working principle of the cache is that when the CPU wants to read a data, it first searches in the CPU cache, finds it immediately, and reads and sends it to the CPU for processing; if it is not found, it is read from the relatively slow memory and sent to the CPU for processing, and at the same time the data block where the data is located is called into the cache, so that subsequent reading of the entire block of data is performed from the cache without calling the memory. Such a reading mechanism increases the hit rate of the CPU reading the cache, that is, the next data to be read by the CPU has a higher probability of being in the CPU cache, and only a small amount of data needs to be read from the memory. This greatly saves the time of the CPU reading the memory directly, and also makes the CPU read data without waiting basically.

[0048] The data in the cache is only a copy of part of the data in the memory, so when the CPU looks for data in the cache, it can also not find it (because some data has not been copied from the memory to the cache), at which time the CPU will still read the data from the memory, so the data reading speed of the CPU is relatively slower, but the CPU will copy the read data to the cache for the next use. Therefore, the more frequently the data is accessed, the longer it will exist in the cache. At the same time, with the change of time, the data that is accessed most frequently will also change, so the data in the cache needs to be replaced frequently according to a certain algorithm, so as to ensure that the data in the cache is always the data that is accessed most frequently.

[0049] The technical scheme of the embodiment of the present application is applicable to a single-level cache processor architecture, that is, a single-layer cache is arranged between the processor and the system main memory.

[0050] In other embodiments, the technical scheme of the embodiment of the present application is also applicable to a multi-level cache processor architecture, which includes multiple levels of cache, such as two levels of cache, three levels of cache, four levels of cache, and any number of levels of cache.

[0051] In the above multi-level cache, according to the distance between the cache and the processor core, the multi-level cache can be defined as a first-level cache, a second-level cache, a third-level cache, and so on. The closer the level of the cache, the closer the distance to the processor core, and the faster the speed of reading data from the processor core. Conversely, the farther the level of the cache, the farther the distance to the processor core, and the slower the speed of reading data from the processor core. For example, the speed of reading data from the first-level cache is higher than that from the second-level cache, and the speed of reading data from the second-level cache is higher than that from the third-level cache.

[0052] Generally, the closer the level of the cache, the higher the frequency of reading the stored data by the processor core, and the farther the level of the cache, the lower the frequency of reading the stored data by the processor core. Moreover, generally, the closer the level of the cache, the smaller the space, and the farther the level of the cache, the larger the space.

[0053] Figure 1 The multi-level cache processor architecture provided by the embodiment of the present application includes a first-level cache L1, a second-level cache L2, and a third-level cache L3.

[0054] The first-level cache L1 is further divided into an instruction cache L1I and a data cache L1D, the instruction cache L1I is used to cache instructions, and the data cache L1D is used to cache data.

[0055] The first level cache L1 includes instruction cache L1I and data cache L1D, and shares the second level cache L2.

[0056] In the multi-level cache processor architecture, a plurality of processor cores are included, and for each processor core, a dedicated first level cache (including instruction cache L1I and data cache L1D) and a second level cache L2 are configured respectively. The plurality of processor cores share a third level cache L3.

[0057] Continuing to refer to Figure 1 For the plurality of processor cores, different regions can also be divided, and for each processor core in each region, a dedicated first level cache (including instruction cache L1I and data cache L1D) and a second level cache L2 are configured respectively, and the processor cores in the region share a third level cache L3. The processor cores in the plurality of regions share a system main memory through an on-chip network.

[0058] In the above processor architecture, when a LOAD instruction misses the data to be read in L1D, L1D sends a read request to L2 to read the data from L2. If the data is still not in L2, a read request is sent to L3 to read the data from L3. If the data is still not in L3, the data needs to be read from the main memory. In the above process, if the data to be read is read in a certain level cache, the data is returned to the upper cache in turn until it is returned to the processor. For example, if the data is read from L2, the cache line where the data is located is returned to L1, and the cache line is stored in L1, and L1 returns the cache line to the processor.

[0059] The embodiment of the application can be applied to the cache in a single-level cache processor architecture, or to any level cache in the above multi-level cache processor architecture, to implement data error detection and correction processing in the process of reading data from the cache, and to ensure that correct data is read from the cache.

[0060] In the cache, a tag storage body (Tag Ram) and a data storage body (Data Ram) are usually included, wherein the address information and the valid bit are saved in the Tag Ram, and the valid bit is used to identify whether a block (cacheline) contains a valid address. If the bit is not set, the content in the block (cacheline) cannot be used. These address information can be used to determine whether the data in the cache is the desired data. The data of the address is saved in the Data Ram.

[0061] When the cache capacity is small, the tag memory (Tag Ram) and the data memory (Data Ram) can share one memory bank, and when the cache capacity is large, the tag memory (Tag Ram) and the data memory (Data Ram) need to occupy different memory banks respectively.

[0062] A cache pipeline is arranged in the cache, and all the requests entering the cache enter the pipeline and are processed according to the processing procedure of the pipeline.

[0063] In addition, in order to improve the cache reading efficiency, the cache can also be divided into a plurality of BANKs (sub-caches), and each BANK is configured with a pipeline, so that each BANK in the cache can process the requests in parallel, thereby improving the cache reading efficiency. Each BANK in the cache can process the read and write requests independently, and the tag memory (Tag Ram) and the data memory (Data Ram) in the BANK can share the same memory bank (when the BANK capacity is small) or occupy different memory banks (when the BANK capacity is large). Each BANK in the cache shares the same response channel, that is, although the cache is divided into a plurality of BANKs and each BANK has its own pipeline, the pipelines of the BANKs ultimately return data to the upper level through the same response channel of the cache.

[0064] Due to the existence of interference, the data in the memory bank of the cache can change unpredictably. In a single bit error, a data bit can change from 0 to 1 or from 1 to 0, and in a burst error, multiple data bits can change. This can cause errors in the data in the memory bank of the cache. During the processing of the read and write requests by the cache pipeline, the error data read from the cache should be detected and corrected in time to ensure that the correct data is returned.

[0065] To meet the above requirements, the embodiment of the present application provides a cache error correction method, which can realize efficient cache data error detection and correction processing.

[0066] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0067] The embodiment of the present application first provides a cache error correction method, which is applied to a processor cache and can be executed by a cache controller of the processor cache or an error correction device in the processor cache.

[0068] As introduced in the above embodiments, the tag memory and the data memory in the cache can occupy the same memory bank or different memory banks. When the tag memory and the data memory occupy the same memory bank or different memory banks, the data error detection and correction processing flow of the memory bank is different. The most direct difference is that when the tag memory and the data memory occupy the same memory bank, only the data read from the same memory bank needs to be subjected to data error detection and correction, while when the tag memory and the data memory occupy different memory banks, the data read from the tag memory and the data memory needs to be subjected to error detection and correction respectively.

[0069] First, referring to Figure 2 When the tag memory and the data memory in the cache occupy the same memory bank, the pipeline processing steps of reading data from the cache can include reading the memory bank, error detection, judging whether a hit occurs, and returning data. Since the tag memory and the data memory occupy the same memory bank, the operation of reading tag information and reading data can be realized by reading one memory bank. After reading data from the memory bank, the read data is subjected to error detection and judgment whether the required read data is hit from the memory bank. If the read data is correct and the required read data is hit, the data is returned. In the processing process shown in the above pipeline, if error data is found during error detection, data correction processing needs to be performed, that is, the cache correction method provided in the embodiments of the present application can be performed for data correction processing.

[0070] Referring to Figure 3 When the tag memory and the data memory in the cache occupy different memory banks respectively, the pipeline processing steps of the cache include reading the tag memory, error detection, judging whether a hit occurs, reading the data memory, error detection, and returning data. In the above pipeline process, the data read from the tag memory and the data read from the data memory need to be subjected to error detection respectively, which also causes that in the pipeline processing process, error data read from the tag memory can be detected, and error data read from the data memory can also be detected.

[0071] In the above case, the processor cache detects error data in the running process, which can be from the tag memory bank or from the data memory bank, so error detection and correction processing can be performed on the data read from the tag memory bank and on the data read from the data memory bank, respectively. That is, the cache correction method provided in the embodiments of the present application can be applied in the process of error detection and correction processing of the data read from the tag memory bank, or in the process of error detection and correction processing of the data read from the data memory bank. The specific processing process of the cache correction method provided in the embodiments of the present application is consistent in the above two stages, and the execution of the above cache correction method can still be performed by the error correction device in the cache. Among them, the error correction device can be configured for the tag memory bank and the data memory bank respectively, and is used for data error detection and correction of the data in the tag memory bank and the data in the data memory bank, or the tag memory bank and the data memory bank can share the same error correction device, which is used for error detection and correction of the data in the tag memory bank and the data memory bank.

[0072] It can be understood that whether the tag memory bank and the data memory bank in the cache occupy the same memory bank or different memory banks, data error detection and correction processing is performed after reading data from the memory bank, that is, the cache correction method proposed in the embodiments of the present application is performed after reading data from the memory bank.

[0073] Therefore, the embodiments of the present application focus on introducing the specific processing process of the above cache correction method, which is applicable to error correction of the data read from the tag memory bank and also applicable to error correction of the data read from the data memory bank. When the cache correction method proposed in the embodiments of the present application needs special processing when performing error correction of the data read from the tag memory bank or when performing error correction of the data read from the data memory bank, it will be described separately in the embodiment introduction.

[0074] Referring to Figure 4 The cache correction method provided in the embodiments of the present application includes:

[0075] S101, when the cache detects error data in the process of processing read and write requests, pause new read and write requests from entering the cache.

[0076] Specifically, when the read and write requests enter the pipeline of the cache, the cache processes according to the processing flow of the pipeline, and after reading data from the memory bank, the running error detection step is used to detect whether the read data is error data. For example, in the error detection step, the error correction device performs data error detection by means of Hamming code error detection, parity check, consistency detection, redundancy check, etc., to judge whether the read data is error data.

[0077] For example, when the tag memory and the data memory in the cache share the same memory, the cache pipeline processes according to the processing flow shown in FIG. 2, and after reading data from the memory, error detection processing of the data is performed. Figure 2

[0078] Or, when the tag memory and the data memory in the cache occupy different memories respectively, the cache pipeline processes according to the processing flow shown in FIG. 3, and after reading a tag from the tag memory or reading data from the data memory, error detection processing is performed. Figure 3

[0079] If the error correction device confirms that the data read from the memory is error data in the process of processing the read / write request, a global error correction mode prompt signal is generated for prompting the entire cache to switch to the error correction mode. At this time, the error correction device blocks the read / write request from the outside or inside of the entire cache into the pipeline, that is, it suspends to allow new read / write request into the cache pipeline. However, the request that has already entered the cache pipeline is continued to be processed.

[0080] For example, when the tag memory and the data memory in the cache share the same memory, if it is detected that the data read from the memory is error data, the read / write request from the outside or inside of the cache into the cache pipeline is blocked. When the tag memory and the data memory in the cache occupy different memories respectively, as long as it is detected that the data read from any memory is error data, the read / write request from the outside or inside of the cache into the cache pipeline is blocked.

[0081] In some embodiments, when the error correction device confirms that error data or error tag is read by the cache in the process of processing the read / write request, a global error correction mode prompt signal is generated, which is used to indicate that the entire cache suspends to receive new read / write request, so as to achieve the purpose of blocking new read / write request into the cache pipeline.

[0082] In other embodiments, when the cache detects error data in the process of processing the read / write request, the read / write request that finds the error data is also stored to the buffer, that is, the read / write request is suspended and waits to be reprocessed by re-entering the pipeline subsequently.

[0083] S102, an error correction step is added in the pipeline of the cache.

[0084] Specifically, after the error correction device confirms that the data read from the memory by the cache in the process of processing the read / write request is error data, and suspends new read / write request into the cache, a cache internal error correction prompt signal is generated, which is used to prompt the subsequent read / write request that has entered the cache pipeline to perform data error detection and error correction operation. ​​

[0085] At the same time, an additional step is added to the cache pipeline to perform an error correction step, which is used to correct detected erroneous data.

[0086] In some embodiments, such as Figure 5 As shown, when the tag storage and data storage occupy the same storage, the above-mentioned error correction step is added after the error detection step in the cache pipeline and is adjacent to the error detection step. That is, the error correction step is the next step after the error detection step, so that the error correction step can be executed immediately after the error detection step in the cache pipeline processing.

[0087] In other embodiments, when the mark storage and data storage occupy different storage units, the above-mentioned error correction step can also be added after the error detection step in the cache pipeline and adjacent to the error detection step, that is, the error correction step is the next step after the error detection step.

[0088] like Figure 6 As shown, when an error flag is detected when read from the flag storage, an error correction step is added after error detection of the data read from the flag storage. Alternatively, as... Figure 7 As shown, when erroneous data is detected when the data read from the data storage is detected, an error correction step is added after the data read from the data storage is checked for errors.

[0089] By adding an error correction step to the cache pipeline, the pipeline can perform error detection and error correction operations on erroneous data during the processing of read and write requests. In other words, for subsequent read and write requests that have already entered the cache pipeline, the error correction step can correct any erroneous data read, ensuring that these requests can continue to be processed and ultimately retrieve the correct data, thus completing these requests smoothly and reducing latency.

[0090] In some embodiments, the above-described error correction steps correct erroneous data using any data error correction method, such as Hamming code error correction.

[0091] In some embodiments, when the error data is detected in the process of handling the read / write request in step S101, the read / write request that finds the error data is also stored in the buffer. At this time, after step S102 is performed, the effective error correction of the error data can be realized due to the addition of the error correction step in the cache pipeline, so that the correct data is finally read, and thus the read / write request stored in the buffer can be read out by the error correction device at this time, so as to re-enter the cache pipeline, that is, to rehandle the read / write request. At this time, the read / write request can be processed through data reading, data error detection, and data error correction, and finally the correct data is read.

[0092] S103, generating an error correction request.

[0093] Specifically, the addition of the error correction step in the cache pipeline through the operation of step S102 can enable the subsequent read / write request that has entered the cache pipeline to obtain correct data, but cannot enable the data stored in the storage to be updated to correct data. In order to enable the data stored in the storage to be correct, the error correction device generates an in-cache error correction request in addition to the addition of the error correction step in the cache pipeline, which is used to request that the error data detected from the cache storage be modified to correct data.

[0094] S104, performing the error correction request to read out the error data from the cache and modify the error data to correct data, and then writing the correct data into the cache.

[0095] Specifically, the error correction device performs the error correction request, detects the error data detected in step S101 from the cache storage, and modifies the error data to correct data, and then writes the correct data back to the cache storage, so as to update the data in the storage to correct data.

[0096] The above operation can update the error data in the cache storage to correct data, and fundamentally solve the problem of data error in the storage.

[0097] In some embodiments, when the error data is detected in the process of handling the read / write request in step S101, the read / write request that finds the error data is also stored in the buffer. At this time, after step S104 is performed, the cache enters the error correction mode, and the read / write request stored in the buffer is read out by the error correction device at this time, so as to re-enter the cache pipeline, that is, to rehandle the read / write request. At this time, the read / write request can directly read the correct data from the cache.

[0098] As can be seen from the above description, the cache error correction method provided by the embodiment of the present application can find error data in the cache, and by adding an error correction step in the cache pipeline, the subsequent read-write request that has entered the cache pipeline can obtain correct data, so that the read-write request is successfully processed. The method can not only realize effective cache data error detection and correction processing, but also ensure that the processor obtains correct data from the cache in time without affecting the cache operation as much as possible, thereby avoiding increasing data reading delay due to data errors. On the other hand, the method also modifies the error data stored in the cache memory bank to correct data, which fundamentally solves the data error problem.

[0099] In another embodiment, when the error correction device performs the error correction request, modifies the data read from the cache to correct data, and writes the correct data into the cache, the cache formally enters the error correction mode.

[0100] At this time, the error correction device releases the cache pipeline entrance, that is, a new read-write request enters the cache, and a timer is started to start timing.

[0101] The timer is used to count the working time of the cache in the error correction mode.

[0102] If the cache does not detect error data within a set time, that is, the cache works in the error correction mode for a set time, and no error data is detected in the process of processing the read-write request, the error correction device generates a normal mode switching request. At this time, the cache pipeline is blocked again, and the new read-write request does not enter the cache pipeline. When the read-write request that has entered the cache pipeline is processed, the error correction step in the cache pipeline is removed. At this time, the cache pipeline returns to the form shown in FIG. 1. Figure 2 Or Figure 3 .

[0103] The above scheme updates the error data in the memory bank of the cache to correct data, and makes the cache work in the error correction mode for a period of time. During the period of time, if the cache does not occur data error again, the error correction step in the pipeline is removed. In this way, when the cache processes the read-write request and finds error data again, the data error correction can be performed in time, and the data reading efficiency is further guaranteed.

[0104] Another embodiment of the present application provides another cache error correction method, which is applied to a processor cache. The cache is internally divided into different BANKs. These BANKs can receive and process requests independently as different sub-caches, thereby improving the parallel request processing capability of the cache.

[0105] In the embodiment of the present application, the data error detection and correction process in different sub-caches in the cache is introduced by taking the cache including a first sub-cache and a second sub-cache as an example.

[0106] In addition, as introduced in the above embodiments, the tag storage and the data storage in the cache can occupy the same storage or different storages. The first sub-cache and the second sub-cache have their own dedicated pipelines, which means that the first sub-cache and the second sub-cache are independent of each other. Therefore, the tag storage and the data storage in the first sub-cache and the second sub-cache can occupy the same storage or different storages. That is, the pipelines of the first sub-cache and the second sub-cache can be in the form shown in Figure 2 or in the form shown in Figure 3 .

[0107] In either the first sub-cache or the second sub-cache, the cache error correction method provided in the embodiments of the present application can be performed, and the method can be performed by the error correction device in the cache.

[0108] Referring to Figure 8 , the method comprises the following steps.

[0109] S201. When the first sub-cache detects error data in the process of processing read / write requests, new read / write requests are paused from entering the cache.

[0110] Specifically, after the read / write requests enter the pipeline of the first sub-cache, the data read from the storage is detected for error by running the error detection step. For example, in the error detection step, the error correction device performs data error detection by means of Hamming code error detection, parity check, consistency detection, redundancy check, etc., to determine whether the read data is error data.

[0111] For example, when the tag storage and the data storage in the first sub-cache share the same storage, the pipeline of the first sub-cache processes according to the processing flow shown in Figure 2 , and after reading data from the storage, error detection processing of the data is performed.

[0112] Or, when the tag storage and the data storage in the first sub-cache occupy different storages, the pipeline of the first sub-cache processes according to the processing flow shown in Figure 3 , and after reading the tag from the tag storage or reading data from the data storage, error detection processing is performed.

[0113] If the error correction device confirms that the data read from the storage is error data by performing the error detection step in the process of the first sub-cache processing read / write requests, the read / write requests from the outside or inside of the entire cache are blocked from entering the pipeline, that is, new read / write requests are paused from entering the pipeline of the cache. In this way, the pipelines of the first sub-cache and the second sub-cache are no longer entered by new read / write requests. However, the requests that have entered the pipelines of the first sub-cache and the second sub-cache are still processed.

[0114] For example, when the tag store and data store in the first sub-cache share the same storage, if erroneous data is detected being read from that storage, all read / write requests, whether external or internal to the cache, are blocked from entering the cache pipeline. Conversely, when the tag store and data store in the first sub-cache occupy different storage, any read / write request, whether external or internal to the cache, is blocked from entering the cache pipeline if erroneous data is detected being read from either storage.

[0115] In some embodiments, when the error correction device confirms that the first sub-cache has read erroneous data or error flags during the processing of read / write requests, it generates a global error correction mode prompt signal. This global error correction mode prompt signal is used to instruct all sub-caches in the entire cache to suspend receiving new read / write requests, thereby blocking new read / write requests from entering the cache pipeline.

[0116] In other embodiments, when the cache detects erroneous data during the processing of a read / write request, it also stores the read / write request containing the erroneous data in a buffer, that is, suspends the read / write request and waits for it to re-enter the pipeline for reprocessing.

[0117] S202. Add an error correction step to the pipeline of the first sub-buffer.

[0118] Specifically, when the error correction device confirms that the data read from the storage is erroneous when the first sub-cache processes a read / write request, and suspends new read / write requests from entering the cache, it generates an error correction prompt signal in the first sub-cache. This signal is used to prompt subsequent read / write requests in the pipeline that have entered the first sub-cache to perform data error detection and correction operations.

[0119] At the same time, an additional step is added to the pipeline of the first sub-buffer to perform an error correction step, which is used to correct the detected erroneous data.

[0120] In some embodiments, such as Figure 5 As shown, when the mark storage and data storage occupy the same storage, the above-mentioned error correction step is added after the error detection step in the first sub-cached pipeline and adjacent to the error detection step. That is, the error correction step is the next step after the error detection step, so that the error correction step can be executed immediately after the error detection step in the processing of the first sub-cached pipeline.

[0121] In other embodiments, when the mark storage and data storage occupy different storage units, the above-mentioned error correction step can also be added after the error detection step of the first sub-cached pipeline and adjacent to the error detection step, that is, the error correction step is the next step after the error detection step.

[0122] As shown in FIG. 2, when it is detected that the read data from the tag memory bank is an error tag, an error correction step is added after the error detection of the read data from the tag memory bank. Figure 6 As shown in FIG. 3, when it is detected that the read data from the data memory bank is error data, an error correction step is added after the error detection of the read data from the data memory bank. Figure 7 As shown in FIG. 3, when it is detected that the read data from the data memory bank is error data, an error correction step is added after the error detection of the read data from the data memory bank.

[0123] By adding the error correction step in the pipeline of the first sub-cache, the pipeline of the first sub-cache can perform error detection and error correction of the error data when processing the read / write requests. That is, for the read / write requests that have entered the pipeline of the first sub-cache, the error data can be corrected by performing the error correction step in the pipeline, so that the read / write requests can continue to be processed and finally obtain correct data, thereby successfully completing the requests and reducing the delay.

[0124] In some embodiments, the error correction step for error data can be any data error correction method, such as a Hamming code error correction method.

[0125] In some embodiments, when the first sub-cache detects error data in the process of processing the read / write requests, the read / write request that finds the error data is also stored in the buffer in step S201. At this time, after step S202 is performed, since the error correction step is added in the pipeline of the first sub-cache, effective error correction of the error data can be achieved, so that the correct data is finally read. Therefore, the read / write request stored in the buffer can be read out at this time, so that it re-enters the pipeline of the first sub-cache, that is, the read / write request is re-processed. At this time, the read / write request can be processed through data reading, data error detection and data error correction, and finally correct data is read.

[0126] S203, generating an error correction request in the first sub-cache.

[0127] Specifically, by adding the error correction step in the pipeline of the first sub-cache through the operation of step S202, subsequent read / write requests that have entered the pipeline of the first sub-cache can obtain correct data, but the data stored in the memory bank cannot be updated to correct data. In order to make the data stored in the memory bank correct, the error correction device generates an error correction request in the first sub-cache, which is used to request that the error data detected from the memory bank of the first sub-cache be modified to correct data.

[0128] S204, execute the error correction request to read the error data from the cache and modify the error data to correct data, and then write the correct data into the cache.

[0129] Specifically, the error correction device executes the error correction request to detect the error data detected in step S201 from the memory bank of the first sub-cache, and modify the error data to correct data, and then write the correct data back to the memory bank of the cache, so that the data in the memory bank is updated to correct data.

[0130] The above operation can update the error data in the memory bank of the first sub-cache to correct data, and fundamentally solve the problem of error data in the memory bank.

[0131] S205, add the error correction step in the pipeline of the second sub-cache.

[0132] Specifically, since the new read-write request has been suspended into the cache in step S201, for the first sub-cache and the second sub-cache, after step S201 is executed, only the read-write request that has entered the pipeline exists in the pipeline of the first sub-cache and the second sub-cache, and no new read-write request will enter temporarily. When these read-write requests that have entered the pipeline are processed, the pipeline of the first sub-cache and the second sub-cache is emptied, that is, there is no read-write request to be processed.

[0133] When the pipeline of the first sub-cache and the second sub-cache is emptied, the error correction device adds the error correction step in the pipeline of the first sub-cache and the pipeline of the second sub-cache, so that the first sub-cache and the second sub-cache enter the error correction mode at the same time.

[0134] For example, the error correction step is added in the pipeline of the second sub-cache in the same way as the error correction step is added in the pipeline of the first sub-cache, that is, after the error correction step is added in the pipeline of the first sub-cache and the pipeline of the second sub-cache, the pipelines of the first sub-cache and the second sub-cache are consistent.

[0135] The above operation enables the first sub-cache and the second sub-cache to enter the error correction mode at the same time, so that the pipeline processes of the first sub-cache and the second sub-cache are consistent. Since the first sub-cache and the second sub-cache share the same response channel, the above operation can reduce the shared resource conflict caused by the inconsistent pipeline processes of the first sub-cache and the second sub-cache. For example, the pipeline processes of the first sub-cache and the second sub-cache are consistent, but the pipeline process of one of them is increased by an error correction step, so that the pipeline processes of the first sub-cache and the second sub-cache are inconsistent, that is, the pipeline processes of the first sub-cache and the second sub-cache are different, and only one bus can return data at the same time, which causes the shared resource conflict of the first sub-cache and the second sub-cache. The embodiment of the present application enables the first sub-cache and the second sub-cache to enter the error correction mode at the same time, and the error correction step is added to the pipeline process of each of the first sub-cache and the second sub-cache, so that the pipeline processes of the first sub-cache and the second sub-cache are consistent, and the above situation is reduced.

[0136] In some other embodiments, when the first sub-cache detects error data in the process of processing the read-write request, the read-write request in which the error data is found is also stored in the buffer in step S201. When step S204 is performed, the first sub-cache enters the error correction mode, and the error correction device reads out the read-write request stored in the buffer, so that the read-write request reenters the first sub-cache pipeline, that is, the read-write request is reprocessed. At this time, the read-write request can directly read the correct data from the first sub-cache.

[0137] As can be seen from the above description, the cache error correction method provided by the embodiment of the present application can enable the subsequent read-write request that has entered the cache pipeline to obtain correct data when error data is found in a sub-cache in the cache, so that the read-write request is successfully processed. The method not only can realize effective cache data error detection and correction processing, but also can ensure that the processor obtains correct data from the cache in time without affecting the operation of the cache as much as possible, thereby avoiding the increase of data reading delay caused by data error. On the other hand, the method also modifies the error data stored in the cache storage to correct data, which fundamentally solves the problem of data error.

[0138] In addition, the cache error correction method provided by the embodiment of the present application adds the error correction step to the pipeline process of each sub-cache and synchronously removes the error correction step when error data is found in one of the sub-caches, so that the different sub-caches in the cache are switched between the error correction mode and the normal mode synchronously, the pipeline processes of the different sub-caches are consistent, the complex resource conflict scenario is effectively avoided, and the probability of the shared resource conflict between the different sub-caches is reduced.

[0139] In another embodiment, when the error correction steps are added in the pipelines of the first sub-cache and the second sub-cache respectively, so that the first sub-cache and the second sub-cache enter the error correction mode at the same time, a new read-write request is initiated to enter the cache, and a timer is started to begin timing.

[0140] In the case that no error data is detected in the first sub-cache and the second sub-cache within a set time period, the error correction steps in the pipelines of the first sub-cache and the second sub-cache are removed synchronously.

[0141] Specifically, after the error correction steps are added in the pipelines of the first sub-cache and the second sub-cache respectively, the first sub-cache and the second sub-cache enter the error correction mode at the same time, and the error correction device initiates a new read-write request to enter the cache, that is, the new read-write request is allowed to enter the first sub-cache and the second sub-cache.

[0142] At the same time, when the new read-write request is initiated to enter the cache, the timer is started to begin timing. If no error data is detected in the first sub-cache and the second sub-cache during the operation within a set time period, it is indicated that there is no error data in the cache, and at this time, the error correction steps in the pipelines of the first sub-cache and the second sub-cache can be removed synchronously to switch the first sub-cache and the second sub-cache back to the normal working mode synchronously.

[0143] When the error correction steps in the pipelines of the first sub-cache and the second sub-cache are removed synchronously, the external or internal read-write request entering the pipeline of the first sub-cache or the second sub-cache is blocked, that is, the new read-write request entering the cache pipeline is paused, and after the read-write request in the pipeline of the first sub-cache and the second sub-cache is processed, that is, the pipeline of the first sub-cache and the second sub-cache is emptied, the error correction steps in the pipeline of the first sub-cache and the second sub-cache are removed.

[0144] In another embodiment of the cache error correction method, for the case that the mark storage body and the data storage body in the cache occupy different storage bodies respectively, when error data is detected from the data storage body, a different error correction scheme can be used.

[0145] Specifically, in the cache error correction method provided in this embodiment, when error data is detected from the mark storage body during the process of processing the read-write request of the cache, the cache error correction method introduced in the above embodiment can be used for processing, and the specific processing process can be referred to the above embodiment.

[0146] When error data is detected from the data storage body during the process of processing the read-write request of the cache, the following operations are performed:

[0147] returning data read from the data storage to a request source sending the read-write request, and sending error data prompt information, and modifying the error data in the data storage to correct data.

[0148] The error data prompt information is used to instruct the request source to resend the read-write request.

[0149] Specifically, in the process of processing the read-write request by the cache pipeline, when error data is found in the cache data storage, in order to ensure the read-write performance, in the returning data stage of the cache pipeline, the data read from the data storage is directly returned to the request source, so that the request source can obtain the data in time and the cache read-write delay is reduced.

[0150] However, in the case that the data read from the data storage is error data, the error data is returned to the request source, and error data prompt information is also sent to the request source to inform the request source that the returned data is error data. After receiving the returned data carrying the error data prompt information, the request source resends the read-write request to request correct data.

[0151] The request source mentioned above refers to a processor core or an upper-level cache sending a read-write request to the cache. For example, when the processor architecture includes a single-level cache, the request source sending a read-write request to the cache is a processor or a processor core. When the processor architecture includes multiple-level caches, for the cache closest to the processor core, the request source sending a read-write request to the cache is a processor or a processor core, and for other caches, the request source sending a read-write request to the cache is the upper-level cache of the cache.

[0152] In the process of executing the returning data operation by the cache pipeline, the error correction device reads the error data in the data storage, corrects it to correct data, and then writes the correct data into the data storage.

[0153] After the above operation, when the request source receives the returned data carrying the error data prompt information, the request source resends the read-write request. When the cache pipeline receives the read-write request again, the cache pipeline processes the read-write request again according to the pipeline process. Since the error data in the data storage has been updated to correct data, correct data can be read from the data storage and returned to the request source.

[0154] When there are multiple sub-caches in the cache, the tag storage and the data storage of the sub-caches occupy different storages. When any sub-cache reads error data from the data storage in the process of processing the read-write request, the error data can be processed according to the above embodiment.

[0155] The above processing manner directly corrects the error data in the data storage when the error data is found from the data storage, realizes the correction of the error data without delaying the progress of the cache pipeline, and ensures that the request source can read the correct data from the cache.

[0156] Corresponding to the cache correction method described above, the embodiment of the application further provides a correction device, which can be applied to a processor cache and used to execute the cache correction method introduced in the above embodiment.

[0157] The correction device provided by the embodiment of the application comprises:

[0158] The first control unit is configured to pause a new read-write request from entering the cache when error data is detected in the process of processing the read-write request by the cache;

[0159] The first processing unit is configured to add a correction step in the pipeline of the cache, and the correction step is used for correcting error data.

[0160] The second processing unit is configured to generate a correction request, and the correction request is used for modifying the error data in the cache into correct data.

[0161] The second control unit is configured to execute the correction request to read out the error data from the cache, modify the error data into correct data, and then write the correct data into the cache.

[0162] In some implementations, the first control unit is further configured to store the read-write request to a buffer.

[0163] The first processing unit is further configured to take the read-write request out of the buffer and re-enter the pipeline of the cache after the correction step is added in the pipeline of the cache.

[0164] In some implementations, the second control unit is further configured to:

[0165] After the correct data is written into the cache, a new read-write request is started to enter the cache, and a timer is started to start timing.

[0166] If the cache does not detect error data within a set time length, the correction step in the pipeline of the cache is removed.

[0167] In some implementations, the cache comprises a first sub-cache and a second sub-cache.

[0168] The first processing unit adds a correction step in the pipeline of the cache, comprising adding a correction step in the pipeline of the first sub-cache.

[0169] After the second control unit writes the correct data into the cache, the first processing unit is further configured to add the error correction step in the pipeline of the second sub-cache.

[0170] In some implementations, the second control unit is further configured to start a new read-write request into the cache, and start a timer to start timing;

[0171] In the case that the first sub-cache and the second sub-cache do not detect error data within a set time period, the error correction step in the pipeline of the first sub-cache and the second sub-cache is synchronously removed.

[0172] In some implementations, the mark storage and the data storage in the cache share the same storage; or, the mark storage and the data storage in the cache occupy different storages respectively.

[0173] In the case that the mark storage and the data storage in the cache occupy different storages respectively, the cache detects error data in the process of processing the read-write request, comprising:

[0174] The cache detects error data in the mark storage in the process of processing the read-write request; or, the cache detects error data in the data storage in the process of processing the read-write request.

[0175] In some implementations, in the case that the mark storage and the data storage in the cache occupy different storages respectively, the cache detects error data in the process of processing the read-write request, comprising: the cache detects error data in the mark storage in the process of processing the read-write request.

[0176] The apparatus further comprises:

[0177] The third control unit is configured to, in the case that the cache detects error data in the data storage in the process of processing the read-write request, return the data read from the data storage to the request source sending the read-write request, and send error data prompt information, and modify the error data in the data storage to correct data.

[0178] The error data prompt information is used to instruct the request source to resend the read-write request.

[0179] The error correction device provided by the embodiment belongs to the same application concept as the cache error correction method provided by the above-mentioned embodiments of the application, can execute the cache error correction method provided by any of the above-mentioned embodiments of the application, and has the function modules and beneficial effects corresponding to the execution method. The technical details not described in detail in the embodiment can be seen from the specific processing content of the cache error correction method provided by the above-mentioned embodiments of the application, and will not be described here.

[0180] The functions implemented by the above-mentioned units can be implemented by the same or different processors, and the embodiments of the application are not limited.

[0181] It should be understood that the units in the above device can be implemented in the form of processor calling software. For example, the device includes a processor connected with a memory, the memory stores instructions, and the processor calls the instructions stored in the memory to implement any of the above methods or to implement the functions of the units of the device, wherein the processor can be a general processor, such as a CPU or a microprocessor, and the memory can be an internal memory or an external memory of the device. Alternatively, the units in the device can be implemented in the form of hardware circuit. The functions of part or all of the units can be implemented by designing the hardware circuit. The hardware circuit can be understood as one or more processors. For example, in one implementation, the hardware circuit is an ASIC, and the functions of part or all of the units are implemented by designing the logical relationship of elements in the circuit. For another example, in another implementation, the hardware circuit can be implemented by a PLD. Taking an FPGA as an example, it can include a large number of logic gate circuits, and the connection relationship between the logic gate circuits is configured by a configuration file, so as to implement the functions of part or all of the units. All units of the above device can be implemented in the form of processor calling software, or implemented in the form of hardware circuit, or partially implemented in the form of processor calling software and the remaining part implemented in the form of hardware circuit.

[0182] In the embodiments of the application, the processor is a circuit with signal processing capability. In one implementation, the processor can be a circuit with instruction reading and running capability, such as CPU, microprocessor, GPU, or DSP, etc. In another implementation, the processor can implement certain functions through the logical relationship of hardware circuit, and the logical relationship of the hardware circuit is fixed or can be reconfigured. For example, the processor is an ASIC or a PLD implemented hardware circuit, such as FPGA, etc. In the reconfigurable hardware circuit, the process of the processor loading the configuration document to implement the configuration of the hardware circuit can be understood as the process of the processor loading the instructions to implement the functions of part or all of the units. In addition, it can also be a hardware circuit designed for artificial intelligence, which can be understood as a kind of ASIC, such as NPU, TPU, DPU, etc.

[0183] It can be seen that each unit in the above apparatus can be one or more processors (or processing circuits) configured to implement the above methods, for example: CPU, GPU, NPU, TPU, DPU, microprocessor, DSP, ASIC, FPGA, or a combination of at least two of these processor forms.

[0184] In addition, each unit in the above apparatus can be integrated together or can be independently implemented. In one implementation, these units are integrated together to implement a SOC. The SOC can include at least one processor for implementing any of the above methods or functions of the units of the apparatus, and the at least one processor can be different, for example, including CPU and FPGA, CPU and artificial intelligence processor, CPU and GPU, etc.

[0185] Another embodiment of the present application also provides a cache controller applied to a processor cache, the cache controller being configured to perform the cache error correction method described in any of the above embodiments.

[0186] Another embodiment of the present application also provides a computer device, the processor of which includes the error correction apparatus described above, or includes the cache controller described above.

[0187] For example, the computer device can be a personal computer, an industrial computer, a server, a smart terminal, a handheld terminal, a wearable device, etc.

[0188] In addition to the above methods and devices, the embodiments of the present application can also be a computer program product, which includes computer program instructions that, when executed by a processor, cause the processor to perform the steps of the cache error correction method described in any of the above embodiments of the present application.

[0189] The computer program product can be written in any combination of one or more programming languages to perform the operations of the embodiments of the present application, including object-oriented programming languages such as Java, C++, etc., and conventional procedural programming languages such as "C" language or similar programming languages. Program code can be executed entirely on a user computing device, partially on a user device, as a separate software package, partially on a user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0190] In addition, the embodiments of the present application can also be a storage medium having a computer program stored thereon, the computer program being executed by a processor to perform the steps of the cache error correction method described in any of the above embodiments of the present application.

[0191] For simple description, each of the foregoing method embodiments is described as a combination of a series of actions, but those skilled in the art shall understand that the present application is not limited to the action sequence described, because according to the present application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art shall understand that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the present application.

[0192] It should be noted that each of the embodiments in the specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be understood by referring to each other. For device embodiments, because they are basically similar to method embodiments, they are described more simply, and the relevant parts refer to the part of the method embodiment.

[0193] The steps in the method of each embodiment of the present application can be adjusted, combined and reduced in sequence according to actual needs, and the technical features recorded in each embodiment can be replaced or combined.

[0194] The modules and sub-modules in the device and terminal of each embodiment of the present application can be combined, divided and reduced according to actual needs.

[0195] In several embodiments provided by the present application, it should be understood that the disclosed terminal, device and method can be implemented by other ways. For example, the terminal embodiments described above are only schematic, for example, the division of modules or sub-modules is only a logical function division, and actual implementation can have another division manner, for example, a plurality of sub-modules or modules can be combined or integrated into another module, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the shown or discussed mutual ones can be indirect coupling or communication connection through some interfaces, devices or modules, and can be electrical, mechanical or other forms.

[0196] The modules or sub-modules described as separate components can or can not be physically separated, and the components of the modules or sub-modules can or can not be physical modules or sub-modules, that is, they can be located in one place, or can be distributed to multiple network modules or sub-modules. According to actual needs, some or all of the modules or sub-modules can be selected to achieve the purpose of the present embodiment.

[0197] Furthermore, the functional modules or sub-modules in the various embodiments of this application can be integrated into one processing module, or each module or sub-module can exist physically separately, or two or more modules or sub-modules can be integrated into one module. The integrated modules or sub-modules described above can be implemented in hardware or in the form of software functional modules or sub-modules.

[0198] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0199] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software unit executed by a processor, or a combination of both. The software unit can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0200] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0201] The above description of disclosed embodiments enables one of ordinary skill in the art to make and use the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A cache error correction method, characterized in that, Applied to processor cache, the method includes: When the cache detects erroneous data during the processing of a read or write request, new read or write requests are paused from entering the cache. An error correction step is added to the cache pipeline, the error correction step being used to correct erroneous data; Generate an error correction request, which is used to modify the erroneous data in the cache into correct data; The error correction request is executed to read the erroneous data from the cache, modify the erroneous data to correct data, and then write the correct data into the cache.

2. The method according to claim 1, characterized in that, When the cache detects erroneous data during the processing of a read / write request, the method further includes: Store the read / write request in the buffer; as well as, After adding the error correction step to the cache pipeline, the read / write request is retrieved from the buffer and re-enters the cache pipeline.

3. The method according to claim 1, characterized in that, The method further includes: After the correct data is written to the cache, a new read / write request is initiated to enter the cache, and a timer is started. If the cache does not detect erroneous data within a set time period, the error correction step in the cache pipeline is removed.

4. The method according to claim 1, characterized in that, The cache includes a first sub-cache and a second sub-cache; The step of adding an error correction step to the pipeline of the cache includes: adding an error correction step to the pipeline of the first sub-cache; After writing the correct data to the cache, the method further includes: The error correction step is added to the pipeline of the second sub-buffer.

5. The method according to claim 4, characterized in that, The method further includes: A new read / write request is initiated into the cache, and a timer is started. If no erroneous data is detected in either the first sub-cache or the second sub-cache within a set time period, the error correction steps in the pipelines of the first and second sub-caches are removed synchronously.

6. The method according to any one of claims 1 to 5, characterized in that, The tag storage and data storage in the cache share the same storage; or, the tag storage and data storage in the cache occupy different storage. When the tag storage and data storage in the cache occupy different storage units, the cache detects erroneous data during the processing of read and write requests, including: During the process of processing read and write requests, the cache detected erroneous data in the tag storage. Alternatively, the cache may detect erroneous data in the data storage during the processing of read / write requests.

7. The method according to any one of claims 1 to 5, characterized in that, When the tag storage and data storage in the cache occupy different storage units, the cache detects erroneous data during the process of processing read and write requests, including: the cache detects erroneous data in the tag storage unit during the process of processing read and write requests; The method further includes: During the processing of read and write requests, if erroneous data is detected in the data storage, the cache returns the data read from the data storage to the request source that sent the read and write request, sends an error data prompt message, and modifies the erroneous data in the data storage to correct data. The error data message is used to instruct the request source to resend the read / write request.

8. An error correction device, characterized in that, The error correction device, applied to the processor cache, includes: The first control unit is configured to pause new read / write requests from entering the cache when the cache detects erroneous data during the processing of read / write requests. The first processing unit is configured to add an error correction step to the pipeline of the cache, the error correction step being used to correct erroneous data; The second processing unit is used to generate an error correction request, which is used to modify the erroneous data in the cache into correct data. The second control unit is configured to execute the error correction request, read the erroneous data from the cache, modify the erroneous data to correct data, and then write the correct data into the cache.

9. A cache controller, characterized in that, Applied to a processor cache, the cache controller is configured to perform the cache error correction method as described in any one of claims 1 to 7.

10. A computer device, characterized in that, It includes the error correction device as described in claim 9, or the cache controller as described in claim 10.

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