A method, apparatus, device, and medium for verifying the integrity of chip signals.

Abstract

This application discloses a method, apparatus, device, and medium for verifying the integrity of chip signals, relating to the field of testing technology. The method includes: establishing a transmission line model in preset electromagnetic simulation software and obtaining material parameters related to the inter-symbol interference test board that affect signal integrity; inputting the material parameters into the transmission line model and performing simulation calculations on a target transmission line of a preset fixed length to obtain the scattering parameters of the target transmission line; calculating scattering parameters corresponding to different transmission line lengths based on port de-embedding technology and the scattering parameters of the target transmission line, and establishing a mapping relationship between insertion loss and transmission line length based on each scattering parameter; when a test requirement is obtained, determining the target insertion loss in the test requirement, and obtaining the target scattering parameters corresponding to the target insertion loss based on the mapping relationship, so as to perform integrity verification of the chip signal under test based on the target scattering parameters. This provides a simpler and more accurate signal integrity verification scheme.

Description

Technical Field

[0001] This invention relates to the field of testing technology, and in particular to a method, apparatus, device, and medium for verifying the integrity of chip signals. Background Technology

[0002] PCI-Express (PCIe) is a point-to-point high-speed serial computer expansion bus standard, which has become the mainstream interconnection technology between processors and peripheral devices in servers, computers, and other equipment. After several iterations, its speed has been greatly improved. However, with the continuous increase in speed, signal integrity issues have become increasingly prominent. Although the "0" and "1" code streams transmit digital information, the voltage or current waveforms carrying that information are analog signals, which are susceptible to distortion due to noise, losses, unstable power supply, and other factors. If the distortion is severe enough, the receiver may misinterpret the "0" and "1" codes output by the transmitter; this is the so-called signal integrity problem.

[0003] While chip and related equipment manufacturers currently adhere to the PCIe protocol specifications in their research and development, varying levels of development among manufacturers mean that some chips cannot provide key indicators such as system design parameters and maximum drive capability. This makes it difficult to effectively assess the rationality of the topology design, link risks, and whether signal integrity requirements are met during system-level design. Figure 1 This diagram illustrates the system topology design. To address the aforementioned issues, a common industry approach is to conduct physical verification based on ISI (Inter-Symbol Interference) test boards. This method involves sequentially inserting physical ISI boards with different loss values ​​into the test link to determine the maximum channel loss limit the chip can withstand. However, this method suffers from problems such as insufficient equipment resources, frequent plugging and unplugging leading to poor contact or damage causing test errors, and complex connection topologies prone to errors.

[0004] In summary, how to provide a simpler and more accurate signal integrity verification solution while reducing costs is a problem that needs to be solved. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide a method, apparatus, device, and medium for verifying the integrity of chip signals, which can provide a simpler and more accurate signal integrity verification scheme and reduce costs. The specific scheme is as follows:

[0006] In a first aspect, this application discloses a method for verifying the integrity of chip signals, comprising:

[0007] A transmission line model is established in the preset electromagnetic simulation software, and material parameters related to the inter-symbol interference test board that affect signal integrity are obtained.

[0008] The material parameters are input into the transmission line model, and the target transmission line of a preset fixed length is simulated to obtain the scattering parameters of the target transmission line.

[0009] Based on port de-embedding technology and the scattering parameters of the target transmission line, the scattering parameters corresponding to different transmission line lengths are calculated, and the mapping relationship between insertion loss and transmission line length is established based on each scattering parameter.

[0010] When the test requirements are obtained, the target insertion loss in the test requirements is determined, and the target scattering parameters corresponding to the target insertion loss are obtained based on the mapping relationship, so as to perform integrity verification of the signal of the chip under test based on the target scattering parameters.

[0011] Optionally, based on port de-embedding techniques and the scattering parameters of the target transmission line, the scattering parameters corresponding to different transmission line lengths are calculated, including:

[0012] The scattering parameters of the target transmission line are processed using port de-embedding technology to obtain the processed scattering parameters;

[0013] Based on the target transmission line and the processed scattering parameters, the scattering parameters corresponding to different transmission line lengths are calculated according to the proportional relationship between different transmission line lengths and a preset fixed length.

[0014] Optionally, the scattering parameters of the target transmission line are processed using port de-embedding techniques to obtain processed scattering parameters, including:

[0015] Simulation calculations were performed on an empty port without a transmission line to obtain the scattering parameters of the empty port;

[0016] Remove the scattering parameters of the empty port from the scattering parameters of the target transmission line to obtain the processed scattering parameters.

[0017] Optionally, the material parameters are parameters related to the stack-up structure and board material model of the inter-symbol interference test board. The material parameters include dielectric thickness, dielectric constant, bottom width of impedance line, top width of impedance line, differential line spacing, finished copper thickness, substrate solder mask thickness, solder mask thickness on copper foil or traces, and solder mask dielectric constant.

[0018] Optionally, a mapping relationship between insertion loss and transmission line length can be established based on various scattering parameters, including:

[0019] Obtain the fundamental frequency of the chip signal and set the insertion loss sequence; wherein, the interval between any two adjacent insertion losses in the insertion loss sequence is the same;

[0020] Analyze the scattering parameters to obtain the insertion loss at the fundamental frequency for different transmission line lengths;

[0021] The insertion loss of different transmission line lengths at the fundamental frequency is matched with the insertion loss of the insertion loss sequence to establish the mapping relationship between each insertion loss in the insertion loss sequence and the transmission line length and scattering parameters, and the mapping relationship is stored in a preset database.

[0022] Optionally, integrity verification of the chip signal under test is performed based on the target scattering parameters, including:

[0023] The target scattering parameters are imported into the oscilloscope so that the oscilloscope can monitor the signal quality of the chip under test under the target insertion loss in real time based on the target scattering parameters, and perform integrity verification of the chip under test signal based on the signal quality.

[0024] Optional metrics for monitoring signal quality include eye diagrams and bit error rate curves;

[0025] Accordingly, integrity verification of the signal of the chip under test is performed based on signal quality, including:

[0026] If the height and width of the eye diagram both meet the corresponding preset standard values, and the bit error rate is determined to be lower than the preset threshold based on the bit error rate curve, then the integrity verification of the signal of the chip under test is deemed to be passed.

[0027] Secondly, this application discloses a chip signal integrity verification device, comprising:

[0028] The parameter acquisition module is used to build a transmission line model in the preset electromagnetic simulation software and acquire material parameters related to the inter-symbol interference test board that affect signal integrity.

[0029] The simulation calculation module is used to input material parameters into the transmission line model and perform simulation calculations on a target transmission line of a preset fixed length to obtain the scattering parameters of the target transmission line.

[0030] The data processing module is used to calculate the scattering parameters corresponding to different transmission line lengths based on port de-embedding technology and the scattering parameters of the target transmission line, and to establish a mapping relationship between insertion loss and transmission line length based on each scattering parameter.

[0031] The verification module is used to determine the target insertion loss in the test requirements when the test requirements are obtained, and to obtain the target scattering parameters corresponding to the target insertion loss based on the mapping relationship, so as to perform integrity verification of the signal of the chip under test based on the target scattering parameters.

[0032] Thirdly, this application discloses an electronic device, including:

[0033] Memory, used to store computer programs;

[0034] A processor for executing a computer program to implement the steps of the aforementioned disclosed chip signal integrity verification method.

[0035] Fourthly, this application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the steps of the aforementioned disclosed chip signal integrity verification method.

[0036] As can be seen, this application establishes a transmission line model in a pre-defined electromagnetic simulation software and obtains material parameters related to the inter-symbol interference test board that affect signal integrity; inputs the material parameters into the transmission line model and performs simulation calculations on a target transmission line of a pre-defined fixed length to obtain the scattering parameters of the target transmission line; calculates scattering parameters corresponding to different transmission line lengths based on port de-embedding technology and the scattering parameters of the target transmission line, and establishes a mapping relationship between insertion loss and transmission line length based on each scattering parameter; when the test requirements are obtained, the target insertion loss in the test requirements is determined, and the target scattering parameters corresponding to the target insertion loss are obtained based on the mapping relationship, so as to verify the signal integrity of the chip under test based on the target scattering parameters.

[0037] Beneficial Effects: This application establishes a transmission line model using pre-set electromagnetic simulation software and imports the material parameters of the inter-symbol interference (ISI) test board to ensure that the scattering parameters of the target transmission line obtained from the simulation can accurately reflect the signal transmission characteristics of the actual link. Simultaneously, this application eliminates port parasitic interference based on port de-embedding technology and derives scattering parameters for different transmission line lengths. Furthermore, based on these scattering parameters, a mapping relationship between insertion loss and transmission line length is established, which can accurately match the actual working scenario of the chip under test. After obtaining the test requirements, the target scattering parameters corresponding to the target insertion loss can be quickly determined, adapting to the link loss scenarios of different projects. Compared to the traditional solution of building test links based on physical ISI boards, this application does not require the purchase of multiple ISI boards. It can construct a verification system covering multiple loss scenarios simply through electromagnetic simulation and parameter derivation, effectively solving the problem of insufficient equipment resources during parallel development of multiple projects and reducing equipment procurement expenses. It also avoids problems such as wear and tear and poor contact caused by frequent insertion and removal of physical boards, eliminating the need for repeated calibration of loss values ​​and reducing the workload of engineers. Moreover, this application can quickly adapt to different test requirements without rebuilding the hardware link, further simplifying the verification process and reducing time and manpower costs in the R&D process. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0039] Figure 1 A schematic diagram of a system design topology;

[0040] Figure 2 This is a flowchart of a chip signal integrity verification method disclosed in this application;

[0041] Figure 3 This is a schematic diagram of a 3D model of a microstrip line disclosed in this application;

[0042] Figure 4 This is a flowchart of a specific chip signal integrity verification method disclosed in this application;

[0043] Figure 5 This is a schematic diagram of the structure of a chip signal integrity verification device disclosed in this application;

[0044] Figure 6 This is a structural diagram of an electronic device disclosed in this application. Detailed Implementation

[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0046] While chip and related equipment manufacturers in the market all adhere to the PCIe protocol specifications in their R&D and design, the varying levels of development among manufacturers mean that some chips cannot provide key indicators such as system design parameters and maximum drive capability. This makes it difficult to effectively evaluate the rationality of the topology design, link risks, and whether signal integrity requirements are met during system-level design. A commonly used method in the industry is physical verification based on ISI (Inter-Symbol Interference) test boards. This approach involves sequentially inserting physical ISI boards with different loss values ​​into the test link to find the maximum channel loss limit that the chip can withstand. However, this method suffers from problems such as insufficient equipment resources, frequent insertion and removal leading to poor contact or damage causing test errors, and complex connection topologies prone to errors. Therefore, this application discloses a chip signal integrity verification method, apparatus, device, and medium, providing a simpler and more accurate signal integrity verification scheme while reducing costs.

[0047] See Figure 2 As shown in the figure, this application discloses a method for verifying the integrity of chip signals, the method comprising:

[0048] Step S11: Establish a transmission line model in the preset electromagnetic simulation software and obtain the material parameters related to the inter-symbol interference test board that affect signal integrity.

[0049] In this embodiment, a transmission line model is established using preset electromagnetic simulation software, and material parameters related to the inter-symbol interference test board that affect signal integrity are imported to ensure that the scattering parameters of the target transmission line obtained in subsequent simulations can truly reflect the signal transmission characteristics of the actual link.

[0050] In a specific implementation, HFSS (High Frequency Structure Simulator) 3D electromagnetic simulation software can be used to establish a parameterized 3D model of the transmission line. The model types can primarily include differential microstrip lines, differential striplines, etc. Figure 3 This is a schematic diagram of a 3D model of a microstrip line disclosed in this application. That is, this application changes the traditional solution of physical connection through an ISI board (i.e., inter-symbol interference test board) to a method of modeling and simulation software. In this way, transmission line models with different structures can be obtained simply by changing the parameter values, so as to solve the problems of insufficient equipment resources, large test errors, and complex operation in related technologies.

[0051] In addition, when obtaining the material parameters of the ISI board, you can refer to the relevant documents on ISI boards uniformly released by the PCIe Association, and focus on extracting parameters related to signal integrity (SI), such as the ISI board's stack-up structure and board type, to provide a basis for subsequent model parameter settings. That is, the material parameters are those related to the stack-up structure and board type of the inter-symbol interference test board. The specific material parameters include dielectric thickness (H1), dielectric constant (Er1), impedance line bottom width (W1), impedance line top width (W2), differential line spacing (S1), finished copper thickness (T1), substrate solder mask thickness (C1), solder mask thickness on copper foil or traces (C2), and solder mask dielectric constant (CEr).

[0052] Step S12: Input the material parameters into the transmission line model and perform simulation calculations on the target transmission line of a preset fixed length to obtain the scattering parameters of the target transmission line.

[0053] In this embodiment, the material parameters of the obtained ISI board are input into the transmission line model, and the scattering parameters of the target transmission line are obtained by simulation calculation on a target transmission line of a preset fixed length. The preset fixed length is generally a relatively short transmission line length, for example, 200 mil. It should be noted that electromagnetic field simulations (such as HFSS) require meshing the model before complex calculations. The larger the model size and the more meshes, the more exponentially the calculation time increases, consuming a significant amount of computer memory and CPU. A simple 200 mil transmission line model can complete the simulation relatively quickly. Furthermore, scattering parameters (S-parameters) are key parameters describing the transmission characteristics of high-speed signals in a transmission line, including loss and reflection, and are data in the frequency domain. Among these, the two most important scattering parameters are insertion loss (IL) and return loss (RL).

[0054] Step S13: Calculate the scattering parameters corresponding to different transmission line lengths based on port de-embedding technology and the scattering parameters of the target transmission line, and establish a mapping relationship between insertion loss and transmission line length based on each scattering parameter.

[0055] In this embodiment, port parasitic interference needs to be eliminated based on port de-embedding technology, that is, the influence of the port itself on the signal needs to be removed. The scattering parameters of different transmission line lengths are derived based on the scattering parameters of the target transmission line. Then, the mapping relationship between insertion loss and transmission line length is established based on each scattering parameter, which can accurately match the actual working scenario of the chip under test.

[0056] Understandably, due to the physical dimensions and electromagnetic field distribution of the port itself, a small electrical length and parasitic effects are introduced into the simulation, affecting the accuracy of the scattering parameters. In other words, the scattering parameters of the target transmission line obtained through simulation actually include both the signal transmission characteristics of the transmission line itself and the parasitic characteristics of the port in the simulation model. Therefore, this application needs to utilize port de-embedding technology to eliminate the port's influence on the signal, thereby obtaining only a pure scattering parameter that reflects only the characteristics of the transmission line itself. Then, scattering parameters for different transmission line lengths can be derived from this. For example, based on the scattering parameters of a 200mil transmission line, scattering parameters for transmission lines of 1 inch, 2 inches, and 3 inches can be derived to cover various link lengths that may be used in actual testing.

[0057] Step S14: When the test requirements are obtained, the target insertion loss in the test requirements is determined, and the target scattering parameters corresponding to the target insertion loss are obtained based on the mapping relationship, so as to perform integrity verification of the signal of the chip under test based on the target scattering parameters.

[0058] In this embodiment, after obtaining the test requirements, since the mapping relationship between insertion loss and transmission line length has been established in advance, the corresponding target scattering parameters can be quickly determined based on the target insertion loss in the test requirements, adapting to the link loss scenarios of different projects. Compared with the traditional solution of building test links based on physical ISI boards, this application does not require the purchase of multiple sets of ISI boards. A verification system covering multiple loss scenarios can be built simply through electromagnetic simulation and parameter derivation, effectively solving the problem of insufficient equipment resources when developing multiple projects in parallel and reducing equipment procurement expenses. At the same time, it avoids problems such as wear and tear and poor contact caused by frequent insertion and removal of physical boards, and eliminates the need for repeated calibration of loss values, reducing the workload of engineers. Furthermore, this application can quickly adapt to different test requirements without rebuilding the hardware link, further simplifying the verification process and reducing time and manpower costs in the R&D process.

[0059] In the specific implementation manner, integrity verification of the signal of the chip under test is performed based on the target scattering parameters, including: importing the target scattering parameters into an oscilloscope so that the oscilloscope can monitor in real time the signal quality of the chip under test at the target insertion loss based on the target scattering parameters, and performing integrity verification of the signal of the chip under test based on the signal quality. That is, in the actual measurement process, the target scattering parameters are imported into the oscilloscope and converted into a filter file format recognizable by the oscilloscope, so that the oscilloscope can automatically superimpose the loss characteristics of the target scattering parameters during signal acquisition to form a complete test verification link topology, thereby monitoring in real time the signal quality of the chip under test at the target insertion loss, and further performing integrity verification of the signal of the chip under test based on the signal quality. Among them, during the conversion into the filter file, it is necessary to ensure that the key information of the scattering parameters is completely retained, including the fundamental frequency point, insertion loss, return loss, etc., to ensure that the filter file can accurately reproduce the signal transmission characteristics of the target transmission line.

[0060] In the specific implementation manner, the indicators for monitoring signal quality specifically include the eye diagram and the bit error rate curve; correspondingly, performing integrity verification of the signal of the chip under test based on the signal quality includes: if both the height and width of the eye diagram meet the corresponding preset standard values, and it is determined based on the bit error rate curve that the bit error rate is lower than the preset threshold, then it is determined that the integrity verification of the signal of the chip under test is passed. That is, during the actual chip test, a high-speed oscilloscope is used for eye diagram test or bit error rate test. In the specific implementation manner, if the eye diagram opening degree meets the PCIe protocol specification, that is, if both the height and width of the eye diagram meet the standard and the bit error rate is lower than the preset threshold, it indicates that the signal integrity of the chip under test is qualified in the target loss scenario.

[0061] As can be seen, this application establishes a transmission line model using pre-set electromagnetic simulation software and imports the material parameters of the inter-symbol interference test board to ensure that the scattering parameters of the target transmission line obtained from the simulation can truly reflect the signal transmission characteristics of the actual link. Simultaneously, this application eliminates port parasitic interference based on port de-embedding technology and derives scattering parameters for different transmission line lengths. Furthermore, based on these scattering parameters, a mapping relationship between insertion loss and transmission line length is established, which can accurately match the actual working scenario of the chip under test. After obtaining the test requirements, the target scattering parameters corresponding to the target insertion loss can be quickly determined, adapting to the link loss scenarios of different projects. Compared to the traditional solution of building test links based on physical ISI boards, this application does not require the purchase of multiple ISI boards. It can construct a verification system covering multiple loss scenarios simply through electromagnetic simulation and parameter derivation, effectively solving the problem of insufficient equipment resources during parallel development of multiple projects and reducing equipment procurement expenses. It also avoids problems such as wear and poor contact caused by frequent insertion and removal of physical boards, eliminating the need for repeated calibration of loss values ​​and reducing the workload of engineers. Moreover, this application can quickly adapt to different test requirements without rebuilding the hardware link, further simplifying the verification process and reducing time and manpower costs in the R&D process.

[0062] See Figure 4 As shown, this application discloses a specific method for verifying the integrity of chip signals. Compared to the previous embodiment, this embodiment further explains and optimizes the technical solution. Specifically, it includes:

[0063] Step S21: Establish a transmission line model in the preset electromagnetic simulation software and obtain the material parameters related to the inter-symbol interference test board that affect signal integrity.

[0064] Step S22: Input the material parameters into the transmission line model and perform simulation calculations on the target transmission line of a preset fixed length to obtain the scattering parameters of the target transmission line.

[0065] Step S23: Process the scattering parameters of the target transmission line based on port de-embedding technology to obtain the processed scattering parameters.

[0066] In this embodiment, after the scattering parameters of the target transmission line are obtained through simulation calculation, the scattering parameters of the target transmission line need to be processed using port de-embedding technology to remove the influence of the port itself on the signal, thereby obtaining the processed scattering parameters.

[0067] In a specific implementation, the scattering parameters of the target transmission line are processed using port de-embedding technology to obtain processed scattering parameters. This includes: performing simulation calculations on an empty port without a transmission line to obtain the scattering parameters of the empty port; and removing the scattering parameters of the empty port from the scattering parameters of the target transmission line to obtain the processed scattering parameters. It can be understood that the scattering parameters S_total of the target transmission line obtained through simulation actually include both the signal transmission characteristics of the transmission line itself and the parasitic characteristics of the port in the simulation model. To eliminate port interference, the empty port without a transmission line can be simulated separately using HFSS3D electromagnetic simulation software to obtain the scattering parameters of the port itself, denoted as S_port. This parameter only reflects the signal loss and reflection characteristics of the port structure and is independent of the transmission line length. Furthermore, the scattering parameters of the empty port are removed from the scattering parameters of the target transmission line to obtain the processed scattering parameters, that is, S_port is removed from S_total to calculate scattering parameters that only reflect the characteristics of the transmission line itself.

[0068] Step S24: Based on the target transmission line and the processed scattering parameters, calculate the scattering parameters corresponding to different transmission line lengths based on the proportional relationship between different transmission line lengths and the preset fixed length, and establish the mapping relationship between insertion loss and transmission line length based on each scattering parameter.

[0069] In this embodiment, since the processed scattering parameters have eliminated port interference, they can accurately represent the signal loss, reflection, and coupling characteristics of a transmission line of a fixed length (e.g., 200 mil), and can serve as a benchmark for subsequently deriving scattering parameters for different transmission line lengths. It is understood that, under the same substrate and structure, the scattering parameters of a transmission line have a quantifiable linear relationship with its length. Therefore, this application uses the target transmission line and the processed scattering parameters as benchmarks, and calculates the scattering parameters corresponding to different transmission line lengths based on the proportional relationship between different transmission line lengths and a preset fixed length. Taking the insertion loss in the scattering parameters as an example, assuming the insertion loss corresponding to a length of 200 mil is IL_200, then for a transmission line of length L (unit: mil), its insertion loss IL_L = IL_200 × (L / 200).

[0070] In a specific implementation, a mapping relationship between insertion loss and transmission line length is established based on various scattering parameters. This includes: obtaining the fundamental frequency of the chip signal and setting an insertion loss sequence; wherein the interval between any two adjacent insertion losses in the insertion loss sequence is the same; parsing various scattering parameters to obtain the insertion loss at the fundamental frequency for different transmission line lengths; matching the insertion loss at the fundamental frequency for different transmission line lengths with the insertion loss in the insertion loss sequence to establish a mapping relationship between each insertion loss in the insertion loss sequence, the transmission line length, and the scattering parameters, and storing the mapping relationship in a preset database. In this embodiment, the fundamental frequency of the chip signal is first determined, and an insertion loss sequence with equal steps is set, i.e., the interval between any two adjacent insertion losses in the insertion loss sequence is the same, for example, the interval can be 1 dB / step or 2 dB / step, etc. Further, by parsing the scattering parameters corresponding to different transmission line lengths, the insertion loss at the fundamental frequency for different transmission line lengths is obtained. For example, assuming the fundamental frequency is 16 GHz, the insertion loss values ​​at 16 GHz for the scattering parameters of transmission line lengths of 1 inch, 2 inches, 3 inches...n inches need to be obtained respectively. Then, the insertion loss at the fundamental frequency for different transmission line lengths is matched with the insertion loss in the insertion loss sequence to establish a mapping relationship between each insertion loss in the insertion loss sequence and the transmission line length and scattering parameters. For example, the transmission line lengths corresponding to 1dB@16G, 2dB@16G, and 3dB@16G are 2 inches, 4 inches, and 5 inches, respectively. Finally, the obtained mapping relationship is stored in a preset database.

[0071] Based on this, since the new generation of PCIe protocol supports dynamic rate adjustment, in addition to designing for a fixed base frequency (such as 16 GHz), the frequency range of transmission line simulation can be expanded, for example, from 100MHz to 200GHz. This ensures the scattering parameters corresponding to different frequency points, such as 2.5G, 5G, 16G, 32G, 64G, and 128G, thereby establishing a database of frequency value-loss curves. This supports automatically calling the scattering parameters of the corresponding frequency according to the actual negotiated rate, enabling real-time verification in dynamic rate scenarios.

[0072] Step S25: When the test requirements are obtained, the target insertion loss in the test requirements is determined, and the target scattering parameters corresponding to the target insertion loss are obtained based on the mapping relationship, so as to perform integrity verification of the signal of the chip under test based on the target scattering parameters.

[0073] For more detailed processing procedures of steps S21, S22 and S25, please refer to the corresponding content disclosed in the foregoing embodiments, which will not be repeated here.

[0074] As can be seen, this application provides a more comprehensive, simpler, and more accurate signal integrity verification scheme. On the one hand, it simplifies the relevant connection configuration and improves verification accuracy; on the other hand, it addresses the issue of insufficient equipment resources per capita, while reducing R&D expenses and increasing economic benefits. This allows for precise assessment of the high-speed signal link design of relevant topologies during actual project design, based on the specific chip type used. When the chip's driving capability is weak and does not meet the maximum link loss requirements defined by the protocol specification, risk points can be identified in a timely manner to optimize the design scheme. This avoids project cycle extensions caused by discovering problems only during the testing phase after production and PCB fabrication, thereby reducing R&D expenses and increasing economic benefits.

[0075] See Figure 5 As shown in the figure, this application discloses a chip signal integrity verification device, which includes:

[0076] The parameter acquisition module 11 is used to establish a transmission line model in the preset electromagnetic simulation software and acquire material parameters related to the inter-symbol interference test board that affect signal integrity.

[0077] The simulation calculation module 12 is used to input material parameters into the transmission line model and perform simulation calculations on a target transmission line of a preset fixed length to obtain the scattering parameters of the target transmission line.

[0078] The data processing module 13 is used to calculate the scattering parameters corresponding to different transmission line lengths based on port de-embedding technology and the scattering parameters of the target transmission line, and to establish a mapping relationship between insertion loss and transmission line length based on each scattering parameter.

[0079] The verification module 14 is used to determine the target insertion loss in the test requirements when the test requirements are obtained, and to obtain the target scattering parameters corresponding to the target insertion loss based on the mapping relationship, so as to perform integrity verification of the signal of the chip under test based on the target scattering parameters.

[0080] As can be seen, this application establishes a transmission line model using pre-set electromagnetic simulation software and imports the material parameters of the inter-symbol interference test board to ensure that the scattering parameters of the target transmission line obtained from the simulation can truly reflect the signal transmission characteristics of the actual link. Simultaneously, this application eliminates port parasitic interference based on port de-embedding technology and derives scattering parameters for different transmission line lengths. Furthermore, based on these scattering parameters, a mapping relationship between insertion loss and transmission line length is established, which can accurately match the actual working scenario of the chip under test. After obtaining the test requirements, the target scattering parameters corresponding to the target insertion loss can be quickly determined, adapting to the link loss scenarios of different projects. Compared to the traditional solution of building test links based on physical ISI boards, this application does not require the purchase of multiple ISI boards. It can construct a verification system covering multiple loss scenarios simply through electromagnetic simulation and parameter derivation, effectively solving the problem of insufficient equipment resources during parallel development of multiple projects and reducing equipment procurement expenses. It also avoids problems such as wear and poor contact caused by frequent insertion and removal of physical boards, eliminating the need for repeated calibration of loss values ​​and reducing the workload of engineers. Moreover, this application can quickly adapt to different test requirements without rebuilding the hardware link, further simplifying the verification process and reducing time and manpower costs in the R&D process.

[0081] Since the embodiments of the device part correspond to the embodiments described above, please refer to the embodiments described in the method part for the embodiments of the device part, and will not be repeated here.

[0082] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Specifically, it may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the chip signal integrity verification method performed by the electronic device as disclosed in any of the foregoing embodiments.

[0083] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0084] The processor 21 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 21 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 21 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 21 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0085] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored on it include operating system 221, computer program 222 and data 223, etc., and the storage method can be temporary storage or permanent storage.

[0086] The operating system 221 manages and controls the various hardware devices and computer programs 222 on the electronic device 20 to enable the processor 21 to perform calculations and processing on the massive amounts of data 223 in the memory 22. The operating system 221 can be Windows, Unix, Linux, etc. The computer program 222, in addition to including a computer program capable of performing the chip signal integrity verification method executed by the electronic device 20 as disclosed in any of the foregoing embodiments, may further include computer programs capable of performing other specific tasks. The data 223 may include data received by the electronic device from external devices, as well as data collected by its own input / output interface 25.

[0087] Furthermore, embodiments of this application also disclose a computer-readable storage medium storing a computer program. When the computer program is loaded and executed by a processor, it implements the chip signal integrity verification method steps disclosed in any of the foregoing embodiments.

[0088] This invention also discloses a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the chip signal integrity verification method disclosed in any of the foregoing embodiments.

[0089] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0090] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0091] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, compact disc read-only memory (CD-ROM), or any other form of storage medium known in the art.

[0092] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0093] The present invention provides a detailed description of a chip signal integrity verification method, apparatus, device, and medium. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only intended to help understand the method and core ideas of the present invention. At the same time, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for verifying the integrity of a chip signal, characterized by, The method comprises the following steps: establishing a transmission line model in a preset electromagnetic simulation software, and obtaining material parameters related to an inter-symbol interference test board and affecting signal integrity; inputting the material parameters into the transmission line model, and performing simulation calculation on a target transmission line with a preset fixed length to obtain scattering parameters of the target transmission line; calculating scattering parameters corresponding to different transmission line lengths based on a port de-embedding technology and the scattering parameters of the target transmission line, and establishing a mapping relationship between insertion loss and transmission line length based on the scattering parameters; when a test requirement is obtained, determining a target insertion loss in the test requirement, and obtaining a target scattering parameter corresponding to the target insertion loss based on the mapping relationship, to verify the integrity of a to-be-tested chip signal based on the target scattering parameter; wherein the calculation of scattering parameters corresponding to different transmission line lengths based on the port de-embedding technology and the scattering parameters of the target transmission line comprises: processing the scattering parameters of the target transmission line based on the port de-embedding technology to obtain processed scattering parameters; based on the target transmission line and the processed scattering parameters, calculating scattering parameters corresponding to different transmission line lengths based on the proportional relationship between different transmission line lengths and the preset fixed length; the establishment of the mapping relationship between insertion loss and transmission line length based on the scattering parameters comprises: obtaining the basic frequency of a chip signal and setting an insertion loss sequence; wherein the interval between any two adjacent insertion losses in the insertion loss sequence is the same; analyzing the scattering parameters to obtain the insertion loss of different transmission line lengths at the basic frequency; matching the insertion loss of different transmission line lengths at the basic frequency with the insertion loss of the insertion loss sequence to establish the mapping relationship between each insertion loss in the insertion loss sequence and the transmission line length and the scattering parameter, and store the mapping relationship in a preset database.

2. The chip signal integrity verification method according to claim 1, wherein the processing of the scattering parameters of the target transmission line based on the port de-embedding technology to obtain the processed scattering parameters comprises: performing simulation calculation on an empty port without a transmission line to obtain the scattering parameters of the empty port; removing the scattering parameters of the empty port from the scattering parameters of the target transmission line to obtain the processed scattering parameters.

3. The chip signal integrity verification method of claim 1, wherein, The material parameters are parameters related to the laminated structure and the model of the inter-symbol interference test board, and the material parameters include medium thickness, dielectric constant, impedance line bottom width, impedance line top width, differential line spacing, finished copper thickness, substrate solder mask thickness, solder mask thickness on copper skin or wiring, and solder mask dielectric constant.

4. The chip signal integrity verification method of claim 1, wherein, the integrity verification of the to-be-tested chip signal based on the target scattering parameter comprises: importing the target scattering parameter into an oscilloscope, so that the oscilloscope monitors the signal quality of the to-be-tested chip signal under the target insertion loss in real time based on the target scattering parameter, to verify the integrity of the to-be-tested chip signal based on the signal quality.

5. The chip signal integrity verification method according to claim 4, wherein The indicators for monitoring signal quality include eye diagram and bit error rate curve; correspondingly, the integrity verification of the to-be-tested chip signal based on the signal quality comprises: If the height and width of the eye diagram both satisfy the corresponding preset standard value, and the bit error rate is determined to be lower than the preset threshold value based on the bit error rate curve, it is determined that the integrity verification of the to-be-tested chip signal is passed.

6. A device for verifying the integrity of a chip signal, characterized by The method comprises the following steps: The parameter acquisition module is configured to establish a transmission line model in a preset electromagnetic simulation software, and acquire material parameters related to an inter-symbol interference test board and used for affecting signal integrity. The simulation calculation module is configured to input the material parameters into the transmission line model, and perform simulation calculation on a target transmission line with a preset fixed length to obtain scattering parameters of the target transmission line. The data processing module is configured to calculate scattering parameters corresponding to different transmission line lengths based on a port de-embedding technology and the scattering parameters of the target transmission line, and establish a mapping relationship between insertion loss and transmission line length based on the scattering parameters. The verification module is configured to determine a target insertion loss in a test requirement when the test requirement is acquired, acquire a target scattering parameter corresponding to the target insertion loss based on the mapping relationship, and perform integrity verification on a to-be-tested chip signal based on the target scattering parameter. The data processing module is configured to process the scattering parameters of the target transmission line based on a port de-embedding technology to obtain processed scattering parameters, and calculate scattering parameters corresponding to different transmission line lengths based on a proportional relationship between different transmission line lengths and the preset fixed length with the target transmission line and the processed scattering parameters as a reference. The data processing module is configured to acquire a basic frequency of a chip signal, set an insertion loss sequence, wherein the interval between any two adjacent insertion losses in the insertion loss sequence is the same, analyze the scattering parameters to acquire insertion losses of different transmission line lengths at the basic frequency, match the insertion losses of different transmission line lengths at the basic frequency with the insertion losses of the insertion loss sequence, establish a mapping relationship between each insertion loss in the insertion loss sequence and the transmission line length and the scattering parameters, and store the mapping relationship in a preset database.

7. An electronic device, comprising: The method comprises the following steps: The memory is configured to save a computer program. The processor is configured to execute the computer program to implement the steps of the chip signal integrity verification method according to any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, The computer program is stored in the memory and is executed by the processor to implement the steps of the chip signal integrity verification method according to any one of claims 1 to 5.

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