A method for online modification of switch device admittance values in real-time simulation modeling

Abstract

The present application is suitable for the field of power electronics simulation technology, and provides a kind of on-line modification method of switch device admittance numerical value in real-time simulation modeling.The present application loads circuit topology by host computer, selects switch device needing dynamic switching admittance numerical value in the circuit model to be simulated;Admittance parameter list is preset in host computer interface, and circuit admittance matrix corresponding to multiple test conditions to be measured is calculated and generated;Multiple circuit admittance matrices are sent to real-time simulator FPGA as simulation data, and corresponding switching is carried out in real-time simulation running, and circuit solving is executed.Switching admittance numerical value can be modified on-line when simulating different test conditions to be measured, and simulation error introduced by switching equivalent parasitic parameters is reduced, so that switching admittance parameter setting optimization of different test conditions is realized.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power electronics simulation, and particularly relates to a method for modifying the numerical value of a switching device admittance in real-time simulation modeling. BACKGROUND

[0002] In the existing small-step 1-microsecond-level electromagnetic transient real-time simulation method, in order to complete model calculation within a simulation step, a constant admittance model is usually used to model a switch. The switch conduction is equivalent to an inductance, and the switch turn-off is equivalent to a capacitance. The numerical values of the switch conduction and turn-off admittances are equal, and the numerical values of the switch conduction and turn-off admittances are equal when the switch switches between the conduction and turn-off states, so there is no need to dynamically solve the circuit admittance matrix.

[0003] In the prior art, there are certain defects when the simulation model runs under different operating conditions. For example, in order to enhance the blocking effect of the switch, the Gs (a parameter representing the numerical value of the admittance, which can be solved by the simulation step and Gs) of the circuit breaker needs to be set to a small value. However, when the switch switches from off to on, the equivalent inductance will increase with the decrease of Gs, and a large inductance is additionally introduced, which will affect the simulation accuracy of the circuit. The constant numerical value method of the switch admittance is difficult to cope with different operating conditions of different simulation models. SUMMARY

[0004] The purpose of the embodiment of the application is to provide a method for modifying the numerical value of a switching device admittance in real-time simulation modeling, which aims to solve the technical problems existing in the prior art mentioned in the background.

[0005] The embodiment of the application is implemented as follows:

[0006] A method for modifying the numerical value of a switching device admittance in real-time simulation modeling, the method specifically comprises the following steps:

[0007] The host computer loads the circuit topology, and selects a switching device whose numerical value needs to be dynamically switched in the to-be-simulated circuit model;

[0008] The numerical value of the admittance is preset in the host computer interface, a plurality of circuit admittance matrices corresponding to to-be-tested operating conditions are calculated and generated;

[0009] The plurality of circuit admittance matrices are sent to a real-time simulator FPGA as simulation data, and corresponding switching is performed in real-time simulation running, and circuit solving is performed.

[0010] As a further limitation of the technical scheme of the embodiment of the application, the host computer loads the circuit topology, and in the circuit model to be simulated, selects a switching device that needs to dynamically switch the admittance value, the switching device includes a fully controlled device, a semi-controlled device and an uncontrolled device, the fully controlled device is an IGBT, an IGBT with a reverse-parallel diode, a MosFET, a circuit breaker or an ideal switch, the semi-controlled device is a thyristor, and the uncontrolled device is a diode.

[0011] As a further limitation of the technical scheme of the embodiment of the application, the preset admittance parameter list in the host computer interface, the calculation and generation of the circuit admittance matrix corresponding to a plurality of to-be-tested working conditions specifically include the following steps:

[0012] The admittance parameter list in the host computer interface is preset, and the admittance values of a plurality of switching devices under a plurality of to-be-tested working conditions are configured in the admittance parameter list.

[0013] According to the plurality of admittance values in the admittance parameter list, the circuit admittance matrix corresponding to a plurality of to-be-tested working conditions is calculated and generated.

[0014] As a further limitation of the technical scheme of the embodiment of the application, the preset admittance parameter list in the host computer interface, the admittance values of a plurality of switching devices under a plurality of to-be-tested working conditions are configured in the admittance parameter list specifically include the following steps:

[0015] The plurality of switching devices in the circuit are modeled by LC equivalence, the switching device is equivalent to an inductor when the switching device is turned on, and the switching device is equivalent to a capacitor when the switching device is turned off, the switching device is discretized by using the backward Euler method, and the switching device is equivalent to a conductance and is injected with a current source.

[0016] A plurality of groups of admittance parameter tables containing default working conditions are constructed, and the admittance values of a plurality of switching devices under a plurality of to-be-tested working conditions are configured; when the switching admittance is not specified in the to-be-tested working condition, the default admittance value is used.

[0017] As a further limitation of the technical scheme of the embodiment of the application, according to the plurality of admittance values in the admittance parameter list, the circuit admittance matrix is calculated and generated according to the plurality of admittance values in the admittance parameter list, and each to-be-tested working condition corresponds to a group of coefficient equations.

[0018] As a further limitation of the technical scheme of the embodiment of the application, the plurality of circuit admittance matrices are sent to the real-time simulator FPGA as simulation data, and corresponding switching is performed in the real-time simulation running to execute circuit solving, specifically including the following steps:

[0019] The plurality of circuit admittance matrices are sent to the real-time simulator FPGA as simulation data.

[0020] In the real-time simulation running, the corresponding circuit admittance matrix is switched in real time according to different to-be-tested working conditions;

[0021] The simulator FPGA performs circuit solving according to the circuit admittance matrix.

[0022] As a further limitation of the technical scheme of the embodiment of the application, in the real-time simulation running, the current to-be-tested working condition is switched manually through the upper computer control or is automatically selected and switched through the software program calculation output condition.

[0023] Compared with the prior art, the application has the following beneficial effects:

[0024] (1) The application can modify the switch admittance value online when simulating different to-be-tested working conditions, reduce the simulation error introduced by the equivalent parasitic parameters of the switch, and thus realize the optimization of the switch admittance parameter setting of different test working conditions.

[0025] (2) The application can select different switch Gs values according to different working states of the circuit, thereby adjusting the inductance and capacitance parameters introduced by the simulation modeling method, reducing the non-real switch switching loss and equivalent parameters caused thereby, and improving the circuit simulation accuracy. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 A flowchart of the switch device admittance value online modification method in the real-time simulation modeling provided by the embodiment of the application is shown;

[0027] Figure 2 A circuit schematic diagram of the to-be-simulated circuit model provided by the embodiment of the application is shown;

[0028] Figure 3 A schematic diagram of the actual Gs setting provided by the embodiment of the application is shown;

[0029] Figure 4 A schematic diagram of the simulation efficiency calculation method provided by the embodiment of the application is shown;

[0030] Figure 5 A different admittance parameter simulation efficiency diagram provided by the embodiment of the application is shown;

[0031] Figure 6 A different admittance parameter simulation waveform diagram provided by the embodiment of the application is shown. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical scheme and advantages of the application clearer, the application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the application and do not limit the application.

[0033] It can be understood that in the prior art, there are certain defects when the simulation model runs in different operating conditions. For example, in order to enhance the blocking effect of the switch, the Gs (a parameter representing the admittance value, which can be solved by the simulation step and the Gs) of the circuit breaker needs to be set to a smaller value. However, when the switch is switched from off to on, the equivalent inductance will increase with the decrease of the Gs, and the introduction of the larger inductance will affect the accuracy of the circuit simulation. It is difficult to cope with different operating conditions of different simulation models by using the constant switch admittance value method.

[0034] To solve the above problems, the embodiment of the present application discloses a switch device admittance value online modification method in real-time simulation modeling. The host computer loads the circuit topology, selects the switch device whose admittance value needs to be dynamically switched in the to-be-simulated circuit model; the admittance parameter list is preset in the host computer interface, the circuit admittance matrix corresponding to multiple to-be-tested operating conditions is calculated and generated; the multiple circuit admittance matrices are sent to the real-time simulator FPGA as simulation data, and corresponding switching is performed in the real-time simulation running to execute circuit solving. The switch admittance value can be modified online when different to-be-tested operating conditions are simulated, the simulation error introduced by the equivalent parasitic parameters of the switch is reduced, and the optimization of the switch admittance parameter setting in different test operating conditions is realized.

[0035] Specifically, Figure 1 The flowchart of the switch device admittance value online modification method in real-time simulation modeling provided by the embodiment of the present application is shown.

[0036] In a preferred embodiment provided by the present application, a switch device admittance value online modification method in real-time simulation modeling, the method specifically comprises the following steps:

[0037] Step one, the host computer loads the circuit topology, and selects the switch device whose admittance value needs to be dynamically switched in the to-be-simulated circuit model.

[0038] In the embodiment of the present application, as Figure 2 The circuit schematic diagram of the to-be-simulated circuit model provided by the embodiment of the present application is shown, the switch device in the to-be-simulated circuit model includes a grid-side circuit breaker and a two-level six-tube inverter bridge. In the to-be-simulated circuit model, the inverter grid-side inductance is 10uH, the inverter rated output current effective value is 650A, and the direct current voltage is 650V. The switch device whose admittance value needs to be dynamically switched is selected: the two-level six-tube inverter bridge and the circuit breaker. It can be understood that the switch device includes a fully controlled device, a semi-controlled device and a non-controlled device, wherein: the fully controlled device is an IGBT, an IGBT with a reverse parallel diode, a MosFET, a circuit breaker or an ideal switch; the semi-controlled device is a thyristor; and the non-controlled device is a diode.

[0039] Step two, preset the admittance parameter list in the host computer interface, calculate and generate the circuit admittance matrix corresponding to multiple test conditions.

[0040] In the embodiment of the application, the power electronic switch in the circuit is modeled by LC equivalence, when the switch is turned on, it is equivalent to an inductor, and when it is turned off, it is equivalent to a capacitor, the switch is discretized into a conductance in parallel with an injected current source by using the backward Euler method, the Gs value of the switch in different states is preset, before the simulation starts, the Gs parameter of the switch in each condition is set according to the test condition and the switching state of the device, for example, Figure 3 The actual setting Gs schematic diagram provided by the embodiment of the application is shown, from left to right, corresponding to circuit breaker open test scene one; circuit breaker open test scene two; circuit breaker closed test scene three - set the inverter output active 0; circuit breaker closed test scene four - set the inverter output active current effective value 650A, according to the admittance parameter list data, the admittance matrix of the circuit corresponding to each condition is calculated and generated, and 4 sets of circuit admittance matrices can be obtained by 4 sets of coefficient equations.

[0041] Step three, send multiple circuit admittance matrices to the real-time simulator FPGA as simulation data, and switch correspondingly in real-time simulation to execute circuit solving.

[0042] In the embodiment of the application, the host computer compresses the admittance matrix of the circuit in each condition in CSR format, and preloads it to the condition parameter storage area of the real-time simulator FPGA through the PCIe interface, before the circuit starts simulation, the real-time simulator loads the admittance matrix corresponding to the default condition, and starts circuit solving, during simulation, the user selects the condition in real time through the interface control or external program instruction, and the real-time simulator loads the corresponding simulation data according to the user instruction.

[0043] In the specific implementation process, for the real-time simulation result analysis of the grid-connected inverter dynamically switching Gs in different working modes:

[0044] The real-time simulation test compares the measured data of the inverter in different working modes with different Gs settings, the circuit breaker is open, and the inverter capacitor phase voltage is compared under two groups of circuit breaker Gs parameters. The stronger the blocking effect of the switch, the lower the amplitude of the inverter capacitor phase voltage, when the circuit breaker switch sets Gs to 1, the simulation step is 1us, and the equivalent capacitance value when the switch is off is , similarly, when Gs is set to 0.1, the off equivalent capacitance is 0.1uF. In a 50Hz power grid, the capacitive reactance of a 1uF capacitor is , and the capacitive reactance of a 0.1uF capacitor is 10 times that of a 1uF capacitor, therefore, when the circuit breaker is open, the blocking effect is better when Gs is set to a smaller value.

[0045] The net side circuit breaker is closed, the switch is equivalent to an inductor, and when Gs is set to 1, the inductor value When Gs is 0.1, the inductor value is 10uH, the original parameter of the circuit is 10uH, at this time, the inductor equivalent to the switch makes the equivalent inductor value in the actual simulation increase by one time, and the influence on the circuit parameter is large;

[0046] Therefore, for the Gs setting of the circuit breaker, the blocking effect and the on-state inductance are contradictory, a smaller Gs can enhance the blocking effect of the switch, but will increase the inductance value in the on state; a larger Gs has a smaller inductance value in the on state, but the blocking effect is reduced. The method of dynamically modifying the Gs of the circuit breaker can select a suitable value in different switch states, for example, a large Gs value is set when the switch is on to reduce the on-state inductance, and a small Gs value is set when the switch is off to reduce the off-state capacitance and enhance the blocking effect.

[0047] As Figure 4 The schematic diagram of the simulation efficiency method provided by the embodiment of the application is shown, when the circuit breaker is disconnected, the working condition 0 and the working condition 1 parameter set the capacitor AB line voltage waveform, it can be seen that when the working condition 0 sets Gs 0.1, the actual test switch blocking effect is better, which is consistent with the theoretical judgment.

[0048] The circuit breaker is set to be closed, the inverter outputs different active currents, the values of the DC side power under different inverter Gs settings are compared, and the influence of different Gs settings on the simulation loss is quantitatively evaluated. The judgment basis of the simulation loss is that the average value of the DC side current is measured when the fixed inverter output active power to the power grid is set. When the inverter output power is constant, the larger the DC side current is, the higher the loss is.

[0049] The inverter output active power is set to 0, and the Gs parameters are set to working condition 2 and working condition 3 respectively. As Figure 5 The simulation efficiency diagram of different admittance parameters provided by the embodiment of the application is shown, when the inverter bridge sets Gs to 0.1, the average value of the DC side current is about 2A; when the inverter bridge sets Gs to 1, the average value of the DC side current is about 18.8A. It can be seen that when the inverter output power is small, setting a smaller Gs value is beneficial to reduce the loss.

[0050] The inverter output AC current effective value is set to 650A, and the Gs parameters are set to working condition 3 and working condition 2 respectively, as Figure 6The simulation waveforms of different admittance parameters provided by the embodiment of the application are shown. When the inverter bridge is set as Gs=1, the average value of the DC side current is about 568.8 A; when the inverter bridge is set as Gs=0.1, the average value of the DC side current is about 611 A. It can be seen that when the output power of the inverter is large, setting a larger Gs value is beneficial to reduce the loss. Therefore, by modifying the switching admittance value online during simulation of different working conditions, the simulation error caused by the switching equivalent parasitic parameters can be reduced, so that the switching admittance parameter setting optimization of different test working conditions can be realized.

[0051] It should be understood that although each step in the flowchart of each embodiment of the application is shown in sequence according to the arrow, these steps are not necessarily executed in sequence according to the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, at least part of the steps in each embodiment can include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these sub-steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least part of other steps or sub-steps or stages of other steps.

[0052] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing related hardware. The program can be stored in a non-volatile computer readable storage medium, and when the program is executed, it can include the processes of the above-mentioned embodiments of each method. Any reference to memory, storage, database or other medium used in each embodiment provided by the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0053] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be noted that for ordinary skilled persons in the art, without departing from the concept of the present application, several modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for online modification of the admittance value of switching devices in real-time simulation modeling, characterized in that, The method specifically includes the following steps: The host computer loads the circuit topology and selects the switching devices that need to dynamically switch the admittance value in the circuit model to be simulated. In the host computer interface, a list of admittance parameters is preset, and the circuit admittance matrices corresponding to multiple test conditions are calculated and generated. Multiple circuit admittance matrices are sent to the real-time simulator FPGA as simulation data, and corresponding switching is performed during real-time simulation to execute circuit solving. The host computer loads the circuit topology and selects the switching devices that need to dynamically switch admittance values ​​in the circuit model to be simulated. The switching devices include fully controlled devices, semi-controlled devices, and uncontrolled devices. The fully controlled devices are IGBTs, IGBTs with anti-parallel diodes, MOSFETs, circuit breakers, or ideal switches; the semi-controlled devices are thyristors; and the uncontrolled devices are diodes. The step of presetting the admittance parameter list in the host computer interface and calculating and generating circuit admittance matrices corresponding to multiple test conditions specifically includes the following steps: A list of admittance parameters is preset in the host computer interface, and the admittance values ​​of multiple switching devices under multiple test conditions are configured in the admittance parameter list. Based on the multiple admittance values ​​in the admittance parameter list, calculate and generate multiple circuit admittance matrices corresponding to the test conditions; The step of presetting an admittance parameter list in the host computer interface, wherein the admittance parameter list is configured with admittance values ​​of multiple switching devices under multiple test conditions, specifically includes the following steps: Multiple switching devices in the circuit are modeled using LC equivalents. When the switching device is on, it is equivalent to an inductor; when the switching device is off, it is equivalent to a capacitor. The switching device is discretized using the backward Euler method and is equivalent to a current source injected in parallel with conductance. Construct multiple admittance parameter tables containing default operating conditions, and configure the admittance values ​​of multiple switching devices under multiple operating conditions under test; when the switch admittance is not specified in the operating condition under test, the default admittance value is used; The step of sending multiple circuit admittance matrices to the real-time simulator FPGA as simulation data and switching them accordingly during real-time simulation to perform circuit solving specifically includes the following steps: Multiple circuit admittance matrices are sent to the real-time simulator FPGA as simulation data. During real-time simulation, the corresponding circuit admittance matrix is ​​switched in real time according to different operating conditions under test. The FPGA simulator performs circuit solving based on the circuit admittance matrix.

2. The method for online modification of the admittance value of switching devices in real-time simulation modeling according to claim 1, characterized in that, In the step of calculating and generating multiple circuit admittance matrices corresponding to the test conditions based on multiple admittance values ​​in the admittance parameter list, each test condition corresponds to a set of coefficient equations.

3. The method for online modification of the admittance value of switching devices in real-time simulation modeling according to claim 1, characterized in that, During the real-time simulation, the current test condition can be manually switched via the host computer control, or the current test condition can be automatically selected and switched via the conditions calculated and output by the software program.

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