Field programmable gate array (FPGA) embedded radio frequency unit testing method based on universal interconnection bus
By adopting an FPGA-embedded RF unit testing method based on a universal interconnect bus, automated testing is achieved by utilizing the internal resources of the FPGA, which solves the problems of complex external test platforms and high costs, and realizes efficient and reliable RF unit testing.
Patent Information
- Application Number
- CN202511019892.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-23
- Publication Date
- 2025-11-04
AI Technical Summary
In the existing technology, testing the RF unit embedded in the FPGA requires a complex external test platform and high testing costs, and manually modifying the configuration parameters is not suitable for automated production testing.
An FPGA-embedded RF unit testing method based on a universal interconnect bus is adopted. The RF unit is configured through the FPGA embedded processor, the RF signal is generated by the internal programmable logic resources, the test data is cached in the on-chip memory, the test results are compared using the embedded processor, and the signal is detected by combining with an automated test machine to achieve automated testing.
It enables automated testing of FPGA-embedded RF units, saving testing costs, improving testing speed and reliability, reducing cache size, and eliminating the need for external memory and complex external testing equipment.
Smart Images
Figure CN120895077A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuits and relates to a test method for FPGA embedded radio frequency units based on a universal interconnect bus. Background Technology
[0002] FPGA (Field Programmable Gate Array) has been widely used in product design and prototyping. An FPGA integrates various unit modules and IP cores, including programmable radio frequency (RF) processors, digital signal processors, high-performance memory, high-speed serial interfaces, PCIe (Peripheral Component Interconnect Express), and Ethernet, enabling a single chip to support an entire system application. It features miniaturization, low cost, high performance, and flexible design.
[0003] Testing FPGA-embedded radio frequency (RF) units presents challenges such as complex external test platforms and high testing costs. Furthermore, establishing a connection between the RF unit and the FPGA typically involves manually modifying configuration parameters, which is unsuitable for automated production testing. Summary of the Invention
[0004] The technical problem solved by this invention is to overcome the shortcomings of the prior art and propose a test method for FPGA embedded radio frequency units based on a universal interconnect bus, which can realize automated testing of FPGA embedded radio frequency units without the need for external test equipment, thus saving test costs.
[0005] The solution of the present invention is:
[0006] FPGA embedded RF unit testing methods based on universal interconnect bus include:
[0007] Step 1: Configure the FPGA embedded RF unit according to the configuration parameters and transmit / receive duplex mode using the FPGA embedded processor;
[0008] Step 2: Based on the programmable logic resources inside the FPGA, generate the first radio frequency signal corresponding to the configuration parameters in the radio frequency unit embedded in the FPGA;
[0009] Step 3: Establish a first radio frequency channel for receiving the first radio frequency signal using the FPGA embedded radio frequency unit; detect the first radio frequency signal received by the first radio frequency channel to obtain first detection data;
[0010] Step 4: Use the FPGA on-chip memory to cache the configuration parameters, the first radio frequency signal, and the first detection data;
[0011] Step 5: Use the FPGA embedded processor to compare the first detection data with the specification value to obtain the test results of the first RF channel;
[0012] Step 6: Use an automated testing machine to generate a second radio frequency signal according to the configuration parameters;
[0013] Step 7: Establish a second radio frequency channel for receiving the second radio frequency signal using the FPGA embedded radio frequency unit;
[0014] Step 8: Detect the second radio frequency signal received by the second radio frequency channel to obtain the second detection data;
[0015] Step 9: Using the FPGA embedded processor, compare the second detection data with the standard value according to the method in Step 5 to obtain the test results of the second RF channel.
[0016] Step 10: Repeat steps 6 to 9 to obtain the test results of the remaining RF channels of the FPGA embedded RF unit; and determine whether the FPGA embedded RF unit test passed or failed.
[0017] In the above-described FPGA embedded RF unit testing method based on a universal interconnect bus, the specific method for configuring the FPGA embedded RF unit according to configuration parameters and transmit / receive duplex mode by the FPGA embedded processor in step one is as follows:
[0018] Based on the configuration parameters, the FPGA embedded processor is used to write the initial value of the FPGA embedded radio frequency unit configuration register.
[0019] Configure the FPGA's embedded RF unit to transmit / receive full-duplex mode and determine its operating parameters.
[0020] In the above-described FPGA embedded RF unit testing method based on a universal interconnect bus, the specific method for generating the first RF signal corresponding to the configuration parameters in step two of the FPGA embedded RF unit is as follows:
[0021] Using the programmable logic resources inside the FPGA, a first single-tone signal is generated through direct digital frequency synthesis; based on the first single-tone signal, the phase word and frequency word corresponding to the configuration parameters are configured in the RF unit embedded in the FPGA, and the first RF signal corresponding to the configuration parameters is output.
[0022] In the above-described FPGA embedded RF unit test method based on a universal interconnect bus, the method for establishing the first RF channel for the FPGA embedded RF unit to receive the first RF signal in step three is as follows:
[0023] By connecting one RF transmit pin of the FPGA embedded RF unit to multiple RF receive pins of the FPGA embedded RF unit through a power divider, multiple first RF channels for the FPGA embedded RF unit to receive the first RF signal are obtained.
[0024] In the above-mentioned FPGA embedded RF unit testing method based on a universal interconnect bus, the method for obtaining the first detection data is as follows:
[0025] The first radio frequency signal received by the first radio frequency channel is buffered across clock domains using the FPGA on-chip memory; the buffered first radio frequency signal is converted from parallel to serial according to the corresponding radio frequency channel to obtain the converted signal; the converted signal is then subjected to a fast Fourier transform to obtain the transformed signal; the signal strength and signal-to-noise ratio of the received first radio frequency signal are determined based on the transformed signal; and the first detection data is determined based on the first radio frequency signal transmission power and the signal strength and signal-to-noise ratio of the received first radio frequency signal.
[0026] In the above-described FPGA embedded RF unit testing method based on a universal interconnect bus, the method for obtaining the test results of the first RF channel in step five is as follows:
[0027] Using the FPGA embedded processor, the signal strength, signal-to-noise ratio and transmitted signal power of the first radio frequency signal received by the first radio frequency channel are compared with the corresponding standard values in the electrical parameter table.
[0028] When the difference between the signal strength, signal-to-noise ratio, and transmitted signal power and the corresponding standard values does not exceed the preset value, the first radio frequency channel is judged to be working normally; when any of the differences exceeds the preset value, the first radio frequency channel is judged to be working abnormally.
[0029] In the above-described FPGA embedded RF unit testing method based on a universal interconnect bus, the method for generating the second RF signal in step six is as follows:
[0030] The second monotone signal is generated using an automated testing machine.
[0031] Configure the FPGA embedded RF unit using an automated test bench according to the configuration parameters described above;
[0032] Based on the second single-tone signal, the second radio frequency signal corresponding to the configuration parameters is output by the radio frequency unit embedded in the FPGA.
[0033] In the above-described FPGA embedded RF unit testing method based on a universal interconnect bus, the method for establishing the second RF channel in step seven is as follows:
[0034] Connect the signal generator and spectrum analyzer to the automatic test bench via the GPIB interface; connect one RF receiving pin of the FPGA embedded RF unit to the signal generator; connect one RF transmitting pin of the FPGA embedded RF unit to the spectrum analyzer to obtain the second RF channel for the FPGA embedded RF unit to receive the second RF signal.
[0035] In the above-described FPGA embedded RF unit testing method based on a universal interconnect bus, the method for detecting the second RF signal and obtaining the second detection data in step eight is as follows:
[0036] The automatic test equipment acquires the received second radio frequency signal through the GPIB interface and calculates the signal strength and signal-to-noise ratio of the received second radio frequency signal; the automatic test equipment reads the spectrum analyzer through the GPIB interface to acquire the transmission power of the second radio frequency signal; and determines the second test data based on the transmission power of the second radio frequency signal and the signal strength and signal-to-noise ratio of the received second radio frequency signal.
[0037] In the above-described FPGA embedded RF unit testing method based on a universal interconnect bus, the method for determining the FPGA embedded RF unit testing status in step ten is as follows:
[0038] If all RF channels of the FPGA embedded RF unit test results are normal, the FPGA embedded RF unit test is considered passed; otherwise, the FPGA embedded RF unit test is considered failed.
[0039] The advantages of this invention compared to the prior art are:
[0040] (1) This invention adopts an in-chip FPGA testing method to complete signal processing inside the chip, realizing an automated test of an FPGA embedded radio frequency unit based on a universal interconnect bus. It does not require external testing equipment, saving testing costs; it has strong versatility and can test multiple frequency points, bandwidth and other parameters by loading different configuration files.
[0041] (2) Based on the FPGA embedded radio frequency unit and FPGA embedded processor and other FPGA internal programmable logic resources, the present invention uses a general interconnect bus to interact with the FPGA internal data, which can realize the pipelined processing of test signal transmission, reception and judgment, speed up the test processing speed and reduce the test buffer amount.
[0042] (3) This invention does not require additional hardware design. It can achieve FPGA built-in testing by using only the on-chip memory of the FPGA for caching, without the need for external DDR or other memory.
[0043] (4) The present invention compares the test results of the automatic test machine with the test results of the FPGA embedded radio frequency unit based on the universal interconnect bus, which can enhance the reliability of the final test results. Attached Figure Description
[0044] Figure 1 This is a flowchart of the FPGA embedded radio frequency unit test process of the present invention;
[0045] Figure 2 This is a flowchart of a test method for FPGA embedded radio frequency units based on a universal interconnect bus, according to an embodiment of the present invention.
[0046] Figure 3 This is a flowchart illustrating the software module design of an embodiment of the present invention.
[0047] Figure 4 This is a block diagram of the hardware circuit principle of the FPGA initialization radio frequency unit in an embodiment of the present invention;
[0048] Figure 5 This is a flowchart of the FPGA embedded radio frequency unit testing method with an automated testing machine, as shown in the embodiment of the present invention. Detailed Implementation
[0049] The present invention will be further described below with reference to the embodiments.
[0050] This invention provides a test method for FPGA embedded radio frequency units based on a universal interconnect bus, which can realize automated testing of FPGA embedded radio frequency units without the need for external test equipment, thus saving test costs.
[0051] Test methods for FPGA embedded RF units based on universal interconnect buses, such as Figure 1 As shown, the specific steps include the following:
[0052] Step 1: Configure the FPGA embedded RF unit according to the configuration parameters and transmit / receive duplex mode using the FPGA embedded processor.
[0053] The specific method for configuring the FPGA embedded RF unit according to the configuration parameters and transmit / receive duplex mode by the FPGA embedded processor is as follows:
[0054] Based on the configuration parameters, the FPGA embedded processor is used to write the initial value of the FPGA embedded radio frequency unit configuration register.
[0055] Configure the FPGA's embedded RF unit to transmit / receive full-duplex mode and determine its operating parameters.
[0056] Step 2: Based on the programmable logic resources inside the FPGA, generate the first radio frequency signal corresponding to the configuration parameters in the radio frequency unit embedded in the FPGA.
[0057] The specific method for generating the first radio frequency signal corresponding to the configuration parameters in the FPGA embedded radio frequency unit is as follows:
[0058] Using the programmable logic resources inside the FPGA, a first single-tone signal is generated through direct digital frequency synthesis; based on the first single-tone signal, the phase word and frequency word corresponding to the configuration parameters are configured in the RF unit embedded in the FPGA, and the first RF signal corresponding to the configuration parameters is output.
[0059] Step 3: Establish a first radio frequency channel for receiving the first radio frequency signal using the FPGA embedded radio frequency unit; detect the first radio frequency signal received by the first radio frequency channel to obtain the first detection data.
[0060] The method for establishing a first radio frequency channel for receiving a first radio frequency signal using an embedded radio frequency unit in an FPGA is as follows:
[0061] By connecting one RF transmit pin of the FPGA embedded RF unit to multiple RF receive pins of the FPGA embedded RF unit through a power divider, multiple first RF channels for the FPGA embedded RF unit to receive the first RF signal are obtained.
[0062] The method for obtaining the first detection data is as follows:
[0063] The first radio frequency signal received by the first radio frequency channel is buffered across clock domains using the FPGA on-chip memory; the buffered first radio frequency signal is converted from parallel to serial according to the corresponding radio frequency channel to obtain the converted signal; the converted signal is then subjected to a fast Fourier transform to obtain the transformed signal; the signal strength and signal-to-noise ratio of the received first radio frequency signal are determined based on the transformed signal; and the first detection data is determined based on the first radio frequency signal transmission power and the signal strength and signal-to-noise ratio of the received first radio frequency signal.
[0064] Step 4: Use the FPGA on-chip memory to cache the configuration parameters, the first radio frequency signal, and the first detection data.
[0065] Step 5: Use the FPGA embedded processor to compare the first detection data with the standard value to obtain the test results of the first RF channel.
[0066] The method for obtaining the test results of the first RF channel is as follows:
[0067] Using the FPGA embedded processor, the signal strength, signal-to-noise ratio, and transmit signal power of the first radio frequency signal received by the first radio frequency channel are compared with the corresponding specification values in the electrical parameter table.
[0068] When the difference between the signal strength, signal-to-noise ratio, and transmitted signal power and the corresponding standard values does not exceed the preset value, the first radio frequency channel is judged to be working normally; when any of the differences exceeds the preset value, the first radio frequency channel is judged to be working abnormally.
[0069] Step 6: Use an automated testing machine to generate a second radio frequency signal according to the configuration parameters.
[0070] The method for generating the second radio frequency signal is as follows:
[0071] The second monotone signal is generated using an automated testing machine.
[0072] Configure the FPGA embedded RF unit using an automated test bench according to the specified configuration parameters.
[0073] Based on the second single-tone signal, the second radio frequency signal corresponding to the configuration parameters is output by the radio frequency unit embedded in the FPGA.
[0074] Step 7: Establish a second radio frequency channel for receiving the second radio frequency signal using the FPGA embedded radio frequency unit.
[0075] The method for establishing a second radio frequency channel is as follows:
[0076] Connect the signal generator and spectrum analyzer to the automatic test bench via the GPIB interface; connect one RF receiving pin of the FPGA embedded RF unit to the signal generator; connect one RF transmitting pin of the FPGA embedded RF unit to the spectrum analyzer to obtain the second RF channel for the FPGA embedded RF unit to receive the second RF signal.
[0077] Step 8: Detect the second radio frequency signal received by the second radio frequency channel to obtain the second detection data.
[0078] The method for detecting the second radio frequency signal to obtain the second detection data is as follows:
[0079] The automatic test equipment acquires the received second radio frequency signal through the GPIB interface and calculates the signal strength and signal-to-noise ratio of the received second radio frequency signal; the automatic test equipment reads the spectrum analyzer through the GPIB interface to acquire the transmission power of the second radio frequency signal; and determines the second test data based on the transmission power of the second radio frequency signal and the signal strength and signal-to-noise ratio of the received second radio frequency signal.
[0080] Step 9: Using the FPGA embedded processor, compare the second test data with the standard value according to the method in Step 5 to obtain the test results of the second RF channel.
[0081] Step 10: Repeat steps 6 to 9 to obtain the test results of the remaining RF channels of the FPGA embedded RF unit; and determine whether the FPGA embedded RF unit test passed or failed.
[0082] The method for determining the test status of the FPGA embedded RF unit is as follows:
[0083] If all RF channels of the FPGA embedded RF unit test results are normal, the FPGA embedded RF unit test is considered passed; otherwise, the FPGA embedded RF unit test is considered failed.
[0084] The above-mentioned FPGA embedded radio frequency unit testing method based on a universal interconnect bus provided by the present invention includes: configuring the FPGA embedded radio frequency unit according to configuration parameters and transmit / receive duplex mode using an FPGA embedded processor; generating a first radio frequency signal corresponding to the configuration parameters in the FPGA embedded radio frequency unit based on the FPGA's internal programmable logic resources; establishing a first radio frequency channel for the FPGA embedded radio frequency unit to receive the first radio frequency signal; detecting the first radio frequency signal received by the first radio frequency channel to obtain first detection data, and transmitting the first detection data to the FPGA embedded processor; transmitting the configuration parameters, the first radio frequency signal, and the first detection data through the universal interconnect bus, and caching them using the FPGA's on-chip memory; and comparing the first detection data with the specified value using the FPGA embedded processor to obtain the test result of the first radio frequency channel.
[0085] The FPGA embedded processor is used to configure the FPGA embedded radio frequency unit according to the configuration parameters and transmit / receive duplex mode. This includes: writing the initial value of the FPGA embedded radio frequency unit configuration register according to the configuration parameters; configuring the FPGA embedded radio frequency unit to transmit / receive duplex mode and determining the operating parameters; and using the FPGA embedded processor to call the hardware abstraction layer function to initialize the states of multiple operating parameters in the FPGA application layer.
[0086] Based on the programmable logic resources inside the FPGA, a first radio frequency signal corresponding to the configuration parameters is generated in the radio frequency unit embedded in the FPGA, including: using the programmable logic resources inside the FPGA to generate a first single-tone signal through direct digital frequency synthesis; based on the first single-tone signal, configuring the phase word and frequency word corresponding to the configuration parameters in the radio frequency unit embedded in the FPGA, and outputting the first radio frequency signal corresponding to the configuration parameters.
[0087] Establishing a first radio frequency channel for receiving a first radio frequency signal by an embedded radio frequency unit in an FPGA includes: connecting a radio frequency transmitting pin of an embedded radio frequency unit in an FPGA to multiple radio frequency receiving pins of the embedded radio frequency unit in an FPGA through a power divider, thereby obtaining multiple first radio frequency channels for receiving the first radio frequency signal by the embedded radio frequency unit in an FPGA.
[0088] The method involves detecting a first radio frequency (RF) signal received through a first RF channel to obtain first detection data, and transmitting the first detection data to an FPGA embedded processor. This includes: buffering the first RF signal received through the first RF channel across clock domains using the FPGA's on-chip memory; performing a parallel-to-serial conversion on the buffered first RF signal according to the corresponding RF channel to obtain a parallel-to-serial converted signal; performing a fast Fourier transform on the parallel-to-serial converted signal to obtain a transformed signal; determining the signal strength and signal-to-noise ratio (SNR) of the received first RF signal based on the transformed signal; determining the first detection data based on the first RF signal's transmit power and the received first RF signal's signal strength and SNR; and transmitting the first detection data to the FPGA embedded processor.
[0089] Specifically, using the FPGA embedded processor, the first detection data and the standard value are compared to obtain the test results of the first radio frequency channel. This includes: using the FPGA embedded processor, comparing the signal strength, signal-to-noise ratio, and transmit signal power of the first radio frequency signal received by the first radio frequency channel with the corresponding standard values in the electrical parameter table; when the difference between the signal strength, signal-to-noise ratio, and transmit signal power and the corresponding standard value does not exceed a preset value, the first radio frequency channel is determined to be working normally; when the difference between the signal strength, signal-to-noise ratio, or transmit signal power and the corresponding standard value exceeds a preset value, the first radio frequency channel is determined to be working abnormally.
[0090] The FPGA embedded RF unit testing method based on a universal interconnect bus provided by this invention further includes: using an automatic test bench to generate a second RF signal according to configuration parameters; establishing a second RF channel for the FPGA embedded RF unit to receive the second RF signal; detecting the second RF signal received by the second RF channel to obtain second detection data, and transmitting the second detection data to the FPGA embedded processor; using the FPGA embedded processor to compare the second detection data with the specification value to obtain the test result of the second RF channel; when the test results of the first RF channel and the second RF channel are both normal, the FPGA embedded RF unit based on the universal interconnect bus passes the test.
[0091] Using an automated test bench to generate a second radio frequency signal according to configuration parameters includes: using the automated test bench to generate a second single-tone signal; using the automated test bench to configure the FPGA embedded radio frequency unit according to the configuration parameters; and based on the second single-tone signal, outputting the second radio frequency signal corresponding to the configuration parameters from the FPGA embedded radio frequency unit.
[0092] Establishing a second radio frequency channel for receiving a second radio frequency signal by an FPGA embedded radio frequency unit includes: connecting a signal generator and a spectrum analyzer to an automatic test bench via a GPIB interface; connecting one radio frequency receiving pin of the FPGA embedded radio frequency unit to the signal generator; and connecting one radio frequency transmitting pin of the FPGA embedded radio frequency unit to the spectrum analyzer, thereby obtaining a second radio frequency channel for receiving a second radio frequency signal by the FPGA embedded radio frequency unit.
[0093] The second radio frequency signal received by the second radio frequency channel is detected to obtain second detection data, including: the automatic test equipment acquires the received second radio frequency signal through the GPIB interface and calculates the signal strength and signal-to-noise ratio of the received second radio frequency signal; the automatic test equipment reads the spectrum analyzer through the GPIB interface to obtain the transmission power of the second radio frequency signal; and the second detection data is determined based on the transmission power of the second radio frequency signal and the signal strength and signal-to-noise ratio of the received second radio frequency signal.
[0094] Example
[0095] To more clearly illustrate the FPGA embedded RF unit testing method based on a universal interconnect bus, the following example demonstrates the design of the internal test software code using Verilog and C languages. Figure 2 The steps in the embodiments of the present invention will be described in detail below.
[0096] The FPGA embedded RF unit testing method based on a universal interconnect bus according to an embodiment of the present invention includes steps S1 to S6, each step of which is described in detail below:
[0097] S1: Use the FPGA embedded processor to configure the FPGA embedded RF unit according to the configuration parameters and transmit / receive duplex mode.
[0098] S2: Based on the programmable logic resources inside the FPGA, the first radio frequency signal corresponding to the configuration parameters is generated by the radio frequency unit embedded in the FPGA.
[0099] S3: Establish the first radio frequency channel for the FPGA embedded radio frequency unit to receive the first radio frequency signal.
[0100] S4: Detect the first radio frequency signal received by the first radio frequency channel, obtain the first detection data, and transmit the first detection data to the FPGA embedded processor.
[0101] S5: Transmits configuration parameters, first RF signal and first detection data through a universal interconnect bus, and uses FPGA on-chip memory for caching.
[0102] S6: Using the FPGA embedded processor, the first detection data and the standard value are compared to obtain the test results of the first RF channel.
[0103] In the above embodiments, an in-chip FPGA testing method is adopted to complete signal processing within the chip, realizing automated testing of the FPGA embedded RF unit based on a universal interconnect bus. This eliminates the need for external testing equipment, saving testing costs. It is highly versatile, allowing testing of multiple frequency points, bandwidths, and other parameters by loading different configuration files. Based on the FPGA's embedded RF unit and embedded processor, and other internal programmable logic resources, the universal interconnect bus enables pipelined processing of test signal transmission, reception, and judgment, accelerating test processing speed, reducing test buffer size, and eliminating the need for additional hardware design. FPGA-integrated testing can be achieved using only the FPGA's on-chip memory for caching, without the need for external DDR or other memory.
[0104] In some specific embodiments of step S1, the FPGA embedded processor is used to configure the FPGA embedded RF unit according to configuration parameters and transmit / receive duplex mode. This includes: writing the initial value of the FPGA embedded RF unit configuration register using the FPGA embedded processor according to the configuration parameters; configuring the FPGA embedded RF unit in transmit / receive duplex mode and determining the operating parameters; and using the FPGA embedded processor to call the Hardware Abstraction Layer (HAL) C language function to initialize multiple operating parameter states at the FPGA application layer, so as to enable subsequent testing of the RF unit at different frequencies and with different operating parameters. The aforementioned operating parameters include key parameters such as operating frequency, gain, and attenuation.
[0105] For example, the operating parameters for testing the FPGA-embedded RF unit are as follows: Under the maximum, minimum, and typical frequency points and bandwidths specified in the configuration parameters, the signal-to-noise ratio (SNR) of the received signal from the RF unit is measured. This allows for the measurement of RF parameters such as transmit attenuation range, receive gain range, maximum operating bandwidth, minimum operating bandwidth, maximum operating frequency, minimum operating frequency, transmit signal strength, and receive signal-to-noise ratio. The testing method remains the same when testing different frequency points or bandwidths; only the FPGA's configuration bitstream needs to be changed to make the RF unit operate in the specified mode.
[0106] In some specific embodiments of step S2, based on the programmable logic resources inside the FPGA, a first radio frequency signal corresponding to the configuration parameters is generated in the FPGA-embedded radio frequency unit. This includes: using the programmable logic resources inside the FPGA to generate a first single-tone signal through direct digital frequency synthesis; based on the first single-tone signal, configuring the phase word and frequency word corresponding to the configuration parameters in the FPGA-embedded radio frequency unit, and outputting the first radio frequency signal corresponding to the configuration parameters. Specifically, based on direct digital frequency synthesis, a single-tone signal is generated inside the FPGA using digital frequency synthesis. After configuring the phase word and frequency word, a digital quadrature intermediate frequency signal of the required frequency is output. Direct digital frequency synthesis refers to generating a series of digital signals and converting them into analog signals via a digital-to-analog converter. DDS is the abbreviation for Direct Digital Synthesizer. DDS converts a series of digital signals into analog signals via a digital-to-analog converter. DDS directly synthesizes the required waveform based on the phase concept. Compared with traditional frequency synthesizers, DDS has advantages such as low cost, low power consumption, high resolution, and fast conversion time.
[0107] In some specific embodiments of step S3, establishing a first radio frequency channel for the FPGA embedded radio frequency unit to receive the first radio frequency signal includes: connecting one radio frequency transmit pin of the FPGA embedded radio frequency unit to multiple radio frequency receive pins of the FPGA embedded radio frequency unit through a power divider, thereby obtaining multiple first radio frequency channels for the FPGA embedded radio frequency unit to receive the first radio frequency signal. For example, using an SMA (SubMiniature version A) cable, one radio frequency transmit pin TX1 of the FPGA embedded radio frequency unit is connected to multiple radio frequency receive pins RX11, RX12, to RX1N of the FPGA embedded radio frequency unit through a power divider. The established one or more first radio frequency channels are self-transmitting and self-receiving channels of the FPGA embedded radio frequency unit, used for testing single-tone signals inside the FPGA, realizing the self-transmitting and self-receiving of the FPGA embedded radio frequency unit. By detecting the transmitted and received signals of the first radio frequency channels, the FPGA embedded radio frequency unit is tested.
[0108] In some specific embodiments of step S4, detecting the first radio frequency signal received by the first radio frequency channel to obtain first detection data, and transmitting the first detection data to the FPGA embedded processor, includes: buffering the first radio frequency signal received by the first radio frequency channel across clock domains using the FPGA on-chip memory; converting the buffered first radio frequency signal into a parallel-to-serial converter according to the corresponding radio frequency channel to obtain a parallel-to-serial converter signal; performing a Fast Fourier Transform on the parallel-to-serial converter signal to obtain a transformed signal; determining the signal strength and signal-to-noise ratio of the received first radio frequency signal based on the transformed signal; determining the first detection data based on the first radio frequency signal transmission power and the signal strength and signal-to-noise ratio of the received first radio frequency signal; and transmitting the first detection data to the FPGA embedded processor. The transmit and receive signal parameters, i.e., the first detection data, collected in step S4 serve as the basis for testing the FPGA embedded radio frequency unit.
[0109] In step S5, the configuration parameters, the first radio frequency signal, and the first detection data from the preceding steps are transmitted via the general-purpose interconnect bus, and the above data and related data are cached using the FPGA on-chip memory. Specifically, the basic configuration of the hardware platform, the configuration of the radio frequency unit parameters, and the transmission of the intermediate frequency digital signal are read and written using the general-purpose interconnect bus. On the FPGA embedded processor, the frequency point is checked for correctness, and the signal-to-noise ratio result is printed via serial port and GPIO (General-purpose input / output).
[0110] In existing technologies, testing of FPGA-embedded RF units involves complex external test platforms, generating a large amount of test data. This massive amount of test data relies on the complex processing flow of these external test platforms, requiring data transfer between different external test platform data interfaces. This results in multiple unnecessary data conversion processes and necessitates multiple verifications of the converted data, leading to long data processing times. Consequently, much of this data cannot be processed in real time and needs to be cached in memory for later retrieval. While FPGA on-chip memory offers fast processing speeds as a cache, its small cache size cannot meet the large amount of cached data generated by FPGA-embedded RF unit testing in existing technologies. Therefore, in current technologies, DDR (Double Data Rate Synchronous Dynamic Random Access Memory) is typically used as an external memory for FPGA on-chip systems to cache data. DDR has a large storage capacity, but as an external device, the data stored in DDR needs to be transferred to the FPGA before test data can be exchanged, which reduces the test data processing speed. Furthermore, external DDR also increases the cost of FPGA-embedded RF unit testing.
[0111] In step S5, based on the FPGA's internal programmable logic resources such as the FPGA's embedded radio frequency unit and embedded processor, a general-purpose interconnect bus is used to interact with the FPGA's internal data, avoiding multiple unnecessary data conversion processes, improving data transmission speed, enabling pipelined processing of test signal transmission, reception, and judgment, accelerating test processing speed, reducing test buffer size, and eliminating the need for additional hardware design. Only the FPGA's on-chip memory is used to buffer configuration parameters, the first radio frequency signal, the first detection data, and other related data, which enables FPGA-built-in testing without the need for external DDR or other memory.
[0112] In some specific embodiments of step S6, the FPGA embedded processor is used to compare the first detection data with the standard value to obtain the test result of the first radio frequency channel. This includes: using the FPGA embedded processor to compare the signal strength, signal-to-noise ratio, and transmit signal power of the first radio frequency signal received by the first radio frequency channel with the corresponding standard values in the electrical parameter table; when the difference between the signal strength, signal-to-noise ratio, and transmit signal power and the corresponding standard value does not exceed a preset value, the first radio frequency channel is determined to be working normally; when the difference between the signal strength, signal-to-noise ratio, or transmit signal power and the corresponding standard value exceeds a preset value, the first radio frequency channel is determined to be working abnormally.
[0113] Step S6 completes the single-tone signal test inside the FPGA, realizing the self-transmission and self-reception of the FPGA's embedded RF unit. The FPGA's embedded RF unit is tested by detecting the transmit and receive signals of the first RF channel.
[0114] The above steps S1 to S6 are used for FPGA internal single-tone signal testing. In actual testing, FPGA external single-tone signal testing can also be added. The consistency of the FPGA internal single-tone signal test results and the FPGA external single-tone signal test results is judged. When both the FPGA internal single-tone signal test results and the FPGA external single-tone signal test results pass, the FPGA embedded RF unit test is determined to be passed.
[0115] In some specific implementations of adding external single-tone signal testing to the FPGA described above, automated processing can be achieved by designing corresponding software modules. The design process of the corresponding software modules is as follows: Figure 3 As shown, it includes the following steps:
[0116] Step 1: Based on the programmable logic resources inside the FPGA, develop an RF unit test stimulus generation module to generate the first RF signal.
[0117] Step 2: Generate the RF unit configuration module and configure the RF unit to the corresponding working mode to enable testing of the RF unit at different frequencies and under different working conditions.
[0118] Step 3: Based on the programmable logic resources inside the FPGA, develop an RF unit test response analysis module to detect the first RF signal received by the first RF channel, obtain the first detection data, and transmit the first detection data to the FPGA embedded processor; or to detect the second RF signal received by the second RF channel, obtain the second detection data, and transmit the second detection data to the FPGA embedded processor.
[0119] Step 4: Implement data interaction between the test stimulus generation module, RF unit configuration module, test response analysis module and RF unit through the FPGA's internal universal interconnect bus.
[0120] Step 5: Establish the physical connection of the RF channel, complete the FPGA code stream configuration, generate the input signal required for testing through the FPGA or an external signal source, and process the RF output result through the FPGA's internal test response analysis module to realize the built-in self-test of the FPGA's embedded RF unit.
[0121] Data interaction of the above software modules, such as Figure 4 As shown, RFSoC (Radio Frequency System on Chip) represents a system-on-a-chip with an embedded radio frequency unit within an FPGA. This embedded RF unit receives and transmits radio frequency signals via a universal interconnect bus. The configuration module is based on the FPGA's embedded processor. GPIO is a general-purpose input / output interface. Data interaction between the test stimulus generation module, configuration module, test response analysis module, and the RF unit is conducted via the universal interconnect bus.
[0122] In some specific implementations of adding external single-tone signal testing to the FPGA, the present invention provides a test method for an FPGA embedded radio frequency unit based on a universal interconnect bus, which further includes: using an automatic test machine to generate a second radio frequency signal according to configuration parameters; establishing a second radio frequency channel for the FPGA embedded radio frequency unit to receive the second radio frequency signal; detecting the second radio frequency signal received by the second radio frequency channel to obtain second detection data, and transmitting the second detection data to the FPGA embedded processor; using the FPGA embedded processor to compare the second detection data with the specification value to obtain the test result of the second radio frequency channel; when the test results of the first radio frequency channel and the test results of the second radio frequency channel are both normal, the FPGA embedded radio frequency unit based on the universal interconnect bus passes the test.
[0123] For example, such as Figure 5As shown, hardware and software test platforms were built. The software platform refers to the aforementioned software modules, and the hardware platform refers to the external automated test bench. Physical connections for the RF channel were established, FPGA code stream configuration was completed, and the GPIB control signal source generated the required input signals and external reference clock. The automated test bench configured the FPGA via SMAP. The FPGA's embedded processor configured the FPGA's embedded RF units and automatically established connections.
[0124] Figure 5 Transmit channel 1 and receive channel 1 correspond to the second radio frequency (RF) channel, used for the transmission and reception of the second RF signal on the hardware platform. The second RF signal received by the second RF channel is detected to obtain second detection data. For example, an automated test instrument reads the spectrum analyzer through the GPIB interface to obtain the transmit power of the second RF signal. Based on the transmit power of the second RF signal and the signal strength and signal-to-noise ratio of the received second RF signal, the second detection data is determined. A decision is made on the second RF channel: the second detection data is compared with the specified value to obtain the test result of the second RF channel, and the function and performance of the second RF channel are judged.
[0125] Figure 5 The remaining channels, corresponding to the first RF channels, are used for RF signal transmission and reception by the software platform, i.e., the FPGA's embedded RF unit's self-transmission and self-reception of the first RF signal. Specifically, multiple first RF channels can be formed by establishing one-to-many pin connections. For example, one RF transmit pin TX1 of the FPGA's embedded RF unit can be connected to multiple RF receive pins RX11, RX12, and RX1N of the FPGA's embedded RF unit through a power divider, thus obtaining multiple first RF channels such as TX1 to RX11, TX1 to RX12, and TX1 to RX13. The first RF channels are then judged: the first detection data of each of the multiple first RF channels is compared with the standard value to obtain the test results of the multiple first RF channels.
[0126] Figure 5 In the process, the RF output results are processed by the FPGA internal test response analysis module, and the decision results of the first RF channel and the second RF channel are processed to realize the built-in self-test of the FPGA embedded RF unit and end the test.
[0127] In the above-described implementation scheme with an automated test bench, comparing the test results from the automated test bench with the test results of the FPGA embedded RF unit based on the universal interconnect bus of this invention enhances the reliability of the final test results. Furthermore, by adding only the automated test bench, the number of external test platforms required for testing the FPGA embedded RF unit in existing technologies is reduced, simplifying the complex external test platforms in the prior art.
[0128] In some specific implementations, an automated test bench is used to generate a second radio frequency (RF) signal according to configuration parameters. This includes: generating a second single-tone signal using the automated test bench; configuring the FPGA-embedded RF unit according to the configuration parameters using the automated test bench; and outputting the second RF signal corresponding to the configuration parameters from the FPGA-embedded RF unit based on the second single-tone signal. For example, the automated test bench configures the FPGA using SMAP (Service Management Access Point); after successful configuration of the FPGA code stream, the FPGA-embedded processor starts and automatically configures the FPGA-embedded RF unit, enabling the FPGA-embedded RF unit to operate in a preset working state.
[0129] In some specific implementations, establishing a second radio frequency (RF) channel for the FPGA-embedded RF unit to receive a second RF signal includes: connecting a signal generator and a spectrum analyzer to an automated test bench via a GPIB (General-Purpose Interface Bus) interface; connecting one RF receiver pin of the FPGA-embedded RF unit to the signal generator; and connecting one RF transmitter pin of the FPGA-embedded RF unit to the spectrum analyzer, thus obtaining a second RF channel for the FPGA-embedded RF unit to receive the second RF signal. For example, using an SMA cable, the RF receiver pin RX2 of the FPGA-embedded RF unit is externally connected to a signal generator, and the RF transmitter pin TX2 of the FPGA-embedded RF unit is externally connected to a spectrum analyzer. The signal generator and spectrum analyzer are connected to the automated test bench via a GPIB interface.
[0130] The general interconnect bus, GPIO, and GPIB mentioned above are different. The general interconnect bus is used for internal signal interconnection in FPGA, GPIO is a general I / O interface, and GPIB is an interface for an ATE (Automatic Test Equipment) machine. GPIB controls the signal source to generate the required input signals and external reference clock.
[0131] In some specific implementations, the second radio frequency (RF) signal received by the second RF channel is detected to obtain second detection data. This includes: an automated test instrument acquiring the received RF signal via a GPIB interface and calculating the signal strength and signal-to-noise ratio (SNR) of the received RF signal; the automated test instrument reading from a spectrum analyzer via the GPIB interface to obtain the transmit power of the RF signal; and determining the second detection data based on the transmit power and the signal strength and SNR of the received RF signal. For example, the automated test instrument captures digital interface data and calculates the signal strength and received SNR of the received RF signal; the automated test instrument reading from the spectrum analyzer via GPIB to obtain the transmit power of the RF signal. The second detection data, including the transmit power, signal strength, and SNR of the received RF signal, is transmitted to the FPGA embedded processor. Using the standard values in the electrical parameter table as standard values, the FPGA embedded processor compares the second detection data with the standard values to obtain the test results of the second RF channel, thereby determining the function and performance of the second RF channel. When both the test results of the second RF channel and the test results of the first RF channel pass, that is, when both the test results of the single-tone signal inside the FPGA and the test results of the single-tone signal outside the FPGA pass, the FPGA embedded RF unit test is deemed to have passed.
[0132] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.
Claims
1. A test method for FPGA embedded RF units based on a universal interconnect bus, characterized in that: include: Step 1: Configure the FPGA embedded RF unit according to the configuration parameters and transmit / receive duplex mode using the FPGA embedded processor; Step 2: Based on the programmable logic resources inside the FPGA, generate the first radio frequency signal corresponding to the configuration parameters in the radio frequency unit embedded in the FPGA; Step 3: Establish the first radio frequency channel for receiving the first radio frequency signal using the FPGA embedded radio frequency unit; The first radio frequency signal received by the first radio frequency channel is detected to obtain the first detection data; Step 4: Use the FPGA on-chip memory to cache the configuration parameters, the first radio frequency signal, and the first detection data; Step 5: Use the FPGA embedded processor to compare the first detection data with the specification value to obtain the test results of the first RF channel; Step 6: Use an automated testing machine to generate a second radio frequency signal according to the configuration parameters; Step 7: Establish a second radio frequency channel for receiving the second radio frequency signal using the FPGA embedded radio frequency unit; Step 8: Detect the second radio frequency signal received by the second radio frequency channel to obtain the second detection data; Step 9: Using the FPGA embedded processor, compare the second detection data with the standard value according to the method in Step 5 to obtain the test results of the second RF channel. Step 10: Repeat steps 6 to 9 to obtain the test results of the remaining RF channels of the FPGA embedded RF unit; and determine whether the FPGA embedded RF unit test passed or failed.
2. The FPGA embedded RF unit testing method based on a universal interconnect bus according to claim 1, characterized in that: In step one, the specific method for configuring the FPGA embedded RF unit according to the configuration parameters and transmit / receive duplex mode by the FPGA embedded processor is as follows: Based on the configuration parameters, the FPGA embedded processor is used to write the initial value of the FPGA embedded radio frequency unit configuration register. Configure the FPGA's embedded RF unit to transmit / receive full-duplex mode and determine its operating parameters.
3. The FPGA embedded RF unit testing method based on a universal interconnect bus according to claim 1, characterized in that: In step two, the specific method for generating the first radio frequency signal corresponding to the configuration parameters in the FPGA embedded radio frequency unit is as follows: Using the programmable logic resources inside the FPGA, a first single-tone signal is generated through direct digital frequency synthesis; based on the first single-tone signal, the phase word and frequency word corresponding to the configuration parameters are configured in the RF unit embedded in the FPGA, and the first RF signal corresponding to the configuration parameters is output.
4. The FPGA embedded RF unit testing method based on a universal interconnect bus according to claim 1, characterized in that: In step three, the method for establishing the first radio frequency channel for receiving the first radio frequency signal using the FPGA embedded radio frequency unit is as follows: By connecting one RF transmit pin of the FPGA embedded RF unit to multiple RF receive pins of the FPGA embedded RF unit through a power divider, multiple first RF channels for the FPGA embedded RF unit to receive the first RF signal are obtained.
5. The FPGA embedded RF unit testing method based on a universal interconnect bus according to claim 4, characterized in that: The method for obtaining the first detection data is as follows: The first radio frequency signal received by the first radio frequency channel is buffered across clock domains using the FPGA on-chip memory; the buffered first radio frequency signal is converted from parallel to serial according to the corresponding radio frequency channel to obtain the converted signal; the converted signal is then subjected to a fast Fourier transform to obtain the transformed signal; the signal strength and signal-to-noise ratio of the received first radio frequency signal are determined based on the transformed signal; and the first detection data is determined based on the first radio frequency signal transmission power and the signal strength and signal-to-noise ratio of the received first radio frequency signal.
6. The FPGA embedded RF unit testing method based on a universal interconnect bus according to claim 5, characterized in that: In step five, the method for obtaining the test results of the first radio frequency channel is as follows: Using the FPGA embedded processor, the signal strength, signal-to-noise ratio and transmitted signal power of the first radio frequency signal received by the first radio frequency channel are compared with the corresponding standard values in the electrical parameter table. When the difference between the signal strength, signal-to-noise ratio, and transmitted signal power and the corresponding standard values does not exceed the preset value, the first radio frequency channel is judged to be working normally; when any of the differences exceeds the preset value, the first radio frequency channel is judged to be working abnormally.
7. The FPGA embedded RF unit testing method based on a universal interconnect bus according to claim 1, characterized in that: In step six, the method for generating the second radio frequency signal is as follows: A second monotone signal is generated using an automated testing machine; Configure the FPGA embedded RF unit using an automated test bench according to the configuration parameters described above; Based on the second single-tone signal, the second radio frequency signal corresponding to the configuration parameters is output by the radio frequency unit embedded in the FPGA.
8. The FPGA embedded RF unit testing method based on a universal interconnect bus according to claim 1, characterized in that: In step seven, the method for establishing the second radio frequency channel is as follows: Connect the signal generator and spectrum analyzer to the automatic test bench via the GPIB interface; connect one RF receiving pin of the FPGA embedded RF unit to the signal generator; connect one RF transmitting pin of the FPGA embedded RF unit to the spectrum analyzer to obtain the second RF channel for the FPGA embedded RF unit to receive the second RF signal.
9. The FPGA embedded RF unit testing method based on a universal interconnect bus according to claim 1, characterized in that: In step eight, the method for detecting the second radio frequency signal to obtain the second detection data is as follows: The automatic test equipment acquires the received second radio frequency signal through the GPIB interface and calculates the signal strength and signal-to-noise ratio of the received second radio frequency signal; the automatic test equipment reads the spectrum analyzer through the GPIB interface to acquire the transmission power of the second radio frequency signal; and determines the second test data based on the transmission power of the second radio frequency signal and the signal strength and signal-to-noise ratio of the received second radio frequency signal.
10. The FPGA embedded RF unit testing method based on a universal interconnect bus according to claim 1, characterized in that: In step ten, the method for determining the test status of the FPGA embedded RF unit is as follows: If all RF channels of the FPGA embedded RF unit test results are normal, the FPGA embedded RF unit test is considered passed; otherwise, the FPGA embedded RF unit test is considered failed.