Memory system and method for setting failure flag in failed memory unit
By detecting and marking faulty memory units in the memory system and using an erasure coding algorithm to recover data, the problem of ineffective management and recovery of faulty memory units in the prior art is solved, achieving cost reduction and improved recovery efficiency.
Patent Information
- Application Number
- CN202411770040.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-05-02
- Filing Date
- 2024-12-04
- Publication Date
- 2025-11-04
AI Technical Summary
In volatile memory, existing technologies struggle to effectively manage and recover faulty memory units that cannot be corrected by ECC, resulting in high management costs and low recovery efficiency.
By detecting faulty memory units in the memory system and setting fault flags, and by sending fault flag setting commands through the controller, the resource requirements for managing faulty memory units are reduced, and an erasure coding algorithm is used to recover uncorrectable faulty data.
It reduces the cost of managing faulty memory units, improves the efficiency of faulty data recovery, reduces redundant testing and error correction operations, and enables rapid recovery.
Smart Images
Figure CN120895081A_ABST
Abstract
Description
[0001] Cross-references to related applications
[0002] This application claims priority to Korean Patent Application No. 10-2024-0058446, filed with the Korean Intellectual Property Office on May 2, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field
[0003] Embodiments of this disclosure relate to a memory system and a method of operating which sets a fault flag in a fault memory unit. Background Technology
[0004] In volatile memory (e.g., SRAM or DRAM), the stored data is lost when the power supply is cut off, while in non-volatile memory (e.g., NAND flash, PRAM or MRAM), the stored data is retained even when the power supply is cut off.
[0005] During the manufacturing process or when using volatile memory, faults may occur in areas of the volatile memory. When it is determined that a fault in the data stored in the corresponding area cannot be corrected using existing ECC (Error Correction Code), different algorithms are required to recover the data stored in the corresponding area of the volatile memory. Summary of the Invention
[0006] Various embodiments of this disclosure are intended to provide a memory system and related methods that can reduce the cost required to manage information at the location of a failure and recover from failures that cannot be corrected by ECC.
[0007] In one aspect, a memory system may include: i) a memory medium including a plurality of memory chips, each of the plurality of memory chips including a plurality of memory units, and each of the plurality of memory units including a plurality of memory cells; and ii) a controller configured to detect a faulty memory unit from among the plurality of memory units included in the memory medium and send a fault flag setting command to the memory medium for setting a fault flag for the faulty memory unit.
[0008] In another aspect, a method for operating a memory system may include: i) detecting a faulty memory unit in a memory medium, the memory medium including a plurality of memory chips, each of the plurality of memory chips including a plurality of memory units, and each of the plurality of memory units including a plurality of memory cells; ii) sending a fault flag setting command to the memory medium for setting a fault flag for the faulty memory unit; and iii) setting a fault flag in the memory medium in response to the fault flag setting command.
[0009] According to embodiments of the present disclosure, it is possible to reduce the cost required to manage information on a location where a failure occurs and quickly recover a failure that cannot be corrected by ECC. BRIEF DESCRIPTION OF DRAWINGS
[0010] Figure 1 is a diagram illustrating a structure of a memory system according to an embodiment of the present disclosure.
[0011] Figure 2 is a diagram illustrating an operation of a memory system according to an embodiment of the present disclosure.
[0012] Figure 3 is a diagram illustrating an operation of a memory system determining whether a specific memory unit is a failed memory unit according to an embodiment of the present disclosure.
[0013] Figure 4 is a diagram illustrating an operation of a memory system setting a failure flag in a failed memory unit according to an embodiment of the present disclosure.
[0014] Figure 5 is a diagram illustrating an operation of a memory system reading N data units from N memory units according to an embodiment of the present disclosure.
[0015] Figure 6 is a diagram illustrating an operation of a memory system reading a failed memory unit according to an embodiment of the present disclosure.
[0016] Figure 7 is a diagram illustrating an operation of a memory system recovering a data unit according to an embodiment of the present disclosure.
[0017] Figure 8 is a diagram illustrating a method of operating a memory system according to an embodiment of the present disclosure. DETAILED DESCRIPTION
[0018] Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. Throughout the specification, reference to "an embodiment" or "another embodiment" or "one embodiment" does not necessarily refer to the same embodiment, and different embodiments are not necessarily limited by the same embodiments. As used herein, the term "embodiment" does not necessarily refer to all embodiments.
[0019] Various embodiments of the present disclosure are described in greater detail below, with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, the described embodiments are provided as exemplary of the present disclosure so that it will be thorough and complete, and fully convey the scope of the present disclosure to not only those skilled in the art, but also to others skilled in this technical field. Throughout the disclosure, like reference numerals refer to like parts throughout the various drawings and embodiments of the present disclosure.
[0020] The methods, processes and / or operations described herein can be executed by code or instructions to be run using a computer, a processor, a controller or other signal processing apparatus. The computer, processor, controller or other signal processing apparatus can be the computer, processor, controller or other signal processing apparatus described herein or one in addition to the elements described herein. Because the detailed description forms the basis of the algorithms that form the methods (or the operations of the computer, processor, controller or other signal processing apparatus), the code or instructions for implementing the operations of the method embodiments can transform the computer, processor, controller or other signal processing apparatus into a special purpose processor for performing the methods herein.
[0021] When implemented at least partly in software, the controllers, processors, apparatuses, modules, units, multiplexers, logic, interfaces, decoders, drivers, generators and other signal generation and signal processing features can include, among other things, a memory or other storage for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller or other signal processing apparatus.
[0022] Figure 1 is a diagram illustrating a structure of a memory system according to an embodiment of the present disclosure.
[0023] Referring to Figure 1 The memory system 100 can include a memory medium 110 and a controller 120.
[0024] The memory medium 110 can include a plurality of memory chips MC. Each of the plurality of memory chips MC can include a plurality of memory units MU. Each of the memory units MU can include a plurality of memory cells CELL.
[0025] The memory medium 110 can control the plurality of memory chips MC in parallel. That is, the memory medium 110 can perform a read operation or a write operation on the plurality of memory chips MC in parallel.
[0026] The memory medium 110 can be implemented in various ways.
[0027] For example, the memory medium 110 can be configured as a dynamic random access memory medium. The memory medium 110 can perform a periodic refresh operation to maintain stored data. When power supplied to the memory medium 110 is cut off, data stored in the memory medium 110 can be lost.
[0028] Each of the plurality of memory units MU included in each of the memory chips MC can be a bank, a matrix, or a word line.
[0029] In another example, the memory medium 110 can be implemented by a non-volatile memory medium (e.g., NAND flash or NOR flash). Each of the memory units MU included in the memory medium 110 can be a die, a plane, or a memory block.
[0030] The controller 120 can control the memory medium 110. To control the memory medium 110, the controller 120 can transmit a command to the memory medium 110 and receive a response to the command from the memory medium 110. This will be described in detail with reference to Figure 2 .
[0031] The controller 120 can also be implemented in various ways.
[0032] For example, the controller 120 can be implemented by an integrated circuit including logic gates for running the above-described operations. The controller 120 can be implemented by an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).
[0033] In another example, the controller 120 can include a processor that performs calculations to control operations of processing a plurality of operation requests, and a working memory that can store data required for processing a plurality of operation requests.
[0034] The processor can control operations of the controller 120 by running firmware. The processor can drive the firmware to control overall operations of the controller 120 and perform logical calculations. The firmware is a program that is run in the controller 120 to drive the controller 120, and the firmware can include binary data that defines code for running the above-described overall operations and logical calculations.
[0035] The firmware can be stored in a storage space (e.g., a working memory, a ROM, a flash memory) located inside or outside the controller 120. The processor can load all or part of the firmware stored in the storage space.
[0036] The working memory can store data (e.g., a plurality of operation requests or firmware) required for the controller 120 to process operation requests. For example, the working memory can include a separate memory medium (e.g., an SRAM) to store data.
[0037] Figure 2 is a diagram illustrating an operation of a memory system according to an embodiment of the present disclosure.
[0038] Referring to Figure 2 , the controller 120 of the memory system 100 can detect a failed memory unit FAIL_MU from among a plurality of memory units MU included in the memory medium 110.
[0039] The failed memory unit FAIL_MU can be a memory unit in which an uncorrectable error can occur in a process of reading or writing data.
[0040] Specifically, the failed memory unit FAIL_MU can be determined as a memory unit having a lower reliability compared to other memory units. When the controller 120 determines that data stored in a memory unit MU among the plurality of memory units MU cannot be recovered using an error correction circuit, the memory unit MU is the failed memory unit FAIL_MU. The controller 120 can classify the memory units MU included in the memory medium 110 into a failed memory unit and a normal memory unit, i.e., a non-failed memory unit.
[0041] The controller 120 can detect the failed memory unit FAIL_MU using error information that occurs in a process of performing an operation (e.g., a read operation or a write operation) on the memory units MU included in the memory medium 110. This will be described in detail below with reference to Figure 3 .
[0042] The controller 120 can transmit a failure flag setting command FLG_CMD to the memory medium 110, the failure flag setting command FLG_CMD instructing the memory medium 110 to set a failure flag with respect to the detected failed memory unit FAIL_MU. The failure flag setting command FLG_CMD can include information (e.g., an address or an index of the failed memory unit FAIL_MU) for identifying the failed memory unit FAIL_MU.
[0043] By transmitting the failure flag setting command FLG_CMD to the memory medium 110, the controller 120 can control the memory medium 110 to store information about a location of the failed memory unit FAIL_MU.
[0044] Accordingly, the controller 120 can reduce a cost associated with resources (e.g., SRAM or latches) required to directly manage information of the failed memory unit FAIL_MU.
[0045] Since the location of the failed memory unit FAIL_MU can be designated in the storage medium 110, the controller 120 does not need to repeatedly perform an operation of detecting a memory unit that has failed.
[0046] Figure 3 FIG. 2 is a diagram illustrating an operation of a memory system determining whether a specific memory unit is a failed memory unit according to an embodiment of the disclosure.
[0047] Referring to Figure 3 The controller 120 of the memory system 100 can count the number of memory cells that have failed in a specific memory unit (S310). For example, the controller 120 can count the number of memory cells that have failed during a read operation or a write operation of the memory unit for a predetermined period of time.
[0048] The controller 120 determines whether the number of memory cells that have failed in the memory unit is equal to or greater than a threshold value (S320).
[0049] When the number of memory cells that have failed in the memory unit is equal to or greater than the threshold value (S320-Yes), the controller 120 can determine that the corresponding memory unit is a failed memory unit FAIL_MU (S330).
[0050] On the other hand, when the number of memory cells that have failed in the corresponding memory unit is less than the threshold value (S320-No), the controller 120 can determine that the corresponding memory unit is not a failed memory unit FAIL_MU (S340).
[0051] Figure 4 FIG. 4 is a diagram illustrating an operation of a memory system setting a failure flag in a failed memory unit according to an embodiment of the disclosure.
[0052] Referring to Figure 4 The storage medium 110 of the memory system 100 can receive a failure flag setting command FLG_CMD from the controller 120, and in response to the failure flag setting command FLG_CMD, can set a failure flag for at least one of the memory cells CELL in the failed memory unit FAIL_MU.
[0053] The location of the memory cell CELL having the failure flag within the failed memory unit FAIL_MU can be determined in various ways.
[0054] For example, the memory cell CELL having the failure flag can be located at a preset address among the memory cells CELL included in the failed memory unit FAIL_MU.
[0055] In another example, the memory unit CELL having the failure flag can be included in a reserved area in which data requested to be written by the controller 120 is not stored.
[0056] In the above example, the operation in which the memory system 100 detects the failed memory unit FAIL_MU and sets the failure flag for the detected failed memory unit FAIL_MU has been described.
[0057] Hereinafter, the operation in which the memory system 100 reads data stored in the failed memory unit FAIL_MU having the set failure flag will be described.
[0058] Figure 5 FIG. 1 is a diagram illustrating an operation in which a memory system reads N data units from N memory units according to an embodiment of the disclosure.
[0059] Referring to Figure 5 , the controller 120 of the memory system 100 can read N data units DU from N (where N is a natural number of 2 or more) memory units MU among a plurality of memory units MU included in the memory medium 110. Each of the N memory units MU can store one of the N data units DU.
[0060] The N memory units MU can be included in different memory chips MC. The controller 120 can read the N data units DU from the N memory units MU in parallel.
[0061] In Figure 5 , one of the N memory units MU can be a failed memory unit FAIL_MU. That is, the controller 120 can read data units DU stored in N-1 normal memory units MU and the failed memory unit FAIL_MU.
[0062] Figure 6 FIG. 2 is a diagram illustrating an operation in which a memory system reads a failed memory unit according to an embodiment of the disclosure.
[0063] Referring to Figure 6 , the controller 120 of the memory system 100 can transmit a read request including a failed memory unit FAIL_MU to the memory medium 110. However, the controller 120 does not know whether the target of the read request is a memory unit MU having the failed memory unit FAIL_MU.
[0064] However, the memory medium 110 can check whether the controller 120 has transmitted a read request for the failed memory unit FAIL_MU using the failure flag set for the failed memory unit FAIL_MU.
[0065] In response to the read request for the failed memory unit FAIL_MU, the memory media 110 can transmit the preset pattern data PAT_DATA.
[0066] In other words, the memory media 110 transmits the preset pattern data PAT_DATA to the controller 120 instead of transmitting data actually stored in the failed memory unit FAIL_MU, thereby indicating the controller 120 that the memory unit MU to which the read request of the controller 120 is directed is the failed memory unit FAIL_MU.
[0067] The pattern data PAT_DATA can be determined in various ways.
[0068] For example, all bits of the pattern data PAT_DATA can be 0.
[0069] In another example, all bits of the pattern data PAT_DATA can be 1.
[0070] In yet another example, the pattern data PAT_DATA can be an ID value preset for the memory media 110.
[0071] In an embodiment of the disclosure, when the controller 120 of the memory system 100 reads N data units DU from N memory units MU, and one of the N memory units MU is a failed memory unit FAIL_MU, one of the N data units DU can include the pattern data PAT_DATA.
[0072] The pattern data PAT_DATA is data generated by the memory media 110, not data stored in the memory unit MU that is to be responded to a read request. Therefore, the controller 120 needs to recover the data unit DU including the pattern data PAT_DATA in order to generate data in the failed memory unit actually stored in the memory media 110.
[0073] The controller 120 can detect a first data unit DU_1 having the pattern data PAT_DATA from among the N data units DU, and can perform a recovery operation on the first data unit DU_1. This will be described in detail below with reference to Figure 7 FIG. 1.
[0074] Figure 7 is a diagram illustrating an operation of a memory system to recover a data unit according to an embodiment of the disclosure.
[0075] Referring to Figure 7The controller 120 of the memory system 100 can restore the first data unit DU_1 including the pattern data PAT_DATA among the N data units DU using the remaining data units except for the first data unit DU_1. As described above with reference to Figure 5 The N data units DU respectively correspond to the N memory units MU. Among the N data units DU, the first data unit DU_1 corresponds to the failed memory unit FAIL_MU.
[0076] The controller 120 can check the pattern data PAT_DATA included in the first data unit DU_1 to confirm that the first data unit DU_1 is the data unit DU that has failed among the N data units DU.
[0077] Accordingly, the controller 120 does not need to separately track and manage the data unit DU that has failed. In addition, it is not necessary to repeatedly perform an error correction operation on all of the N data units DU to detect the data unit DU having a failure. Accordingly, the controller 120 can restore the data unit DU that has failed more quickly.
[0078] The controller 120 can restore the first data unit DU_1 using various algorithms.
[0079] For example, the controller 120 can restore the first data unit DU_1 using an erasure coding algorithm.
[0080] Erasure coding is a data restoration technique that restores data through a decoding process using a remaining portion of data in which no failure has occurred when a portion of data encoded using an encoding matrix called an erasure code has failed.
[0081] Erasure coding can use a data region and a parity region that are set to be suitable for a user environment, and thus the reliability of data and an overhead caused during a restoration process can vary depending on the size of the data region and the parity region.
[0082] Figure 8 is a diagram illustrating a method of operating a memory system according to an embodiment of the disclosure.
[0083] Referring to Figure 8 A method of operating a memory system 100 can include a step S810 of detecting a failed memory unit FAIL_MU in a memory medium 110. The memory medium 110 can include a plurality of memory chips MC. Each of the plurality of memory chips MC can include a plurality of memory units MU. Each of the plurality of memory units MU can include a plurality of memory cells CELL.
[0084] For example, in step S810, among the plurality of memory units MU included in the memory medium 110, the memory unit MU in which the number of failed memory cells is equal to or greater than the threshold value can be determined as the failed memory unit FAIL_MU.
[0085] The method of operating the memory system 100 can include a step S820 of transmitting a failure flag setting command FLG_CMD to the memory medium 110, the failure flag setting command FLG_CMD instructing to set a failure flag for the failed memory unit FAIL_MU.
[0086] The method of operating the memory system 100 can include a step S830 of setting the failure flag in the memory medium 110 in response to the failure flag setting command FLG_CMD.
[0087] For example, in step S830, the failure flag can be set for at least one of the plurality of memory cells CELL included in the failed memory unit FAIL_MU.
[0088] The method of operating the memory system 100 can further include reading N data units DU from N (where N is a natural number of 2 or more) memory units MU among the plurality of memory units MU included in the memory medium 110. One of the N memory units MU can be the failed memory unit FAIL_MU.
[0089] The data unit read from the failed memory unit FAIL_MU can include preset pattern data PAT_DATA. For example, all bits of the preset pattern data PAT_DATA can be 0.
[0090] The method of operating the memory system 100 can further include a step of recovering a first data unit DU_1 including the pattern data PAT_DATA among the N data units DU.
[0091] For example, the step of recovering the first data unit DU_1 can recover the first data unit DU_1 using an erasure coding algorithm.
[0092] Although the exemplary embodiments of the present disclosure are described for illustrative purposes, those skilled in the art will understand that various modifications, additions and substitutions are possible without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed above and in the drawings should be considered to be merely descriptive, not limiting the technical scope. The technical scope of the present disclosure is not limited by the embodiments and drawings. The idea and scope of the present disclosure should be interpreted in conjunction with the claims, and encompass all equivalents falling within the scope of the claims.
Claims
1. A memory system, comprising: A memory medium includes a plurality of memory chips, each of the plurality of memory chips including a plurality of memory units, and each of the plurality of memory units including a plurality of memory cells; as well as The controller detects a faulty memory unit from among the plurality of memory units included in the memory medium and sends a fault flag setting command to the memory medium, the fault flag setting command being used to set a fault flag for the faulty memory unit.
2. The memory system according to claim 1, wherein, The controller identifies the memory units in the memory medium whose number of faulty memory units is equal to or greater than a threshold as the faulty memory units.
3. The memory system according to claim 1, wherein, The memory medium receives the fault flag setting command and sets the fault flag for at least one of the plurality of memory cells included in the fault memory unit.
4. The memory system according to claim 1, wherein, The controller reads N data units from N memory units among the plurality of memory units included in the memory medium. One of the N memory units is the faulty memory unit, and N is a natural number of 2 or greater.
5. The memory system according to claim 4, wherein, In response to a read request for the faulty memory unit, the memory medium sends preset mode data to the controller.
6. The memory system according to claim 5, wherein, All bits of the preset mode data are 0.
7. The memory system according to claim 5, wherein, The controller uses the remaining data units among the N data units, excluding the data units of the fault memory unit, to recover the data of the fault memory unit, including the preset pattern data.
8. The memory system according to claim 7, wherein, The controller uses an erasure coding algorithm to recover the data from the faulty memory unit.
9. A method for operating a memory system, comprising: Detecting faulty memory units in a memory medium, the memory medium comprising a plurality of memory chips, each of the plurality of memory chips comprising a plurality of memory units, and each of the plurality of memory units comprising a plurality of memory cells; Send a fault flag setting command to the memory medium, the fault flag setting command being used to set a fault flag for the faulty memory unit; as well as In response to the fault flag setting command, the fault flag is set in the memory medium.
10. The method according to claim 9, wherein, Detecting the faulty memory unit further includes: identifying the memory unit among the plurality of memory units included in the memory medium whose number of faulty memory cells is equal to or greater than a threshold as the faulty memory unit.
11. The method according to claim 9, wherein, Setting the fault flag further includes setting the fault flag for at least one of the plurality of memory cells included in the fault memory unit.
12. The method of claim 9, further comprising: N data units are read from N memory units among the plurality of memory units included in the memory medium. Among them, one of the N memory units is the faulty memory unit, and N is a natural number of 2 or greater.
13. The method according to claim 12, wherein, Data is read from the fault memory unit and a preset pattern data is returned.
14. The method according to claim 13, wherein, All bits of the preset mode data are 0.
15. The method of claim 14, further comprising: Recover the data of the faulty memory unit, including the preset pattern data.
16. The method of claim 14, wherein, The data in the faulty memory unit is recovered using an erasure coding algorithm.