Semiconductor element and forming method thereof

Abstract

A method of forming a semiconductor device includes forming a dielectric layer over a substrate; forming a conductive layer over the dielectric layer; forming a photoresist layer over the conductive layer, the photoresist layer comprising a magnetic material; performing an exposure process on the photoresist layer to form an exposed region and an unexposed region in the photoresist layer; applying a directional magnetic field to the photoresist layer; performing a post-exposure baking process on the photoresist layer; performing a developing process to remove a portion of the photoresist layer; and transferring the pattern of the remaining portion of the photoresist layer to the conductive layer and the dielectric layer. According to the method, a poorer outline appearing on the photoresist layer due to inaccurate control in a photoetching process can be repaired.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device and a method of forming the same. BACKGROUND

[0002] Inaccuracies in lithography processes can result in a photoresist layer used for patterning having a poor profile, leading to unacceptable variations in line / space. As semiconductor manufacturing processes continue to advance, the negative impact of line / space variations on subsequent processes, measurements, and even yield becomes more and more significant. SUMMARY

[0003] One aspect of the present disclosure provides a method of forming a semiconductor device, comprising forming a dielectric layer over a substrate; forming a conductive layer over the dielectric layer; forming a photoresist layer over the conductive layer, wherein the photoresist layer comprises a magnetic material; performing an exposure process on the photoresist layer to form exposed regions and unexposed regions in the photoresist layer; applying a directional magnetic field to the photoresist layer; performing a post-exposure bake process on the photoresist layer; performing a development process to remove portions of the photoresist layer; and transferring a pattern of the remaining portions of the photoresist layer to the conductive layer and the dielectric layer.

[0004] In some embodiments, the method further comprises forming a source region and a drain region in the substrate after the transferring of the pattern of the remaining portions of the photoresist layer to the conductive layer and the dielectric layer.

[0005] In some embodiments, the method further comprises forming a word line electrically coupled to the conductive layer; forming a bit line electrically coupled to the source region; and forming a capacitor electrically coupled to the drain region.

[0006] In some embodiments, the photoresist layer comprises a positive photoresist material or a negative photoresist material.

[0007] In some embodiments, the applying of the directional magnetic field to the photoresist layer is performed during the exposure process.

[0008] In some embodiments, the method further comprises applying another directional magnetic field to the photoresist layer during the post-exposure bake process.

[0009] In some embodiments, the applying of the directional magnetic field to the photoresist layer is performed during the post-exposure bake process.

[0010] In some embodiments, the directional magnetic field is applied to the photoresist layer along a vertical direction.

[0011] In some embodiments, the directional magnetic field is applied to the photoresist layer along a horizontal direction.

[0012] In some embodiments, the magnetic material comprises iron (Fe), cobalt (Co), or nickel (Ni).

[0013] In some embodiments, the magnetic material in the photoresist layer diffuses downwards to the top portion of the conductive layer during the post-exposure baking process.

[0014] In some embodiments, the concentration of magnetic material decreases downwards from the top portion of the conductive layer.

[0015] In some embodiments, after the post-exposure baking process is completed, the bottom portion of the conductive layer has no magnetic material.

[0016] In some embodiments, the conductive layer is made of polycrystalline silicon.

[0017] One aspect of the present invention provides a semiconductor device comprising: a substrate; and a transistor located above the substrate, comprising: a source region and a drain region located in the substrate; and a gate structure located above the substrate, having a dielectric layer and a conductive layer located above the dielectric layer, wherein the top portion of the conductive layer comprises a magnetic material.

[0018] In some embodiments, the semiconductor element further includes: word lines electrically coupled to a gate structure; bit lines electrically coupled to a source region; and capacitors electrically coupled to a drain region.

[0019] In some embodiments, the magnetic material comprises iron (Fe), cobalt (Co), or nickel (Ni).

[0020] In some embodiments, the concentration of magnetic material decreases downwards from the top portion of the conductive layer.

[0021] In some embodiments, the bottom portion of the conductive layer does not contain magnetic material.

[0022] In some embodiments, the top portion of the conductive layer is thinner than the bottom portion of the conductive layer.

[0023] It should be understood that the foregoing general description and the following detailed description are by way of example and are intended to provide a further explanation of the claims made in this invention. Attached Figure Description

[0024] The scope of the invention is best understood by reading the accompanying drawings and the following detailed description. Note that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0025] Figures 1 to 7 Cross-sectional views of various stages in forming a semiconductor element according to certain embodiments of the present invention are shown.

[0026] Figures 8 to 12 Cross-sectional views of various stages in forming a semiconductor element according to certain embodiments of the present invention are shown.

[0027] Figure 13 This is a circuit diagram of a memory cell of a memory according to some embodiments of the present invention.

[0028] Figures 14 to 18 These are cross-sectional views of various stages in forming a memory cell according to some embodiments of the present invention. Detailed Implementation

[0029] Reference will now be made in detail to embodiments of the invention, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar components.

[0030] As used herein, “approximately,” “about,” or “substantially” generally means within 20%, 10%, or 5% of a given value or range. The values ​​given herein are approximate and the terms “approximately,” “about,” or “substantially” can be inferred unless explicitly stated otherwise. However, those skilled in the art will recognize that the values ​​or ranges listed throughout the description are merely examples and can be reduced or changed as integrated circuits shrink.

[0031] Figures 1 to 7 Cross-sectional views of various stages in forming a semiconductor device according to certain embodiments of the present invention are shown. Figure 1 The image shows a semiconductor element 100. In some embodiments, the semiconductor element 100 may include a dielectric layer 110, a conductive layer 120 above the dielectric layer 110, a hard mask 130 above the conductive layer 120, and a photoresist layer 140 above the hard mask 130. In some embodiments, the dielectric layer 110 may include a suitable dielectric material, such as silicon oxide, silicon nitride, etc. In some embodiments, the conductive layer 120 may be formed of a conductive material such as polycrystalline silicon, polycrystalline silicon germanium, metal nitride, metal silicide, metal oxide, metal, or a combination thereof. In some embodiments, the photoresist layer 140 may include a photoresist material. Photoresist material is a photosensitive compound widely used in the manufacture of semiconductors. Typically, photoresist materials are made of organic polymers and / or photosensitive compounds and can be divided into two categories: positive photoresist and negative photoresist, each type reacting differently to light. Positive photoresist becomes soluble when exposed to a light source (e.g., ultraviolet light). On the other hand, the solubility of negative photoresist decreases when exposed to light. In some embodiments, the photoresist layer 140 also includes a magnetic material. In some embodiments, the magnetic material may include iron (Fe), cobalt (Co), nickel (Ni), or other suitable magnetic materials. In some embodiments, the photoresist layer 140 may be formed, for example, by dispersing magnetic metal powder comprising the magnetic material during the deposition of the photoresist layer 140. In some embodiments, the photoresist layer 140 may be formed, for example, by doping the photoresist layer 140 with magnetic material during the deposition of the photoresist layer 140.

[0032] Reference is made to Figure 2 exposure process is performed to pattern the photoresist layer 140 according to a predetermined pattern. As a result, the exposed photoresist layer 140 includes exposed regions 140A and unexposed regions 140B. As mentioned above, the photoresist layer 140 can include a positive photoresist material or a negative photoresist material. Here, the example of a negative photoresist material is discussed as the photoresist layer 140. However, it should be understood that in other embodiments, the photoresist layer 140 can also be a positive photoresist material. Thus, in embodiments where the photoresist layer 140 is a negative photoresist material, the exposed regions 140A exposed to light become insoluble in a developer solution (e.g., an organic solution), while the unexposed regions 140B become soluble in the developer solution. In other words, as a result of the exposure process, the exposed regions 140A become harder than the unexposed regions 140B.

[0033] Figure 3 An enlarged view portion of the example semiconductor element 100 shown in Figure 2 In some embodiments, due to physical limitations of the exposure process, the exposed regions 140A and the unexposed regions 140B can include a rough interface. More specifically, one or more gaps GP can exist between the exposed regions 140A and the unexposed regions 140B. The contrast between the exposed regions 140A and the unexposed regions 140B can result in undesirable photolithography performance.

[0034] To address the above-mentioned problems, embodiments of the present application provide a photoresist layer 140 including a magnetic material. In addition, a directed magnetic field can be applied to the photoresist layer 140 during the exposure process. When the photoresist layer 140 is a negative photoresist, the unexposed regions 140B can be softer than the exposed regions 140A, and the magnetic field can pull and fill the gaps GP between the exposed regions 140A and the unexposed regions 140B with the softer unexposed regions 140B. As the exposure process continues, the portion of the unexposed regions 140B that fills the gaps GP is subjected to the exposure process, and this portion becomes the exposed regions 140A. Based on the above discussion, applying a directed magnetic field to the photoresist layer 140 including a magnetic material can result in a smoother profile of the exposed regions 140A of the photoresist layer 140.

[0035] In some embodiments, the directed magnetic field can be applied to the photoresist layer 140 throughout the exposure process. In other embodiments, the directed magnetic field can be applied to the photoresist layer 140 after a period of time of the exposure process. That is, the exposure process can include a first phase and a second phase after the first phase, where the second phase of the exposure process is performed with the directed magnetic field, and the first phase of the exposure process is performed without the directed magnetic field. Thus, during the first phase, the photoresist layer 140 can undergo the exposure process to produce the exposed regions 140A and the unexposed regions 140B. During the second phase, the directed magnetic field can be applied to the photoresist layer 140 to fill the gaps GP between the exposed regions 140A and the unexposed regions 140B with the softer unexposed regions 140B. Figure 3The second stage of the directional magnetic field starts to repair the rough profile of the exposed region 140A of the photoresist layer 140.

[0036] Once the exposure process is completed, a post-exposure bake process can be performed to cure the exposed region 140A of the photoresist layer 140. In some embodiments, another directional magnetic field can be applied to the photoresist layer 140 during the post-exposure bake process, which is also beneficial to repair the rough profile of the exposed region 140A of the photoresist layer 140.

[0037] In some embodiments, a directional magnetic field can be applied during the post-exposure bake process, while the application of the directional magnetic field can be omitted during the exposure process. In other embodiments, a directional magnetic field can be applied during the exposure process, while the application of the directional magnetic field can be omitted during the post-exposure bake process.

[0038] In some embodiments, the directional magnetic field can be applied to the photoresist layer 140 along a vertical direction. For example, the directional magnetic field can be applied to the photoresist layer 140 along a direction from top to bottom. In other embodiments, the directional magnetic field can be applied to the photoresist layer 140 along a horizontal direction. In such embodiments, the directional magnetic field can be applied along a first horizontal direction to repair one side of the exposed region 140A of the photoresist layer 140, and then the coating is performed along a second horizontal direction opposite to the first horizontal direction to repair the other side of the exposed region 140A of the photoresist layer 140.

[0039] Referring to Figure 4 , a development process is performed. As a result, the unexposed region 140B is dissolved in the developer, while the exposed region 140A remains on the hard mask 130.

[0040] In some embodiments, after the development process, a rinsing process is performed to remove any residues and / or particles on the semiconductor element 100. Next, a post-development bake (PDB) process is performed to ensure the structural stability of the exposed region 140A.

[0041] Referring to Figure 5 , the exposed region 140A of the photoresist layer 140 can be used as an etching mask to perform an etching process to remove part of the hard mask 130. The hard mask 130 can be etched by a suitable etching process (e.g., an anisotropic dry etching process). In some embodiments, the magnetic material in the photoresist layer 140 can increase the etch resistance of the photoresist layer 140, which is also beneficial to pattern the underlying hard mask 130.

[0042] Referring to Figure 6 , after the pattern of the exposed region 140A of the photoresist layer 140 is transferred to the hard mask 130, the exposed region 140A of the photoresist layer 140 can be removed.

[0043] Referring toFigure 7 The conductive layer 120 can be patterned using a patterned hard mask 130 as an etching mask. In some embodiments, the conductive layer 120 can be patterned using a suitable etching process, such as anisotropic dry etching or isotropic wet etching. After transferring the pattern of the remaining portion of the hard mask 130 (or photoresist layer 140) to the conductive layer 120, the hard mask 130 can be removed.

[0044] Figures 8 to 12 Cross-sectional views of various stages in forming a semiconductor device according to certain embodiments of the present invention are shown. Figure 8 The image shows a semiconductor element 200. In some embodiments, the semiconductor element 200 may include a dielectric layer 210, a conductive layer 220 above the dielectric layer 210, and a photoresist layer 230 above the conductive layer 220. In some embodiments, the dielectric layer 210 may include a suitable dielectric material, such as silicon oxide, silicon nitride, etc. In some embodiments, the conductive layer 220 may be formed of a conductive material such as polycrystalline silicon, polycrystalline silicon germanium, metal nitride, metal silicide, metal oxide, metal, or combinations thereof. In some embodiments, the material and fabrication method of the photoresist layer 230 are similar to those of the photoresist layer 140.

[0045] Please refer to Figure 9 An exposure process is performed to pattern the photoresist layer 230 according to a predetermined pattern. Therefore, the exposed photoresist layer 230 includes an exposed region 230A and an unexposed region 230B. As described above, the photoresist layer 230 may include a positive or negative photoresist material, similar to photoresist layer 140. Here, a negative photoresist material is discussed as an example of the photoresist layer 230. However, it should be understood that in other embodiments, the photoresist layer 230 may also be a positive photoresist material. Therefore, in embodiments where the photoresist layer 230 is a negative photoresist material, the exposed region 230A becomes insoluble in the developer (e.g., an organic solution), while the unexposed region 230B becomes soluble in the developer.

[0046] Figure 10 Some embodiments of the present invention are shown. Figure 9 The image shows a magnified view of the exemplary semiconductor device 200. In some embodiments, due to physical limitations of the exposure process, the exposed region 230A and the unexposed region 230B may contain a rough interface. More specifically, one or more gaps GP may exist between the exposed region 230A and the unexposed region 230B. The poor contrast between the exposed region 230A and the unexposed region 230B may result in suboptimal lithography performance.

[0047] To address the above issues, embodiments of the present disclosure provide a photoresist layer 230 including a magnetic material. Further, applying a directed magnetic field to the photoresist layer 230 including the magnetic material during an exposure process can smooth the profile of the exposed regions 230A of the photoresist layer 230 and fill the gaps GP between the exposed regions 230A and the unexposed regions 230B with softer unexposed regions 230B.

[0048] In some embodiments, the directed magnetic field can be applied to the photoresist layer 230 throughout the exposure process. In other embodiments, the directed magnetic field can be applied to the photoresist layer 230 after the exposure process has been performed for a period of time. That is, the exposure process can include a first phase and a second phase after the first phase, where the second phase of the exposure process is performed with the directed magnetic field and the first phase of the exposure process is performed without the directed magnetic field. Thus, during the first phase, the photoresist layer 230 can undergo the exposure process and develop a profile as shown in Figure 10

[0049] After the exposure process is complete, a post-exposure bake process can be performed to cure the exposed regions 230A of the photoresist layer 230. In some embodiments, another magnetic field of a different direction can be applied to the photoresist layer 230 during the post-exposure bake process, which can also help to repair the rough profile of the exposed regions 230A of the photoresist layer 230.

[0050] In some embodiments, the directed magnetic field can be applied during the post-exposure bake process and omitted during the exposure process. In other embodiments, the directed magnetic field can be applied during the exposure process and omitted during the post-exposure bake process.

[0051] In some embodiments, the directed magnetic field can be applied to the photoresist layer 230 along a vertical direction. In some embodiments, the directed magnetic field can be applied to the photoresist layer 230 along a horizontal direction. In some embodiments, the magnetic material in the photoresist layer 230 can diffuse downward into the underlying conductive layer 220 during a thermal process (e.g., the post-exposure bake process). Thus, the top portion 220T of the conductive layer 220 can include some material from the photoresist layer 230, e.g., the magnetic material of the photoresist layer 230. In some embodiments, the bottom portion 220B of the conductive layer 220 can be free of material from the photoresist layer 230. In some embodiments, the concentration of the magnetic material can decrease downward in the top portion 220T of the conductive layer 220. In some embodiments, the top portion 220T of the conductive layer 220 can be thinner than the bottom portion 220B of the conductive layer 220.

[0052] Reference is made to Figure 11 ​The exposed regions 230A of the photoresist layer 230 can be used as an etch mask to perform an etch process to remove portions of the conductive layer 220. The conductive layer 220 can be etched by a suitable etch process, such as an anisotropic dry etch process or an isotropic wet etch process. In some embodiments, the magnetic material in the photoresist layer 230 can increase the etch resistance of the photoresist layer 230, which can also facilitate the patterning of the underlying conductive layer 220. After the pattern of the exposed regions 230A of the photoresist layer 230 is transferred to the conductive layer 220, the exposed regions 230A can be removed.

[0053] In some embodiments, a cleaning process can be performed after the development process to remove any residue and / or particles on the semiconductor device. Subsequently, a post-development bake (PDB) process can be performed to ensure the structural stability of the exposed regions 230A.

[0054] Referring to Figure 12 , the exposed regions 230A of the photoresist layer 230 can be used as an etch mask to perform an etch process to remove portions of the conductive layer 220. The conductive layer 220 can be etched by a suitable etch process, such as an anisotropic dry etch process or an isotropic wet etch process. In some embodiments, the magnetic material in the photoresist layer 230 can increase the etch resistance of the photoresist layer 230, which can also facilitate the patterning of the underlying conductive layer 220. After the pattern of the exposed regions 230A of the photoresist layer 230 is transferred to the conductive layer 220, the exposed regions 230A can be removed.

[0055] Figure 13 is a circuit diagram of a memory cell of a memory according to some embodiments of the present disclosure. Referring to Figure 13 , the memory 300 is composed of a plurality of memory cells 302 arranged in a rectangular matrix configuration. In some embodiments, the memory 300 is a dynamic random access memory (DRAM) device. The memory cell 302 of the memory 300 is constructed with a transistor 300T and a capacitor 300C electrically connected to the transistor 300T as the main structure. One side of the capacitor 300C is coupled to the drain region of the transistor 300T, and the other side of the capacitor 300C is coupled to ground. The memory 300 also includes a word line 300W coupled to the gate region of the transistor 300T, and a bit line 300B coupled to the source region of the transistor 300T.

[0056] Figures 14 to 18 is a cross-sectional view of various stages of forming a memory cell according to some embodiments of the present disclosure. As shown in Figure 14 , the memory cell 400 can include a substrate 410, a gate dielectric layer 420 over the substrate 410, a gate conductive layer 430 over the gate dielectric layer 420, and a photoresist layer 440 over the gate conductive layer 430. In some embodiments, the gate dielectric layer 420 can include a suitable dielectric material, such as silicon oxide, silicon nitride, etc. In some embodiments, the gate conductive layer 430 can be formed of a conductive material, such as polysilicon, polysilicon germanium, metal nitride, metal silicide, metal oxide, metal, or a combination thereof. In some embodiments, the material and fabrication method of the photoresist layer 440 are similar to those of the photoresist layer 140.

[0057] Referring to Figure 15 , an exposure process is performed to pattern the photoresist layer 440 according to a predetermined pattern. Thus, the photoresist layer 440 includes exposed regions 440A and unexposed regions 440B. As mentioned above, the photoresist layer 440 can include a positive photoresist material or a negative photoresist material, similar to the photoresist layer 140. Herein, in the following discussion, a negative photoresist material is taken as an example of the photoresist layer 440. However, it should be understood that in other embodiments, the photoresist layer 440 can also be a positive photoresist material. Thus, in embodiments where the photoresist layer 440 is a negative photoresist material, the exposed regions 440A exposed to light become insoluble in a developer solution (e.g., an organic solution), while the unexposed regions 440B become soluble in the developer solution.

[0058] In some embodiments, due to physical limitations of the exposure process, the exposed regions 440A and the unexposed regions 440B can include rough interfaces. More specifically, one or more gaps (not shown in FIG. 4) can exist between the exposed regions 440A and the unexposed regions 440B. The contrast between the exposed regions 440A and the unexposed regions 440B can result in undesirable photolithography performance. Figure 15

[0059] To address the above issues, embodiments of the present disclosure provide a photoresist layer 440 including a magnetic material. Moreover, by applying a directed magnetic field to the photoresist layer 440 including the magnetic material during the exposure process, the profile of the exposed regions 440A of the photoresist layer 440 can be smoothed, and the gaps between the exposed regions 440A and the unexposed regions 440B can be filled with softer unexposed regions 440B.

[0060] In some embodiments, the directed magnetic field can be applied to the photoresist layer 440 throughout the exposure process. In other embodiments, the directed magnetic field can be applied to the photoresist layer 440 after a period of time of the exposure process. That is, the exposure process can include a first stage and a second stage after the first stage, where the second stage of the exposure process utilizes the directed magnetic field, while the first stage of the exposure process does not utilize the directed magnetic field. Thus, in the first stage, the photoresist layer 440 undergoes the exposure process, resulting in rough profiles of the exposed regions 440A and the unexposed regions 440B, while the directed magnetic field of the second stage begins to repair the profile of the exposed regions 440A of the photoresist layer 440.

[0061] After the exposure process is completed, a post-exposure bake process can be performed to cure the exposed regions 440A of the photoresist layer 440. In some embodiments, another magnetic field of a different direction can be applied to the photoresist layer 440 during the post-exposure bake process, which also helps to repair the rough profile of the exposed regions 440A.

[0062] ​In some embodiments, the directed magnetic field can be applied in a post-exposure bake process, while the application of the directed magnetic field can be omitted in the exposure process. In other embodiments, the directed magnetic field can be applied in the exposure process, while the application of the directed magnetic field can be omitted in the post-exposure bake process.

[0063] In some embodiments, the directed magnetic field can be applied to the photoresist layer 440 along a vertical direction or a horizontal direction.

[0064] In some embodiments, during a thermal process (e.g., a post-exposure bake process), the magnetic material in the photoresist layer 440 can diffuse downward into the underlying gate conductive layer 430. As a result, a top portion 430T of the gate conductive layer 430 can include some material from the photoresist layer 440, e.g., the magnetic material of the photoresist layer 440. In some embodiments, a bottom portion 430B of the gate conductive layer 430 can be free of the magnetic material from the photoresist layer 440. In some embodiments, the concentration of the magnetic material in the top portion 430T of the gate conductive layer 430 can decrease downward. In some embodiments, the top portion 430T of the gate conductive layer 430 can be thinner than the bottom portion 430B of the gate conductive layer 430.

[0065] Referring to Figure 16 , a development process is performed. As a result, the unexposed regions 440B of the photoresist layer 440 are dissolved in the developer, while the exposed regions 440A remain on the gate conductive layer 430.

[0066] In some embodiments, after the development process, a rinse process is performed to remove any residue and / or particles on the memory cell 400. Subsequently, a post-development bake (PDB) process is performed to ensure the structural stability of the exposed regions 440A.

[0067] Referring to Figure 17 , an etching process can be performed to remove portions of the gate conductive layer 430 and the gate dielectric layer 420 using the exposed regions 440A as an etching mask. In some embodiments, the patterned gate conductive layer 430 and the patterned gate dielectric layer 420 can be collectively referred to as a gate structure GS. An appropriate etching process, such as an anisotropic dry etching process or an isotropic wet etching process, can be employed to etch the gate conductive layer 430 and the gate dielectric layer 420. In some embodiments, the magnetic material in the photoresist layer 440 can increase the etch resistance of the photoresist layer 440, which can also facilitate the patterning of the underlying gate conductive layer 430 and the gate dielectric layer 420. After the pattern of the exposed regions 440A of the photoresist layer 440 is transferred to the gate conductive layer 430 and the gate dielectric layer 420, the exposed regions 440A can be removed.

[0068] Referring to Figure 18In the substrate 410, a source region 415S and a drain region 415D are formed on opposite sides of the gate structure GS. In some embodiments, the substrate 410 (e.g., a channel region), the gate structure GS, the source region 415S, and the drain region 415D can be a transistor of the memory cell 400. Next, a bit line 400W is formed that is electrically coupled to the gate structure GS, a bit line 400B is formed that is electrically coupled to the source region 415S, and a capacitor 400C is formed that is electrically coupled to the drain region 415D. In some embodiments, Figure 18 An equivalent circuit diagram of the memory cell 400 shown can be similar to Figure 13 The memory 300 discussed is similar.

[0069] While the present application has been described with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0070] The foregoing outlines features of several embodiments so that those skilled in the art can better understand the present disclosure presented herein. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[0071] SYMBOL DESCRIPTION

[0072] 100: semiconductor element

[0073] 110: dielectric layer

[0074] 120: conductive layer

[0075] 130: hard mask

[0076] 140: photoresist layer

[0077] 140A: exposed region

[0078] 140B: unexposed region

[0079] 200: semiconductor element

[0080] 210: dielectric layer

[0081] 220: conductive layer

[0082] 220B: bottom portion

[0083] 220T: top portion

[0084] 230: photoresist layer

[0085] 230A: exposed region

[0086] 230B: unexposed region

[0087] 300: memory

[0088] 300B: bit line

[0089] 300C: capacitor

[0090] 300T: transistor

[0091] 300W: word line

[0092] 302: memory cell

[0093] 400: memory cell

[0094] 400B: bit line

[0095] 400C: capacitor

[0096] 400W: bit line

[0097] 410: substrate

[0098] 415D: drain region

[0099] 415S: source region

[0100] 420: gate dielectric layer

[0101] 430: gate conductive layer

[0102] 430B: bottom portion

[0103] 430T: top portion

[0104] 440: photoresist layer

[0105] 440A: exposed region

[0106] 440B: unexposed region

[0107] GP: gap

[0108] GS: gate structure.

Claims

1. A method for forming a semiconductor device, characterized in that, Include: A dielectric layer is formed above the substrate; A conductive layer is formed above the dielectric layer; A photoresist layer is formed above the conductive layer, wherein the photoresist layer contains a magnetic material; An exposure process is performed on the photoresist layer to form exposed and unexposed areas within the photoresist layer; A directional magnetic field is applied to the photoresist layer; A post-exposure baking process was performed on the photoresist layer; A development process is performed to remove multiple portions of the photoresist layer; as well as The pattern of multiple remaining portions of the photoresist layer is transferred to the conductive layer and the dielectric layer.

2. The method according to claim 1, wherein, Further includes: After the pattern of the plurality of remaining portions of the photoresist layer is transferred to the conductive layer and the dielectric layer, a source region and a drain region are formed in the substrate.

3. The method according to claim 2, wherein, Further includes: Character lines are formed and electrically coupled to the conductive layer; Forming bit lines that are electrically coupled to the source region; and A capacitor is formed, electrically coupled to the drain region.

4. The method according to claim 1, wherein the photoresist layer comprises a positive photoresist material or a negative photoresist material.

5. The method of claim 1, wherein the application of the directional magnetic field to the photoresist layer is performed during the exposure process.

6. The method according to claim 5, wherein, Further includes: Another directional magnetic field is applied to the photoresist layer during the post-exposure baking process.

7. The method of claim 1, wherein the application of the directional magnetic field to the photoresist layer is performed during the post-exposure baking process.

8. The method of claim 1, wherein the directional magnetic field is applied to the photoresist layer in a vertical direction.

9. The method of claim 1, wherein the directional magnetic field is applied to the photoresist layer in a horizontal direction.

10. The method of claim 1, wherein the magnetic material comprises iron, cobalt, or nickel.

11. The method of claim 1, wherein the magnetic material in the photoresist layer diffuses downward to the top portion of the conductive layer during the post-exposure baking process.

12. The method of claim 11, wherein the concentration of the magnetic material decreases downward from the top portion of the conductive layer.

13. The method of claim 11, wherein after the post-exposure baking process is completed, the bottom portion of the conductive layer is free of the magnetic material.

14. The method of claim 11, wherein the conductive layer is made of polycrystalline silicon.

15. A semiconductor element, characterized in that, Include: Substrate; and A transistor, located above the substrate, includes: The source and drain regions are located in the substrate; and A gate structure is located above the substrate and has a dielectric layer and a conductive layer located above the dielectric layer, wherein the top portion of the conductive layer contains a magnetic material.

16. The semiconductor device according to claim 15, wherein, Further includes: The character line is electrically coupled to the gate structure; Bit lines are electrically coupled to the source region; as well as The capacitor is electrically coupled to the drain region.

17. The semiconductor device of claim 15, wherein the magnetic material comprises iron, cobalt, or nickel.

18. The semiconductor device of claim 15, wherein the concentration of the magnetic material decreases downward from the top portion of the conductive layer.

19. The semiconductor device of claim 15, wherein the bottom portion of the conductive layer does not contain the magnetic material.

20. The semiconductor device of claim 19, wherein the top portion of the conductive layer is thinner than the bottom portion of the conductive layer.

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