An asymmetric half-bridge flyback converter light load efficiency optimization method

Abstract

The application discloses a light-load efficiency optimization method of an asymmetric half-bridge flyback converter, and belongs to the technical field of asymmetric half-bridge flyback converters. The method comprises the following steps: starting a first switch period; starting a second switch period when the first switch period is completed; turning on an input voltage of a first switch tube in the asymmetric half-bridge flyback converter at the beginning of the second switch period; increasing excitation current to a peak value of excitation current based on the input voltage; and turning off the first switch tube. The asymmetric half-bridge flyback converter is controlled by adopting N first switch periods and a first interval time to form a second switch period, and meanwhile, the length of the second switch period is adjusted to stabilize output voltage. In the case of realizing soft switching of the converter, the method can avoid excessively high switching frequency of the first switch period, thereby reducing driving loss and switching loss and improving light-load efficiency of the converter.

Description

Technical Field

[0001] This invention relates to the field of asymmetric half-bridge flyback converter technology, specifically a method for optimizing the efficiency of asymmetric half-bridge flyback converter under light load. Background Technology

[0002] Traditional flyback converters are widely used in low-power applications due to their low cost and simple control. However, due to the drawback of leakage inductance energy causing voltage oscillations in the switching transistors, improved flyback converters such as RCD-clamped flyback, active-clamped flyback, quasi-resonant flyback, and asymmetric half-bridge flyback have been developed. Among them, the asymmetric half-bridge flyback converter achieves soft switching by utilizing leakage inductance energy. Furthermore, the voltage stress on the primary-side switching transistors of the asymmetric half-bridge flyback converter is lower, and the resonant capacitor also participates in energy storage, resulting in a smaller transformer size, which is beneficial to improving the performance of the flyback converter.

[0003] Soft switching is a zero-voltage switch (ZVS) or zero-current switch that uses the principle of resonance to make the voltage (or current) of the switching transistor in the switching converter change according to a sinusoidal (or quasi-sinusoidal) law. It turns on the device when the voltage crosses zero, or turns off the device when the current naturally crosses zero, thereby reducing switching losses, improving converter efficiency and switching frequency, and reducing the size of passive components.

[0004] The circuit diagram of a common asymmetric half-bridge flyback converter is as follows: Figure 1 and Figure 2 As shown, the resonant cavities of the two circuits are located in different positions, but their working principles are the same. In the diagram, Q1 and Q2 are the two switching transistors of the half-bridge. The transistor that forms the resonant circuit with the leakage inductance Lr, magnetizing inductance Lm, ideal transformer TR, and resonant capacitor Cr is the second switching transistor, and the other is the first switching transistor. Specifically, in... Figure 1 and Figure 2 In the diagram, Q2 is the second switching transistor, and Q1 is the first switching transistor. Figure 1 and Figure 2 In the diagram, Np, Ns, and Na represent the number of turns in the primary, secondary, and auxiliary windings, respectively; C1 and C2 represent the body capacitances of the first and second switching transistors, respectively; Vin represents the input voltage; D1 represents the secondary diode; Vo represents the output voltage; Co represents the output filter capacitor; R1 and R2 represent the first and second voltage divider resistors on the auxiliary winding, respectively; Vaux is used for voltage division in the auxiliary winding; and Vgs1 and Vgs2 represent the drive signals for the first and second switching transistors, respectively.

[0005] by Figure 2 For example, its operating waveform in continuous resonance mode (i.e., Q1 and Q2 are complementary conductions) is as follows: Figure 2As shown, Vgs1 and Vgs2 are the drive signals for the first and second switches, respectively; iLm is the primary-side magnetizing current waveform, and iLr is the leakage inductance current, i.e., the primary-side current of the half-bridge; Vaux is the voltage across the auxiliary winding. To prevent the first switch Q1 and the second switch Q2 from conducting simultaneously and causing an input short circuit, a certain dead time (such as td1 and td2) needs to be left between the drive voltage signals of the first switch Q1 and the second switch Q2. In steady state, the circuit operates as follows: during the conduction of the first switch, the output voltage charges the magnetizing inductor, leakage inductor, and resonant capacitor. During this phase, the leakage inductor current equals the magnetizing inductor current. Since the transformer is flyback type, the secondary diode is turned off due to reverse voltage. After the first switch turns off, the forward half-bridge current turns on the second switch's body diode, and then the second switch turns on with zero voltage. The voltage across the resonant capacitor acts on the leakage inductor and magnetizing inductor, causing the secondary diode to conduct, entering the energy transfer phase. During this phase, the voltage across the magnetizing inductor is clamped at N*Vo (N=Np / Ns), the magnetizing current decreases linearly, and the leakage inductor and resonant capacitor enter the resonance phase. Afterward, there are two scenarios. The first scenario is that the resonance phase ends when the leakage inductor current equals the magnetizing current, the secondary diode turns off with zero current, the leakage inductor current equals the magnetizing current and continues to decrease under the influence of the primary resonant capacitor voltage, and then the second switch turns off. Figure 2 As shown; the second scenario is that the leakage inductance current has not yet resonated to equal the magnetizing current before the second switch is turned off. In this case, the resonance phase ends quickly, and the leakage inductance current rises rapidly to equal the magnetizing current. In this scenario, the secondary diode cannot turn off with zero current. When the second switch is turned off, if the currents on the magnetizing inductance and leakage inductance are negative and there is enough energy to charge the body capacitor of the second switch and discharge the body capacitor of the first switch, then the first switch can achieve soft-start in the next cycle.

[0006] Pulse width modulation (PWM) is a fundamental control method for asymmetric half-bridge flyback converters. This method adjusts the duty cycle of the first switching transistor based on the error between the output voltage and a reference value to achieve voltage regulation. However, this method is most difficult to implement with soft switching under full load conditions. If soft switching is achieved under full load conditions through parameter design, the valley value of the primary-side magnetizing current decreases as the output current decreases. This results in the converter driving a large portion of negative magnetizing current under light load or no-load conditions. This current exists entirely in the primary side as a circulating current, leading to additional losses and reducing the converter's light-load efficiency.

[0007] Another fundamental control method for asymmetric half-bridge flyback converters is peak current control. This method turns off the first switch when the leakage inductance current reaches a set peak value after the first switch is turned on. Then, after a dead time, the second switch is turned on. Through a series of methods (such as current detection and integral value judgment), the second switch is turned off when the excitation current reaches a threshold value. This method can control the energy transferred in each cycle by adjusting the peak current setpoint, thus achieving voltage regulation. The excitation current threshold when the second switch is turned off is the current value that allows the first switch to turn on at zero voltage at the start of the next cycle. The threshold is negative and its magnitude depends on the input voltage, dead time, and the capacitance of the first and second switches. The peak current control method described above can achieve soft switching of the converter and control the excitation current valley, thus avoiding the negative circulating current problem that occurs under pulse width modulation. However, as the output current decreases, the peak current setpoint also decreases, leading to an increase in the switching frequency. Under light load or no-load conditions, an excessively high switching frequency will increase drive losses and switching losses, thereby reducing converter efficiency. Therefore, existing control methods for asymmetric half-bridge flyback converters suffer from significant switching losses under light load conditions, resulting in low efficiency under such conditions. Summary of the Invention

[0008] The purpose of this invention is to provide a method for optimizing the light-load efficiency of an asymmetric half-bridge flyback converter. This method can eliminate the excessive negative excitation current circulation under light-load conditions, while the converter switching frequency will not increase significantly. It can reduce drive losses and switching losses, and solve the technical problem of low light-load efficiency caused by large negative circulating current or excessively high switching frequency in existing control methods for asymmetric half-bridge flyback converters.

[0009] To achieve the above objectives, the present invention provides the following technical solution:

[0010] A method for optimizing the light-load efficiency of an asymmetric half-bridge flyback converter, wherein the asymmetric half-bridge flyback converter includes a high-side resonant converter and a low-side resonant converter. Both the high-side and low-side resonant converters include an input voltage Vin, a first switch Q1, a second switch Q2, a transformer magnetizing inductance Lm, a transformer primary leakage inductance Lr, a resonant capacitor Cr, a primary winding Np, a secondary winding Ns, an auxiliary winding Na, a secondary diode D1, an output filter capacitor Co, an output voltage Vo, a first body capacitor C1, and a second body capacitor C2. A voltage divider resistor is connected to each end of the auxiliary winding Na, and the two voltage divider resistors form an auxiliary winding voltage divider voltage Vaux.

[0011] In the high-side resonant converter, the gate of the first switch Q1 is connected to the first switch drive signal Vgs1. The drain of the first switch Q1 is connected to the first terminal of the first body capacitor C1. The source of the first switch Q1 is connected to the second terminal of the first body capacitor C1, the source of the second switch Q2, and the second terminal of the second body capacitor C2. The gate of the second switch Q2 is connected to the second switch drive signal. The drain of the second switch Q2 is connected to the input voltage Vin and the first terminal of the second body capacitor C2. The first terminal of the second body capacitor C2 is connected to the first terminal of the primary leakage inductance Lr of the transformer. The second terminal of the primary leakage inductance Lr of the transformer is connected to the first terminal of the transformer magnetizing inductance Lm and the primary winding Np. The second terminal is connected to the second terminal of the resonant capacitor Cr. The first terminal of the resonant capacitor Cr is connected to the second terminal of the second body capacitor C2. The two ends of the auxiliary winding Na are connected to the first terminal of the first voltage divider resistor R1 and the second terminal of the second voltage divider resistor R2. The second terminal of the first voltage divider resistor R1 is connected to the first terminal of the second voltage divider resistor R2 and the auxiliary winding voltage divider voltage Vaux. The first terminal of the secondary winding Ns is connected to the positive terminal of the secondary diode D1. The negative terminal of the secondary diode D1 is connected to the first terminal of the output filter capacitor Co. The output filter capacitor Co and the second terminal of the secondary winding Ns are connected. The current flowing through the transformer magnetizing inductance Lm is the transformer magnetizing current iLm. The current flowing through the transformer primary leakage inductance Lr is the transformer leakage inductance current iLr.

[0012] In the low-side resonant converter, the gate of the first switch Q1 is connected to the first switch drive signal Vgs1. The drain of the first switch Q1 is connected to the first terminal of the first body capacitor C1 and the input voltage Vin. The source of the first switch Q1 is connected to the second terminal of the first body capacitor C1, the drain of the second switch Q2, and the first terminal of the second body capacitor C2. The gate of the second switch Q2 is connected to the second switch drive signal Vgs2. The drain of the second switch Q2 is connected to the first terminal of the primary leakage inductance Lr of the transformer and the first terminal of the second body capacitor C2. The second terminal of the primary leakage inductance Lr of the transformer is connected to the first terminal of the transformer magnetizing inductance Lm and the primary winding Np. The transformer magnetizing inductance Lm and the second terminal of the primary winding Np are respectively connected to the second terminal of the resonant capacitor Cr. The first terminal of the resonant capacitor Cr is connected to the second terminal of the second body capacitor C2. The two ends of the auxiliary winding Na are respectively connected to the first terminal of the first voltage divider resistor R1 and the second terminal of the second voltage divider resistor R2. The second terminal of the first voltage divider resistor R1 is connected to the first terminal of the second voltage divider resistor R2 and the auxiliary winding voltage divider voltage Vaux. The first terminal of the secondary winding Ns is connected to the positive terminal of the secondary diode D1. The negative terminal of the secondary diode D1 is connected to the first terminal of the output filter capacitor Co. The output filter capacitor Co and the second terminal of the secondary winding Ns are connected. The method includes:

[0013] Start the first switching cycle T1. When the first switching cycle T1 is completed, start the second switching cycle T2. At the beginning of the second switching cycle T2, turn on the input voltage of the first switch Q1 in the asymmetric half-bridge flyback converter. Based on the input voltage, increase the excitation current to the peak excitation current Ip and turn off the first switch.

[0014] When the first switch is turned off for a period of time, the second switch in the asymmetric half-bridge flyback converter is turned on to integrate the auxiliary winding voltage Vaux. When the integral value of the auxiliary winding voltage Vaux is equal to the first integration judgment value Int_v1, the second switch is turned off.

[0015] The integral value Vaux is cleared to zero, and after a second time interval, the next switching cycle begins.

[0016] As a further aspect of the present invention: the integration of the auxiliary winding voltage Vaux includes:

[0017] Zero is used as the initial value for integration;

[0018] From the moment the second switch is turned on, the secondary diode is turned on due to the forward voltage, and the voltage across the magnetizing inductor is clamped at (Np / Ns)*Vo, where Np is the number of turns in the primary winding, Ns is the number of turns in the secondary winding, and Vo is the output voltage value. This voltage causes the magnetizing inductor current to decrease linearly. The corresponding induced voltage on the auxiliary winding is integrated by this voltage.

[0019] As a further aspect of the present invention: the first time is the first dead time td1, the first dead time is the time length between the first switch being turned off and the second switch being turned on, the second time is the second dead time, and the second dead time td2 is the dead time between the second switch being turned off and the first switch being turned on.

[0020] As a further aspect of the present invention: the first integral judgment value Int_v1 is K times (I_p-I_n)*Lm, where I_p is the peak value of the excitation current, I_n is the valley value of the excitation current, Lm is the inductance value of the transformer excitation inductance, and K is the product of Na / Np and R2 / (R1+R2). When the first integral judgment value Int_v1 is K times (I_p-I_n)*Lm, the integral value of the excitation inductance voltage across the primary winding is equal to (I_p-I_n)*Lm, and according to the volt-second balance principle, the excitation current decreases from I_p to I_n at this time.

[0021] As a further aspect of the present invention, the method further includes:

[0022] Under heavy load conditions, the peak value of the excitation current I_p is determined by the error between the output voltage and the reference value. The larger the output current, the larger the peak value of the excitation current I_p. The first delay time is zero, and the valley value of the excitation current I_n = -(C1+C2)*Vin / Td2, where I_n is the valley value of the excitation current, Vin is the input voltage, Td2 is the second dead time, C1 is the body capacitance of the first switching transistor, and C2 is the body capacitance of the second switching transistor. The heavy load condition is the case where only the first switching cycle exists and the second switching cycle does not exist.

[0023] As a further aspect of the present invention: the method also includes a light load condition, which is a condition where there are at least two switching cycles;

[0024] Under light load conditions, the peak value of the excitation current I_p and the valley value of the excitation current I_n remain unchanged. When the output current of the converter decreases, the first interval time Tdelay increases and the second switching period T2 is extended, so that the average value of the output current during the entire second switching period is equal to the actual output current.

[0025] When the converter output current increases, the first interval time Tdelay decreases. When the value of the first interval time Tdelay is less than the first interval time threshold Tdelay_th, the set value of the excitation current peak value I_p is increased and the first interval time Tdelay is reduced to 0, and the asymmetric half-bridge flyback converter enters the heavy load condition.

[0026] As a further aspect of the present invention, the light load condition also includes:

[0027] The switching cycle number N of the pulse jump is adjusted based on the magnitude of the output voltage ripple. When the output voltage ripple does not exceed the preset ripple range, the switching cycle number N is increased. When the output voltage ripple exceeds the preset ripple range, the switching cycle number N is decreased. Since the first switching transistor will hard switch at the beginning of each second switching cycle T2, this operation can take the maximum value of the switching cycle number N, thereby reducing some of the hard switching losses.

[0028] As a further aspect of the present invention: the asymmetric half-bridge flyback converter entering the heavy load condition includes:

[0029] Calculate the error between the output voltage sample value and the output voltage reference value, and based on the error value, use a PI controller to control the frequency of the second switching cycle;

[0030] When the output voltage sample value is lower than the output voltage reference value, the frequency of the second switching cycle is increased; when the output voltage sample value is not lower than the output voltage reference value, the frequency of the second switching cycle is decreased.

[0031] A second switching cycle indicator pulse is generated based on the frequency of the second switching cycle, wherein the second switching cycle indicator pulse is a short pulse at the beginning of each second switching cycle.

[0032] As a further aspect of the present invention: the frequency of the second switching cycle controlled by the PI controller includes:

[0033] The second switching cycle indicator pulse is passed through an OR gate into the RS flip-flop to turn on the first switching transistor and increase the leakage inductance current.

[0034] When the leakage inductance current reaches the peak value of the excitation current I_p, the second comparator outputs a pulse, and the RS flip-flop turns off the first switch and turns on the second switch.

[0035] After the first switch is turned off, the auxiliary winding voltage integral is sampled. When the auxiliary winding voltage integral value reaches the preset first or second integral judgment value, the first switching cycle counter is used to obtain the counter value.

[0036] When the counter value is greater than or equal to N-1, the second integral judgment value is selected; when the counter value is less than N-1, the first integral judgment value is selected.

[0037] The first comparator outputs a second switch turn-off indication pulse, which enters the RS flip-flop through an OR gate to turn on the first switch and turn off the second switch.

[0038] Proceed to the next switching cycle.

[0039] Compared with the prior art, the beneficial effects of the present invention are:

[0040] 1. This invention controls an asymmetric half-bridge converter by using N first switching cycles and a first interval time to form a second switching cycle under light load conditions. At the same time, the length of the second switching cycle is adjusted to stabilize the output voltage. The peak value and valley value of the excitation current remain unchanged within the first switching cycle. This can avoid the switching frequency of the first switching cycle being too high while achieving soft switching of the converter, thereby reducing drive loss and switching loss and improving the light load efficiency of the converter.

[0041] 2. This invention calculates the required voltage integral value across the excitation inductor by using the peak and valley values ​​of the excitation current. After comparing this integral value with the voltage integral value of the auxiliary winding, the turn-off time of the second switch is obtained. The excitation current valley value is effectively controlled by volt-second balance, thus solving the problem of negative circulating current loss caused by the small excitation current valley value. Attached Figure Description

[0042] Figure 1 Diagram of a high-side resonant converter;

[0043] Figure 2 Diagram of a low-side resonant converter;

[0044] Figure 3 This is a waveform diagram of the electrical signal of the present invention;

[0045] Figure 4 This is a waveform diagram of the multi-cycle electrical signal of the present invention;

[0046] Figure 5 This is a structural diagram of the control process module of the present invention;

[0047] Figure 6 This is a circuit structure diagram of an embodiment of the present invention;

[0048] Figure 7 This is a diagram illustrating the method steps of the present invention. Detailed Implementation

[0049] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0050] Example:

[0051] Please see Figures 1-7In this embodiment of the invention, a method for optimizing the light-load efficiency of an asymmetric half-bridge flyback converter is provided. The asymmetric half-bridge flyback converter is a low-side resonant converter. In the low-side resonant converter, the gate of the first switch Q1 is connected to the first switch drive signal Vgs1, the drain of the first switch Q1 is connected to the first terminal of the first body capacitor C1 and the input voltage Vin, the source of the first switch Q1 is connected to the second terminal of the first body capacitor C1, the drain of the second switch Q2 and the first terminal of the second body capacitor C2, the gate of the second switch Q2 is connected to the second switch drive signal Vgs2, and the drain of the second switch Q2 is connected to the first terminal of the primary leakage inductance Lr of the transformer and the first terminal of the second body capacitor C2. The two ends of the transformer magnetizing inductor Lm and the first end of the primary winding Np are connected. The second ends of the transformer magnetizing inductor Lm and the primary winding Np are respectively connected to the second ends of the resonant capacitor Cr. The first end of the resonant capacitor Cr is connected to the second end of the second body capacitor C2. The two ends of the auxiliary winding Na are respectively connected to the first end of the first voltage divider resistor R1 and the second end of the second voltage divider resistor R2. The second end of the first voltage divider resistor R1 is connected to the first end of the second voltage divider resistor R2 and the auxiliary winding voltage Vaux. The first end of the secondary winding Ns is connected to the positive terminal of the secondary diode D1. The negative terminal of the secondary diode D1 is connected to the first end of the output filter capacitor Co. The output filter capacitor Co and the second end of the secondary winding Ns are connected. The method includes the following steps:

[0052] S1: Start the first switching cycle T1. When the first switching cycle T1 is completed, start the second switching cycle T2. At the beginning of the second switching cycle T2, turn on the input voltage of the first switch Q1 in the asymmetric half-bridge flyback converter. Based on the input voltage, increase the excitation current to the peak excitation current Ip and turn off the first switch.

[0053] S2: When the first switch is turned off for a period of time, the second switch in the asymmetric half-bridge flyback converter is turned on to integrate the auxiliary winding voltage Vaux. When the integral value of the auxiliary winding voltage Vaux is equal to the first integration judgment value Int_v1, the second switch is turned off.

[0054] S3: Clear the integral value Vaux to zero, and enter the next switching cycle after the second time.

[0055] In this embodiment, the primary winding, secondary winding, and auxiliary winding constitute an ideal transformer TR.

[0056] In this embodiment, the two voltage divider resistors are a first voltage divider resistor R1 and a second voltage divider resistor R2. One end of the auxiliary winding Na is connected to the first end of the first voltage divider resistor R1, the second end of the first voltage divider resistor R1 is connected to the first end of the second voltage divider resistor R2, and the second end of the first voltage divider resistor R1 is connected to the second end of the second voltage divider resistor R2.

[0057] Preferably, integrating the auxiliary winding voltage Vaux includes:

[0058] Zero is used as the initial value for integration;

[0059] From the moment the second switch is turned on, the secondary diode is turned on due to the positive voltage, and the voltage across the magnetizing inductor is clamped at (Np / Ns)*Vo. This voltage causes the magnetizing inductor current to decrease linearly. The corresponding induced voltage on the auxiliary winding is integrated by this voltage.

[0060] Preferably, the first time is the first dead time td1, which is the time between the first switch being turned off and the second switch being turned on; the second time is the second dead time, which is the dead time between the second switch being turned off and the first switch being turned on.

[0061] Preferably, the first integral judgment value Int_v1 is K times (I_p-I_n)*Lm, where I_p is the peak value of the excitation current, I_n is the valley value of the excitation current, Lm is the inductance value of the transformer's excitation inductance, and K is the product of Na / Np and R2 / (R1+R2). When the first integral judgment value Int_v1 is K times (I_p-I_n)*Lm, the integral value of the excitation inductance voltage across the primary winding is equal to (I_p-I_n)*Lm, and according to the volt-second balance principle, the excitation current decreases from I_p to I_n.

[0062] Preferably, the method includes a light-load condition, which is a condition where there are at least two switching cycles;

[0063] Under light load conditions, the peak value of the excitation current I_p and the valley value of the excitation current I_n remain unchanged. When the output current of the converter decreases, the first interval time Tdelay increases and the second switching period T2 is extended, so that the average value of the output current during the entire second switching period is equal to the actual output current.

[0064] When the converter output current increases, the first interval time Tdelay decreases. When the value of the first interval time Tdelay is less than the first interval time threshold Tdelay_th, the set value of the excitation current peak value I_p is increased and the first interval time Tdelay is reduced to 0, and the asymmetric half-bridge flyback converter enters the heavy load condition.

[0065] Preferably, light-load conditions also include:

[0066] The switching cycle number N of the pulse jump is adjusted based on the magnitude of the output voltage ripple. When the output voltage ripple does not exceed the preset ripple range, the switching cycle number N is increased. When the output voltage ripple exceeds the preset ripple range, the switching cycle number N is decreased. Since the first switching transistor will hard switch at the beginning of each second switching cycle T2, this operation can take the maximum value of the switching cycle number N, thereby reducing some of the hard switching losses.

[0067] Preferably, the frequency of the second switching cycle is controlled by a PI controller, including:

[0068] The second switching cycle indicator pulse is passed through an OR gate into the RS flip-flop to turn on the first switching transistor and increase the leakage inductance current.

[0069] When the leakage inductance current reaches the peak value of the excitation current I_p, the second comparator outputs a pulse, and the RS flip-flop turns off the first switch and turns on the second switch.

[0070] After the first switch is turned off, the auxiliary winding voltage integral is sampled. When the auxiliary winding voltage integral value reaches the preset first or second integral judgment value, the first switching cycle counter is used to obtain the counter value.

[0071] When the counter value is greater than or equal to N-1, the second integral judgment value is selected; when the counter value is less than N-1, the first integral judgment value is selected.

[0072] The first comparator outputs a second switch turn-off indication pulse, which enters the RS flip-flop through an OR gate to turn on the first switch and turn off the second switch.

[0073] Proceed to the next switching cycle.

[0074] In this embodiment, as Figure 2 and Figure 4 As shown, Figure 4 In this diagram, Vgs1 is the drive signal for the first switch, Vgs2 is the drive signal for the second switch, iLm is the transformer magnetizing current, iLr is the transformer leakage inductance current, Vaux is the auxiliary winding voltage divider, Vaux is equal to the voltage across the magnetizing inductor multiplied by Na / Np and then multiplied by R2 / (R1+R2), I_p is the peak value of the magnetizing current, and I_n is the valley value of the magnetizing current. Int_Q2 is the integral value of Vaux during the second switch's turn-on period. The first dead time td1 is the dead time between the first switch being turned off and the second switch being turned on, and the second dead time td2 is the dead time between the second switch being turned off and the first switch being turned on. T1 is the first switching cycle, T2 is the second switching cycle, and N is the number of pulse jump cycles. The second switching cycle includes N first switching cycles and a first interval time Tdelay, where N is an integer greater than or equal to 1. Figure 3This method is introduced using N=4 as an example. The length of Tdelay (delay) can be adjusted.

[0075] In this embodiment, Figure 4 The lengths of the N first switching cycles are not equal. After N-1 first switching cycles, in the Nth first switching cycle, when the integral value of Vaux equals the second integral judgment value Int_v2, the second switch is turned off. The second integral judgment value is K times I_p*Lm, where K equals the product of Na / Np and R2 / (R1+R2). That is, in the Nth first switching cycle, when the second switch is turned off, the magnetizing current decreases from I_p to 0. Since the first interval time Tdelay begins after the Nth first switching cycle, a negative magnetizing current value is no longer needed to achieve soft switching. This avoids driving an additional magnetizing current, thereby further improving efficiency.

[0076] In this implementation, such as Figure 6 As shown, the control system of this embodiment further includes a current sampling resistor Rc, an integration unit, output voltage divider resistors R3 and R4, an isolation feedback unit, a pulse jump cycle main control unit, and a drive unit. The pulse jump cycle main control unit internally executes... Figure 5 The control logic shown includes an integrator unit that integrates the auxiliary winding voltage and sends the integrated value to the pulse-jumping cycle main control unit. An isolation feedback unit sends the output voltage sample value to the pulse-jumping cycle main control unit in an isolated manner. At the same time, the pulse-jumping cycle main control unit also receives the leakage inductance current sampling signal generated by the sampling resistor Rc. The output of the pulse-jumping cycle main control unit is the drive signal for the first and second switching transistors. The drive signal controls the first and second switching transistors to be turned on or off through the drive unit.

[0077] In this embodiment, the isolation feedback unit can be implemented using, but is not limited to, an optocoupler isolator.

[0078] In this embodiment, the integration unit can be implemented, but is not limited to, by using a transconductance operational amplifier to convert Vaux into a current signal and then charging the capacitor.

[0079] In this embodiment, the driving unit can be implemented using, but is not limited to, various half-bridge driving chips.

[0080] In this embodiment, current sampling can be implemented using, but is not limited to, sampling resistors Rc, current transformers, etc.

[0081] The above are merely preferred embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A method for optimizing the light-load efficiency of an asymmetric half-bridge flyback converter, characterized in that, The asymmetric half-bridge flyback converter includes a high-side resonant converter and a low-side resonant converter. Both the high-side and low-side resonant converters include an input voltage, a first switching transistor, a second switching transistor, a transformer magnetizing inductance, a transformer primary leakage inductance, a resonant capacitor, a primary winding, a secondary winding, an auxiliary winding, a secondary diode, an output filter capacitor, an output voltage, a first body capacitor, and a second body capacitor. A voltage divider resistor is connected to each end of the auxiliary winding, and a voltage division voltage is formed between the two voltage divider resistors for the auxiliary winding. The method includes: The first switching cycle is started, and the second switching cycle is started when the first switching cycle is completed. At the beginning of the second switching cycle, the input voltage of the first switch in the asymmetric half-bridge flyback converter is turned on, the excitation current is increased to the peak value of the excitation current based on the input voltage, and the first switch is turned off. When the first switch is turned off for a period of time equal to the first time, the second switch in the asymmetric half-bridge flyback converter is turned on to integrate the auxiliary winding voltage. When the integral value of the auxiliary winding voltage is equal to the first integral judgment value, the second switch is turned off. The first integral judgment value is K times (I_p-I_n)*Lm, where I_p is the peak value of the excitation current, I_n is the valley value of the excitation current, Lm is the inductance value of the transformer excitation inductance, and K is the product of Na / Np and R2 / (R1+R2). The integral value is cleared to zero, and the next switching cycle begins after a second time interval.

2. The method for optimizing the light-load efficiency of an asymmetric half-bridge flyback converter according to claim 1, characterized in that, The integration of the auxiliary winding voltage includes: Zero is used as the initial value for integration; From the moment the second switch is turned on, the secondary diode is turned on due to the forward voltage, and the voltage across the magnetizing inductor is clamped at (Np / Ns)*Vo, where Np is the number of turns of the primary winding, Ns is the number of turns of the secondary winding, and Vo is the output voltage value.

3. The method for optimizing the light-load efficiency of an asymmetric half-bridge flyback converter according to claim 1, characterized in that, The first time is the first dead time, which is the time between the first switch being turned off and the second switch being turned on. The second time is the second dead time, which is the dead time between the second switch being turned off and the first switch being turned on.

4. The method for optimizing the light-load efficiency of an asymmetric half-bridge flyback converter according to claim 1, characterized in that, The method further includes: Under heavy load conditions, the peak value of the excitation current is determined by the error between the output voltage and the reference value. The larger the output current, the larger the peak value of the excitation current. The first delay time is zero, and the valley value of the excitation current is I_n = -(C1+C2)*Vin / Td2, where I_n is the valley value of the excitation current, Vin is the input voltage, Td2 is the second dead time, C1 is the body capacitance of the first switching transistor, and C2 is the body capacitance of the second switching transistor. The heavy load condition is the case where only the first switching cycle exists and the second switching cycle does not exist.

5. The method for optimizing the light-load efficiency of an asymmetric half-bridge flyback converter according to claim 4, characterized in that, The method also includes a light-load condition, which is a condition where there are at least two switching cycles. Under light load conditions, the peak value and valley value of the excitation current remain unchanged. When the converter output current decreases, the first interval time increases and the second switching cycle is prolonged, so that the average value of the output current during the entire second switching cycle is equal to the actual output current. When the converter output current increases, the first interval time decreases. When the value of the first interval time is less than the first interval time threshold, the set value of the excitation current peak value is increased and the first interval time is reduced to 0, and the asymmetric half-bridge flyback converter enters the heavy load condition.

6. The method for optimizing the light-load efficiency of an asymmetric half-bridge flyback converter according to claim 5, characterized in that, The light load condition also includes: The switching cycle number of the pulse jump is adjusted based on the magnitude of the output voltage ripple. When the output voltage ripple does not exceed the preset ripple range, the switching cycle number is increased; when the output voltage ripple exceeds the preset ripple range, the switching cycle number is decreased.

7. The method for optimizing the light-load efficiency of an asymmetric half-bridge flyback converter according to claim 5, characterized in that, The asymmetric half-bridge flyback converter enters heavy load conditions including: Calculate the error between the output voltage sample value and the output voltage reference value, and based on the error value, use a PI controller to control the frequency of the second switching cycle; When the output voltage sample value is lower than the output voltage reference value, the frequency of the second switching cycle is increased; when the output voltage sample value is not lower than the output voltage reference value, the frequency of the second switching cycle is decreased. A second switching cycle indicator pulse is generated based on the frequency of the second switching cycle, wherein the second switching cycle indicator pulse is a short pulse at the beginning of each second switching cycle.

8. The method for optimizing the light-load efficiency of an asymmetric half-bridge flyback converter according to claim 7, characterized in that, The frequency of the second switching cycle controlled by the PI controller includes: The second switching cycle indicator pulse is passed through an OR gate into the RS flip-flop to turn on the first switching transistor and increase the leakage inductance current. When the leakage inductance current reaches the peak value of the excitation current, the second comparator outputs a pulse, and the RS flip-flop turns off the first switch and turns on the second switch. After the first switch is turned off, the auxiliary winding voltage integral is sampled. When the auxiliary winding voltage integral value reaches the preset first or second integral judgment value, the first switching cycle counter is used to obtain the counter value. When the counter value is greater than or equal to N-1, the second integral judgment value is selected; when the counter value is less than N-1, the first integral judgment value is selected. The first comparator outputs a second switch turn-off indication pulse, which enters the RS flip-flop through an OR gate to turn on the first switch and turn off the second switch. Proceed to the next switching cycle.

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