Driving system and driving method of digital sounding chip

Abstract

The invention discloses a driving system and a driving method for a digital sound production chip, relates to the technical field of digital sound production, and aims to solve the problems of poor universality and high use cost of a special driving chip for the digital sound production chip in the prior art. The driving system of the digital sound production chip at least comprises a processor, a serial-to-parallel converter and the digital sound production chip, a first number of output pins in the processor are connected with corresponding pins in the serial-to-parallel converter, and the processor is at least used for converting a path of received total serial data into a plurality of paths of sub-serial data; the serial-to-parallel converter is used for receiving the multiple paths of sub-serial data and the control signal output by the processor, dynamically adjusting working parameters based on the control signal, and converting the multiple paths of sub-serial data into a second number of parallel high-voltage driving signals so as to drive a second number of to-be-driven sound production units in the digital sound production chip; wherein the first number is smaller than the second number. The universality of the digital sounding chip driving system is improved, and the use cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of digital sound production, in particular to a driving system and a driving method of a digital sound production chip. BACKGROUND

[0002] A digital sound production chip is an array sound production device composed of pixel units. For example, the array of the digital sound production chip can be composed of two groups of individually controllable single pixels and one group of controllably arranged column pixels. Each pixel has a diaphragm, which is controlled by upper and lower electrodes. When there is a voltage difference, the diaphragm is attracted; when there is no voltage difference, the diaphragm is released. To make the pixel produce sound, vibration needs to be triggered. To vibrate, the diaphragm needs to be attracted and released according to a certain frequency to achieve the effect of vibration. For example, when a low level is applied to the lower electrode of all pixels, and a high level is applied to the upper electrode, the diaphragm is attracted. After a period of time, a low level is applied to the upper electrode, and the diaphragm is released to the original position, which is a vibration. By controlling the vibration of multiple pixels, different frequency sounds can be synthesized, and finally complete sound production is achieved. The present application needs to realize a driving system for controlling the vibration and sound production of the digital sound production chip with many pixels according to the corresponding logic.

[0003] To meet the demand for multi-channel (for example, 128 channels) parallel driving of the digital sound production chip, a corresponding application-specific integrated circuit (ASIC) is currently mainly used. The ASIC fixes the driving logic through a hardware circuit (rather than programmable software), integrates at least a plurality of output pins and corresponding driving circuits (for example, a circuit structure for fixing 128 channels of parallel output internally), and can directly drive a plurality of pixel units of the digital sound production chip without an external conversion module.

[0004] The ASIC has the following disadvantages: long design cycle, high cost, and fixed function (the hardware logic is not programmable, and parameters such as driving frequency and duty cycle cannot be modified). Therefore, once the demand for the digital sound production chip changes (such as driving voltage adjustment, pixel quantity increase or decrease), the fixed circuit of the ASIC cannot be adapted, and the ASIC must be redesigned and taped out. The ASIC has poor versatility and cannot be compatible with different models or iterative upgrades of the digital sound production chip. SUMMARY

[0005] The present application aims to provide a driving system and a driving method of a digital sound production chip, to improve the versatility of the driving system of the digital sound production chip and reduce the use cost.

[0006] To achieve the above-mentioned purpose, the present application provides the following technical solutions: In a first aspect, the present application provides a driving system of a digital sound production chip, comprising at least: a processor, a serial-parallel converter, and a digital sound production chip. The first number of output pins in the processor are connected with corresponding pins in the serial-parallel converter, and the processor is used at least for converting one received serial data into multiple sub-serial data; The serial-parallel converter is used for receiving the multiple sub-serial data and control signals output by the processor, dynamically adjusting working parameters based on the control signals, and converting the multiple sub-serial data into second number of parallel high-voltage driving signals to drive second number of to-be-driven sound units in the digital sound chip; wherein the first number is less than the second number.

[0007] Optionally, the serial-parallel converter comprises a shift register group, a latch, a logic gate control circuit and a high-voltage output buffer circuit. The data input end of the shift register group receives the multiple sub-serial data; the shift register group is composed of N groups of M-bit shift registers, each group of M-bit shift registers in the N groups of M-bit shift registers corresponds to receive one sub-serial data in the multiple sub-serial data; the product of N and M is the second number; N and M are both positive integers, and M is the number of bits of each group of M-bit shift registers. The data output end of the shift register group is connected with the data input end of the latch; the latch is a second number of bit latches, the data input end of the latch corresponds to the data output end of the shift register group, and the total number of bits of the shift register group and the latch is the second number. The data output end of the latch is connected with the input end of the logic gate control circuit, and the output end of the logic gate control circuit is connected with the input end of the high-voltage output buffer circuit.

[0008] Optionally, the high-voltage output buffer circuit comprises second number of high-voltage output buffers, each high-voltage output buffer in the second number of high-voltage output buffers is built-in push-pull output circuit, and the push-pull output circuit is used for converting the low-voltage signal output by the logic gate control circuit into a high-voltage driving signal.

[0009] Optionally, the logic gate control circuit comprises second number of logic gates; each group of logic gates in the second number of logic gates is connected with one output end of the second number of bit latches. Each group of logic gates comprises NAND gate and AND gate. The first input end of the NAND gate is connected with the corresponding output end of the latch, and the second input end of the NAND gate is connected with a forced high-voltage signal; The output end of the NAND gate is connected with the first input end of the AND gate, and the second input end of the AND gate is connected with a forced low-voltage signal. The output end of the AND gate is connected with the level signal input end of the corresponding high-voltage output buffer; and the enable signal input end of the high-voltage output buffer is connected with an enable signal.

[0010] Optionally, the high-voltage output buffer circuit is built-in push-pull output circuit, and the push-pull output circuit is used for converting the low-level signal output by the logic gate control circuit into a high-voltage driving signal.

[0011] Optionally, the control signal at least includes a clock signal and a latch signal; and the working parameter at least includes a playing frequency. The processor periodically pulls up the latch signal, so that each time the latch signal generates a rising edge, the serial-parallel converter executes an output according to the data in the current M-bit shift register, and the playing frequency is consistent with the pull-up frequency of the latch signal. The clock signal completes M-bit data transmission in a single latch period.

[0012] Optionally, the control signal further includes a forced low-level signal. The processor controls the serial-parallel converter to output parallel high-voltage driving signals to the digital sound chip and maintain a first time length, then pulls down the forced low-level signal, so that all the parallel high-voltage driving signals are low level to interrupt the output and maintain a second time length, wherein the ratio of the first time length to the second time length matches the preset duty cycle.

[0013] Optionally, the control signal further includes a reset signal. When resetting, the processor pulls up the reset signal, and simultaneously triggers a rising edge of the clock signal and the latch signal, to clear the data in the shift register group and the latch to realize the reset.

[0014] Optionally, the control signal further includes an enable signal and a forced high-level signal. When the enable signal is high level, the AND gate is turned on, and the data output by the latch is input into the high-voltage output buffer after logical processing by the AND gate; when the enable signal is low level, the output of the high-voltage output buffer is in high resistance state. The output signal of the latch is input into the first input end of the AND gate after logical processing by the NAND gate; and the forced low-level signal is input into the second input end of the AND gate. When the driving system detects an abnormality or needs to control the duty cycle, the forced low-level signal is effective level, the AND gate is closed, the data transmission is cut off, and the low level is forced to be output; when the forced high-level signal is effective level, the NAND gate outputs high level, the AND gate is turned on and outputs high level. When the driving system is in normal operation, the forced low level signal and the forced high level signal are both invalid levels, and the output of the AND gate is a signal processed by a NAND gate.

[0015] Optionally, the second quantity is 128. The shift register group comprises four groups of 32-bit shift registers; the four groups of 32-bit shift registers share one clock signal input end, one reset signal input end and one direction signal input end, and each group of 32-bit shift registers has one data input end and 32 data output ends. The latch is a 128-bit latch; the 128 data input ends of the 128-bit latch correspond one by one to the 128 data output ends of the shift register group.

[0016] Compared with the prior art, the driving system of the digital sound chip provided by the application can dynamically adjust the working parameters based on the control signal output by the processor, and when the working parameters of the digital sound chip need to be adjusted, the hardware circuit does not need to be modified as in the traditional technology, thereby breaking through the limitation that the parameters of an ASIC cannot be adjusted.

[0017] The serial-parallel converter can convert the multiple sub-serial data output by the processor into second quantity parallel high-voltage driving signals, and the first quantity is less than the second quantity, so when the number of pixels of the digital sound chip increases or decreases, only the configuration of the shift register group of the serial-parallel converter needs to be adjusted to adapt, without the need to replace the driving chip; meanwhile, the serial-parallel converter supports high-voltage output and can match the different driving voltage requirements of the digital sound chip, thereby solving the problem that an ASIC cannot adapt to parameter changes.

[0018] In a second aspect, the application further provides a driving method of a digital sound chip, applied to the driving system of the digital sound chip in any of the above aspects, and characterized in that the method comprises: The processor receives audio data and outputs multiple sub-serial data and a control signal to the serial-parallel converter through a first quantity of output pins of the processor; The serial-parallel converter receives the multiple sub-serial data and the control signal, dynamically adjusts the working parameters based on the control signal, and converts the multiple sub-serial data into second quantity parallel high-voltage driving signals to drive second quantity of sound units to be driven in the digital sound chip; wherein the first quantity is less than the second quantity. BRIEF DESCRIPTION OF DRAWINGS

[0019] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 One of the schematic diagrams of a driving system for a digital sound chip provided in an embodiment of the present invention; Figure 2 A second schematic diagram of the structure of a driving system for a digital sound-generating chip provided in an embodiment of the present invention; Figure 3 One of the circuit structure diagrams of a serial-to-parallel converter provided according to an embodiment of the present invention; Figure 4 A schematic diagram of the structure of a digital sound-generating chip provided in one embodiment of the present invention; Figure 5 To and Figure 4 The circuit structure diagram of the corresponding serial-to-parallel converter; Figure 6 This is a flowchart illustrating a driving method for a digital sound chip according to an embodiment of the present invention.

[0020] Figure reference numerals: 1-Processor; 2-Serial-to-parallel converter; 21-Shift register group; 210-M-bit shift register; 211-32-bit shift register; 22-Latch; 220-128-bit latch; 23-Logic gate control circuit; 230-NAND gate; 231-AND gate; 24-High voltage output buffer circuit; 240-High voltage output buffer; 3-Digital sound chip; 4-Host computer; 5-Power supply. Detailed Implementation

[0021] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0022] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0023] In the present application, "at least one" means one or more, and "multiple" means two or more. The association relationship of the associated objects is described, which means that there can be three relationships.

[0024] In the current digital sound chip driving technology field, the corresponding special chip, namely ASIC, is currently used to drive the digital sound chip. The circuit structure of ASIC is realized by hardwiring according to fixed functional requirements. Once the design is completed, the circuit connection and logic function inside ASIC are fixed. For example, when designing an ASIC for driving a digital sound chip, the control logic of the driving frequency and the duty cycle is designed and wired according to the established parameters, and it is difficult to modify it later, because modifying these functions means redesigning the entire ASIC circuit layout.

[0025] During the development of digital sound chips, parameters such as driving voltage and pixel quantity will continue to change and improve. Since ASIC is designed for specific parameters of digital sound chips, when the parameters of digital sound chips change, the original ASIC cannot adapt. For example, if an ASIC is designed according to a specific driving voltage, when the digital sound chip needs a higher or lower driving voltage, the ASIC cannot be used directly and must be redesigned to match the new voltage requirement.

[0026] From the design principle of ASIC, most special ASICs will have similar problems. Because of the customization nature of ASIC, it has inherent deficiencies in flexibility and versatility. The specific reasons are as follows: 1) Hardware circuit is not programmable: the driving logic of ASIC (such as frequency control, duty cycle adjustment circuit) is fixed in hardware through processes such as lithography during chip design phase, and cannot be modified by software code like programmable chips. For example, if the driving frequency is fixed at 50KHz during design, the parameters of the internal clock circuit and the timing control circuit have been fixed, and cannot be adjusted to 100KHz through external instructions.

[0027] 2) No flexible configuration interface: ASIC usually only retains simple enable, reset control pins, and does not have configurable registers or communication interfaces (such as I2C, SPI) to receive external parameter instructions. Therefore, the driving frequency, duty cycle and other parameters are fixed after the chip production is completed, and cannot be adjusted according to the different requirements of digital sound chips (such as different pixel vibration frequency requirements).

[0028] 3) Design target limitation: The advantage of ASIC is high integration and low cost (when mass-produced), but its design intention is to optimize for a single scenario, without considering versatility. If you want to support parameter modification, you need to add programmable circuits, which will increase design complexity and cost, which violates the design goal of ASIC.

[0029] Therefore, when the driving demand of the digital sound chip changes (such as the driving voltage increases, the number of pixels increases, and the frequency parameter is adjusted), the ASIC cannot be adapted and must be re-flowed and designed, resulting in poor versatility.

[0030] The prior art also has a parallel driving mode of multi-chip cascade, for example, a plurality of ordinary GPIO expansion chips (General Purpose Input / Output, a general-purpose input / output interface, which is a general-purpose pin on the chip and can be configured as an input or output mode through software, used for transmitting digital signals to communicate or control external devices such as sensors, actuators, other chips, etc.) are cascaded, and 128-way output is realized by combining multiple chips. The disadvantages are: 1. The pin occupation is still high: each 16-way expander needs at least 4-5-way control pins (I2C / SPI bus), 128-way needs 8 chips, and the total control pin is 32-40-way. The core processor needs to reserve 32-40-way dedicated pins, which limits its ability to handle other functions (such as human-computer interaction, sensor data acquisition) at the same time, especially when multiple digital sound chips are cascaded, the number of pins will be doubled, making it difficult to select a processor; 2. Cannot meet the high-voltage requirement: the output voltage of the ordinary GPIO expander is mostly 3.3V / 5V, while the digital sound chip needs a higher driving voltage due to process limitations. The existing expansion chip cannot be directly adapted and needs to be equipped with a complex voltage boosting circuit, increasing the complexity and failure rate of the system; 3. Multi-chip cascade will introduce signal delay differences (clock offset of different chips), and the pixel vibration of the digital sound chip needs to be strictly synchronized (otherwise the synthesized sound will be distorted), and the existing solution cannot guarantee the microsecond-level synchronization accuracy.

[0031] Therefore, whether it is a dedicated ASIC or a multi-chip cascade of ordinary GPIO expansion chips, it essentially does not break through the logic of parallel driving requiring an equal number of control pins, and cannot meet the core requirements of high-voltage output, flexible configuration parameters, and high pin occupation of the core processor. The existing technology either has too strong specialization and high cost, or is limited in function and cannot adapt to the special requirements of the digital sound chip, resulting in multi-way simultaneous driving as a common technical pain point in the industry.

[0032] To solve the above problems, see Figure 1 The embodiment of the present application provides a driving system of a digital sound chip, which at least comprises a processor, a serial-parallel converter and a digital sound chip. The first number of output pins in the processor are connected with corresponding pins in the serial-parallel converter, and the processor is used for converting a received one-way total serial data into multiple sub-serial data. The serial-parallel converter is configured to receive a plurality of sub-serial data and control signals output by the processor, dynamically adjust working parameters based on the control signals, and convert the plurality of sub-serial data into a second number of parallel high-voltage driving signals to drive a second number of to-be-driven sound units in the digital sound chip; wherein the first number is less than the second number.

[0033] Specifically, the processor is a processing unit with programmable logic function, the internal logic of which can be dynamically configured through programming, and the processor can flexibly output serial data and control signals and adjust output timing and logic relationship according to the driving requirements of the digital sound chip; the processor is connected to the serial-parallel converter through a small number of output pins, and the programmable feature of the processor is used to adapt to serial data transmission protocols in different scenarios and support dynamic control of working parameters of the serial-parallel converter. For example, the processor can be an FPGA (Field-Programmable Gate Array).

[0034] It can be understood that, referring to Figure 2 , the driving system can further include a host computer 4 and a power supply 5, the host computer 4 and the processor 1 are connected through TCP for communication, the host computer 4 is configured to send audio data and control instructions, the audio data is processed by the processor 1 and then converted into a plurality of sub-serial data for parallel transmission and transmitted to the serial-parallel converter, and each sub-serial data includes a plurality of bits (for example, 32 bits). The power supply 5 can provide a voltage of, for example, 5V for the processor 1, can provide a voltage of, for example, 5V for the low-voltage area in the serial-parallel converter 2, and can provide high voltage HVDD for the high-voltage area of the serial-parallel converter 2.

[0035] For example, in a specific implementation, the data received by the PS end of the processor FPGA through TCP is often in a frame of 32 bits, and then the data is stored in the DDR according to the addresses in Table 1 below.

[0036] Table 1: Address table

[0037] The data in the base address (i.e. the command address) is read in real time at the PL end of the FPGA to execute the corresponding command, and the correspondence table is as shown in Table 2 below.

[0038] Table 2: Correspondence table

[0039] The audio data sent from the host computer through TCP is stored in the corresponding address of the DDR, and when the command to start playing is received, the data of the DDR is read at a rate of 100M and stored in the FIFO buffer unit at the PL end of the FPGA, and the data is read from the FIFO buffer unit at a rate matching the actual playing frequency.

[0040] Next, the audio data mapping rule is explained. The audio data is sent by the upper computer, and the data format is arranged in the order of T1-T32, T33-L30, B1-B32, B33-R29 in 32-bit groups. Four groups of 32-bit data constitute a frame, and the frame sequence is cyclic until the audio ends.

[0041] Combined with the total number of T, B, L, and R control signals (T: 34, B: 34, L: 30, R: 30, total 128), since the shift register group requires 32-bit input, the T / B type signals exceeding 32 bits are split and spliced, and 128 control signals are mapped through four groups of 32-bit data. Assuming that the four groups of 32-bit data are D1A, D2A, D3A, and D4A, the rules are as follows: (1) Data group D4A (corresponding to the first 32 control signals of T type).

[0042] Bit sequence range: D4A[0]~D4A

[31] .

[0043] Mapping relationship: T1~T32 (covering the first 32 signals of T type) in turn.

[0044] Example: D4A[0]→T1, D4A[1]→T2, …, D4A

[31] →T32 (2) Data group D3A (corresponding to the remaining signals of T type + L type signals).

[0045] Bit sequence range: D3A[0]~D3A

[31] .

[0046] Mapping relationship: T33, T34 (remaining 2 signals of T type) + L1~L30 (all 30 signals of L type), total 32 bits.

[0047] Example: D3A[0]→T33, D3A[1]→T34, D3A[2]→L1, …, D3A

[31] →L30.

[0048] (3) Data group D2A (corresponding to the first 32 control signals of B type).

[0049] Bit sequence range: D2A[0]~D2A

[31] .

[0050] Mapping relationship: B1~B32 (covering the first 32 signals of B type) in turn.

[0051] Example: D2A[0]→B1, D2A[1]→B2, …, D2A

[31] →B32.

[0052] (4) Data group D1A (corresponding to the remaining signals of B type + R type signals).

[0053] Bit sequence range: D1A[0]~D1A

[31] .

[0054] Mapping relationship: B33, B34 (the remaining 2 signals of the B type) + R1~R30 (all 30 signals of the R type), a total of 32 bits.

[0055] Example: D1A[0]→B33, D1A[1]→B34, D1A[2]→R1... D1A

[31] →R30 Mapping logic summary: Grouping logic: 34 signals of the T / B type (more than 32 bits), splitting the remaining 2 signals and splicing 30 signals of the L / R type, adapting the 32-bit input requirement of the shift register group. Total number of signals: 34 (T) + 34 (B) + 30 (L) + 30 (R) = 128, which exactly fills 4 groups x 32 bits = 128 bits.

[0056] Core sequence: The T type takes the first 32 (D4A), and the remaining 2 (T33, T34) are spliced with the L type (D3A); the B type takes the first 32 (D2A), and the remaining 2 (B33, B34) are spliced with the R type (D1A); The bit sequence in each group starts from 0 and is filled in order according to “T / B remaining signals→L / R signals”.

[0057] Through the above rules, the mapping relationship of 128-way control signals→4 groups of 32-bit data is clearly defined, solving the problem of ambiguous splitting of group pixel bit sequence.

[0058] Technical effect analysis of the embodiment: One. The core problem of existing ASIC is that the circuit is fixed, the parameters cannot be changed, and the versatility is poor. This embodiment first uses FPGA as a processor, and FPGA has the feature of field programmable, and its logic function can be modified by programming without the need to redesign the hardware circuit. For example, the driving frequency, duty cycle and other parameters can be flexibly adjusted by updating the program, without the need to reflow like ASIC; secondly, this embodiment also uses a serial-parallel converter for dynamic adaptation. The serial-parallel converter can dynamically adjust the working parameters based on the control signal, and convert the multi-channel parallel high-voltage drive signal by receiving the multi-channel sub-serial data output by the processor (split from one total serial data). When the number of pixels (the second number) of the digital sound chip changes, only the output channel number configuration of the serial-parallel converter needs to be adjusted, without the need to replace the hardware; the high-voltage drive characteristics can also be adapted to different voltage requirements through the converter, avoiding the adaptation problem caused by the fixed voltage design of ASIC.

[0059] The existing multi-chip cascade has the problems of high pin occupation, poor signal synchronization, and inability to directly output high voltage. It can be understood that the existing ASIC also has the problem of high pin occupation. When the pins in the chip also need to be controlled in other aspects, the function cannot be expanded. However, 1) the first number of output pins of the processor FPGA in the embodiment are connected to the serial-parallel converter, a large number of parallel outputs are controlled through parallel transmission of a small number of multi-sub-serial data, and the first number is less than the second number, for example, 10 pins are used to realize 128-way driving, which is much lower than the 32-40 pin of the multi-chip cascade, solving the problem of high pin occupation. 2) The multi-sub-serial data are synchronously converted into parallel signals by the single converter, avoiding the signal delay difference of the multi-chip cascade, which is beneficial to guarantee the timing accuracy of pixel vibration. 3) The serial-parallel converter directly outputs the parallel high-voltage driving signal, without the need for an additional voltage boosting circuit, simplifying the system structure and solving the problem that the ordinary GPIO expander cannot adapt to high voltage.

[0060] In summary, the embodiment breaks through the limitations of ASIC and the defects of multi-chip cascade by the transmission design of splitting one total serial data into multiple sub-serial data by the processor, combining the programmability and the dynamic adaptation of the serial-parallel converter, while meeting the needs of low pin occupation, high voltage output, and flexible parameter configuration, and solving the common pain points of the existing technology.

[0061] In an optional embodiment, referring to Figure 3 , the serial-parallel converter 2 can include a shift register group 21, a latch 22, a logic gate control circuit 23, and a high-voltage output buffer circuit 24; the data input end of the shift register group 21 receives the multi-sub-serial data; the shift register group 21 is composed of N groups of M-bit shift registers 210, each group of M-bit shift registers 210 in the N groups of M-bit shift registers corresponds to receiving one sub-serial data in the multi-sub-serial data; the product of N and M is the second number; N and M are positive integers, and M is the number of bits of each group of M-bit shift registers; the data output end of the shift register group 21 is connected to the data input end of the latch 22; the latch 22 is a second number of bit latches, the data input end of the latch 22 corresponds to the data output end of the shift register group 21, and the total number of bits of the shift register group 21 and the latch 22 is the second number; the data output end of the latch 22 is connected to the input end of the logic gate control circuit 23, the output end of the logic gate control circuit 23 is connected to the input end of the high-voltage output buffer circuit 24, and the output end of the high-voltage output buffer circuit 24 is used to output the high-voltage driving signal.

[0062] Referring to Figure 4For example, the digital sound chip is composed of 34 top-layer single-pixel T, 34 columns of whole-column pixels B, 30 spare pixels L and 30 lower electrode groups R. If the digital sound chip is to be driven, at least 34+34+30+30=128 effective controllable signals are needed, and the second quantity is 128. The shift register group includes 4 groups of 32-bit shift registers. The 4 groups of 32-bit shift registers share 1 clock signal input end, 1 reset signal input end and 1 direction signal input end, and each of the 4 groups of 32-bit shift registers has 1 data input end and 32 data output ends. The latch is a 128-bit latch. The 128 data input ends of the 128-bit latch correspond one by one to the 128 data output ends of the shift register group. Correspondingly, the 11 (i.e., the first quantity) output pins in the processor include 4 sub-serial data output pins, 1 clock signal output pin, 1 latch signal output pin, 1 reset signal output pin, 1 direction signal output pin, 1 enable signal output pin, 1 forced high-level signal output pin, and 1 forced low-level signal output pin. The 4 sub-serial data output pins correspond one by one to the 4 data input ends of the shift register group. The clock signal output pin is connected to the clock signal input end shared by the serial-parallel converter. The reset signal output pin is connected to the reset signal input end shared by the serial-parallel converter. The direction signal output pin is connected to the direction signal input end shared by the serial-parallel converter.

[0063] For the direction signal (DIR signal) shared by the 4 groups of 32-bit shift registers, in the actual application scenario of driving the digital sound chip, the DIR signal does not need to be dynamically switched and adjusted: only the DIR signal needs to be fixedly set to 1 to ensure that the data transmission direction of the shift register group is “D1A→D1B” (i.e., from the data input end of each 32-bit shift register to its 32 data output ends). In actual circuit design, the D1B end of the shift register is not physically connected, and the DIR signal is not set to 0 at all times, which can completely avoid circuit data transmission abnormalities or hardware failures caused by misoperation of the direction signal. D1A is the data input end of the M-bit shift register, and D1B is the data output end corresponding to D1A of the M-bit shift register.

[0064] Beneficial effect analysis of the embodiment: I. From the perspective of data processing, 1) a shift register group composed of N groups of M-bit shift registers is used to receive the parallel sub-serial data of the serial data segment output by the processor through N data input terminals (i.e., the processor splits one total serial data into N parallel transmitted sub-data segments, and each group of shift registers corresponds to receive one sub-serial data), and converts the multi-channel sub-serial data into N times M parallel high-voltage driving signals. This design can effectively resolve the contradiction between the limited number of processor pins and the large number of sound generating units to be driven. By parallel splitting and converting a small amount of sub-serial data, a small number of pins can realize multi-channel driving, breaking the strong binding between the number of ASIC pins and the number of driving channels, and significantly improving the flexibility of the processor in adapting to different numbers of sound generating units. For example, when using 4 groups of 32-bit shift registers, the serial data output by the processor can be split into 4 parallel sub-data segments, and finally converted into 128 parallel signals (4x32=128). The key is that only 11 output pins of the processor are needed to control the 128 driving signals, effectively resolving the contradiction between the small number of processor pins (first quantity) and the large number of sound generating units to be driven (second quantity), allowing the processor with limited pins to drive multiple sound generating units, breaking the strong binding between ASIC pins and driving channels, and improving the flexibility of the processor in adapting to different numbers of sound generating units. 2) With the help of the second number of D-type flip-flops, the dynamic serial data transmitted by the shift register is converted into static parallel data form, avoiding data jitter in the conversion link. For example, a 128-bit latch can convert the dynamic data output by the shift register into stable 128-channel static parallel data. Digital sound chips have strict requirements for timing synchronization (pixel vibration of sound generating units needs to be accurately aligned), and the latch can ensure the synchronous effect of the corresponding second number of signals, solving the problem of inconsistent signal delay in the traditional multi-chip cascade scheme and improving the consistency of signal output.

[0065] II. From the perspective of cost reduction and efficiency improvement, 1) the N groups of shift registers share the clock signal input end, the reset signal input end and the direction signal input end, only 1 set of control pins is needed, and no control pins need to be configured for each group of shift registers. Taking 4 groups of shift registers as an example, 1 clock signal, 1 reset signal and 1 direction signal output by the processor are connected to the clock signal input end, the reset signal input end and the direction signal input end shared by the 4 groups of shift registers, that is, the processor includes at least 1 clock signal output pin, 1 reset signal output pin, 1 direction signal output pin, combined with 4 sub-serial data output pins of the processor, 1 latch signal output pin, 1 enable signal output pin, 1 forced high-level signal output pin and 1 forced low-level signal output pin, a total of only 11 output pins, which can realize the cooperative control of the 4 groups of shift registers, instead of configuring independent control pins for the 4 groups of shift registers. Compared with the multi-chip cascade scheme in the prior art which needs to occupy more control pins (for example, 32-40 channels), the embodiment greatly reduces the occupation of hardware resources, makes the system hardware architecture more simple, and reduces the hardware cost and design complexity. 2) Through the cooperation of the shift register group and the latch, the number of parallel signals output can accurately match the actual driving channel number required by the digital sound chip. For example, for a digital sound chip composed of 34 top single-pixel T, 34 columns of whole-pixel B, 30 spare pixels L and 30 lower electrode groups R, the 34+34+30+30=128 effective controllable signals required can be accurately matched by the 128 parallel signals output by the shift register group and the latch of the embodiment, and the control is realized through only 11 processor output pins throughout the process, avoiding the problems of redundant or insufficient driving channels. The customized parallel conversion mechanism adapts to the chip structure, and compared with the general GPIO expander in the prior art, the embodiment has more advantages in channel adaptation and conversion efficiency, and improves the adaptability of the driving system and the chip.

[0066] III. From the perspective of signal stability, 1) The transmission mode of multi-channel parallel receiving multi-path sub-serial data is adopted (the shift register group synchronously receives N sub-serial data through N data input terminals), for example, under the precise control of 11 output pins, this transmission stage belongs to the transmission of weak signal and high frequency control signal (low signal amplitude, such as 3.3V / 5V, and high frequency driving demand needs to be matched), which is more sensitive to electromagnetic interference. At this time, through a small number of signal lines (for example, 4 sub-serial data correspond to 4 lines), compared with the parallel transmission in the ASIC in the prior art which needs to use a large number of signal lines (such as 128 lines are needed for 128-way driving), the embodiment can greatly reduce the probability of electromagnetic coupling (crosstalk) between lines. Even if the transmission process is disturbed, it usually only affects 1 sub-serial data, and does not cause multiple baseband signals to be wrong at the same time due to the dense arrangement of multiple lines, which is caused by the traditional parallel transmission. This design effectively solves the crosstalk problem that is prone to occur in long-distance parallel transmission, and is especially suitable for high-frequency driving scenes such as high-speed vibration control of digital sound chip, and can reliably guarantee the accuracy of signal transmission and significantly improve the stability of the driving system in high-frequency scenes. 2) The latch converts the 128 parallel signals output by the shift register group into stable parallel signals and temporarily stores them, on the one hand, it realizes the signal isolation between the processor and the high-voltage driving link, avoids the reverse interference of the high-voltage output buffer circuit on the weak signal output by the processor when it is working, and guarantees the stable operation of the processor; on the other hand, the 128 parallel signals after latching are strong signals (high amplitude, up to 80V) and have static output characteristics (the signal state remains unchanged within the latching period), and the anti-interference ability is much stronger than that of the weak signal in the transmission stage. At the same time, the latch and the high-voltage output buffer circuit are isolated by the logic gate control circuit, and the high-voltage output buffer circuit has a built-in push-pull output circuit, which can further enhance the signal driving ability and suppress noise. Therefore, even if 128 parallel transmission is used after latching, the probability of error caused by crosstalk is much lower than that of the weak signal in the transmission stage, and it is complementary to the anti-interference design in the transmission stage, which improves the overall reliability of the system.

[0067] IV. From the perspective of high-voltage driving, 1) Compared with the ordinary GPIO expander in the prior art, the output voltage is mostly 3.3V / 5V, which is difficult to drive directly. The high-voltage output buffer circuit in the embodiment can convert the low-voltage control signal output by the logic gate into the high-voltage driving signal required by the digital sound chip, without the need for additional boost circuit, simplifying the system structure.

[0068] In addition, the first number of output pins of the processor are connected with the first number of input pins of the shift register group in a one-to-one correspondence, for example, through 11-pin control of 128-way driving, which ensures the orderly transmission of control signals and data signals, further strengthens the stability and reliability of the serial-parallel conversion process, and ensures that the driving system operates efficiently according to the preset logic.

[0069] In an alternative embodiment, the high-voltage output buffer circuit includes a second number of high-voltage output buffers, each of the second number of high-voltage output buffers having a push-pull output circuit built-in, which is used to convert the low-voltage signal (e.g. 3.3V / 5V) output by the logic gate control circuit into a high-voltage driving signal (e.g. up to 80V). The circuit structure of the push-pull output circuit can refer to related technologies, and this embodiment will not be described again.

[0070] The push-pull output circuit realizes efficient conversion from low voltage to high voltage (e.g. 3.3V / 5V→up to 80V), directly adapts to the high-voltage driving requirements of the digital sound chip, without the need for additional voltage boosting circuits, simplifying the system structure and reducing the failure rate.

[0071] For example, the high-voltage output buffer can include: a level isolation circuit, a timing buffer unit, a push-pull output circuit (including a high-power push-pull enhancement stage), an overcurrent protection circuit, a high-voltage low-dropout regulator (HV-LDO) + energy storage capacitor network, and a 128-way current equalization distribution circuit, a total of 6 types of core modules.

[0072] The signal transmission link is: the low-voltage output end of the logic gate control circuit (3.3V / 5V)→the input end of the level isolation circuit (optocoupler / isolation amplifier)→the output end of the level isolation circuit→the input end of the timing buffer unit (RC filter+delay calibration sub-circuit)→the output end of the timing buffer unit→the control signal input end of the push-pull output circuit (including a high-power enhancement stage)→the high-voltage output end of the push-pull output circuit→the input end of the 128-way current equalization distribution circuit→the output end of the 128-way current equalization distribution circuit→the digital sound chip.

[0073] The safety and voltage stabilization link is: the high-voltage output end of the push-pull output circuit→the current sampling end of the overcurrent protection circuit (with a series milliohm sampling resistor)→the protection signal end of the overcurrent protection circuit, one way is fed back to the shutdown control end of the push-pull output circuit, and the other way is fed back to the abnormality detection pin of the processor. The high-voltage power supply→the input end of the high-voltage low-dropout regulator→the output end of the HV-LDO→the power supply end Vpp of the push-pull output circuit.

[0074] Power supply and ground: 1) Level isolation circuit, timing buffer unit: powered by 5V low voltage power supply (share low voltage with logic gate control circuit), ground terminal connects digital ground DGND; 2) Push-pull output circuit, overcurrent protection circuit, HV-LDO, current equalization distribution circuit: high voltage side is powered by Vpp, ground terminal connects power ground PGND, bottom DGND and PGND share ground.

[0075] The functions of each circuit module in the high-voltage output buffer: 1) Level isolation: high and low voltage circuit electrical isolation is realized through optocoupler / isolation amplifier to prevent high voltage side (80V) large current / high voltage from interfering with low voltage side logic circuit (processor, logic gate); 2) Timing synchronization and noise reduction: RC filter sub-circuit of timing buffer unit filters out high-frequency noise, and delay calibration sub-circuit compensates for 128-way signal timing deviation, ensuring synchronization of driving signals and avoiding vibration of sound generating units out of sync; 3) High voltage conversion and high power driving: push-pull output circuit converts low voltage signal to 80V high voltage signal, combined with high-power push-pull enhancement stage (such as using 4-6 groups of STP80NF70MOS transistors in parallel with IR2110 driving IC), to improve single channel filling / pulling current and total driving capacity, meeting the large current demand of 128-way simultaneous driving; 4) Overcurrent protection: overcurrent protection circuit samples output current in real time, cuts off the push-pull circuit when the threshold is exceeded, and feeds back to the processor to prevent electrode overcurrent breakdown of the sound generating unit; 5) Power stabilization: HV-LDO compensates for load current changes to ensure Vpp≥76V (voltage drop≤5%) when fully loaded, and energy storage capacitor network suppresses high and low frequency ripple to stabilize power voltage; 6) Current equalization: 128-way current equalization distribution circuit (series high-precision resistors or constant current loop) balances the load current of each way to avoid impedance deviation of the sound generating unit.

[0076] In an alternative embodiment, the logic gate control circuit includes a second number of groups of logic gates; each group of logic gates in the second number of groups of logic gates is connected to an output terminal of a second number of flip-flops; each group of logic gates includes a NAND gate and an AND gate; a first input terminal of the NAND gate is connected to a corresponding output terminal of the latch, and a second input terminal of the NAND gate is connected to a forced high level signal; an output terminal of the NAND gate is connected to a first input terminal of the AND gate; a second input terminal of the AND gate is connected to a forced low level signal; an output terminal of the AND gate is connected to a level signal input terminal of a high-voltage output buffer in the high-voltage output buffer circuit; and an enable signal input terminal of the high-voltage output buffer is connected to an enable signal.

[0077] and Figure 4 Correspondingly, see Figure 5 , Figure 5 is Figure 3In one embodiment, the shift register group 21 includes four groups of 32-bit shift registers 211, the latch 22 is a 128-bit latch 220, the logic gate control circuit 23 includes 128 groups of logic gates, each group of logic gates includes a NAND gate 230 and an AND gate 231, and the high-voltage output buffer circuit 24 includes 128 groups of high-voltage output buffers 240.

[0078] Referring to the embodiment in Figure 5 , the logic gate control circuit 23 includes 128 groups of logic gates; each group of logic gates in the 128 groups of logic gates is connected to an output terminal of the 128-bit latch 220, and the 128-bit latch 220 includes 128 data input terminals D0 to D127 and 128 data output terminals Q0 to Q127. Each group of 32-bit shift registers includes 32 data output terminals. For example, the first data output terminal of the first 32-bit shift register is connected to the first data input terminal D0 of the 128-bit latch 220, and so on, the 32nd data output terminal of the first 32-bit shift register is connected to the 125th data input terminal D124 of the 128-bit latch 220; the first data output terminal of the second 32-bit shift register is connected to the second data input terminal D1 of the 128-bit latch 220, and so on, the 32nd data output terminal of the second 32-bit shift register is connected to the 126th data input terminal D125 of the 128-bit latch 220; the first data output terminal of the third 32-bit shift register is connected to the third data input terminal D2 of the 128-bit latch 220, and so on, the 32nd data output terminal of the third 32-bit shift register is connected to the 127th data input terminal D126 of the 128-bit latch 220; the first data output terminal of the fourth 32-bit shift register is connected to the fourth data input terminal D3 of the 128-bit latch 220, and so on, the 32nd data output terminal of the fourth 32-bit shift register is connected to the 128th data input terminal D127 of the 128-bit latch 220.

[0079] In Figure 5 , the input terminal of the first NAND gate 230 is connected to the first data output terminal Q0 of the 128-bit latch 220, and so on, the input terminal of the 128th NAND gate 230 is connected to the 128th data output terminal Q127 of the 128-bit latch 220.

[0080] The second input terminal of the NAND gate 230 is connected to a forced high-level signal OH; the output terminal of the NAND gate 230 and the first input terminal of the AND gate 231 are connected; the second input terminal of the AND gate 231 is connected to a forced low-level signal OL; the output terminal of the AND gate 231 is connected to the level signal input terminal of the corresponding high-voltage output buffer 240 in the high-voltage output buffer circuit 24; and the enable signal input terminal of the high-voltage output buffer 240 is connected to the enable signal OE.

[0081] It should be noted that the first input end of the NOT gate is equivalent to a NOT gate, which has the function of reversing the input signal.

[0082] The embodiment has the following technical effects: 1) accurate signal screening and transmission. Each set of logic gates realizes dynamic screening of the latch output signal through the combination logic of the forced high-level signal OH, the forced low-level signal OL, and the enable signal OE: only when the signal meets the preset logic (for example, OL=1, OH=1, and OE=1 during normal operation), is allowed to enter the high-voltage output buffer circuit, ensuring the accuracy of the driving signal. 2) has multi-scene adaptation ability. Through the level switching of OL and OH signals, forced low-level (interrupt output) and forced high-level (continuous driving) special modes can be quickly realized, which not only meets the dynamic demand of duty cycle adjustment, but also can cut off the output when the system is abnormal, protecting the digital sound chip from damage by abnormal signals. 3) has isolation and synergistic effect. The logic gate control circuit acts as an intermediate layer between the latch and the high-voltage output buffer circuit, which not only isolates the direct interaction between low-voltage logic signals and high-voltage driving signals, but also realizes the synchronous control of 128 signals through unified logic rules, ensuring the action consistency of multiple sound emitting units.

[0083] The control logic of the driving system is described as follows.

[0084] The control signals include clock signal CLK, latch signal LE, forced low-level signal OL, enable signal OE, forced high-level signal OH, reset signal RST, and direction signal. The core working parameters include at least playing frequency and duty cycle.

[0085] (1) Data transmission: the processor controls N sets of M-bit shift registers to receive serial data synchronously based on the rising edge of the clock signal CLK; every time the processor inputs 1-bit data to the M-bit shift register, the data in the M-bit shift register is shifted left by 1 bit, and the highest bit overflows when it exceeds M bits (for example, when M=32, the 33rd bit input will squeeze out the 1st bit).

[0086] (2) Output control: when the latch signal LE is high, the second number of bit latches transmit the second number of parallel data output by the N sets of M-bit shift registers to the logic gate control circuit; when the latch signal LE is low, the second number of bit latches maintain the current output state, ensuring signal stability.

[0087] (3) Play frequency adjustment: the processor pulls up the latch signal LE periodically, so that the serial-parallel converter performs an output according to the current data in the M-bit shift register every time the latch signal generates a rising edge, and the play frequency is consistent with the pull-up frequency of the latch signal. For example, when a play frequency of 50K is required, the processor controls the LE signal to be pulled up once every 20us, that is, the pull-up frequency of LE is 50K.

[0088] The clock signal needs to meet the following conditions: the clock signal completes M-bit (for example, 32-bit) data transmission within a single latch period (the time interval between two adjacent LE pull-ups). For example, when the play frequency is 200K, the single LE period is 5us, and the CLK frequency needs to be ≥6M to ensure that M-bit data is input within 5us.

[0089] (4) Duty cycle adjustment: the processor controls the serial-parallel converter to output parallel high-voltage drive signals to the digital sound chip and maintain the first duration according to the preset duty cycle, and then pulls down the forced low signal OL to make all parallel high-voltage drive signals low to interrupt the output and maintain the second duration. The ratio of the first duration to the second duration matches the preset duty cycle to form a cycle of "output-interrupt". For example, a 50% duty cycle means that the first duration=the second duration.

[0090] It should be noted that the OL signal line of the serial-parallel converter has the function of forcibly pulling down all outputs. By pulling down the OL signal, all current outputs can be interrupted, thereby realizing duty cycle control (for example, a 50% duty cycle corresponds to half the time with drive signal output and half the time without drive signal output). The OL signal needs to be pulled down after the xth clock cycle according to the set duty cycle. Here, x is the key clock cycle count parameter required to achieve the target duty cycle.

[0091] Further, in the FPGA, the main clock of the driving system is 100M, and the preset frequency duty cycle is all frequency division according to the 100M main clock. When the host computer sends the required frequency duty cycle, for example, 50KHz, 50% duty cycle, it can be calculated that under the condition of 100M main clock, every 2000 main clock cycles is a single output of 50KHz. The duty cycle is calculated after frequency division, and 50% is 1000 main clock cycles. This 1000 is the x of the xth clock cycle in the above duty cycle control, and x is an integer.

[0092] It should be noted that the adjustment of the play frequency in this embodiment is completely dependent on the timing dynamic change of the control signal LE, which conforms to the core logic of "serial-parallel converter dynamically adjusts working parameters based on control signal": From the principle of parameter adjustment, the essence of the playing frequency is the frequency of the serial-parallel converter outputting the driving signal to the digital sound chip, which does not need to modify the hardware circuit and only needs to change the pull-up timing of the LE signal: for example, if the playing frequency needs to be raised from 50KHz to 200KHz, the pull-up period of the LE signal needs to be shortened from 20μs to 5μs, so that the LE pull-up frequency can be synchronized with the target playing frequency.

[0093] From the hardware support, the driving system adopts FPGA as the processor, the main clock of which is 100M, and the playing frequency parameter is calculated based on the division of the main clock: 50KHz playing frequency corresponds to “pulling up LE once every 2000 100M main clock periods”, and 200KHz playing frequency corresponds to “pulling up LE once every 500 100M main clock periods”, so that the processor only needs to modify the division coefficient of the main clock through programming to realize the dynamic adjustment of the LE signal pull-up frequency and further change the playing frequency.

[0094] Compared with the prior art ASIC, the playing frequency of the ASIC is fixed by the internal clock circuit, timing control circuit and other hardware parameters, and if the frequency needs to be adjusted (such as from 50KHz to 200KHz), the ASIC must be redesigned and taped out; while in this embodiment, the playing frequency can be flexibly switched by modifying the pull-up timing of the LE signal (control signal) combined with FPGA division programming, which completely solves the defect that the parameters of the ASIC cannot be changed.

[0095] The adjustment of the duty cycle is also realized by the dynamic change of the timing of the control signal (OL), which completely fits the logic of “dynamic adjustment of working parameters based on control signal”: From the principle of parameter adjustment, the essence of the duty cycle is the ratio of the effective driving time (first time) to the interruption time (second time), and its adjustment follows the core link of “preset duty cycle (target) → calculation of OL pull-down opportunity (control signal modulation) → OL signal pull-down (control signal change) → output of the duty cycle meeting the target”: for 30% duty cycle, only the OL pull-down opportunity needs to be adjusted: at 50KHz frequency (corresponding to 2000 main clock periods), the control serial-parallel converter outputs the driving signal for 600 main clock periods (first time) and then pulls down the OL, and the output is interrupted for 1400 main clock periods (second time), so that the ratio of “30%:70%” can be realized without modifying the hardware circuit.

[0096] From the accuracy guarantee, the value of x clock periods in the adjustment of the duty cycle can be dynamically calculated by “preset duty cycle multiplied by the total period number corresponding to the frequency” (such as 50KHz frequency total period number is 2000, and 30% duty cycle corresponds to x=2000x30%=600), and the calculation process only needs software programming without hardware intervention, which ensures the accuracy of the adjustment of the duty cycle.

[0097] Compared with the prior art ASIC, the duty cycle of the ASIC is fixed by internal hardware logic such as AND gates and OR gates, and if the duty cycle needs to be adjusted from 50% to 30%, the driving logic circuit must be redesigned; and the application can realize dynamic switching of the duty cycle through "modification of the OL pull-down timing (control signal) combined with x value calculation", highlighting the superiority of adjusting the working parameters based on the control signal and solving the pain points of fixed function and unchangeable working parameters of the traditional technology ASIC.

[0098] It should be noted that in the present drive system, the DDR read rate can be 100M, the clock frequency of the serial-parallel converter corresponds to 30M, and the LE signal frequency is obtained by frequency division according to the set value of the upper computer; the PL end of the FPGA realizes data read-write rate matching through the FIFO buffer unit, the FIFO is designed with 32-bit width and 16384 depth, data is written from the DDR using a fixed 100M clock, data is read to the serial-parallel converter using a 30M clock, and after each time 32-bit data is read, the LE signal output is completed, and the next reading is performed. When the playing frequency changes, the FPGA dynamically controls the data reading speed of the FIFO according to the playing frequency (i.e. the LE signal frequency), to ensure that the data output rhythm is consistent with the storage rhythm of the shift register group.

[0099] (5) Drive system reset: when resetting, the processor pulls up the reset signal RST, and triggers the rising edges of the clock signal CLK and the latch signal LE at the same time, to clear the data in the shift register group and the latch, so as to realize the reset and make the system return to the initial state.

[0100] (6) Signal logic screening and output state control: when the enable signal OE is high, the AND gate is turned on, and the data output by the latch is processed by the AND gate and then enters the high-voltage output buffer; when the enable signal OE is low, the output of the high-voltage output buffer is in a high-impedance state; the output signal of the latch and the forced high-level signal OH are processed by the NAND gate and then input to the first input end of the AND gate; the forced low-level signal OL is connected to the second input end of the AND gate; when the drive system detects an abnormality or needs to control the duty cycle, the forced low-level signal OL is an effective level OL=0, the AND gate is closed, the data transmission is cut off, and a low level is forced to be output; when the forced high-level signal OH is an effective level (OH=0), the NAND gate outputs a high level, the AND gate is turned on and outputs a high level; when the drive system works normally, the forced low-level signal and the forced high-level signal are both ineffective levels (OL=1, OH=1), and the AND gate outputs the signal processed by the NAND gate.

[0101] Specifically, the high resistance state (high impedance state) is the switch in the circuit is off: at this time the output of the high voltage output buffer neither output high (such as 80V), nor output low (such as 0V), but presents the open circuit state, equivalent to the digital sound chip between the sound unit is disconnected, will not have any voltage or current effect on it.

[0102] In a specific embodiment, the series-parallel converter containing 4 groups of 32-bit shift registers, 128-bit latch is taken as an example, the signal configuration rules, initial state, driving timing logic are further described.

[0103] Table 3: 16-way key signal configuration required for normal operation of series-parallel converter

[0104] (1) signal initialization before playing (after receiving the start playing command).

[0105] FPGA needs to adjust 3-way key signals first, so that the series-parallel converter switches from the initial state to the standby state: Release forced high / low level: OH=1, OL=1 (release the lock of "forced high level" and "forced low level", allow the high voltage output to change with data); Open output enable: OE=1 (make the high voltage output end of HV583 switch from high resistance state to effective output state, which can output high voltage driving signal subsequently).

[0106] (2) data transmission and timing control during playing.

[0107] FPGA transmits data to the series-parallel converter according to fixed timing to ensure synchronous output of 128-way high voltage signals: Data storage: on the rising edge of each CLK (clock signal), DnA (D1A~D4A) stores 1-bit data into the corresponding 32-bit shift register; Data latch output: every 32-bit data (corresponding to 1 group of complete subserial data) is stored, FPGA pulls up LE (latch signal) for 1 clock cycle, and then pulls it down. When LE is pulled up, 32-bit data in the 32-bit shift register is transmitted to the 128-bit latch synchronously, and finally output to the digital sound chip through the high voltage buffer, realizing 1-time pixel vibration driving.

[0108] (3) duty cycle control output interrupt logic.

[0109] The duty cycle adjustment is realized by an OL (forced low level) signal, and the high voltage output is interrupted to match the preset duty cycle: when the FPGA counts the "duty cycle stop playing part" (such as the no output period of 50% duty cycle), OL=0 (force all high voltage outputs to low level); at this time, whether there is data in the shift register or not, the HVOUT (output of the serial-parallel converter) outputs low level, realizes output interruption, and after the stop period ends, OL=1 is restored to normal output, forming a cycle of "output-interruption" (i.e. duty cycle control).

[0110] The embodiment has the following technical effects: 1) The multiple serial-parallel converters are independent and controlled by independent GPIO of the FPGA, without the need of designing a complex chip cascade circuit, reducing the number of hardware interfaces and wiring difficulty, and reducing the system failure rate. 2) The same CLK, LE and OE signals are shared by the serial-parallel converters, ensuring that all serial-parallel converters complete data reception, latching and high voltage output at the same timing, avoiding the synchronization difference of pixel vibration caused by the delay difference of control signals of multiple digital sound generation chips, and preventing audio distortion. 3) The FPGA controls each serial-parallel converter by independent GPIO, and can individually configure the data distribution logic of each serial-parallel converter (such as the difference of pixel driving requirements of different digital sound generation chips); at the same time, the unified control signal ensures synchronization, supports flexible expansion of multiple chips, and does not need to sacrifice driving consistency, solving the contradiction between difficult expansion and synchronization difference of traditional multiple chip driving.

[0111] The serial-parallel converter designed in the embodiment of the application needs to be distinguished from other types of serial-parallel converters in the field of digital sound generation, and the following is described.

[0112] For example, in the traditional technology, a multi-channel digital loudspeaker system also includes a serial-parallel converter, the front end of the system is connected to a sound field controller, the multi-channel parallel PCM signal is first converted into a single-channel high-speed serial data (the sampling rate is increased to L times) by the serial-parallel converter, then processed by a generalized encoder (converting PCM encoding to binary state encoding) and an extraction selector (selecting a single-channel encoded signal), and converted back to L parallel data by the serial-parallel converter; the back end is connected to a multi-channel digital power amplifier, and outputs a 1-bit wide, low voltage (such as 3.3V) parallel binary encoded signal to the power amplifier, which is finally amplified by the power amplifier to drive the loudspeaker array. The core function of this type of serial-parallel conversion unit is to reduce the number of transmission lines and reduce multi-channel signal interference through parallel-serial-parallel format conversion, and to realize beam directivity optimization and frequency response flatness correction with the sound field controller. The circuit structure takes data selector, clock frequency division and clock frequency multiplication unit as the core, without high voltage driving hardware and multi-channel synchronization control capability.

[0113] The series-parallel converter is specially adapted to the high-voltage driving requirement of the digital sound chip, front-end connection of the FPGA receives multi-channel sub-serial data and control signals output by 11 control pins, and rear-end direct connection of the digital sound chip outputs 128 channels of 80V high-voltage parallel driving signals. The core function is not only format conversion, but also integration of 4 groups of 32-bit shift registers + 128-bit latches, to realize few-pin control of multiple channels (for example, 11 control pins control 128 channels) and synchronous output of high-voltage signals, and support dynamic adjustment of playing frequency and duty cycle through LE / OL signals, to directly drive pixel diaphragm vibration sound.

[0114] In an optional embodiment, when the driving system drives multiple digital sound chips, the FPGA controls multiple series-parallel converters through different GPIO pins by hardware circuits; meanwhile, the FPGA outputs the same clock signal (CLK), latch signal (LE) and enable signal (OE) to each series-parallel converter to guarantee timing synchronization, and the data end distributes sub-serial data according to timing, to finally realize synchronous output of parallel high-voltage driving signals.

[0115] Referring to Figure 6 The embodiment of the present application also provides a driving method of the digital sound chip, which is applied to the driving system of the digital sound chip in any of the above embodiments, and can include the following steps. Step 610: The processor receives audio data, and outputs multi-channel sub-serial data and control signals to the series-parallel converter through a first number of output pins of the processor; Step 620: The series-parallel converter receives the multi-channel sub-serial data and control signals, dynamically adjusts working parameters based on the control signals, and converts the multi-channel sub-serial data into a second number of parallel high-voltage driving signals, to drive a second number of to-be-driven sound units in the digital sound chip; wherein the first number is less than the second number.

[0116] Although the present application is described herein in conjunction with various embodiments, other variations of the disclosed embodiments can be understood and implemented by those skilled in the art with reference to the attached drawings, disclosure, and appended claims in implementing the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. Measures described in mutually different dependent claims can be combined and produce beneficial results.

[0117] Although the present application has been described in connection with the preferred embodiments thereof with reference to the specific content thereof, it will be apparent to those skilled in the art that various modifications and changes can be made thereto without departing from the spirit and scope of the application. Accordingly, it is intended that the present application cover all such modifications and changes as fall within the scope of the application, along with all equivalents thereof. It will be understood by those within the art that, in general, terms used herein, and especially to the immediately preceding description and claims attached hereto, are intended to be given their broadest interpretation consistent with the specification and the patent statutes.

Claims

1. A driving system of a digital sound chip, characterized in that, At least comprising: a processor, a serial-parallel converter and a digital sound chip; a first number of output pins in the processor are connected with corresponding pins in the serial-parallel converter, and the processor is used at least for converting a received total serial data into multiple sub serial data; the serial-parallel converter is used for receiving the multiple sub serial data and a control signal output by the processor, dynamically adjusting working parameters based on the control signal, and converting the multiple sub serial data into a second number of parallel high-voltage driving signals to drive a second number of sound units to be driven in the digital sound chip; wherein the first number is less than the second number.

2. The driving system of a digital sound production chip according to claim 1, wherein, the serial-parallel converter comprises a shift register group, a latch, a logic gate control circuit and a high-voltage output buffer circuit; a data input end of the shift register group receives the multiple sub serial data; the shift register group is composed of N groups of M-bit shift registers, each group of M-bit shift registers corresponds to receive a sub serial data in the multiple sub serial data; the product of N and M is the second number; N and M are both positive integers, and M is the number of bits of each group of M-bit shift registers; a data output end of the shift register group is connected with a data input end of the latch; the latch is a second number of bit latches, the data input end of the latch corresponds to the data output end of the shift register group, and the total number of bits of the shift register group and the latch is the second number; a data output end of the latch is connected with an input end of the logic gate control circuit, and an output end of the logic gate control circuit is connected with an input end of the high-voltage output buffer circuit.

3. The driving system of the digital sound production chip according to claim 2, wherein, the high-voltage output buffer circuit comprises a second number of high-voltage output buffers, each high-voltage output buffer in the second number of high-voltage output buffers is built-in push-pull output circuit, and the push-pull output circuit is used for converting a low-level signal output by the logic gate control circuit into a high-voltage driving signal.

4. The driving system of the digital sound production chip according to claim 3, wherein, the logic gate control circuit comprises a second number of logic gates; each group of logic gates in the second number of logic gates is connected with an output end of the second number of bit latches; each group of logic gates comprises a NAND gate and an AND gate; a first input end of the NAND gate is connected with a corresponding output end of the latch, and a second input end of the NAND gate is connected with a forced high-level signal; an output end of the NAND gate is connected with a first input end of the AND gate, and a second input end of the AND gate is connected with a forced low-level signal; an output end of the AND gate is connected with a level signal input end of a corresponding high-voltage output buffer, and an enable signal input end of the high-voltage output buffer is connected with an enable signal.

5. The driving system of the digital sound production chip according to claim 4, wherein, the control signal at least comprises a clock signal and a latch signal; and the working parameters at least comprise a playing frequency; the processor periodically pulls up the latch signal, so that each time the latch signal generates a rising edge, the serial-parallel converter executes an output according to the data in the current M-bit shift register, and the playing frequency is consistent with the pull-up frequency of the latch signal; The clock signal completes M-bit data transmission in a single latch cycle.

6. The driving system of a digital sound chip according to claim 5, wherein, The control signal further comprises a forced low signal; The processor controls the serial-parallel converter to output parallel high-voltage driving signals to the digital sound production chip for a first time length according to a preset duty cycle, and then pulls the forced low signal low to make all the parallel high-voltage driving signals low to interrupt the output for a second time length; wherein the ratio of the first time length to the second time length matches the preset duty cycle.

7. The driving system of the digital sound production chip according to claim 5, wherein, The control signal further comprises a reset signal; When reset, the processor pulls the reset signal high, and triggers the rising edges of the clock signal and the latch signal once to clear the data in the shift register group and the latch to achieve reset.

8. The driving system of the digital sound production chip according to claim 5, wherein, The control signal further comprises an enable signal and a forced high signal; When the enable signal is high, the AND gate is turned on, and the data output by the latch is input into the high-voltage output buffer after logical processing by the AND gate; when the enable signal is low, the output of the high-voltage output buffer is in a high-impedance state. The output signal of the latch and the forced high signal are input into the first input end of the AND gate after logical processing by the NAND gate; the forced low signal is input into the second input end of the AND gate; When the driving system detects an abnormality or needs to control the duty cycle, the forced low signal is at an effective level, the AND gate is closed, the data transmission is cut off, and a low level is forced to be output; when the forced high signal is at an effective level, the NAND gate outputs a high level, the AND gate is turned on, and a high level is output. When the driving system is working normally, the forced low signal and the forced high signal are both at invalid levels, and the AND gate outputs the signal processed by the NAND gate.

9. The driving system of a digital sound chip according to claim 2, wherein, The second number is 128; The shift register group comprises four groups of 32-bit shift registers; the four groups of 32-bit shift registers share one clock signal input end, one reset signal input end, and one direction signal input end, and each group of 32-bit shift registers has one data input end and 32 data output ends; The latch is a 128-bit latch; the 128 data input ends of the 128-bit latch correspond to the 128 data output ends of the shift register group one by one.

10. A driving method of a digital sound chip, applied to the driving system of the digital sound chip of claim 1, characterized in that, The method comprises: The processor receives audio data, and outputs multiple sub-serial data and control signals to the serial-parallel converter through a first number of output pins of the processor; The serial-parallel converter receives the multiple sub-serial data and the control signals, dynamically adjusts working parameters based on the control signals, and converts the multiple sub-serial data into a second number of parallel high-voltage driving signals to drive a second number of sound production units to be driven in the digital sound production chip; wherein the first number is less than the second number.

Images