MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure, power semiconductor device and manufacturing method of MOSFET structure
By integrating a split trench gate structure and a Schottky junction in SiC MOSFET devices, the bipolar degradation effect caused by body diode turn-on is solved, improving switching characteristics and reverse conduction capability, and achieving cell refinement and area utilization efficiency.
Patent Information
- Application Number
- CN202410470800.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-18
- Publication Date
- 2025-11-04
AI Technical Summary
The body diode of SiC MOSFET devices turns on during reverse freewheeling, causing bipolar degradation, and existing solutions cannot achieve further cell refinement and reduce parasitic capacitance.
It adopts a split trench gate structure, integrates a Schottky junction, reduces the coupling area between the gate and drain, lowers the gate-drain parasitic capacitance, and suppresses the body diode turn-on in reverse conduction mode.
It improves switching characteristics, reduces power consumption, enhances reverse conduction capability and chip reliability, achieves cell refinement, and increases the effective usable area.
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Figure CN120897481A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor technology, in particular to a MOSFET structure, a power semiconductor device and a manufacturing method of the MOSFET structure. BACKGROUND
[0002] SiC material has advantages of wide band gap, high thermal conductivity, high breakdown field strength, high saturation velocity and the like, and is very suitable for manufacturing high-temperature and high-power semiconductor devices. SiC-based power devices can greatly exert the characteristics of high temperature, high frequency and low loss, so that they have great application prospects in high voltage, high temperature, high frequency, high power and strong radiation and the like. In particular, SiC power MOSFET devices have been commercialized by many manufacturers.
[0003] With the improvement of use requirements, N-channel SiC MOSFET gradually develops from a planar structure to a trench structure; however, both the planar structure and the trench structure have a parasitic PIN body diode, which is turned on during reverse current conduction of the chip, causing a "bipolar degradation effect". At present, the most effective solution is to integrate an SBD diode in the chip cell, however, such a design must reserve a key dimension of the SBD in the source region, and cannot achieve further refinement of the cell. In addition, in order to achieve higher electric energy conversion efficiency, reducing the parasitic capacitance (especially the gate-drain capacitance CGD) in the SiC MOSFET structure has always been a research hotspot in the industry. SUMMARY
[0004] Therefore, the embodiments of the present application provide a MOSFET structure, a power semiconductor device and a manufacturing method of the MOSFET structure, which solve the problem that the SiC MOSFET trench structure has a parasitic PIN body diode, which is turned on during reverse current conduction of the chip, causing a "bipolar degradation effect".
[0005] In a first aspect, an embodiment of the present application provides a MOSFET structure, comprising:
[0006] a substrate, a first epitaxial layer located on an upper surface of the substrate;
[0007] a first conductive type well region and a second conductive type doping layer formed in sequence on an upper surface of the first epitaxial layer;
[0008] a split gate metal layer penetrating through the first conductive type well region, the second conductive type doping layer and the first epitaxial layer, wherein the split gate metal layer extends to a preset depth in a direction from an upper surface of the first epitaxial layer to the substrate;
[0009] an isolation dielectric layer, a gate layer and a gate oxide layer formed in sequence on a side wall of the split gate metal layer;
[0010] a Schottky junction layer extending from the bottom of the split gate metal layer to the inside of the first epitaxial layer by a preset depth.
[0011] In one embodiment, the MOSFET structure comprises: the electric field shielding layer wrapped on the bottom and part of the sidewall of the Schottky junction layer, part of the isolation medium layer, the gate layer, the gate oxide layer, the split gate metal layer, and the Schottky junction layer.
[0012] In one embodiment, the MOSFET structure comprises: the source ohmic layer formed on part of the top surface of the second conductive type doped layer.
[0013] The source layer is formed on the source ohmic layer, the first interlayer dielectric layer, and part of the second conductive type doped layer.
[0014] In one embodiment, the bottom surface of the substrate forms a drain.
[0015] In one embodiment, the MOSFET is a silicon carbide metal oxide semiconductor field effect transistor.
[0016] In a second aspect, an embodiment of the present application provides a power semiconductor device, comprising the MOSFET structure described above.
[0017] In a third aspect, an embodiment of the present application provides a manufacturing method of a MOSFET structure, comprising:
[0018] providing a substrate, and forming a first epitaxial layer on the substrate;
[0019] performing ion implantation on the top surface of the first epitaxial layer to form a first conductive type well region in part of the first epitaxial layer;
[0020] forming a second conductive type doped layer on the top surface of the first conductive type well region;
[0021] forming a first trench on the second conductive type doped layer, the first conductive type well region, and the first epitaxial layer; the first trench penetrates the second conductive type doped layer and the first conductive type well region, and extends to the first epitaxial layer by a preset depth in the direction of the substrate;
[0022] performing ion implantation on the bottom of the first trench to form an electric field shielding layer, the electric field shielding layer extending to the first epitaxial layer by a preset depth in the direction of the substrate;
[0023] forming a gate oxide layer in the inside and bottom of the first trench, and forming a gate layer on the gate oxide layer at the bottom of the first trench, the gate layer filling in the first trench;
[0024] forming a source ohmic layer on a part of the upper surface of the second conductive type doped layer;
[0025] forming a polysilicon layer on the source ohmic layer, the gate oxide layer, the gate layer and the second conductive type doped layer;
[0026] etching the polysilicon layer, the gate layer, the gate oxide layer and the first epitaxial layer to form a second trench, the second trench extending through the polysilicon layer, the gate layer and the gate oxide layer and extending a preset depth from the upper surface of the first epitaxial layer towards the substrate, the width of the second trench being smaller than the width of the first trench;
[0027] forming an isolation medium layer on the sidewall of the second trench;
[0028] forming a third trench in the bottom of the second trench, and forming a Schottky alloy layer in the third trench, the Schottky alloy layer extending a preset depth from the bottom of the second trench towards the first epitaxial layer;
[0029] filling a split gate metal layer in the second trench;
[0030] forming a first interlayer dielectric layer on the gate oxide layer, the gate layer, the isolation medium layer, the split gate metal layer and a part of the second conductive type doped layer;
[0031] forming a source layer on the source ohmic layer, the first interlayer dielectric layer and a part of the second conductive type doped layer;
[0032] forming a drain on the side of the substrate away from the first epitaxial layer.
[0033] In one embodiment, the method for manufacturing a MOSFET structure includes:
[0034] coating a photoresist on the first trench and the upper surface of the part of the second conductive type doped layer, and performing photoetching on the photoresist to form a first photoetching pattern;
[0035] performing ion implantation with the photoresist having the first photoetching pattern as a mask to form the electric field shielding layer in the region where the electric field shielding layer is needed.
[0036] In one embodiment, the method for manufacturing a MOSFET structure includes:
[0037] forming a gate layer on the gate oxide layer at the bottom of the first trench, the gate layer filling the first trench;
[0038] before the forming of the source ohmic layer on the partial region of the upper surface of the second conductive type doped layer, further comprising: removing the gate layer and the gate oxide layer on the first epitaxial layer.
[0039] In one embodiment, the forming of the source ohmic layer on the partial region of the upper surface of the second conductive type doped layer comprises:
[0040] forming a second interlayer dielectric layer on the second conductive type doped layer, the gate oxide layer and the gate layer;
[0041] performing etching on the second interlayer dielectric layer to form a first opening, the first opening being located on a partial upper surface of the second conductive type doped layer;
[0042] performing sputtering process and annealing at the bottom of the first opening to form a source ohmic layer.
[0043] In one embodiment, the forming of the isolation dielectric layer on the sidewall of the second trench comprises:
[0044] depositing isolation dielectric material on the upper surface of the polysilicon layer, the sidewall and the bottom of the second trench;
[0045] removing the isolation dielectric material on the upper surface and the bottom of the second trench to form an isolation dielectric layer.
[0046] In one embodiment, the performing of sputtering process at the bottom of the second trench to form a Schottky alloy layer comprises: sputtering titanium metal on the upper surface of the polysilicon layer and the bottom of the second trench and performing annealing process;
[0047] the filling of the split gate metal layer in the second trench comprises: forming a split gate metal layer in the second trench and on the titanium metal;
[0048] before the filling of the split gate metal layer in the second trench, comprising: removing the titanium metal on the upper surface of the polysilicon layer and the split gate metal layer.
[0049] In one embodiment, the forming of the first interlayer dielectric layer on the gate oxide layer, the gate layer, the isolation dielectric layer, the split gate metal layer and a partial region of the second conductive type doped layer comprises:
[0050] forming a first interlayer dielectric material on the gate oxide layer, the gate layer, the isolation dielectric layer, the split gate metal layer and part of the second conductive type doped layer;
[0051] forming a second opening on the first interlayer dielectric material to form a first interlayer dielectric layer; wherein the second opening exposes the source.
[0052] In an embodiment, the substrate is a silicon carbide substrate.
[0053] The MOSFET structure, the power semiconductor device and the manufacturing method of the MOSFET structure provided by the embodiments of the present application can reduce the coupling area of the gate and the drain, directly reduce the gate-drain parasitic capacitance CGD, improve the switching characteristic and reduce the power consumption; meanwhile, the Schottky junction is integrated in the split gate region, which can inhibit the opening of the SiC MOSFET body diode in the reverse conduction mode, improve the reverse conduction capability and the reverse recovery characteristic, and improve the chip reliability; the Schottky junction is integrated in the gate split region, which can realize the cell refinement and improve the effective use area of the chip cell. BRIEF DESCRIPTION OF DRAWINGS
[0054] Figures 1-15 Fig. 1 shows a flow chart of a manufacturing method of a MOSFET structure provided by an embodiment of the present application.
[0055] Figure 16 Fig. 2 shows a schematic diagram of a MOSFET structure provided by an embodiment of the present application.
[0056] Figure 17 Fig. 3 shows a schematic diagram of a MOSFET structure provided by another embodiment of the present application.
[0057] Figure 18 Fig. 4 shows a schematic diagram of a MOSFET structure provided by another embodiment of the present application. DETAILED DESCRIPTION
[0058] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.
[0059] In an embodiment, the MOSFET structure is as shown in Fig. 2. Figure 15As shown, the MOSFET structure comprises: a substrate 01, a first epitaxial layer 02 on the upper surface of the substrate 01, a first conductive type well region 03 and a second conductive type doped layer 04 formed in sequence on the upper surface of the first epitaxial layer 02, a split gate metal layer 05 penetrating the first conductive type well region 03, the second conductive type doped layer 04 and the first epitaxial layer 02, wherein the split gate metal layer 05 extends from the upper surface of the first epitaxial layer 02 to the substrate 01 by a preset depth, an isolation medium layer 06, a gate layer 07 and a gate oxide layer are formed in sequence on the sidewall of the split gate metal layer 05, and a Schottky junction layer extends from the bottom of the split gate metal layer 05 to the inside of the first epitaxial layer 02 by a preset depth.
[0060] It can be understood that the MOSFET structure can be a silicon carbide metal oxide semiconductor field effect transistor, or the type of the MOSFET structure can be selected, and the type of the MOSFET structure is not limited in the application.
[0061] In an embodiment of the application, the bottom and part of the sidewall of the split gate metal layer 05, the isolation medium layer 06, the gate layer 07, the gate oxide layer, and part of the Schottky junction layer are wrapped to form the electric field shielding layer 13.
[0062] In an embodiment of the application, part of the upper surface of the second conductive type doped layer 04 is formed with a source ohmic layer 09, and the source ohmic layer 09, the first interlayer dielectric layer 10 and part of the second conductive type doped layer 04 are formed with a source layer 11.
[0063] In an embodiment of the application, the lower surface of the substrate 01 is formed with a drain 12.
[0064] In an embodiment of the application, a MOSFET structure is provided, which is provided with three trenches (a first trench, a second trench and a third trench) with different widths and depths from top to bottom at the gate trench, and a split gate metal is designed in the first trench center region and the second trench from top to bottom, and a Schottky junction is designed in the third trench. Compared with the source integrated Schottky junction, the structure can realize cell refinement and save the effective area of the chip cell. In addition, the second and third trenches with reduced width can increase the current channel in the lateral direction and improve the chip current carrying capacity.
[0065] Meanwhile, the split gate metal in the first trench center region and the second trench is separated from the gate by an isolation medium, and the split gate metal is interconnected with the source to the ground. This design reduces the coupling area of the gate bottom and the drain 12, directly reduces the gate-drain parasitic capacitance CGD, improves the switching characteristics, and reduces the device power consumption.
[0066] And, the Schottky junction designed in the third trench is connected with the split gate metal to ground, which not only forms a depletion extension layer to protect the trench gate oxide in the positive bias, but also has excellent freewheeling effect in the reverse bias, avoiding the opening of the device body diode and improving the reliability of the device.
[0067] In addition, the electrode lead-out design of the trench gate and the split gate metal is as shown in Figure 8 and Figure 18 The lengths of the first trench and the second trench (including the third trench) are designed to be staggered, and the gate lead-out metal and the split gate lead-out metal are independently led out at both ends, avoiding mutual contact of the two electrodes.
[0068] The embodiment provides a manufacturing method of a MOSFET structure, and the manufacturing method of the MOSFET structure comprises the following steps: Figures 1-15 as shown in the drawings, the manufacturing method of the MOSFET structure comprises the following steps:
[0069] Step 01: providing a substrate 01, and forming a first epitaxial layer 02 on the substrate 01.
[0070] The substrate 01 is a silicon carbide substrate 01.
[0071] Optionally, the substrate 01 is a high-concentration N+ substrate, and the concentration is greater than 5E18 cm -3 ; the first epitaxial layer 02 is a relatively thin N-type drift region, the drift region has a concentration of about 1E14-5E16 cm-3, and the drift region concentration and thickness need to be optimized according to the chip voltage resistance, and the present application does not limit this.
[0072] Step 02: performing ion implantation on the upper surface of the first epitaxial layer 02 to form a first conductivity type well region 03 in part of the first epitaxial layer 02.
[0073] Step 03: forming a second conductivity type doped layer 04 on the upper surface of the first conductivity type well region 03.
[0074] Based on steps 02 and 03, the P-well and N+ implantation are sequentially performed on the first epitaxial layer 02 to form the first conductivity type well region 03 and the second conductivity type doped layer 04. Optionally, the first conductivity type well region 03 is P-type doped, the concentration of the first conductivity type well region 03 ranges from 1E16 to 1E18 cm-3, and the junction depth is set to 0.5-1.5 μm at the surface; the second conductivity type doped layer 04 is an N+ source region, and the concentration of the second conductivity type doped layer 04 is greater than 1E19 cm-3, and the junction depth is set to 0.2-0.5 μm.
[0075] In addition, P+ can be implanted on the second conductive type doped layer 04 to form a first conductive type doped layer, wherein the doping concentration of the first conductive type doped layer is greater than 1E18 cm-3, and the junction depth is set to 0.5-0.8 μm.
[0076] Step 04: Form a first trench on the second conductive type doped layer 04, the first conductive type well region 03, and the first epitaxial layer 02; the first trench penetrates the second conductive type doped layer 04 and the first conductive type well region 03, and extends to a preset depth on the surface of the first epitaxial layer 02 in the direction of the substrate 01.
[0077] Optionally, the first trench is about 1-2 μm, and the trench width is about 0.5 μm-2 μm. An etching mask can be reserved after etching.
[0078] Step 05: Perform ion implantation at the bottom of the first trench to form an electric field shielding layer 13, which extends to a preset depth in the direction of the first epitaxial layer 02 at the bottom of the first trench.
[0079] Further, the ion implantation at the bottom of the first trench to form the electric field shielding layer 13 comprises:
[0080] Step 051: Apply photoresist in the first trench and on the upper surface of part of the second conductive type doped layer 04, and perform photoetching on the photoresist to form a first photoetching pattern.
[0081] Step 052: Perform ion implantation with the photoresist with the first photoetching pattern as a mask to form the electric field shielding layer 13 in the region where the electric field shielding layer 13 is needed.
[0082] It can be understood that the photoresist is used as an implantation mask, and then P+ ion implantation is performed on the region where the three-dimensional direction discontinuous electric field shielding layer 13 is needed to form the electric field shielding layer 13.
[0083] Optionally, the P+ ion implantation concentration of the electric field shielding layer 13 is greater than 1E18 cm-3, and the junction depth is >2 μm. In the implantation stage, 4 times of oblique implantation is needed, which is upward, downward, leftward, and rightward implantation, and the oblique angles of the 4 times of oblique implantation are consistent: the included angle with the horizontal direction is 70°-85°. The implantation schematic diagram and the formation effect are shown in Figure 2 .
[0084] The technical route of first groove etching and then inclined injection can obtain a deeper P+ junction depth under the same ion injection energy condition, and has a better trench bottom electric field shielding effect. Meanwhile, the multi-angle inclined injection scheme can obtain a P+ junction with a more uniform ion concentration distribution in three-dimensional directions at the trench bottom, which can further improve the trench protection effect and improve the device reliability.
[0085] Step 06: forming a gate oxide layer 08 in the inside and bottom of the first trench, and forming a gate layer 07 on the gate oxide layer 08 at the bottom of the first trench, the gate layer 07 filling in the first trench.
[0086] Step 07: forming a source ohmic layer 09 on a part of the upper surface of the second conductive type doped layer 04.
[0087] Based on steps 06 and 07, optionally, a C film is used for protection, ion activation is performed under a high temperature condition of 1800℃, and the thickness of the C film is >100nm. After completion, high-temperature gate oxidation, gate filling, and backside drain 12 ohmic alloy processes are respectively performed.
[0088] The gate oxide layer 08 is formed on the first epitaxial layer 02 in the inside and bottom of the first trench. The gate layer 07 is formed on the gate oxide layer 08 at the bottom of the first trench and the first epitaxial layer 02, and the gate layer 07 fills in the first trench. Therefore, before the source ohmic layer 09 is formed on a part of the upper surface of the second conductive type doped layer 04, the gate layer 07 and the gate oxide layer 08 on the first epitaxial layer 02 are also removed.
[0089] Further, the source ohmic layer 09 is formed on a part of the upper surface of the second conductive type doped layer 04, including:
[0090] Step 071: forming a second interlayer dielectric layer on the second conductive type doped layer 04, the gate oxide layer 08, and the gate layer 07.
[0091] Step 072: etching the second interlayer dielectric layer to form a first opening, the first opening being located on a part of the upper surface of the second conductive type doped layer 04.
[0092] Step 073: performing a sputtering process and annealing at the bottom of the first opening to form a source ohmic layer 09.
[0093] It can be understood that the CMP (Chemical-Mechanical Planarization) process is used to remove the gate layer 07 and the gate oxide layer 08 on the top of the trench, and a second interlayer dielectric layer is deposited, a selective first opening is etched on the second interlayer dielectric layer, Ni metal is sputtered and annealed to form a source ohmic alloy.
[0094] Step 08: Form a polysilicon layer (POLY) on the source ohmic layer 09, the gate oxide layer 08, the gate layer 07 and the second conductivity type doped layer 04.
[0095] It can be understood that the CMP process is used again to remove the second interlayer dielectric on the top of the trench, and a polysilicon layer is formed on the surface by the PVD (Physical Vapor Deposition) process.
[0096] Step 09: Etch the polysilicon layer, the gate layer 07, the gate oxide layer 08 and the first epitaxial layer 02 to form a second trench, the second trench penetrates the polysilicon layer, the gate layer 07 and the gate oxide layer 08, and extends a predetermined depth on the surface of the first epitaxial layer 02 towards the substrate 01 direction, the width of the second trench is smaller than the width of the first trench.
[0097] Optionally, an etching mask is used to etch the trench to form a second trench.
[0098] Step 10: Form an isolation dielectric layer 06 on the sidewall of the second trench.
[0099] Further, the isolation dielectric layer 06 formed on the sidewall of the second trench comprises:
[0100] Step 101: Deposit an isolation dielectric material on the upper surface of the polysilicon layer, the sidewall and the bottom of the second trench.
[0101] Step 102: Remove the isolation dielectric material on the upper surface and the bottom of the second trench to form an isolation dielectric layer 06.
[0102] Step 11: Form a third trench at the bottom of the second trench, form a Schottky alloy layer 14 in the third trench, and the third trench extends a predetermined depth in the direction of the first epitaxial layer 02 at the bottom of the second trench.
[0103] Step 12: Fill the split gate metal layer 05 in the second trench.
[0104] Optionally, the material of the split gate metal layer 05 is SiO2 dielectric or the like; using SiO2 dielectric can further reduce the gate-source capacitance and reduce the charging and discharging time of the device switching process. The split gate metal layer 05 in the split gate metal layer 05 can also be replaced by other materials, and the present application does not limit the material of the split gate metal layer 05.
[0105] Optionally, since SiO2 dielectric is not conductive, when the Schottky alloy layer 14 is connected to the ground, the split gate metal layer 05 needs to be directly connected to the Schottky alloy layer 14, so the SiO2 dielectric needs to be regionally etched to expose the Schottky alloy layer 14, as shown in Figure 18
[0106] In the third trench, the Schottky alloy layer 14 is formed, including: sputtering titanium metal in the third trench and performing annealing treatment; the split gate metal layer 05 is filled in the second trench, including: forming the split gate metal layer 05 in the second trench and on the titanium metal; before filling the split gate metal layer 05 in the second trench, including: removing the titanium metal on the upper surface of the polysilicon layer and the split gate metal layer 05.
[0107] Based on steps 09-12, it can be understood that the polysilicon layer, the gate layer 07, the gate oxide layer 08 and the first epitaxial layer 02 are etched using an etching mask to form a second trench, as shown in Figure 8 After removing the etching mask, a layer of SiO2 dielectric is deposited, as shown in Figure 9 SiO2 self-alignment etching is performed to remove the SiO2 on the surface and the bottom of the trench to form an isolation dielectric layer 06, as shown in Figure 10 A layer of Ti metal is sputtered and annealed to form a Schottky alloy layer 14 at the bottom of the trench, as shown in Figure 11 The split gate metal layer 05 is filled in the trench by PVD process, as shown in Figure 12 Finally, the polysilicon layer, the Schottky alloy layer 14 and the split gate metal layer 05 on the surface of the trench are removed by CMP process, as shown in Figure 13
[0108] Step 13: Forming a first interlayer dielectric layer 10 on the gate oxide layer 08, the gate layer 07, the isolation dielectric layer 06, the split gate metal layer 05 and part of the second conductive type doped layer 04.
[0109] Further, the first interlayer dielectric layer 10 is formed on the gate oxide layer 08, the gate layer 07, the isolation dielectric layer 06, the split gate metal layer 05 and part of the second conductive type doped layer 04, including:
[0110] Step 131: forming a first interlayer dielectric material on the gate oxide layer 08, the gate layer 07, the isolation dielectric layer 06, the split gate metal layer 05 and part of the second-conductivity-type doped layer 04.
[0111] Step 132: forming a second opening on the first interlayer dielectric material to form a first interlayer dielectric layer 10; wherein the second opening exposes the source electrode.
[0112] Based on the above steps, it can be understood that, by the process flow of Figures 7-13 , the second and third trenches can be formed on the structure of Figure 6 , and the Schottky alloy layer 14, the split gate metal layer 05 and the isolation dielectric layer 06 can be formed to isolate the gate and the split gate metal layer 05, as shown in Figure 14 .
[0113] Step 14: forming a source layer 11 on the source ohmic layer 09, the first interlayer dielectric layer 10 and part of the second-conductivity-type doped layer 04.
[0114] Step 15: forming a drain 12 on the substrate 01 away from the first epitaxial layer 02.
[0115] The finally formed MOSFET structure can refer to Figure 15 .
[0116] The embodiment provides a power semiconductor device, which comprises the MOSFET structure described in any one of the above embodiments.
[0117] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the above-described device embodiment is merely illustrative, and the division of the units is merely a logical function division, and there can be another division manner in actual implementation, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms. The units described as separated components can or can not be physical separate units, and the units shown as components can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purposes of the embodiments.
[0118] The present application has the following beneficial effects:
[0119] Beneficial effect 1: the third groove is formed by using a self-aligned etching process, which can improve the overlay accuracy; meanwhile, the self-aligned etching mask is used as an isolation medium of the split gate POLY, thereby saving manufacturing processes.
[0120] Beneficial effect 2: the trench bottom electric field shielding layer 13 is formed by using a method of trench etching first and then rotating and inclined implantation, which can obtain an implantation effect of a deeper junction depth and a more uniform concentration distribution, thereby further improving the device reliability.
[0121] Beneficial effect 3: the trench gate oxide, the front and back ohmic alloy, and the Schottky alloy processes are sequentially completed by using a process sequence of high temperature first and then low temperature, thereby avoiding the influence of temperature effects on various processes and structures.
[0122] The above describes the basic principles of the present application in combination with specific embodiments, but it should be pointed out that the advantages, advantages, effects and the like mentioned in the present application are only examples and are not limited, and these advantages, advantages, effects and the like cannot be considered as the must-have of each embodiment of the present application. In addition, the above specific details are only for the purpose of example and for the purpose of understanding, and are not limited to the above specific details, and the above specific details do not limit the present application to be implemented by using the above specific details.
[0123] The block diagrams of the devices, apparatuses, equipment, systems involved in the present application are only illustrative examples and are not intended to require or imply the connection, arrangement, configuration shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, equipment, systems can be connected, arranged, configured in any way.
[0124] It should also be pointed out that in the devices, equipment and methods of the present application, each component or each step can be decomposed and / or recombined. These decompositions and / or recombination should be considered as equivalent solutions of the present application.
[0125] The above description of the disclosed aspects is provided so that any person skilled in the art can make or use the present application. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of the present application. Therefore, the present application is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.
[0126] In the description of the present application, the meaning of "a plurality" is at least two, for example, two, three, and the like, unless otherwise explicitly and specifically limited. All directional indications, such as upper, lower, left, right, front, rear, top, bottom, and the like, are used with respect to the orientation of the figure as shown in the respective figure, and are not meant to limit the position of the component relative to the orientation of the figure in which the component is shown. In addition, the terms "comprise", "comprising", "have", "having", "include", "including", "contain", "containing", and any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or apparatus that comprises a list of steps or units is not limited to the listed steps or units, but can optionally further include additional steps or units not listed, or can optionally further include steps or units inherent to the process, method, system, product, or apparatus.
[0127] In addition, reference herein to "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. It is expressly understood that the embodiments described herein are merely examples from a multitude of possible embodiments and are not meant to limit the application in any way.
[0128] The above description is only the preferred embodiment of the application, but the protection scope of the application is not limited to this. Any skilled person in the art can easily think of changes or replacements within the technical range disclosed by the application, which should be covered by the protection scope of the application. Therefore, the protection scope of the application should be subject to the protection scope of the claims. The above description is only the preferred embodiment of the application, but the protection scope of the application is not limited to this. Any skilled person in the art can easily think of changes or replacements within the technical range disclosed by the application, which should be covered by the protection scope of the application. Therefore, the protection scope of the application should be subject to the protection scope of the claims. The above description is only the preferred embodiment of the application, but the protection scope of the application is not limited to this. Any skilled person in the art can easily think of changes or replacements within the technical range disclosed by the application, which should be covered by the protection scope of the application. Therefore, the protection scope of the application should be subject to the protection scope of the claims.
Claims
1. A MOSFET structure, characterized in that, include: Substrate, and a first epitaxial layer located on the upper surface of the substrate; A first conductivity type well region and a second conductivity type doped layer are sequentially formed on the upper surface of the first epitaxial layer; A split gate metal layer extends through the first conductivity type well region, the second conductivity type doped layer, and the first epitaxial layer, wherein the split gate metal layer extends a predetermined depth from the upper surface of the first epitaxial layer toward the substrate. An isolation dielectric layer, a gate layer, and a gate oxide layer are sequentially formed on the sidewall of the split gate metal layer. The Schottky junction layer extends from the bottom of the split gate metal layer into the interior of the first epitaxial layer to a predetermined depth.
2. The MOSFET structure according to claim 1, characterized in that, include: The electric field shielding layer is formed on the bottom and part of the sidewalls of the isolation dielectric layer, the gate layer, the gate oxide layer, the split gate metal layer, and the Schottky junction layer.
3. The MOSFET structure according to claim 1, characterized in that, include: An active ohmic layer is formed on a portion of the upper surface of the second conductivity type doped layer; A source layer is formed on the source ohmic layer, the first interlayer dielectric layer, and a portion of the second conductivity type doped layer.
4. The MOSFET structure according to claim 1, characterized in that, A drain electrode is formed on the lower surface of the substrate.
5. The MOSFET structure according to claim 1, characterized in that, The MOSFET is a silicon carbide metal oxide semiconductor field-effect transistor.
6. A power semiconductor device, characterized in that, The MOSFET structure includes any one of claims 1 to 5.
7. A method for fabricating a MOSFET structure, characterized in that, include: A substrate is provided, and a first epitaxial layer is formed on the substrate; Ion implantation is performed on the upper surface of the first epitaxial layer to form a first conductivity type well region in a portion of the first epitaxial layer; A second conductivity type doped layer is formed on the upper surface of the well region of the first conductivity type; A first trench is formed on the second conductivity type doped layer, the first conductivity type well region, and the first epitaxial layer; The first trench penetrates the second conductivity type doped layer and the first conductivity type well region, and extends to a predetermined depth on the upper surface of the first epitaxial layer toward the substrate. Ion implantation is performed at the bottom of the first trench to form an electric field shielding layer, which extends to a predetermined depth from the bottom of the first trench toward the first epitaxial layer. A gate oxide layer 08 is formed inside and at the bottom of the first trench, and a gate layer is formed on the gate oxide layer 08 located at the bottom of the first trench, the gate layer filling the first trench; A source ohmic layer is formed in a portion of the upper surface of the second conductivity type doped layer; A polysilicon layer is formed on the source ohmic layer, the gate oxide layer 08, the gate layer, and the second conductivity type doped layer; The polysilicon layer, the gate layer, the gate oxide layer 08, and the first epitaxial layer are etched to form a second trench. The second trench penetrates the polysilicon layer, the gate layer, and the gate oxide layer 08, and extends to a predetermined depth on the upper surface of the first epitaxial layer toward the substrate. The width of the second trench is smaller than the width of the first trench. An isolation medium layer is formed on the sidewall of the second trench; A third trench is formed at the bottom of the second trench, and a Schottky alloy layer 14 is formed in the third trench. The third trench extends to a predetermined depth from the bottom of the second trench toward the first epitaxial layer. The second trench is filled with a split gate metal layer; A first interlayer dielectric layer is formed on the gate oxide layer 08, the gate layer, the isolation dielectric layer, the split gate metal layer, and a portion of the second conductivity type doped layer; A source layer is formed on the source ohmic layer, the first interlayer dielectric layer, and a portion of the second conductivity type doped layer; A drain electrode is formed on the side of the substrate away from the first epitaxial layer.
8. The method for fabricating the MOSFET structure according to claim 7, characterized in that, The step of forming an electric field shielding layer by ion implantation at the bottom of the first trench includes: Photoresist is coated in the first trench and on the upper surface of the portion of the second conductivity type doped layer, and the photoresist is photolithographically developed to form a first photolithographic pattern. Ion implantation is performed using the photoresist with the first photolithographic pattern as a mask to form the electric field shielding layer in the region where the electric field shielding layer needs to be formed.
9. The method for fabricating the MOSFET structure according to claim 7, characterized in that, The step of forming a gate oxide layer inside and at the bottom of the first trench includes: forming a gate oxide layer inside and at the bottom of the first trench, and on the first epitaxial layer; The step of forming a gate layer on the gate oxide layer located at the bottom of the first trench, the gate layer filling the first trench, includes: forming a gate layer on the gate oxide layer at the bottom of the first trench and on the first epitaxial layer, the gate layer filling the first trench; Before forming a source ohmic layer in a portion of the upper surface of the second conductivity type doped layer, the method further includes: removing the gate layer and the gate oxide layer on the first epitaxial layer.
10. The method for fabricating the MOSFET structure according to claim 7, characterized in that, The formation of a source ohmic layer in a portion of the upper surface of the second conductivity type doped layer includes: A second interlayer dielectric layer is formed on the second conductivity type doped layer, the gate oxide layer, and the gate layer; The second interlayer dielectric layer is etched to form a first opening, the first opening being located on a portion of the upper surface of the second conductivity type doped layer; A sputtering process is performed at the bottom of the first opening, followed by annealing, to form a source ohmic layer.
11. The method for fabricating the MOSFET structure according to claim 7, characterized in that, The step of forming an isolation medium layer on the sidewall of the second trench includes: An insulating dielectric material is deposited on the upper surface of the polycrystalline silicon layer, the sidewalls of the second trench, and the bottom. Remove the insulating medium material from the upper surface and the bottom of the second trench to form an insulating medium layer.
12. The method for fabricating the MOSFET structure according to claim 7, characterized in that, Forming a Schottky alloy layer in the third trench includes: sputtering titanium metal in the third trench and performing an annealing treatment; The step of filling the second trench with a split gate metal layer includes: forming a split gate metal layer in the second trench and on the titanium metal; Before filling the split gate metal layer in the second trench, the process includes: removing titanium metal from the upper surface of the polysilicon layer and the split gate metal layer.
13. The method for fabricating the MOSFET structure according to claim 7, characterized in that, The formation of a first interlayer dielectric layer on the gate oxide layer, the gate layer, the isolation dielectric layer, the split gate metal layer, and a portion of the second conductivity type doped layer includes: A first interlayer dielectric material is formed on the gate oxide layer, the gate layer, the isolation dielectric layer, the split gate metal layer, and a portion of the second conductivity type doped layer; A second opening is formed on the first interlayer dielectric material to form a first interlayer dielectric layer; wherein the second opening exposes the source electrode.