Crystalline oxide semiconductor thin film, thin film transistor and manufacturing method thereof

Abstract

The invention discloses a crystalline oxide semiconductor thin film, a thin film transistor and a manufacturing method thereof. The material of the crystalline oxide semiconductor thin film comprises indium oxide, the material of the crystalline oxide semiconductor thin film further comprises a first element and / or a second element, the indium oxide and the first element form DxInyO, the first element comprises at least one of Ga, Sc and Y, x + y = 1, and x is more than or equal to 0.10 and less than or equal to 0.35; the second element comprises at least one of Eu, Pr, Tb and Yb; in DxNzInyO composed of indium oxide, the first element and the second element, x + y + z = 1, x is larger than or equal to 0.10 and smaller than or equal to 0.35, z is larger than or equal to 0.0001 and smaller than or equal to 0.05, N is NzInyO composed of the second element, indium oxide and the second element, y + z = 1, and z is larger than or equal to 0.0001 and smaller than or equal to 0.05. The carrier mobility and the stability of the thin film transistor can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a crystalline oxide semiconductor thin film, a thin film transistor, and a method for fabricating the same. Background Technology

[0002] In existing metal-oxide-semiconductor (MOS) systems, In₂O₃ thin films contain a large number of oxygen vacancy defects, resulting in severe lattice distortion. This leads to poor film crystallinity and excessive carrier transport scattering, ultimately reducing the carrier mobility of the crystalline oxide semiconductor film. Furthermore, oxygen vacancies result in numerous shallow donor level defects and deep acceptor level defects. This leads to uncontrollable threshold voltage and poor stability in thin-film transistor devices fabricated using In₂O₃ thin films.

[0003] In the prior art, In2O3 can be doped with In. 3+ Ga with a comparable number of ions 3+ Ions regulate oxygen vacancies. Simultaneously, doping with Zn ions in an amount comparable to that of In can suppress material crystallization, maintaining the amorphous structure of the thin film and forming an indium gallium zinc oxide (IZGO) metal-oxide semiconductor material. At this point, Ga in IGZO... 3+ and Zn 2+ The addition of a large number of ions significantly diluted In. 3+ The ion concentration is reduced, which in turn reduces the overlap of 5s orbitals and decreases carrier mobility. Summary of the Invention

[0004] This invention provides a crystalline oxide semiconductor thin film, a thin film transistor, and a method for fabricating the same, to improve the carrier mobility of the crystalline oxide semiconductor thin film and enhance the stability of the thin film transistor.

[0005] In a first aspect, embodiments of the present invention provide a crystalline oxide semiconductor thin film, wherein the material of the crystalline oxide semiconductor thin film includes indium oxide, and the material of the crystalline oxide semiconductor thin film further includes a first element and / or a second element, wherein the indium oxide and the first element form a Dc x In y O, wherein In is the In element in the indium oxide, O is the oxygen element in the indium oxide, D is the first element, the first element includes at least one of Ga, Sc and Y, x+y=1, 0.10≤x≤0.35;

[0006] The second element includes at least one of Eu, Pr, Tb, and Yb; wherein, the indium oxide, the first element, and the second element constitute D x Nz In y In O, x + y + z = 1, 0.10 ≤ x ≤ 0.35, 0.0001 ≤ z ≤ 0.05, and N is the second element. The N-type oxide is composed of indium oxide and the second element. z In y In O, y+z=1, 0.0001≤z≤0.05.

[0007] Optionally, the material of the crystalline oxide semiconductor thin film further includes a third element, which includes at least one selected from Al, Ti, Nb, Ta, and Zn; wherein the indium oxide, the first element, and the third element constitute D x B a In y In O, x + y + a = 1, 0.10 ≤ x ≤ 0.35, 0.005 ≤ a ≤ 0.03, and the D composed of indium oxide, the first element, the second element, and the third element. x N z B a In y In O, x + y + a + z = 1, 0.10 ≤ x ≤ 0.35, 0.0001 ≤ z ≤ 0.05, 0.005 ≤ a ≤ 0.03, and the N-oxide composed of the indium oxide, the second element, and the third element. z B a In y In O, z + y + a = 1, 0.0001 ≤ z ≤ 0.35, 0.005 ≤ a ≤ 0.03, and the indium oxide and the third element constitute B. a In y In O, a+z=1, 0.005≤a≤0.03; B is the third element.

[0008] Optionally, the crystalline phase of the crystalline oxide semiconductor film is the indium oxide manganese oxide structure, and the angle between the indium ion arrangement direction and the charge carrier transport direction in the crystalline oxide semiconductor film is in the range of 0° to 45°.

[0009] Optionally, the ratio of the crystallinity of the crystallization peak (400) to the crystallinity of the crystallization peak (222) of the crystalline oxide semiconductor film ranges from 0.45 to 1.25, and the proportion of the (400) crystal plane of the indium oxide to all crystal planes of the indium oxide is greater than 35%.

[0010] Optionally, the crystalline oxide semiconductor thin film includes a plurality of sub-layers stacked together, each sub-layer including an indium oxide layer and a first element oxide layer disposed adjacent to each other.

[0011] Optionally, the thickness of the crystalline oxide semiconductor thin film ranges from 5 nm to 100 nm.

[0012] Optionally, the carrier concentration of the crystalline oxide semiconductor thin film is less than 2 × 10⁻⁶. 19 cm -3 .

[0013] In a second aspect, embodiments of the present invention also provide a thin-film transistor, including a gate, a gate insulating layer, a source, a drain, and the crystalline oxide semiconductor thin film described in the first aspect; the crystalline oxide semiconductor thin film includes a source region, a channel region, and a drain region arranged sequentially; along the thickness direction of the thin-film transistor, the gate insulating layer is disposed between the gate and the channel region, the source is connected to the source region, and the drain is connected to the drain region.

[0014] Thirdly, embodiments of the present invention also provide a method for fabricating a thin-film transistor, used to fabricate the thin-film transistor described in the second aspect; the method includes:

[0015] A raw oxide semiconductor thin film is deposited on the first surface of the substrate;

[0016] The original oxide semiconductor film is annealed to form the crystalline oxide semiconductor film; wherein the annealing temperature of the original oxide semiconductor film is greater than or equal to 200°C, the material of the crystalline oxide semiconductor film includes indium oxide, and the material of the crystalline oxide semiconductor film further includes a first element and / or a second element, wherein the indium oxide and the first element form D. x In y O, wherein In is the In element in the indium oxide, O is the oxygen element in the indium oxide, D is the first element, the first element includes at least one of Ga, Sc and Y, x+y=1, 0.10≤x≤0.35; the second element includes at least one of Eu, Pr, Tb and Yb; wherein, the indium oxide, the first element and the second element constitute D x N z In y In O, x + y + z = 1, 0.10 ≤ x ≤ 0.35, 0.0001 ≤ z ≤ 0.05, and N is the second element. The N-type oxide is composed of indium oxide and the second element. z In y In O, y+z=1, 0.0001≤z≤0.05.

[0017] Optionally, before depositing the original oxide semiconductor thin film on the first surface of the substrate, the method further includes:

[0018] The first surface of the substrate is treated to make its surface energy greater than 500 mJ / m 2 .

[0019] The technical solution of this invention, by doping a small amount of a first element and / or a second element into a crystalline oxide semiconductor thin film, wherein the first element includes at least one of Ga, Sc, and Y, and the second element includes at least one of Eu, Pr, Tb, and Yb, can give the crystalline oxide semiconductor thin film a small oxygen vacancy concentration, while also giving it a complete metal-oxygen six-coordinate octahedral structure. Furthermore, it can ensure the concentration of indium ions in the crystalline oxide semiconductor thin film, thereby reducing lattice distortion and giving the crystalline oxide semiconductor thin film a high carrier mobility. Simultaneously, the complete crystal structure ensures that when the crystalline oxide semiconductor thin film is used to form a thin-film transistor, the thin-film transistor exhibits superior device stability. Attached Figure Description

[0020] Figure 1 A schematic diagram of a thin-film transistor provided in an embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram of the performance curve of device 1 provided in an embodiment of the present invention;

[0022] Figure 3 This is a schematic diagram of the performance curve of device 2 provided in an embodiment of the present invention;

[0023] Figure 4 This is a schematic diagram of the performance curve of device 3 provided in an embodiment of the present invention;

[0024] Figure 5 A schematic flowchart illustrating a method for fabricating a thin-film transistor according to an embodiment of the present invention;

[0025] Figure 6 This is a schematic diagram illustrating the crystallinity of a crystalline oxide semiconductor thin film at different peak positions under different oxygen partial pressures, as provided in an embodiment of the present invention.

[0026] Figure 7 A schematic diagram illustrating the crystallinity of a crystalline oxide semiconductor thin film at different peak positions under different oxygen partial pressures and at different angles, provided as an embodiment of the present invention.

[0027] Figure 8 A schematic diagram showing the percentage of crystallinity at each peak position in a crystalline oxide semiconductor thin film provided in an embodiment of the present invention when the oxygen partial pressure is 10%.

[0028] Figure 9A schematic diagram showing the percentage of crystallinity at each peak position in a crystalline oxide semiconductor thin film provided in an embodiment of the present invention when the oxygen partial pressure is 20%.

[0029] Figure 10 A schematic diagram showing the percentage of crystallinity at each peak position in a crystalline oxide semiconductor thin film provided in an embodiment of the present invention when the oxygen partial pressure is 40%.

[0030] Figure 11 A schematic diagram showing the percentage of crystallinity at each peak position in a crystalline oxide semiconductor thin film provided in an embodiment of the present invention when the oxygen partial pressure is 60%.

[0031] Figure 12 This is a schematic diagram illustrating the performance of a thin-film transistor fabricated under different oxygen partial pressure conditions, as provided in an embodiment of the present invention.

[0032] Figure 13 This is a schematic diagram of a bottom-gate thin-film transistor provided in an embodiment of the present invention. Detailed Implementation

[0033] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0034] This invention provides a crystalline oxide semiconductor thin film, which can be used to form a thin-film transistor. The crystalline oxide semiconductor thin film is made of indium oxide, and further comprises a first element and / or a second element, wherein indium oxide and the first element form a Dc. x In y O, where In is the In element in indium oxide, O is the oxygen element in indium oxide, D is the first element, the first element includes at least one of Ga, Sc and Y, x+y=1, 0.10≤x≤0.35;

[0035] The second element includes at least one of Eu, Pr, Tb, and Yb; wherein, D, composed of indium oxide, the first element, and the second element, is... x N z In y In O, x + y + z = 1, 0.10 ≤ x ≤ 0.35, 0.0001 ≤ z ≤ 0.05, and N is the second element. Indium oxide and the second element form N. z In y In O, y+z=1, 0.0001≤z≤0.05.

[0036] Specifically, in indium oxide (IO), the 5s orbitals of indium ions are isotropic, so the carrier transport channels based on the IO material structure are mainly electron transport channels. The first element includes at least one of Ga, Sc, and Y, which can suppress oxygen vacancies in IO, thereby improving the lattice distortion of the crystalline oxide semiconductor film. Furthermore, x + y = 1, 0.10 ≤ x ≤ 0.35, meaning the content of the first element is relatively low compared to the indium content in IO. While ensuring a low oxygen vacancy concentration in the crystalline oxide semiconductor film, this allows it to possess the complete crystallization characteristics of a metal-oxygen six-coordinate octahedral structure. It also ensures a stable indium ion concentration, reducing lattice distortion and resulting in better crystallinity. This leads to higher carrier mobility and a complete crystal structure in the crystalline oxide semiconductor film, resulting in thin-film transistors with higher carrier mobility and better stability.

[0037] The second element includes at least one of Eu, Pr, Tb, and Yb. It can provide non-radiative transition channels by introducing specific defect energy levels without altering the thin film structure, thereby reducing the impact of photogenerated carriers on the stability of thin-film transistors. Furthermore, the relatively low content of the second element (0.0001 ≤ z ≤ 0.05) ensures adequate indium ion concentration, thus guaranteeing carrier mobility in the crystalline oxide semiconductor thin film and improving the device stability of the thin-film transistor when formed from the crystalline oxide semiconductor film.

[0038] The technical solution of this embodiment, by doping a small amount of a first element and / or a second element into a crystalline oxide semiconductor thin film, wherein the first element includes at least one of Ga, Sc, and Y, and the second element includes at least one of Eu, Pr, Tb, and Yb, can give the crystalline oxide semiconductor thin film a small oxygen vacancy concentration, while also giving it a complete metal-oxygen six-coordinate octahedral structure. Furthermore, it can ensure the concentration of indium ions in the crystalline oxide semiconductor thin film, thereby reducing lattice distortion and giving the crystalline oxide semiconductor thin film a high carrier mobility. Simultaneously, the complete crystal structure ensures that when the crystalline oxide semiconductor thin film is used to form a thin-film transistor, the thin-film transistor exhibits superior device stability.

[0039] In some embodiments, the material of the crystalline oxide semiconductor thin film further includes a third element, which includes at least one selected from Al, Ti, Nb, Ta, and Zn; wherein, the D-structure composed of indium oxide, the first element, and the third element... x B aIn y In O, x + y + a = 1, 0.10 ≤ x ≤ 0.35, 0.005 ≤ a ≤ 0.03, and D is composed of indium oxide, the first element, the second element, and the third element. x N z B a In y In O, x + y + a + z = 1, 0.10 ≤ x ≤ 0.35, 0.0001 ≤ z ≤ 0.05, 0.005 ≤ a ≤ 0.03, and N is composed of indium oxide, the second element, and the third element. z B a In y In O, z + y + a = 1, 0.0001 ≤ z ≤ 0.35, 0.005 ≤ a ≤ 0.03, and B is composed of indium oxide and a third element. a In y In O, a+z=1, 0.005≤a≤0.03; B is the third element.

[0040] Specifically, the third element includes at least one of Al, Ti, Nb, Ta, and Zn, which can further reduce the oxygen vacancy concentration in the crystalline oxide semiconductor thin film. This allows the crystalline oxide semiconductor thin film to have a more complete transistor structure, improving its stability. Furthermore, the relatively low content of the third element (0.005 ≤ a ≤ 0.03) also ensures the concentration of indium ions, thereby guaranteeing the carrier mobility of the crystalline oxide semiconductor thin film and improving the device stability of the thin-film transistor when formed from the crystalline oxide semiconductor thin film.

[0041] In some embodiments, the crystalline phase of the crystalline oxide semiconductor film is an indium oxide manganese oxide structure, and the angle between the arrangement direction of indium ions and the transport direction of charge carriers in the crystalline oxide semiconductor film ranges from 0° to 45°.

[0042] Specifically, when an oxide semiconductor thin film possesses crystalline properties, it ensures superior device stability when used to form a thin-film transistor (TFT). By setting the crystalline phase of the crystalline oxide semiconductor thin film to an indium oxide-manganese permanganate structure, a complete crystal structure can be achieved. Simultaneously, the angle between the alignment direction of indium ions and the transport direction of charge carriers in the crystalline oxide semiconductor thin film ranges from 0° to 45°. That is, when charge carriers are present in the crystalline oxide semiconductor thin film, the angle between the alignment plane of one indium ion and its adjacent indium ions and the transport direction of the charge carriers ranges from 0° to 45°. This results in a highly ordered structure in the crystalline oxide TFT, reducing charge carrier scattering and increasing the charge carrier mobility of the oxide semiconductor thin film. Consequently, the TFT formed from the crystalline oxide semiconductor thin film exhibits higher charge carrier mobility and better stability. For example, when a crystalline oxide semiconductor film is used as the semiconductor layer of a thin-film transistor, the crystalline oxide semiconductor film may include a source region, a channel region, and a drain region arranged sequentially, and the transport direction of charge carriers in the crystalline oxide semiconductor film may be from the source region to the drain region. In some embodiments, the carrier mobility of the crystalline oxide semiconductor film may be greater than or equal to 70 cm² / V·s, which improves the threshold voltage drift and on / off ratio instability of the thin-film transistor.

[0043] The technical solution of this embodiment sets the crystalline phase of the crystalline oxide semiconductor film to an indium oxide-manganese permanganate structure, with the angle between the indium ion alignment direction and the carrier transport direction ranging from 0° to 45°. This allows the oxide semiconductor film to have a complete crystal structure and enables the crystalline oxide thin-film transistor to have a highly ordered structure. This reduces carrier scattering and improves the carrier mobility of the oxide semiconductor film, resulting in thin-film transistors formed from crystalline oxide semiconductor films with higher carrier mobility and better stability.

[0044] In some embodiments, the angle between the arrangement direction of indium ions and the transport direction of charge carriers in the crystalline oxide semiconductor thin film can be set to a range of 0° to 25°, which can further improve the orderliness of the crystalline oxide thin film transistor structure, thereby further improving the carrier mobility of the crystalline oxide semiconductor thin film.

[0045] In some embodiments, the ratio of the crystallinity of the crystallization peak (400) to the crystallinity of the crystallization peak (222) of the crystalline oxide semiconductor thin film ranges from 0.45 to 1.25. The (400) crystal plane of indium oxide accounts for more than 35% of all crystal planes of indium oxide, which can further improve the integrity of the crystal structure of the oxide semiconductor thin film and reduce lattice distortion, so that the crystalline oxide semiconductor thin film exhibits better crystallization characteristics, further improving the carrier mobility of the oxide semiconductor thin film. As a result, the thin film transistor formed by the crystalline oxide semiconductor thin film can have higher carrier mobility and better stability.

[0046] It should be noted that the crystallization characteristics of oxide semiconductor thin films can be adjusted as needed through material composition and preparation process.

[0047] In some embodiments, the crystalline oxide semiconductor thin film includes a plurality of sublayers stacked together, each sublayer including an indium oxide layer and a first element oxide layer disposed adjacent to each other.

[0048] Specifically, the crystalline oxide semiconductor thin film can be configured as a multilayer stack. When the oxide semiconductor thin film includes indium oxide and a first element, each sublayer can include an adjacent indium oxide layer and an oxide layer of the first element. For example, when the first element is Sc, the material of the oxide layer of the first element is In. 1.80 Sc 0.2 O3. By setting each sublayer to include an indium oxide layer and a first element oxide layer, and stacking multiple sublayers, energy level differences can be formed between the multilayer crystalline oxide semiconductor thin films. This restricts the carrier transport space, reduces electron scattering, and improves carrier mobility and stability. At the same time, the multilayer crystalline thin films can also ensure a complete crystal structure, resulting in thin-film transistors with superior device stability.

[0049] In some embodiments, when the crystalline oxide semiconductor film further includes a second element and / or a third element, the sublayer of the crystalline oxide semiconductor film may include an oxide layer of the second element and / or an oxide layer of the third element, and be stacked with an indium oxide layer and an oxide layer of the first element, so that the ionic composition and concentration of the crystalline oxide semiconductor film meet the requirements, thereby ensuring the performance of the crystalline oxide semiconductor film.

[0050] In some embodiments, the thickness of the crystalline oxide semiconductor thin film ranges from 5 nm to 100 nm.

[0051] In some embodiments, the carrier concentration of the crystalline oxide semiconductor thin film is less than 2 × 10⁻⁶. 19 cm -3 .

[0052] By controlling the thickness and carrier concentration of the oxide semiconductor thin film, the total number of carriers within the film can be effectively adjusted. When oxide semiconductor thin films are used to form thin-film transistors (TFTs), the threshold voltage of the TFT can be controlled, thereby meeting the threshold voltage requirements of various types of circuits.

[0053] This invention also provides a thin-film transistor. Figure 1 This is a schematic diagram of a thin-film transistor provided as an embodiment of the present invention. Figure 1 As shown, the thin-film transistor includes a gate 110, a gate insulating layer 120, a source 130, a drain 140, and a crystalline oxide semiconductor thin film 150 provided in any embodiment of the present invention; the crystalline oxide semiconductor thin film 150 includes a source region 151, a channel region 152, and a drain region 153 arranged sequentially; along the thickness direction Z of the thin-film transistor, the gate insulating layer 120 is disposed between the gate 110 and the channel region 152, the source 130 is connected to the source region 151, and the drain 140 is connected to the drain region 153.

[0054] Specifically, the thin-film transistor may further include a substrate 100, a light-shielding layer LS, and a buffer layer 101. The substrate 100 may be made of glass, and the light-shielding layer LS may be made of metal, serving to shield light incident from one side of the substrate 100, preventing light from affecting the performance of the crystalline oxide semiconductor thin film 150. For example, a 200 nm layer of Mo may be deposited on the glass substrate as the light-shielding layer LS. The buffer layer 101 may include at least one layer of stacked silicon nitride and / or silicon oxide. For example, a stacked thin film structure consisting of 300 nm silicon nitride and 100 nm silicon oxide may be sequentially deposited on the light-shielding layer LS using plasma-enhanced chemical vapor deposition (PECVD) as the buffer layer 101. Figure 1The example illustrates a top-gate thin-film transistor (TFT) where a crystalline oxide semiconductor thin film 150 is disposed on a buffer layer 101. The crystalline oxide semiconductor thin film 150 can be deposited as a 60 nm thick film using physical vapor deposition (PVD) and annealed at 450°C. A gate insulating layer 120 is disposed on the side of the crystalline oxide semiconductor thin film 150 away from the substrate 100, and can be a 150 nm thick silicon oxide layer deposited using PECVD. A gate 110 is located on the side of the gate insulating layer 120 away from the substrate 100, forming a top-gate TFT. The material of the gate 110 can be a metal, such as Mo, or a TiW alloy. When forming the gate 110, a gate layer can be deposited using PVD, and then the gate layer can be patterned to form the gate 110. The gate 110 pattern is then used as a self-aligned mask to pattern the gate insulating layer 120. An interlayer insulating layer 160 is also disposed between the gate 110 and the source 130 to prevent short circuits between the gate 110 and the source 130 and drain 140. A 400nm layer of silicon oxide can be deposited using PECVD, and then patterned to form the interlayer insulating layer 160. The source 130 and drain 140 can be made of metal, such as Mo. A 300nm layer of Mo can be deposited using PVD to form the source and drain layers, and then patterned to form the source 130 and drain 140. The source 130 is connected to the source region 151, and the drain 140 is connected to the drain region 153, thus externally connecting the source region 151 and drain region 153 of the thin-film transistor. Finally, a photosensitive polyimide can be prepared using spin coating as a passivation layer to complete the fabrication of the thin-film transistor. Since the thin-film transistor provided in this embodiment includes the crystalline oxide semiconductor thin film provided in any embodiment of the present invention, the thin-film transistor has the same beneficial effects as the crystalline oxide semiconductor thin film provided in any embodiment of the present invention, which will not be repeated here.

[0055] In some embodiments, the material of the crystalline oxide semiconductor thin film may include indium oxide and a first element. Table 1 shows a comparison of the performance of thin-film transistors when the crystalline oxide semiconductor thin film is used to form different thin-film transistors according to different materials provided in the embodiments of the present invention. Wherein, ALD refers to atomic layer deposition (ALD), PVD refers to physical vapor deposition (PVD), and TG refers to top-gate structure. The active layer material is the material of the crystalline oxide semiconductor thin film, and the process refers to the type of process used to form the crystalline oxide semiconductor thin film. P is the ratio of the crystallinity of the crystallization peak (400) to the crystallinity of the crystallization peak (222) of the crystalline oxide semiconductor thin film. The gate insulating layer is the film composition of the gate insulating layer of the thin film transistor, as well as the material and thickness of each film layer. The device annealing temperature is the annealing temperature corresponding to the annealing process of the crystalline oxide semiconductor thin film. The device mobility is the carrier mobility of the thin film transistor. The threshold voltage is the threshold voltage of the thin film transistor. The subthreshold swing is the subthreshold swing of the thin film transistor. The transport direction angle θ is the angle between the arrangement direction of indium ions and the transport direction of carriers in the oxide semiconductor thin film. NBITS is the offset value of the threshold voltage after the negative bias photo-irradiation heating stability test of the thin film transistor. Figure 2 This is a schematic diagram of the performance curve of device 1 provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of the performance curve of device 2 provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of the performance curve of device 3 provided in an embodiment of the present invention. The horizontal axis represents the gate-source voltage difference V of the thin-film transistor. gs (V), where the vertical axis represents the source and drain currents I of the thin-film transistor. ds (A). From Table 1, Figures 2 to 4 It is known that when the crystalline oxide semiconductor thin film has the same material composition and includes the first element, and this crystalline oxide semiconductor thin film is used as the active layer of a thin-film transistor, the θ angle of the transport direction and the proportion of the (400) crystal plane can be adjusted by matching the gate insulating layer material, structure, and process, and by adjusting the annealing process. Ultimately, this adjustment results in high carrier mobility and excellent stability of the thin-film transistor.

[0056] Table 1

[0057]

[0058]

[0059] In some embodiments, the material of the crystalline oxide semiconductor thin film may include indium oxide, a first element, and a second element. Table 2 shows a comparison of the performance of thin-film transistors when the crystalline oxide semiconductor thin film is used to form different thin-film transistors according to different materials provided in the embodiments of the present invention. Here, PVD refers to Physical Vapor Deposition (PVD), BCE refers to Back Channel Etching, and TG refers to Top-Gate Structure. The active layer material is the material of the crystalline oxide semiconductor thin film, and the process refers to the formation process type of the crystalline oxide semiconductor thin film. P represents the ratio of the crystallinity of the crystallization peak (400) to the crystallinity of the crystallization peak (222) of the crystalline oxide semiconductor thin film. The gate insulating layer represents the composition of the gate insulating layer of the thin-film transistor, along with the material and thickness of each layer. The device annealing temperature represents the annealing temperature corresponding to the annealing process of the crystalline oxide semiconductor thin film. The device mobility represents the carrier mobility of the thin-film transistor. The threshold voltage represents the threshold voltage of the thin-film transistor. The subthreshold swing represents the subthreshold swing of the thin-film transistor. The transport direction angle θ represents the angle between the arrangement direction of indium ions and the transport direction of carriers in the oxide semiconductor thin film. NBITS represents the offset of the threshold voltage after the negative bias photothermal heating stability test of the thin-film transistor. As shown in Table 2, when the material of the crystalline oxide semiconductor thin film simultaneously includes the first, second, and third elements, and this crystalline oxide semiconductor thin film is used as the active layer of a thin-film transistor, by setting the transport direction angle θ, combined with the material, structure, and process of the gate insulating layer, and adjusting the annealing process, the carrier mobility of the thin-film transistor can be made high, and its stability excellent.

[0060] Table 2

[0061]

[0062] In some embodiments, the material of the crystalline oxide semiconductor thin film may include indium oxide, a first element, a second element, and a third element. Table 3 shows a comparison of the performance of thin-film transistors when the crystalline oxide semiconductor thin film is used to form different thin-film transistors according to different materials provided in the embodiments of the present invention. Here, PVD refers to Physical Vapor Deposition (PVD), BCE refers to Back Channel Etching, and TG refers to Top-Gate Structure. The active layer material is the material of the crystalline oxide semiconductor thin film, and the process refers to the formation process type of the crystalline oxide semiconductor thin film. P represents the ratio of the crystallinity of the crystallization peak (400) to the crystallinity of the crystallization peak (222) of the crystalline oxide semiconductor thin film. The gate insulating layer represents the film composition, material, and thickness of each layer of the gate insulating layer of the thin-film transistor. The device annealing temperature represents the annealing temperature corresponding to the annealing process of the crystalline oxide semiconductor thin film. The device mobility represents the carrier mobility of the thin-film transistor. The threshold voltage represents the threshold voltage of the thin-film transistor. The subthreshold swing represents the subthreshold swing of the thin-film transistor. The transport direction angle θ represents the angle between the arrangement direction of indium ions and the transport direction of carriers in the oxide semiconductor thin film. NBITS represents the offset value of the threshold voltage after the negative bias photothermal heating stability test of the thin-film transistor. As shown in Table 3, when the material of the crystalline oxide semiconductor thin film includes the first element, the second element, and the third element, and this crystalline oxide semiconductor thin film is used as the active layer of the thin-film transistor, by setting the transport direction angle θ, combined with the material, structure, and process of the gate insulating layer, and adjusting the annealing process, the carrier mobility of the thin-film transistor can be made high, and the stability excellent.

[0063] Table 3

[0064]

[0065] It should be noted that in other embodiments, the thin-film transistor can also be a bottom-gate transistor, in which case the gate 110 is disposed on the side of the crystalline oxide semiconductor thin film 150 close to the substrate 100, which is not limited here.

[0066] This invention also provides a method for fabricating a thin-film transistor (TFT), used to fabricate the TFT provided in any embodiment of this invention. The TFT includes a crystalline oxide semiconductor thin film as the active layer of the TFT provided in any embodiment of this invention. Exemplarily, the crystalline oxide semiconductor thin film can be fabricated using any one of the following methods: single-target sputtering, solution deposition, atomic layer deposition, or pulsed laser deposition. Figure 5This is a schematic flowchart illustrating a method for fabricating a thin-film transistor according to an embodiment of the present invention. Figure 5 As shown, the method includes:

[0067] S210, Deposit a raw oxide semiconductor thin film on the first surface of the substrate;

[0068] Specifically, single-target sputtering can be used to deposit raw oxide semiconductor thin films, reducing fabrication costs and improving performance. During single-target sputtering, the oxygen partial pressure can be adjusted to be greater than or equal to a preset value. This ensures better crystallization of the crystalline oxide semiconductor film and reduces lattice distortion. For example, a preset oxygen partial pressure of 5% (e.g., 60%) results in a low oxygen vacancy concentration, improving lattice integrity.

[0069] For example, Figure 6 This is a schematic diagram of the crystallinity of a crystalline oxide semiconductor thin film at each peak under different oxygen partial pressures, provided in an embodiment of the present invention. Curve 5 is the crystallinity transformation curve of the crystallization peak (222), and curve 6 is the crystallinity transformation curve of the crystallization peak (400). Figure 7 This is a schematic diagram of the crystallinity of a crystalline oxide semiconductor thin film at different angles under different oxygen partial pressures, provided as an embodiment of the present invention. Curve 1 is the crystallinity curve of each peak position at different angles when the oxygen partial pressure is 10%, curve 2 is the crystallinity curve of each peak position at different angles when the oxygen partial pressure is 20%, curve 3 is the crystallinity curve of each peak position at different angles when the oxygen partial pressure is 40%, and curve 4 is the crystallinity curve of each peak position at different angles when the oxygen partial pressure is 60%. Figure 8 This is a schematic diagram illustrating the percentage of crystallinity at each peak position in a crystalline oxide semiconductor thin film provided in an embodiment of the present invention when the oxygen partial pressure is 10%. Figure 9 This is a schematic diagram illustrating the percentage of crystallinity at each peak position in a crystalline oxide semiconductor thin film provided in an embodiment of the present invention when the oxygen partial pressure is 20%. Figure 10 This is a schematic diagram illustrating the percentage of crystallinity at each peak position in a crystalline oxide semiconductor thin film provided in an embodiment of the present invention when the oxygen partial pressure is 40%. Figure 11 This is a schematic diagram illustrating the percentage of crystallinity at each peak position in a crystalline oxide semiconductor thin film provided in an embodiment of the present invention when the oxygen partial pressure is 60%. Figures 6 to 11In the figure, (211) is the crystallization peak (211) used to characterize the crystallized oxide semiconductor film, (222) is the crystallization peak (222) used to characterize the crystallized oxide semiconductor film, (400) is the crystallization peak (400) used to characterize the crystallized oxide semiconductor film, (440) is the crystallization peak (440) used to characterize the crystallized oxide semiconductor film, and (622) is the crystallization peak (622) used to characterize the crystallized oxide semiconductor film. Figure 12 This is a schematic diagram illustrating the performance of a thin-film transistor fabricated under different oxygen partial pressures according to an embodiment of the present invention, wherein the horizontal axis represents the gate-source voltage difference V of the thin-film transistor. gs (V), where the vertical axis represents the source and drain currents I of the thin-film transistor. ds (A) The active layer of this thin-film transistor is a crystalline oxide semiconductor thin film provided in any embodiment of the present invention. Curve 7 is the performance curve of the thin-film transistor prepared under an oxygen partial pressure of 10%, curve 8 is the performance curve of the thin-film transistor prepared under an oxygen partial pressure of 20%, curve 9 is the performance curve of the thin-film transistor prepared under an oxygen partial pressure of 40%, and curve 10 is the performance curve of the thin-film transistor prepared under an oxygen partial pressure of 60%. Figures 6 to 12 As shown, with increasing oxygen partial pressure, the crystallinity of the crystallization peak (222) of the crystalline oxide semiconductor thin film gradually decreases, while the crystallinity of the crystallization peak (400) gradually increases, indicating a competitive relationship between the crystallization peak (400) and the crystallization peak (222). Simultaneously, the mobility of the thin-film transistor gradually increases with increasing oxygen partial pressure. Combined with... Figures 6 to 12 Furthermore, the performance of thin-film transistors (TFTs) can be determined by increasing the orientation of the (400) crystal peak. The carrier mobility of TFTs is relatively high at oxygen partial pressures of 10%, 20%, 40%, and 60%. At an oxygen partial pressure greater than or equal to 40%, the carrier mobility of TFTs is greater than 30 cm⁻¹. 2 / Vs.

[0070] S220. Annealing the original oxide semiconductor film to form a crystalline oxide semiconductor film; wherein the annealing temperature of the original oxide semiconductor film is greater than or equal to 200°C, the material of the crystalline oxide semiconductor film includes indium oxide, and the material of the crystalline oxide semiconductor film further includes a first element and / or a second element, and the indium oxide and the first element form D. x In y O, where In is the indium element in indium oxide, O is the oxygen element in indium oxide, and D is the first element, which includes at least one of Ga, Sc, and Y, where x + y = 1 and 0.10 ≤ x ≤ 0.35; the second element includes at least one of Eu, Pr, Tb, and Yb; wherein, D, composed of indium oxide, the first element, and the second element... x N zIn y In O, x + y + z = 1, 0.10 ≤ x ≤ 0.35, 0.0001 ≤ z ≤ 0.05, and N is the second element. Indium oxide and the second element form N. z In y In O, y+z=1, 0.0001≤z≤0.05.

[0071] Specifically, after forming the original oxide semiconductor film, the original oxide semiconductor film can be annealed to ensure that the formed crystalline oxide semiconductor film has good crystallinity.

[0072] In some embodiments, the crystalline oxide semiconductor thin film comprises indium oxide and a first element; depositing the original oxide semiconductor thin film includes:

[0073] The first step involves depositing at least one cycle of a first-element oxide layer using atomic layer deposition (ALD).

[0074] Specifically, when forming a raw oxide semiconductor thin film using atomic layer deposition (ALD), a first-element oxide layer can be deposited by sampling ALD for at least one cycle. For example, when the first element is Ti, the material of the first-element oxide layer is TiO. The precursor chemical source used for growing the first-element oxide layer can be trimethyl-first-element (TMD), where D corresponds to the first element. The temperature of the TMD chemical source is set to room temperature, the pulse supply time is 0.1 s, the exhaust time is 6 s, and the reactive oxygen source used is deionized water for 2 s. The film formation rate of the first-element oxide layer is on the order of angstroms for the thickness of each reactive deposition cycle. For example, sampling ALD can deposit one cycle of the first-element oxide layer.

[0075] The second step involves depositing at least one cycle of indium oxide layer using atomic layer deposition.

[0076] Specifically, the precursor chemical source for depositing at least one cycle of indium oxide layer using ALD is trimethylindium (TMIn). The temperature of the TMIn chemical source is set to 50°C, the pulse supply time is 0.4 s, the exhaust time is 10 s, the reactive oxygen source is ozone, the reaction time is 20 s, and the indium oxide film deposition rate is 1.1 Å thickness per cycle. For example, 15 cycles of indium oxide layer can be deposited using ALD.

[0077] The first and second steps are repeated at least once to form the original oxide semiconductor thin film.

[0078] Specifically, in forming the original oxide semiconductor thin film, at least one cycle of a first element oxide layer can be deposited first, followed by at least one cycle of an indium oxide layer to form a sublayer. This process can then be repeated to form multiple sublayers to form the original oxide semiconductor thin film. For example, 10 sublayers can be formed in 10 cycles to form the original oxide semiconductor thin film.

[0079] After forming the original oxide semiconductor film, it can be annealed to form a crystalline oxide semiconductor film. After X-ray diffraction testing, the crystallinity ratio p of the crystallization peak (400) to the crystallization peak (222) of the crystalline oxide semiconductor film is 1.1.

[0080] In some embodiments, Figure 13 This is a schematic diagram of a bottom-gate thin-film transistor provided in an embodiment of the present invention. Figure 13 As shown, when the thin-film transistor is a bottom-gate thin-film transistor, before forming the crystalline oxide semiconductor thin film 150, the following steps are also included:

[0081] A gate 110 is formed on the substrate 100. The gate 110 can be a stacked structure, for example, it can include Mo / Al / Mo stacked sequentially. In this case, when forming the gate 110, 50 nm of Mo, 300 nm of Al and 50 nm of Mo can be deposited sequentially on the substrate.

[0082] A gate insulating layer 120 is formed on the side of the gate 110 away from the substrate 100. The gate insulating layer 120 can then serve as a substrate for supporting the crystallized oxide semiconductor thin film. The surface of the gate insulating layer 120 away from the gate 110 can be processed to achieve a surface energy greater than 500 mJ / m². 2 Therefore, when forming a crystalline oxide semiconductor thin film on the gate insulating layer 120, the crystal planes of the crystalline oxide semiconductor thin film can be aligned in a specific direction, such that the angle between the alignment direction of indium ions and the transport direction of charge carriers in the crystalline oxide semiconductor thin film is in the range of 0° to 45°. The gate insulating layer 120 can be formed by PECVD. The gate insulating layer 120 can be a stacked structure of silicon nitride and silicon oxide. For example, when forming the gate insulating layer 120, a stacked structure of 250 nm silicon nitride and 50 nm silicon oxide can be formed by sequentially depositing them by PECVD as the gate insulating layer 120.

[0083] After forming the crystalline oxide semiconductor thin film, the process also includes:

[0084] Source and drain electrodes are formed on the side of the crystalline oxide semiconductor thin film 150 away from the substrate 100. When forming the source and drain electrodes, a 50nm / 500nm Mo / Cu stacked metal layer can be deposited by PVD as the source and drain electrode layer, and then the source and drain electrode layer can be patterned by hydrogen peroxide-based etching solution to form the source electrode 130 and the drain electrode 140.

[0085] A passivation layer is formed on the side of the source and drain electrodes away from the substrate. When forming the passivation layer, a 300 nm layer of silicon oxide can be deposited using PECVD as the first passivation layer 170, followed by a 100 nm layer of silicon nitride as the second passivation layer 180. The carrier mobility of the thin-film transistor formed by this method can reach 45 cm⁻¹. 2 / Vs.

[0086] In some embodiments, prior to depositing a raw oxide semiconductor thin film on a first surface of the substrate, the method further includes:

[0087] The first surface of the substrate is treated to make its surface energy greater than 500 mJ / m 2 .

[0088] Specifically, the first surface of the substrate can be the upper surface of the substrate. The substrate material can be an insulating material used to support the crystalline oxide semiconductor thin film. The first surface of the substrate can be treated using at least one of the following methods: plasma method, ultraviolet / ozone irradiation method, physical vapor deposition method, chemical vapor deposition method, atomic layer deposition method, anodic oxidation method, surface cleaning and activation method with strong oxidants, and surface self-assembly monolayer method, to increase the surface energy of the first surface to be greater than 500 mJ / m². 2 This allows for the formation of a crystalline oxide semiconductor thin film on the first surface, where the angle between the indium ion alignment direction and the carrier transport direction in the crystalline oxide semiconductor thin film ranges from 0° to 45°. This results in a complete crystal structure for the oxide semiconductor thin film and a highly ordered structure in the crystalline oxide thin-film transistor, reducing carrier scattering and increasing the carrier mobility of the oxide semiconductor thin film. Consequently, the thin-film transistor formed from the crystalline oxide semiconductor thin film exhibits higher carrier mobility and better stability. For example, plasma methods can utilize gases such as H2, He, N2, Ar, O2, and N2O for plasma treatment. Specifically, N2O can be used, with a power density of 0.5–1 W / cm². 2A high surface energy insulating layer material can be formed using at least one of physical vapor deposition, chemical vapor deposition, atomic layer deposition, and anodic oxidation methods, serving as the substrate material. Examples include Al₂O₃, TiO₂, MgO, Be₂O₅, Ta₂O₅, HfO₂, ZrO₂, and Y₂O₃. Strong oxidants such as hydrogen peroxide and sulfuric acid-hydrogen peroxide mixtures (Piranha solution) can be used to clean and activate the first surface. Specifically, a hydrogen peroxide / sulfuric acid (volume ratio 1:5) solution can be used for treatment at 80°C for 20 minutes. When using a surface self-assembly monolayer method, specific molecules (such as organosilanes containing polar heads and tails capable of bonding with the substrate) can be used to form an ordered monolayer on the first surface.

[0089] The surface energy of the first surface is greater than 500 mJ / m 2 Then, a crystalline oxide semiconductor thin film is formed on the first surface, such that the crystal planes of the crystalline oxide semiconductor thin film are arranged in a specific direction, and the angle between the arrangement direction of indium ions and the transport direction of charge carriers in the crystalline oxide semiconductor thin film is in the range of 0° to 45°.

[0090] In some embodiments, when the thin-film transistor is a top-gate thin-film transistor, a crystalline oxide semiconductor thin film is disposed on the side of the buffer layer 101 away from the light-shielding layer LS. In this case, the buffer layer 101 can serve as a substrate to support the crystalline oxide semiconductor thin film. The surface of the buffer layer 101 away from the light-shielding layer LS can be processed to make the surface energy of the surface of the buffer layer 101 away from the light-shielding layer LS greater than 500 mJ / m². 2 Therefore, when forming a crystalline oxide semiconductor thin film on the buffer layer 101, the crystal planes of the crystalline oxide semiconductor thin film can be aligned in a specific direction, such that the angle between the alignment direction of indium ions and the transport direction of charge carriers in the crystalline oxide semiconductor thin film is in the range of 0° to 45°. After forming the crystalline oxide semiconductor thin film on the first surface, a gate insulating layer, a gate layer, an interlayer insulating layer, and a source / drain layer can be sequentially formed on the side of the crystalline oxide semiconductor thin film away from the substrate to form a thin film transistor.

[0091] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A crystalline oxide semiconductor thin film, characterized in that, The crystalline oxide semiconductor thin film is made of indium oxide, and further comprises a first element and / or a second element, wherein the indium oxide and the first element form D. x In y O, wherein In is the In element in the indium oxide, O is the oxygen element in the indium oxide, D is the first element, the first element includes at least one of Ga, Sc and Y, x+y=1, 0.10≤x≤0.35; The second element includes at least one of Eu, Pr, Tb, and Yb; wherein, the indium oxide, the first element, and the second element constitute D x N z In y In O, x + y + z = 1, 0.10 ≤ x ≤ 0.35, 0.0001 ≤ z ≤ 0.05, and N is the second element. The N-type oxide is composed of indium oxide and the second element. z In y In O, y+z=1, 0.0001≤z≤0.

05.

2. The crystalline oxide semiconductor thin film according to claim 1, characterized in that, The material of the crystalline oxide semiconductor thin film further includes a third element, which comprises at least one selected from Al, Ti, Nb, Ta, and Zn; wherein the indium oxide, the first element, and the third element constitute D x B a In y In O, x + y + a = 1, 0.10 ≤ x ≤ 0.35, 0.005 ≤ a ≤ 0.03, and the D composed of indium oxide, the first element, the second element, and the third element. x N z B a In y In O, x + y + a + z = 1, 0.10 ≤ x ≤ 0.35, 0.0001 ≤ z ≤ 0.05, 0.005 ≤ a ≤ 0.03, and the N-oxide composed of the indium oxide, the second element, and the third element. z B a In y In O, z + y + a = 1, 0.0001 ≤ z ≤ 0.35, 0.005 ≤ a ≤ 0.03, and the indium oxide and the third element constitute B. a In y In O, a+z=1, 0.005≤a≤0.03; B is the third element.

3. The crystalline oxide semiconductor thin film according to claim 1 or 2, characterized in that, The crystalline phase of the crystalline oxide semiconductor film is the indium oxide manganese oxide structure, and the angle between the indium ion arrangement direction and the charge carrier transport direction in the crystalline oxide semiconductor film is in the range of 0° to 45°.

4. The crystalline oxide semiconductor thin film according to claim 3, characterized in that, The ratio of the crystallinity of the crystallization peak (400) to the crystallinity of the crystallization peak (222) of the crystalline oxide semiconductor thin film ranges from 0.45 to 1.25, and the (400) crystal plane of the indium oxide accounts for more than 35% of all crystal planes of the indium oxide.

5. The crystalline oxide semiconductor thin film according to claim 1, characterized in that, The crystalline oxide semiconductor thin film comprises a plurality of sub-layers stacked together, each sub-layer comprising an adjacent indium oxide layer and a first element oxide layer.

6. The crystalline oxide semiconductor thin film according to claim 1, characterized in that, The thickness of the crystalline oxide semiconductor thin film ranges from 5 nm to 100 nm.

7. The crystalline oxide semiconductor thin film according to claim 1, characterized in that, The carrier concentration of the crystalline oxide semiconductor thin film is less than 2 × 10⁻⁶. 19 cm -3 .

8. A thin-film transistor, characterized in that, The transistor comprises a gate, a gate insulating layer, a source, a drain, and a crystalline oxide semiconductor thin film as described in any one of claims 1-7; the crystalline oxide semiconductor thin film comprises a source region, a channel region, and a drain region arranged sequentially; along the thickness direction of the thin film transistor, the gate insulating layer is disposed between the gate and the channel region, the source is connected to the source region, and the drain is connected to the drain region.

9. A method for fabricating a thin-film transistor, characterized in that, A method for fabricating the thin-film transistor of claim 8; the method includes: A raw oxide semiconductor thin film is deposited on the first surface of the substrate; The original oxide semiconductor film is annealed to form the crystalline oxide semiconductor film; wherein the annealing temperature of the original oxide semiconductor film is greater than or equal to 200°C, the material of the crystalline oxide semiconductor film includes indium oxide, and the material of the crystalline oxide semiconductor film further includes a first element and / or a second element, wherein the indium oxide and the first element form D. x In y O, wherein In is the In element in the indium oxide, O is the oxygen element in the indium oxide, D is the first element, the first element includes at least one of Ga, Sc and Y, x+y=1, 0.10≤x≤0.35; the second element includes at least one of Eu, Pr, Tb and Yb; wherein, the indium oxide, the first element and the second element constitute D x N z In y In O, x + y + z = 1, 0.10 ≤ x ≤ 0.35, 0.0001 ≤ z ≤ 0.05, and N is the second element. The N-type oxide is composed of indium oxide and the second element. z In y In O, y+z=1, 0.0001≤z≤0.

05.

10. The method for fabricating a thin-film transistor according to claim 9, characterized in that, Before depositing the original oxide semiconductor thin film on the first surface of the substrate, the process also includes: The first surface of the substrate is treated to make its surface energy greater than 500 mJ / m 2 .

Images