Uninterruptible power supply device

Abstract

The AC input filter (2) includes a first reactor (12RA) having a first terminal connected to the second terminal of the switch (1), and a second reactor (12RB) having a first terminal connected to the second terminal of the switch (1). The converter (3) includes a first multilevel circuit (3A) connected between the second terminal of the first reactor (12RA) and the first to third DC lines (L1 to L3), and a second multilevel circuit (3B) connected between the second terminal of the second reactor (12RB) and the first to third DC lines (L1 to L3). The control device calculates a first voltage, which is the sum of the voltages between the terminals of the first and second capacitors (C1, C2), and a second voltage, which is the difference between the voltages between the terminals of the first and second capacitors (C1, C2). When the AC power supply is normal, the control device controls the first and second multilevel circuits (3A, 3B) such that the first voltage becomes a reference voltage and the second voltage disappears. When the AC power supply is powered off, the control device controls the first and second multilevel circuits (3A, 3B) so that the second voltage disappears.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an uninterruptible power supply device. BACKGROUND

[0002] For example, an uninterruptible power supply device provided with a converter, a DC voltage converter, and an inverter is disclosed in Japanese Patent Application Publication No. 2013-176296 (Patent Literature 1). The converter converts an alternating-current voltage from an alternating-current power supply into first to third direct-current voltages and outputs to first to third direct-current lines when the alternating-current power supply is normal. The DC voltage converter converts a fourth direct-current voltage from an electric storage device into the first to third direct-current voltages and supplies to the first to third direct-current lines when the alternating-current power supply is out of operation. The inverter converts the first to third direct-current voltages from the first to third direct-current lines into an alternating-current voltage and supplies to a load.

[0003] The uninterruptible power supply device is further provided with a first capacitor connected between the first and second direct-current lines, a second capacitor connected between the second and third direct-current lines, and a control device. As a "balance control" to eliminate imbalance of the terminal-to-terminal voltages of the first and second capacitors, the control device controls the converter so that the sum of the terminal-to-terminal voltages of the first and second capacitors, that is, a first voltage becomes a reference voltage and the difference between the terminal-to-terminal voltages of the first and second capacitors, that is, a second voltage disappears when the alternating-current power supply is normal. When the alternating-current power supply is out of operation, the operation of the converter is stopped, and the DC voltage converter is controlled so that the first voltage becomes the reference voltage and the second voltage disappears.

[0004] As another method of the balance control of the first and second capacitors, an uninterruptible power supply device in which the alternating-current power supply and the load are three-phase 4-wire type is disclosed in International Publication No. 2020 / 105126 (Patent Literature 2). In the uninterruptible power supply device, the control device controls the converter so that the first voltage becomes the reference voltage and the difference between the terminal-to-terminal voltages of the first and second capacitors, that is, the second voltage disappears when the alternating-current power supply is normal. When the alternating-current power supply is out of operation, the control device controls the DC voltage converter so that the first voltage becomes the reference voltage and the second voltage disappears. When the absolute value of the second voltage exceeds a prescribed threshold voltage when the alternating-current power supply is out of operation, the control device also controls the converter to reduce the second voltage.

[0005] PRIOR ART DOCUMENTS

[0006] PATENT LITERATURE

[0007] Patent Literature 1: Japanese Patent Application Publication No. 2013-176296

[0008] Patent Literature 2: International Publication No. 2020 / 105126 SUMMARY

[0009] Problems to be Solved by the Invention

[0010] In the balance control described in Patent Literature 1, in a case where the load current is small at the time of the outage of the alternating current power supply, the output current of the direct current voltage converter becomes small, and thus it can be difficult to eliminate the imbalance of the terminal voltage of the first and second capacitors.

[0011] On the other hand, in the balance control described in Patent Literature 2, in a case where the absolute value of the second voltage exceeds the threshold voltage at the time of the outage of the alternating current power supply, the converter is activated, so that the imbalance of the terminal voltage of the first and second capacitors can be eliminated even in a case where the load current is small.

[0012] However, in Patent Literature 2, at the time of the outage of the alternating current power supply, the alternating current power supply is electrically cut off from the alternating current input filter, and a capacitor (hereinafter also referred to as "filter capacitor") included in the alternating current input filter (LC filter circuit) is used as a power buffer to operate the converter, so that the first and second capacitors are discharged or charged. In this case, the magnitude of the current input and output with respect to the first and second capacitors depends on the difference between the terminal voltage of the first and second capacitors and the terminal voltage of the filter capacitor. However, since the uninterruptible power supply device does not have a detector for detecting the terminal voltage of the filter capacitor, the difference between the terminal voltage of the first and second capacitors and the terminal voltage of the filter capacitor cannot be grasped, and it can be difficult to perform the balance control by the converter.

[0013] In addition, in Patent Literature 2, if the difference between the terminal voltage of the first and second capacitors and the terminal voltage of the filter capacitor disappears, the first and second capacitors cannot be discharged or charged even if the converter is operated, and thus an operation for discharging the filter capacitor is required. Therefore, in Patent Literature 2, the second voltage is reduced by alternately repeating the operation of discharging or charging the first and second capacitors and the operation of discharging the filter capacitor. Thus, at the time of the outage of the alternating current power supply, it can be difficult to quickly eliminate the imbalance of the first and second capacitors.

[0014] The present application has been made to solve the above problems, and an object of the present application is to provide an uninterruptible power supply device capable of simply and quickly eliminating the imbalance of the terminal voltage of the first and second capacitors at the time of the outage of the alternating current power supply.

[0015] Means for Solving the Problems

[0016] The uninterruptible power supply device of one embodiment of the present disclosure includes first to third direct-current lines, a first capacitor, a second capacitor, a switch, an alternating-current input filter, a converter, an inverter, first and second voltage detectors, and a control device. The first capacitor is connected between the first and second direct-current lines. The second capacitor is connected between the second and third direct-current lines. The first terminal of the switch receives an alternating-current voltage supplied from an alternating-current power supply and is turned on when the alternating-current power supply is normal and turned off when the alternating-current power supply is out of operation. The first terminal of the alternating-current input filter is connected to the second terminal of the switch. The converter is connected between the second terminal of the alternating-current input filter and the first to third direct-current lines. The converter converts alternating-current power from the alternating-current power supply into direct-current power and supplies the direct-current power to the first to third direct-current lines when the alternating-current power supply is normal. The inverter is connected between the first to third direct-current lines and a load, converts direct-current power from the first to third direct-current lines into alternating-current power, and supplies the alternating-current power to the load. The first and second voltage detectors detect voltages between the terminals of the first and second capacitors, respectively. The control device controls the converter on the basis of the detection values of the first and second voltage detectors.

[0017] The alternating-current input filter includes a first reactor whose first terminal is connected to the second terminal of the switch and a second reactor whose first terminal is connected to the second terminal of the switch. The converter includes a first multi-level circuit and a second multi-level circuit. The first multi-level circuit is connected between the second terminal of the first reactor and the first to third direct-current lines and is configured to be able to convert an alternating-current voltage and first to third direct-current voltages into each other. The second multi-level circuit is connected between the second terminal of the second reactor and the first to third direct-current lines and is configured to be able to convert an alternating-current voltage and first to third direct-current voltages into each other.

[0018] The control device calculates a sum of the voltages between the terminals of the first and second capacitors, i.e., a first voltage, and a difference between the voltages between the terminals of the first and second capacitors, i.e., a second voltage, on the basis of the detection values of the first and second voltage detectors. When the alternating-current power supply is normal, the control device controls the first and second multi-level circuits so that the first voltage becomes a first reference voltage and the second voltage disappears. When the alternating-current power supply is out of operation, the control device controls the first and second multi-level circuits so that the second voltage disappears.

[0019] Effects of Invention

[0020] According to the present disclosure, an uninterruptible power supply device in which an imbalance in the voltages between the terminals of first and second capacitors can be eliminated simply and quickly when an alternating-current power supply is out of operation can be provided. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is a block diagram illustrating the overall configuration of the uninterruptible power supply device of Embodiment 1.

[0022] Figure 2is a block diagram showing a hardware configuration example of the control device.

[0023] Figure 3 is a block diagram showing a hardware configuration example of the control device. Figure 1 is a circuit diagram showing a configuration example of the converter.

[0024] Figure 4 is a circuit diagram showing a configuration example of the converter. Figure 1 is a circuit diagram showing a configuration example of the DC voltage converter.

[0025] Figure 5 is a block diagram showing a portion of the control device associated with the control of the converter and the DC voltage converter.

[0026] Figure 6 is a block diagram showing a configuration of the first control circuit. Figure 5

[0027] Figure 7 is a block diagram showing a configuration of the PWM circuit. Figure 6

[0028] Figure 8 is a timing chart showing waveforms of the voltage command value, the triangular wave signal, and the PWM signal. Figure 7

[0029] Figure 9 is a diagram showing a switching pattern of the four IGBTs included in each bridge circuit.

[0030] Figure 10 is a timing chart showing an operation of the second control circuit. Figure 5

[0031] is an equivalent circuit diagram showing an operation of one phase of the converter in a case where Ep > En. Figure 11

[0032] is an equivalent circuit diagram showing an operation of one phase of the converter in a case where Ep > En. Figure 12

[0033] is a timing chart showing an operation of the second control circuit. Figure 13 Figure 5 is an equivalent circuit diagram showing an operation of one phase of the converter in a case where Ep < En.

[0034] Figure 14 is an equivalent circuit diagram showing an operation of one phase of the converter in a case where Ep < En.

[0035] Figure 15 is a timing chart showing an operation of the second control circuit.

[0036] Figure 16 Figure 5 ​​​​​A block diagram showing the configuration of the control circuit.

[0037] Figure 17 A flowchart showing an example of balance control of the converter at the time of outage of the commercial AC power supply.

[0038] Figure 18 A circuit diagram showing the main part of the uninterruptible power supply device of Embodiment 3.

[0039] Figure 19 A diagram showing the switching pattern of the four IGBTs included in each bridge circuit.

[0040] Figure 20 A timing chart showing the operation of the second control circuit.

[0041] Figure 21 An equivalent circuit diagram showing the operation of one phase of the converter in the case of Ep > En.

[0042] Figure 22 An equivalent circuit diagram showing the operation of one phase of the converter in the case of Ep > En.

[0043] Figure 23 A timing chart showing the operation of the second control circuit.

[0044] Figure 24 An equivalent circuit diagram showing the operation of one phase of the converter in the case of Ep < En.

[0045] Figure 25 An equivalent circuit diagram showing the operation of one phase of the converter in the case of Ep < En. DETAILED DESCRIPTION

[0046] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In addition, the same or corresponding portions will be labeled with the same reference numerals in the drawings, and the description thereof will not be repeated.

[0047] [Embodiment 1]

[0048] <Configuration of Uninterruptible Power Supply Device>

[0049] Figure 1 A block diagram showing the overall configuration of the uninterruptible power supply device 100 of Embodiment 1. As shown in the drawing, the uninterruptible power supply device 100 includes a switch 1, an AC input filter 2, a converter 3, an inverter 4, an AC output filter 5, a DC voltage converter (hereinafter referred to as "DC / DC") 6, a control device 10, DC lines L1 to L3, a neutral line L4, capacitors C1, C2, voltage detectors 31, 34, 35, current detectors 32, 37, and an outage detector 33. Figure 1 ​

[0050] The switch 1 includes switches 1R, 1S, 1T. First terminals of the switches 1R, 1S, 1T are connected to an R-phase terminal TR, an S-phase terminal TS, and a T-phase terminal TT of the commercial AC power supply 41, respectively, and receive an R-phase voltage VR, an S-phase voltage VS, and a T-phase voltage VT supplied from the commercial AC power supply 41, respectively. A neutral point terminal TN of the commercial AC power supply 41 is connected to one end of a neutral line L4.

[0051] The switches 1R, 1S, 1T are controlled by the control device 10, and are turned on when three-phase AC power is normally supplied from the commercial AC power supply 41 (when the commercial AC power supply 41 is normal), and are turned off when the supply of three-phase AC power from the commercial AC power supply 41 is stopped (when the commercial AC power supply 41 is off). The switches 1R, 1S, 1T are turned off when the commercial AC power supply 41 is off, and electrically cut off the commercial AC power supply 41 from the AC input filter 2.

[0052] The AC input filter 2 is a three-phase LC filter circuit composed of capacitors 11 (capacitors 11R, 11S, 11T) and reactors 12 (reactors 12R, 12S, 12T). Positive electrodes of the capacitors 11R, 11S, 11T are connected to second terminals of the switches 1R, 1S, 1T, respectively, and their negative electrodes are connected to the neutral line L4. First terminals of the reactors 12R, 12S, 12T are connected to the second terminals of the switches 1R, 1S, 1T, respectively, and second terminals of the reactors 12R, 12S, 12T are connected to three input nodes of the converter 3, respectively.

[0053] The AC input filter 2 is a low-pass filter, and passes commercial frequency AC power supplied from the commercial AC power supply 41 through the converter 3, and prevents a switching frequency signal generated by the converter 3 from passing to the commercial AC power supply 41 side.

[0054] First ends of the DC lines L1 to L3 are connected to three output nodes of the converter 3, and second ends thereof are connected to three input nodes of the inverter 4. The DC line L2 is connected to the neutral line L4. In addition, the DC lines L1 to L3 are connected to three high voltage side nodes of the DC voltage converter 6. The DC lines L1 to L3 become positive voltage, neutral point voltage, and negative voltage, respectively, through the converter 3 and the DC voltage converter 6.

[0055] The capacitor Cl is connected between the DC lines L1 and L2, and smoothes and stabilizes a DC voltage Ep between the DC lines L1 and L2. The capacitor C2 is connected between the DC lines L2 and L3, and smoothes and stabilizes a DC voltage En between the DC lines L2 and L3.

[0056] The converter 3 is controlled by the control device 10 to convert the three-phase alternating current power supplied from the commercial alternating current power source 41 via the alternating current input filter 2 into direct current power when the commercial alternating current power source 41 is normal, and to supply the direct current power to the inverter 4 and the direct current voltage converter 6 via the direct current lines LI to L3.

[0057] At this time, the control device 10 controls the converter 3 so that the direct current voltage VDC = Ep + En of the sum of the direct current voltages Ep, En becomes the reference direct current voltage VDCR, and the direct current voltage AE = Ep - En of the difference between the direct current voltages Ep, En becomes 0.

[0058] In addition, the control device 10 controls the converter 3 so that the direct current voltage AE = Ep - En of the difference between the direct current voltages Ep, En becomes 0 when the commercial alternating current power source 41 is out of operation. In the case where the direct current voltage AE = Ep - En of the difference between the direct current voltages Ep, En becomes 0, the control device 10 stops the operation of the converter 3.

[0059] The inverter 4 is controlled by the control device 10 to convert the direct current power from the converter 3 and the direct current voltage converter 6 into three-phase alternating current power of a commercial frequency. The three-phase alternating current power generated by the inverter 4 is supplied to the load 42 via the alternating current output filter 5.

[0060] The alternating current output filter 5 is an LC filter circuit of three phases composed of the reactors 18 (reactors 18U, 18V, 18W) and the capacitors 19 (capacitors 19U, 19V, 19W). The first terminals of the reactors 18U, 18V, 18W are connected to the 3 output nodes of the inverter 4, and the second terminals thereof are connected to the U-phase terminal TU, the V-phase terminal TV, and the W-phase terminal TW of the load 42.

[0061] The positive electrodes of the capacitors 19U, 19V, 19W are connected to the second terminals of the reactors 18U, 18V, 18W, and the negative electrodes thereof are connected to the neutral point line L4. The alternating current output filter 5 is a low pass filter that passes the three-phase alternating current power of a commercial frequency generated by the inverter 4 and prevents signals of a switching frequency generated by the inverter 4 from passing to the load 42. The neutral point terminal TNA of the load 42 is connected to the neutral point line L4. The load 42 is driven by the three-phase alternating current power supplied from the uninterruptible power supply device 100.

[0062] The battery Bl (storage device) is connected between the 2 low voltage nodes of the direct current voltage converter 6. The direct current voltage converter 6 is controlled by the control device 10 to store the direct current power generated by the converter 3 in the battery Bl when the commercial alternating current power source 41 is normal. At this time, the control device 10 controls the direct current voltage converter 6 so that the terminal voltage VB of the battery Bl becomes the reference battery voltage VBR.

[0063] Further, when the commercial AC power source 41 is out of operation, the DC voltage converter 6 supplies the DC power of the battery Bl to the inverter 4 via the DC lines LI to L3. At this time, the control device 10 controls the DC voltage converter 6 in such a manner that the DC voltage VDC = Ep + En of the sum of the DC voltages Ep, En becomes the reference DC voltage VDCR.

[0064] Further, instead of the battery Bl, a capacitor (for example, an electric double layer capacitor) can be connected to the DC voltage converter 6. In the present embodiment, the battery Bl is provided outside the uninterruptible power supply device 100, but the battery Bl can be built in the uninterruptible power supply device 100.

[0065] The voltage detector 31 detects the instantaneous values of the AC voltages VR, VS, VT of the second terminals of the switches IR, IS, IT, and outputs three-phase voltage signals representing the three-phase AC voltages VR, VS, VT to the control device 10 and the power failure detector 33. The current detector 32 detects the instantaneous values of the AC currents IR, IS, IT flowing into the three input nodes of the converter 3, and outputs three-phase current signals representing the three-phase AC currents IR, IS, IT to the control device 10.

[0066] The power failure detector 33 determines whether or not the power failure of the commercial AC power source 41 has occurred on the basis of the three-phase voltage signals from the voltage detector 31, and outputs a power failure signal PC representing the determination result. When the commercial AC power source 41 is normal, the power failure signal PC becomes the inactive level "L" level. When the commercial AC power source 41 is out of operation, the power failure signal PC becomes the active level "H" level. The power failure signal PC is supplied to the control device 10.

[0067] The voltage detector 34 detects the voltage Ep between the terminals of the capacitor Cl, and outputs a signal representing the detected voltage Ep to the control device 10. The voltage detector 35 detects the voltage En between the terminals of the capacitor C2, and outputs a signal representing the detected voltage En to the control device 10. The voltage detector 36 detects the voltage VB between the terminals of the battery Bl, and outputs a signal representing the detected voltage VB to the control device 10. The current detector 37 detects the current IB output from the battery Bl, and outputs a signal representing the detected current IB to the control device 10.

[0068] The control device 10 controls the entire uninterruptible power supply device 100 on the basis of the three-phase voltage signals from the voltage detector 31, the three-phase current signals from the current detector 32, the signals from the voltage detectors 34 to 36, the signal from the current detector 37, the power failure signal PC from the power failure detector 33, and the like.

[0069] The converter 3, the inverter 4, and the DC voltage converter 6 are configured of semiconductor switches including semiconductor switching elements. In the present embodiment, an IGBT (Insulated Gate Bipolar Transistor) is used as the semiconductor switching element. As a control method of the semiconductor switching element, PWM (Pulse Width Modulation) control can be applied.

[0070] Figure 2 is a block diagram showing a hardware configuration example of the control device 10. As shown in Figure 2 , the control device 10 is configured to include a CPU (Central Processing Unit) 102, a memory 104, and an input / output (I / O) circuit 106. The CPU 102, the memory 104, and the I / O circuit 106 can exchange data with each other via a bus 108. A program is stored in a part of the memory 104, and by the CPU 102 executing the program, various functions described later can be implemented. The I / O circuit 106 inputs and outputs signals and data between the outside of the control device 10.

[0071] Alternatively, unlike the example of Figure 2 , at least a part of the control device 10 can be configured using a circuit such as an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit). In addition, at least a part of the control device 10 can be configured by an analog circuit.

[0072] (Circuit configuration example of converter)

[0073] Figure 3 is a circuit diagram showing a configuration example of the converter 3 shown in Figure 1 . As shown in Figure 3 , the converter 3 includes an R-phase arm 3R, an S-phase arm 3S, and a T-phase arm 3T. The circuit configurations of the respective phase arms 3R, 3S, 3T of the converter 3 are the same, and thus the circuit configuration of the R-phase arm 3R will be described representatively.

[0074] As shown in Figure 3As shown, the reactor 12R includes reactors 12RA, 12RB. The R-phase arm 3R includes three-level circuits 3A, 3B. The first terminal of the reactor 12RA is connected to the second terminal of the switch 1R, and the second terminal of the reactor 12RA is connected to the input node 3a of the three-level circuit 3A. The first terminal of the reactor 12RB is connected to the second terminal of the switch 1R, and the second terminal of the reactor 12RB is connected to the input node 3b of the three-level circuit 3B. The reactor 12RA corresponds to an embodiment of the "first reactor", and the reactor 12RB corresponds to an embodiment of the "second reactor".

[0075] The three-level circuit 3A includes IGBTs Q1A to Q4A and diodes D1A to D4A. The collector of the IGBT Q1A is connected to the DC line L1, and the emitter thereof is connected to the input node 3a. The emitters of the IGBTs Q2A, Q4A are connected to each other, and the collectors thereof are connected to the input node 3a and the DC line L2, respectively. The collector of the IGBT Q3A is connected to the input node 3a, and the emitter thereof is connected to the DC line L3. The diodes D1A to D4A are connected in anti-parallel to the IGBTs Q1A to Q4A, respectively.

[0076] The three-level circuit 3A corresponds to an embodiment of the "first multi-level circuit". The IGBT Q1A and the diode D1A constitute a "first switch", the IGBTs Q2A, Q4A and the diodes D2A, D4A constitute a "second switch", and the IGBT Q3A and the diode D3A constitute a "third switch".

[0077] The three-level circuit 3B includes IGBTs Q1B to Q4B and diodes D1B to D4B. The collector of the IGBT Q1B is connected to the DC line L1, and the emitter thereof is connected to the input node 3b. The emitters of the IGBTs Q2B, Q4B are connected to each other, and the collectors thereof are connected to the input node 3b and the DC line L2, respectively. The collector of the IGBT Q3B is connected to the input node 3b, and the emitter thereof is connected to the DC line L3. The diodes D1B to D4B are connected in anti-parallel to the IGBTs Q1B to Q4B, respectively.

[0078] The three-level circuit 3B corresponds to an embodiment of the "second multi-level circuit". The IGBT Q1B and the diode D1B constitute a "fourth switch", the IGBTs Q2B, Q4B and the diodes D2B, D4B constitute a "fifth switch", and the IGBT Q3B and the diode D3B constitute a "sixth switch".

[0079] (Circuit configuration example of DC voltage converter)

[0080] Figure 4 is a circuit diagram showing a configuration example of the DC voltage converter 6. As shown in FIG. 6, the DC voltage converter 6 includes a DC voltage source 2, a switch 1, a three-level circuit 3, and a reactor 12. The DC voltage source 2 includes a DC line L1 and a DC line L2. The switch 1 includes a first terminal and a second terminal. The three-level circuit 3 includes an input node 3a and an input node 3b. The reactor 12 includes a first terminal and a second terminal. Figure 1 is a circuit diagram showing a configuration example of the DC voltage converter 6. As shown in FIG. 6, the DC voltage converter 6 includes a DC voltage source 2, a switch 1, a three-level circuit 3, and a reactor 12. The DC voltage source 2 includes a DC line L1 and a DC line L2. The switch 1 includes a first terminal and a second terminal. The three-level circuit 3 includes an input node 3a and an input node 3b. The reactor 12 includes a first terminal and a second terminal. Figure 4As shown, the DC-DC voltage converter 6 includes a semiconductor switch 21 and a reactor 22. The semiconductor switch 21 is configured as a three-level circuit, including IGBTs Q1D to Q4D connected in series between DC lines L1 and L3, and diodes D1D to D4D connected in anti-parallel to IGBTs Q1D to Q4D.

[0081] Reactor 22 includes reactors 22P and 22N. Reactor 22P is connected between the connection point of IGBTs Q1D and Q2D and the positive terminal of battery B1. Reactor 22N is connected between the connection point of IGBTs Q3D and Q4D and the negative terminal of battery B1. Alternatively, reactor 22 may include either reactor 22P or 22N.

[0082] <Control Structure of Uninterruptible Power Supply Device>

[0083] Figure 5 This is a block diagram showing the part of the control device 10 associated with the control of the converter 3 and the DC voltage converter 6.

[0084] like Figure 5 As shown, the control device 10 includes an adder 51, a subtractor 52, a first control circuit 53, a second control circuit 54, a switching circuit 55, and a control circuit 80.

[0085] Adder 51 adds the voltages Ep and En between the terminals of capacitors C1 and C2 detected by voltage detectors 34 and 35 to calculate the DC voltage VDC between DC lines L1 and L3: VDC = Ep + En. The DC voltage VDC is then supplied to control circuits 53 and 80.

[0086] Subtractor 52 subtracts the voltage between the terminals of capacitor C2 detected by voltage detector 35 from the voltage Ep between the terminals of capacitor C1 detected by voltage detector 34, and calculates the difference between the voltages Ep and En between the terminals of capacitors C1 and C2, i.e., the DC voltage ΔE = Ep - En. The DC voltage ΔE is provided to control circuits 53, 54, and 80, respectively.

[0087] The first control circuit 53 controls the converter 3 based on the three-phase voltage signal from the voltage detector 31, the three-phase current signal from the current detector 32, the signal representing the DC voltage VDC from the adder 51, and the signal representing the DC voltage ΔE from the subtractor 52. Specifically, the first control circuit 53 controls the converter 3 in such a way that the phases of the three-phase AC voltages VR, VS, VT are aligned with the phases of the three-phase AC currents IR, IS, IT, the DC voltage VDC becomes the reference DC voltage VDCR, and the DC voltage ΔE becomes 0.

[0088] The second control circuit 54 controls the converter 3 based on the signal representing the DC voltage ΔE from the subtractor 52. Specifically, the second control circuit 54 controls the converter 3 in a manner that makes the DC voltage ΔE zero.

[0089] A switching circuit 55 is disposed between the control circuits 53 and 54 and the converter 3. Based on the power outage signal PC from the power outage detector 33, the switching circuit 55 connects either of the control circuits 53 and 54 to the converter 3. Specifically, when the power outage signal PC is at an inactive "L" level (when the commercial AC power supply 41 is normal), the switching circuit 55 connects the first control circuit 53 to the converter 3. When the power outage signal PC is at an active "H" level (when the commercial AC power supply 41 is interrupted), the switching circuit 55 connects the second control circuit 54 to the converter 3.

[0090] The switching circuit 55 also controls the switching of switches 1R, 1S, and 1T based on the power outage signal PC from the power outage detector 33. Specifically, the switching circuit 55 turns on switches 1R, 1S, and 1T when the power outage signal PC is at an inactive "L" level (when the commercial AC power supply 41 is normal), and turns off switches 1R, 1S, and 1T when the power outage signal PC is at an active "H" level (when the commercial AC power supply 41 is interrupted).

[0091] (The structure of the first control circuit)

[0092] Figure 6 It means Figure 5 The block diagram shown illustrates the configuration of the first control circuit 53. Figure 6 As shown, the first control circuit 53 includes a voltage command generation circuit 60, a balance control circuit 70, adders 71A to 71C, and a PWM circuit 72.

[0093] The voltage command generation circuit 60 includes a reference voltage generation circuit 61, subtractors 62, 66A to 66C, a DC voltage control circuit 63, a sine wave generation circuit 64, multipliers 65A to 65C, a current control circuit 67, and adders 68A to 68C.

[0094] Reference voltage generation circuit 61 generates a reference DC voltage VDCR. Subtractor 62 calculates the voltage difference ΔVDC = VDCR - VDC between the reference DC voltage VDCR and the DC voltage VDC from adder 51. DC voltage control circuit 63 calculates a current command value I* for controlling the current flowing on the input side of converter 3 in a manner that makes voltage ΔVDC zero. DC voltage control circuit 63 calculates the current command value I*, for example, by performing a proportional operation or a proportional-integral operation on ΔVDC.

[0095] The sine wave generating circuit 64 outputs a sine wave signal in phase with the R-phase voltage VR of the commercial AC power source 41, a sine wave signal in phase with the S-phase voltage VS of the commercial AC power source 41, and a sine wave signal in phase with the T-phase voltage VT of the commercial AC power source 41. The three sine wave signals are input to the multipliers 65A to 65C, respectively, and multiplied by the current command value I*. Thus, the current command values IR*, IS*, IT* in phase with the three-phase AC voltages VR, VS, VT of the commercial AC power source 41 are generated.

[0096] The subtracter 66A calculates the difference between the current command value IR* and the R-phase current IR detected by the current detector 32R. The subtracter 66B calculates the difference between the current command value IS* and the S-phase current IS detected by the current detector 32S. The subtracter 66C calculates the difference between the current command value IT* and the T-phase current IT detected by the current detector 32T.

[0097] The current control circuit 67 generates the voltage command values VRa*, VSa*, VTa* as voltages to be applied to the reactor 12 so that the differences between the current command values IR*, IS*, IT* and the R-phase, S-phase, and T-phase currents IR, IS, IT, respectively, are zero. The current control circuit 67 amplifies the differences between the current command values and the current values detected by the current detector 32, for example, according to proportional control or proportional integral control, thereby generating the voltage command values.

[0098] The adder 68A adds the voltage command value VRa* to the R-phase voltage VR detected by the voltage detector 31 to generate the voltage command value VR0*. The adder 71B adds the voltage command value VSa* to the S-phase voltage VS detected by the voltage detector 31 to generate the voltage command value VS0*. The adder 68C adds the voltage command value VTa* to the T-phase voltage VT detected by the voltage detector 31 to generate the voltage command value VT0*.

[0099] Thus, the voltage command generating circuit 60 receives the three-phase AC voltages VR, VS, VT detected by the voltage detector 31, the three-phase AC currents IR, IS, IT detected by the current detector 32, and the DC voltage VDC calculated by the adder 51, and generates the voltage command values VR0*, VS0*, VT0* corresponding to the R-phase, S-phase, and T-phase, respectively.

[0100] The balance control circuit 70 generates a voltage command value V1* based on the direct current voltage ΔE = Ep- En from the subtracter 52. For example, the balance control circuit 70 generates the voltage command value V1* by performing proportional operation or proportional integral operation on ΔE. In the case of ΔE = Ep- En > 0, the voltage command value V1* is generated in such a manner that the charging time of the capacitor Cl is shorter than the charging time of the capacitor C2. In the case of ΔE = Ep- En < 0, the voltage command value V1* is generated in such a manner that the charging time of the capacitor Cl is longer than the charging time of the capacitor C2.

[0101] The adder 71A adds the voltage command values VR0*, V1* to generate a voltage command value VR*. The adder 71B adds the voltage command values VS0*, V1* to generate a voltage command value VS*. The adder 71C adds the voltage command values VT0*, V1* to generate a voltage command value VT*. The voltage command values VR*, VS*, VT* become sinusoidal wave signals of the commercial frequency.

[0102] The PWM circuit 72 outputs signals for making the three-phase alternating voltages VR, VS, VT detected by the voltage detector 31 respectively equal to the voltage command values VR*, VS*, VT* based on the voltage command values VR*, VS*, VT*. The signals are PWM signals φ1A- φ4A, φ1B- φ4B for controlling the turn-on and turn-off of the eight IGFTs Q1A- Q4A, Q1B- Q4B included in the respective phase arms of the converter 3.

[0103] Figure 7 is a block diagram showing the configuration of the PWM circuit 72. Figure 6 is a block diagram showing the configuration of the PWM circuit 72. Figure 7 is a block diagram showing the configuration of the PWM circuit 72.

[0104] As shown in Figure 7 , the PWM circuit 72 includes an oscillator 90, triangular wave generators 91- 94, comparators 95- 98, buffers 110, 112, 114, 116, and NOT circuits 111, 113, 115, 117.

[0105] The oscillator 90 outputs a clock signal whose frequency is sufficiently higher than the commercial frequency. The triangular wave generators 91- 94 respectively output triangular wave signals Cu1a, Cu1b, Cu2a, Cu2b of the same frequency as the output clock signal of the oscillator 90.

[0106] The triangular wave signals Cu1a, Cu1b are signals of the same phase. The triangular wave signals Cu2a, Cu2b are signals of the same phase. The phase of the triangular wave signal Cu1a is different from that of the triangular wave signal Cu2a. In the example of Figure 7 , the triangular wave signal Cu2a is shifted by 180° in phase from the triangular wave signal Cu1a.

[0107] The comparator 95 compares the voltage command value VR* with the high and low of the triangular wave signal Cu1a from the triangular wave generator 91, and outputs a PWM signal φ1A indicating the comparison result. The buffer 110 supplies the PWM signal φ1A to the three-level circuit 3A. The NOT circuit 111 inverts the PWM signal φ1A, generates a PWM signal φ2A, and supplies it to the three-level circuit 3A. The IGBTs Q1A and Q2A are turned on when the PWM signals φ1A and φ2A are at the "H" level, respectively, and are turned off when the PWM signals φ1A and φ2A are at the "L" level, respectively.

[0108] The comparator 96 compares the voltage command value VR* with the high and low of the triangular wave signal Cu1b from the triangular wave generator 92, and outputs a PWM signal φ3A indicating the comparison result. The buffer 112 supplies the PWM signal φ3A to the three-level circuit 3A. The NOT circuit 113 inverts the PWM signal φ3A, generates a PWM signal φ4A, and supplies it to the three-level circuit 3A. The IGBTs Q3A and Q4A are turned on when the PWM signals φ3A and φ4A are at the "H" level, respectively, and are turned off when the PWM signals φ3A and φ4A are at the "L" level, respectively.

[0109] The comparator 97 compares the voltage command value VR* with the high and low of the triangular wave signal Cu2a from the triangular wave generator 93, and outputs a PWM signal φ1B indicating the comparison result. The buffer 114 supplies the PWM signal φ1B to the three-level circuit 3B. The NOT circuit 115 inverts the PWM signal φ1B, generates a PWM signal φ2B, and supplies it to the three-level circuit 3B. The IGBTs Q1B and Q2B are turned on when the PWM signals φ1B and φ2B are at the "H" level, respectively, and are turned off when the PWM signals φ1B and φ2B are at the "L" level, respectively.

[0110] The comparator 98 compares the voltage command value VR* with the high and low of the triangular wave signal Cu2b from the triangular wave generator 94, and outputs a PWM signal φ3B indicating the comparison result. The buffer 116 supplies the PWM signal φ3B to the three-level circuit 3B. The NOT circuit 117 inverts the PWM signal φ3B, generates a PWM signal φ4B, and supplies it to the three-level circuit 3B. The IGBTs Q3B and Q4B are turned on when the PWM signals φ3B and φ4B are at the "H" level, respectively, and are turned off when the PWM signals φ3B and φ4B are at the "L" level, respectively.

[0111] Figure 8 is a timing chart showing the waveforms of the voltage command value VR*, the triangular wave signals Cu1a, Cu1b, Cu2a, Cu2b, and the PWM signals φ1A to φ4A, φ1B to φ4B. In Figure 7 is a timing chart showing the waveforms of the voltage command value VR*, the triangular wave signals Cu1a, Cu1b, Cu2a, Cu2b, and the PWM signals φ1A to φ4A, φ1B to φ4B. In Figure 8In the drawing, (A) shows the waveforms of the voltage command value VR* and the triangular wave signals Cu1a, Cu1b, Cu2a, Cu2b, and (B) to (E) show the waveforms of the PWM signals φ1A, φ3A, φ4A, φ2A, respectively. (F) to (I) show the waveforms of the PWM signals φ1B, φ3B, φ4B, φ2B, respectively.

[0112] As shown in (A) of FIG. 6, the voltage command value VR* is a sinusoidal wave signal of a commercial frequency. The voltage command value VR* is a voltage command value in the case where Ep= En (i.e., a state where the voltage command value is not corrected by the balance control circuit 70) (VR* = VR0*). Figure 8 The minimum value of the triangular wave signals Cu1a, Cu2a is 0 V, and the maximum value thereof is higher than the positive peak value of the voltage command value VR*. The maximum value of the triangular wave signals Cu1b, Cu2b is 0 V, and the minimum value thereof is lower than the negative peak value of the voltage command value VR*. The triangular wave signals Cu1a, Cu1b are in-phase signals. The triangular wave signals Cu2a, Cu2b are in-phase signals. The triangular wave signal Cu2a is out of phase by 180° from the triangular wave signal Cu1a. The triangular wave signal Cu2b is out of phase by 180° from the triangular wave signal Cu1b.

[0113] As shown in (A) of FIG. 6, the voltage command value VR* is a sinusoidal wave signal of a commercial frequency. The voltage command value VR* is a voltage command value in the case where Ep= En (i.e., a state where the voltage command value is not corrected by the balance control circuit 70) (VR* = VR0*).

[0114] As shown in (A) of FIG. 6, the voltage command value VR* is a sinusoidal wave signal of a commercial frequency. The voltage command value VR* is a voltage command value in the case where Ep= En (i.e., a state where the voltage command value is not corrected by the balance control circuit 70) (VR* = VR0*). Figure 8 As shown in (A) of FIG. 6, the voltage command value VR* is a sinusoidal wave signal of a commercial frequency. The voltage command value VR* is a voltage command value in the case where Ep= En (i.e., a state where the voltage command value is not corrected by the balance control circuit 70) (VR* = VR0*). Figure 8 As shown in (B) of FIG. 6, the PWM signal φ2A is an inverted signal of the PWM signal φ1A.

[0115] As shown in (A) of FIG. 6, the voltage command value VR* is a sinusoidal wave signal of a commercial frequency. The voltage command value VR* is a voltage command value in the case where Ep= En (i.e., a state where the voltage command value is not corrected by the balance control circuit 70) (VR* = VR0*). Figure 8 As shown in (A) of FIG. 6, the voltage command value VR* is a sinusoidal wave signal of a commercial frequency. The voltage command value VR* is a voltage command value in the case where Ep= En (i.e., a state where the voltage command value is not corrected by the balance control circuit 70) (VR* = VR0*). Figure 8 As shown in (C) of FIG. 6, the PWM signal φ4A is an inverted signal of the PWM signal φ3A.

[0116] As shown in (A) of FIG. 6, the voltage command value VR* is a sinusoidal wave signal of a commercial frequency. The voltage command value VR* is a voltage command value in the case where Ep= En (i.e., a state where the voltage command value is not corrected by the balance control circuit 70) (VR* = VR0*).

[0117] As shown in (A) of FIG. 6, the voltage command value VR* is a sinusoidal wave signal of a commercial frequency. The voltage command value VR* is a voltage command value in the case where Ep= En (i.e., a state where the voltage command value is not corrected by the balance control circuit 70) (VR* = VR0*). Figure 8(A), (F) shown, in the case where the level of the triangular wave signal Cu2a is higher than the voltage command value VR* (time t0-t21, t22-t23, t24-t29,...), the PWM signal φ1B becomes "L" level. Conversely, in the case where the level of the triangular wave signal Cu2a is lower than the voltage command value VR* (time t21-t22, t23-t24,...), the PWM signal φ1B becomes "H" level. As Figure 8 (F), (I) shown, the PWM signal φ2B is the inverted signal of the PWM signal φ1B.

[0118] As Figure 8 (A), (G) shown, in the case where the level of the triangular wave signal Cu2b is lower than the voltage command value VR* (time t0-t25, t26-t27,...), the PWM signal φ3B becomes "L" level. Conversely, in the case where the level of the triangular wave signal Cu2b is higher than the voltage command value VR* (time t25-t26, t27-t28,...), the PWM signal φ3B becomes "H" level. As Figure 8 (G), (H) shown, the PWM signal φ4B is the inverted signal of the PWM signal φ

[0119] 3B.

[0120] Further, in Figure 8 (A) to (I) shown, the voltage command value VR* and the waveforms of the signals Cu1a, Cu1b, Cu2a, Cu2b, φ1A to φ4A, φ1B to φ4B corresponding to R phase are the same as those of the voltage command value and the waveforms of the signals corresponding to S phase and T phase, respectively. However, the voltage command value and the waveforms of the signals corresponding to R phase, S phase, and T phase are each shifted by 120°.

[0121] In Embodiment 1, in each phase arm, the two three-level circuits 3A, 3B connected in parallel are driven in a staggered manner. As Figure 9 shown, the triangular wave signals Cu1a, Cu1b and the triangular wave signals Cu2a, Cu2b which are shifted in phase with respect to the triangular wave signals Cu1a, Cu1b are prepared. The comparison result of the voltage command value VR* and the triangular wave signals Cu1a, Cu1b is set as the PWM signals φ

[0122] 1A to φ4A, and the comparison result of the voltage command value VR* and the triangular wave signals Cu2a, Cu2b is set as the PWM signals φ1B to φ4B.

[0123] Thus, by intentionally shifting the phases of the PWM signals φ1A to φ4B and the PWM signals φ

[0124] 1B to φ4B, the fluctuations (variations in current at the time of switching) generated by each three-level circuit can be canceled out.

[0125] Thus, the fluctuation component contained in the current of the sum of the output currents of the three-level circuits 3A, 3B is reduced, and the effective frequency of the fluctuation component becomes twice, so that the AC input filter 2 can be downsized. In addition, in each phase arm, the current is divided to the three-level circuits 3A, 3B, so that the power loss per 1 IGBT is reduced, and as a result, the thermal design of the IGBT becomes easy.

[0126] Here, it is known that the switching pattern of the IGBTs of each bridge circuit is composed of three patterns. Figure 9 is a diagram showing the switching pattern of the four IGBTs included in each bridge circuit. Figure 9 The operation of the bridge circuit 3A in each pattern is shown in

[0127] Figure 9 (A) of shows Pattern 1. In Pattern 1, the IGBTs Q1A, Q4A are on, and the IGBTs Q2A, Q3A are off, and the capacitor Cl on the positive side is charged or discharged. Figure 9 (B) of shows Pattern 2. In Pattern 2, the IGBTs Q2A, Q4A are on, and the IGBTs Q1A, Q3A are off, and the charge states of the capacitor Cl on the positive side and the capacitor C2 on the negative side hardly change. Figure 9 (C) of shows Pattern 3. In Pattern 3, the IGBTs Q2A, Q3A are on, and the IGBTs Q1A, Q4A are off, and the capacitor C2 on the negative side is charged or discharged. In addition, in Figure 8 In (A) and (C) of, the arrow shows the direction of the current flowing at the time of charging. At the time of discharging, the current flows in the direction opposite to the arrow.

[0128] Returning to Figure 10 In the case of Ep < En, the voltage command value VR* becomes a value obtained by adding the voltage command value V1* to the voltage command value VR0*. The voltage command value V1* is positive in the case of Ep < En. In the PWM circuit 72, the switching pattern of the four IGBTs included in each bridge circuit is decided by comparing the voltage command value VR* with the high and low of the triangular wave signals Cu1a, Cu1b, Cu2a, Cu2b. In the case of Ep < En, the time of Pattern 1 (the charging time of the capacitor Cl) becomes longer, and the time of Pattern 3 (the charging time of the capacitor C2) becomes shorter, compared with the case of Ep = En. Therefore, ΔE = Ep - En is reduced.

[0129] In the case where Ep > En, the voltage command value VR* becomes a value obtained by adding the voltage command value V1* to the voltage command value VR0*. The voltage command value V1* is negative in the case where Ep > En. In the PWM circuit 72, the switching pattern of the four IGBTs included in each bridge circuit is determined by comparing the voltage command value VR* with the high and low of the triangular wave signals Cu1a, Cu1b, Cu2a, Cu2b. In the case where Ep > En, the time of pattern 1 (the charging time of the capacitor C1) becomes shorter and the time of pattern 3 (the charging time of the capacitor C2) becomes longer than in the case where Ep = En. Therefore, ΔE = Ep - En is reduced.

[0130] Thus, the first control circuit 53 generates the PWM signals φ1A to φ4A, φ1B to φ4B in such a manner that the phases of the three-phase alternating voltages VR, VS, VT coincide with the phases of the three-phase alternating currents IR, IS, IT, the direct voltage VDC becomes the reference direct voltage VDCR, and the direct voltage ΔE becomes 0. In the case where the power failure signal PC is the inactive level "L" level (when the commercial alternating power source 41 is normal), the first control circuit 53 is connected to the converter 3 through the switching circuit 55. Thus, the PWM signals φ1A to φ4A, φ1B to φ4B are supplied to the gates of the IGBTs Q1A to Q4A, Q1B to Q4B of the R-phase arm 3R through the switching circuit 55, respectively.

[0131] (Second Control Circuit)

[0132] Figure 5 is a timing chart showing the operation of the second control circuit 54 shown in Figure 10 is a timing chart showing the operation of the second control circuit 54 shown in Figure 10 shows the control of one phase (for example, the R-phase arm 3R) of the converter 3 in the case where Ep > En. Figure 10 (A) of shows the waveforms of Ep, En. Figure 11 (B) to (E) of shows the waveforms of the PWM signals φ1A to φ4, φ1B to φ4B generated by the second control circuit 54.

[0133] In the case where Ep > En (at time t1), the PWM signal φ1A is set to the "H" level and the "L" level at the prescribed frequency fc. The PWM signals φ2A to φ4A, φ1B, φ3B are fixed to the "L" level, and the PWM signals φ2B, φ4B are fixed to the "H" level.

[0134] Figure 12 and Figure 11 is an equivalent circuit diagram showing the operation of one phase of the converter 3 in the case where Ep > En. As Figure 11As shown, when the PWM signal φ1A is set to the "H" level, the PWM signals φ2B, φ4B are set to the "H" level, the IGBT Q1A (first switch) is turned on, and the IGBTs Q2B, Q4B (fifth switches) are turned on. As a result, as shown by the arrows, current flows from the positive electrode of the capacitor C1 via the DC line L1, the IGBT Q1A, the reactors 12RA, 12RB, the IGBT Q2B, the diode D4B, the DC line L2 to the negative electrode of the capacitor C1. As a result, the capacitor C1 is discharged, and the terminal-to-terminal voltage Ep of the capacitor C1 decreases. At this time, electromagnetic energy is accumulated in the reactors 12RA, 12RB. Figure 12 As shown, when the PWM signal φ1A is set to the "H" level, the PWM signals φ2B, φ4B are set to the "H" level, the IGBT Q1A (first switch) is turned on, and the IGBTs Q2B, Q4B (fifth switches) are turned on. As a result, as shown by the arrows, current flows from the positive electrode of the capacitor C1 via the DC line L1, the IGBT Q1A, the reactors 12RA, 12RB, the IGBT Q2B, the diode D4B, the DC line L2 to the negative electrode of the capacitor C1. As a result, the capacitor C1 is discharged, and the terminal-to-terminal voltage Ep of the capacitor C1 decreases. At this time, electromagnetic energy is accumulated in the reactors 12RA, 12RB.

[0135] Next, when the PWM signal φ1A is set to the "L" level, as shown by the arrows, the IGBT Q1A (first switch) is turned off. As a result, as shown by the arrows, current flows from the reactor 12RA via the reactor 12RB, the IGBT Q2B, the diode D4B, the DC line L2, the capacitor C2, the DC line L3, the diode D3A to the reactor 12RA. At this time, the electromagnetic energy of the reactors 12RA, 12RB is released, the capacitor C2 is charged, and the terminal-to-terminal voltage En of the capacitor C2 rises. Figure 12 As shown, when the PWM signal φ1A is set to the "H" level, the PWM signals φ2B, φ4B are set to the "H" level, the IGBT Q1A (first switch) is turned on, and the IGBTs Q2B, Q4B (fifth switches) are turned on. As a result, as shown by the arrows, current flows from the positive electrode of the capacitor C1 via the DC line L1, the IGBT Q1A, the reactors 12RA, 12RB, the IGBT Q2B, the diode D4B, the DC line L2 to the negative electrode of the capacitor C1. As a result, the capacitor C1 is discharged, and the terminal-to-terminal voltage Ep of the capacitor C1 decreases. At this time, electromagnetic energy is accumulated in the reactors 12RA, 12RB. Figure 13 As shown, when the PWM signal φ1A is set to the "H" level, the PWM signals φ2B, φ4B are set to the "H" level, the IGBT Q1A (first switch) is turned on, and the IGBTs Q2B, Q4B (fifth switches) are turned on. As a result, as shown by the arrows, current flows from the positive electrode of the capacitor C1 via the DC line L1, the IGBT Q1A, the reactors 12RA, 12RB, the IGBT Q2B, the diode D4B, the DC line L2 to the negative electrode of the capacitor C1. As a result, the capacitor C1 is discharged, and the terminal-to-terminal voltage Ep of the capacitor C1 decreases. At this time, electromagnetic energy is accumulated in the reactors 12RA, 12RB.

[0136] Thus, if the operation of turning on and off the IGBT Q1A (first switch) by setting the PWM signal φ1A to the "H" level and the "L" level is repeated, ΔE = Ep - En gradually decreases. When ΔE = 0 (at time t2), the PWM signals φ1A, φ2B, φ4B are fixed to the "L" level. That is, the IGBTs Q1A - Q4A, Q1B - Q4B are all turned off, and the operation of the converter 3 is stopped.

[0137] Figure 5 is a timing chart showing the operation of the second control circuit 54 shown in FIG. 6. Figure 13 is a timing chart showing the operation of the second control circuit 54 shown in FIG. 6. Figure 13 shows the control of one phase (for example, the R-phase arm 3R) of the converter 3 in the case where Ep < En. Figure 13 (A) of FIG. 7 shows the waveforms of Ep, En. Figure 14 (B) - (E) of FIG. 7 show the waveforms of the PWM signals φ1A - φ4, φ1B - φ4B generated by the second control circuit 54.

[0138] In the case where Ep < En (at time tl), the PWM signal φ3A is set to the "H" level and the "L" level at a predetermined frequency fc. The PWM signals φ1A, φ2A, φ4A, φ1B, φ3B are fixed to the "L" level, and the PWM signals φ2B, φ4B are fixed to the "H" level.

[0139] Figure 15 andFigure 14 is an equivalent circuit diagram showing the operation of one phase of the converter 3 in the case where Ep < En. As shown in Figure 14 , when the PWM signal φ3A is set to the "H" level and the PWM signals φ2B, φ4B are set to the "H" level, the IGBT Q3A (third switch) turns on, and the IGBTs Q2B, Q4B (fifth switches) turn on. Thereby, as shown by the arrows in Figure 15 , current flows from the positive electrode of the capacitor C2 via the DC line L2, the IGBT Q4B, the diode D2B, the reactors 12RB, 12RA, the IGBT Q3A, the DC line L3 to the negative electrode of the capacitor C2. Thereby, the capacitor C2 is discharged, and the terminal-to-terminal voltage En of the capacitor C2 decreases. At this time, electromagnetic energy is accumulated in the reactors 12RA, 12RB.

[0140] Next, when the PWM signal φ3A is set to the "L" level, as shown in Figure 15 , the IGBT Q3A (third switch) turns off. Thereby, as shown by the arrows in Figure 10 , current flows from the reactor 12RB via the reactor 12RA, the diode D1A, the DC line L1, the capacitor C1, the DC line L2, the IGBT Q4B, the diode D2B, the reactor 12RB to the reactor 12RA. At this time, the electromagnetic energy of the reactors 12RA, 12RB is released, the capacitor C1 is charged, and the terminal-to-terminal voltage Ep of the capacitor C1 rises.

[0141] Thus, if the operation of turning on and off the IGBT Q3A (third switch) by setting the PWM signal φ3A to the "H" level and the "L" level is repeated, ΔE = Ep - En gradually decreases. When ΔE = 0 (at time t2), the PWM signals φ3A, φ2B, φ4B are fixed to the "L" level. That is, all of the IGBTs Q1A - Q4A, Q1B - Q4B turn off, and the operation of the converter 3 stops.

[0142] In the case where the power-off signal PC is the "H" level of the active level (when the commercial AC power source 41 is powered off), the second control circuit 54 is connected to the converter 3 by the switching circuit 55. Thereby, the PWM signals φ1A - φ4A, φ1B - φ4B are supplied to the gates of the IGBTs Q1A - Q4A, Q1B - Q4B of the R-phase arm 3R via the switching circuit 55, respectively.

[0143] (Balancing control by the converter)

[0144] Next, the balancing control of the converter 3 when the commercial AC power source 41 is normal will be described. When the commercial AC power source 41 is normal, the first control circuit 53 is connected to the converter 3 by the switching circuit 55.

[0145] When Ep < En, in order to achieve voltage balance between capacitors C1 and C2, the first control circuit 53 adds the positive voltage command value V1* to the voltage command values ​​VR0*, VS0*, and VT0* to generate the voltage command values ​​VR*, VS*, and VT*. When Ep > En, in order to achieve voltage balance between capacitors C1 and C2, the first control circuit 53 adds the negative voltage command value V1* to the voltage command values ​​VR0*, VS0*, and VT0* to generate the voltage command values ​​VR*, VS*, and VT*.

[0146] In the PWM circuit 72, PWM signals φ1A~φ4A and φ1B~φ4B are generated by comparing the voltage command values ​​VR*, VS*, VT* with the triangular wave signals Cu1a, Cu1b, Cu2a, Cu2b. During periods when the voltage command values ​​VR*, VS*, VT* are positive, capacitor C1 is charged. During periods when the voltage command values ​​VR*, VS*, VT* are negative, capacitor C2 is charged.

[0147] When Ep < En, the charging time of capacitor C1 is longer than that of capacitor C2 compared to the case where Ep = En, thus allowing voltage Ep to rise higher than voltage En. The voltage command value V1* is output in such a way that Ep = En, so the voltages of capacitors C1 and C2 are consistent and balanced.

[0148] When Ep > En, the charging time of capacitor C2 is longer than that of capacitor C1 compared to the case where Ep = En. Therefore, the voltage En can rise higher than the voltage Ep. The voltage command value V1* is output in such a way that Ep = En, so the voltages of capacitors C1 and C2 are consistent and balanced.

[0149] Next, the balance control of converter 3 when the commercial AC power supply 41 is interrupted will be explained.

[0150] When Ep > En, in order to achieve voltage balance between capacitors C1 and C2, as follows: Figure 11 As shown, the second control circuit 54 performs the action of turning on the IGBTs Q2B and Q4B (fifth switches) of the three-level circuit 3B, and turning on and off the IGBT Q1A (first switch) of the three-level circuit 3A at a predetermined frequency fc.

[0151] When IGBT Q1A is turned on, as follows Figure 12 As shown, current flows out of capacitor C1, the voltage Ep between the terminals of capacitor C1 decreases, and electromagnetic energy is stored in reactors 12RA and 12RB. When IGBT Q1A is disconnected, as... Figure 13As shown, the electromagnetic energy stored in reactors 12RA and 12RB is released, capacitor C2 is charged, and the voltage En between the terminals of capacitor C2 rises. By switching IGBT Q1A on and off at a specified frequency fc, ΔE = Ep - En gradually decreases. When ΔE = 0, IGBTs Q1A to Q4A and Q1B to Q4B are disconnected, thereby stopping the operation of converter 3.

[0152] When Ep < En, in order to achieve voltage balance between capacitors C1 and C2, as follows: Figure 14 As shown, the second control circuit 54 performs the action of turning on the IGBTs Q2B and Q4B (the fifth switch) of the three-level circuit 3B, and turning on and off the IGBT Q3A (the third switch) of the three-level circuit 3A at a specified frequency fc.

[0153] When IGBT Q3A is turned on, as follows Figure 15 As shown, current flows out of capacitor C2, the voltage En between the terminals of capacitor C2 decreases, and electromagnetic energy is stored in reactors 12RA and 12RB. When IGBT Q3A is disconnected, as... Figure 5 As shown, the electromagnetic energy stored in reactors 12RA and 12RB is released, capacitor C1 is charged, and the voltage Ep between the terminals of capacitor C1 rises. By switching IGBT Q3A on and off at a specified frequency fc, ΔE = Ep - En gradually decreases. When ΔE = 0, IGBTs Q1A to Q4A and Q1B to Q4B are disconnected, thereby stopping the operation of converter 3.

[0154] (The structure of the control circuit)

[0155] return Figure 16 The control circuit 80 controls the DC voltage converter 6 based on the power outage signal PC from the power outage detector 33, the signal representing the battery voltage VB from the voltage detector 36, the signal representing the battery current IB from the current detector 37, and the signal representing the DC voltage VDC from the adder 51.

[0156] Specifically, when the power outage signal PC is at the inactive level "L" level (when the commercial AC power supply 41 is normal), the control circuit 80 controls the DC voltage converter 6 in such a way that the battery current IB, which corresponds to the DC voltage VDC, flows from capacitors C1 and C2 to battery B1, and the battery voltage VB becomes the reference battery voltage VBR.

[0157] The control circuit 80 controls the DC voltage converter 6 in such a manner that the battery current IB of a level corresponding to the battery voltage VB flows from the battery Bl to the capacitors Cl, C2, and the DC voltage VDC becomes the reference DC voltage VDCR, in the case where the power failure signal PC is the active level "H" (when the commercial AC power source 41 is powered off). That is, the balance control by the DC voltage converter 6 is not performed when the commercial AC power source 41 is powered off, unlike the balance control described in Patent Documents 1 and 2.

[0158] Figure 5 is a block diagram showing the configuration of the control circuit 80. As shown in Figure 16 Figure 17 The control circuit 80 includes control sections 81, 82.

[0159] The control section 81 is activated in the case where the power failure signal PC is the inactive level "L" (when the commercial AC power source 41 is normally powered), to control the DC voltage converter 6 in such a manner that the current IB of a level corresponding to the DC voltage VDC flows from the capacitors Cl, C2 to the battery Bl, and the terminal-to-terminal voltage VB of the battery Bl becomes the reference battery voltage VBR.

[0160] The control section 82 is activated in the case where the power failure signal PC is the active level "H" (when the commercial AC power source 41 is powered off), to control the DC voltage converter 6 in such a manner that the current IB of a level corresponding to the terminal-to-terminal voltage VB of the battery Bl flows from the battery Bl to the capacitors Cl, C2, and the DC voltage VDC becomes the reference DC voltage VDCR. Specifically, the control section 82 includes a reference voltage generation circuit 83, subtractors 84, 86, a voltage control circuit 85, a current control circuit 87, and a PWM circuit 88.

[0161] The reference voltage generation circuit 83 generates the reference DC voltage VDCR. The subtractor 84 calculates the voltage AVDC which is the difference between the reference DC voltage VDCR and the DC voltage VDC detected by the adder 51.

[0162] The voltage control circuit 85 calculates the current command value IB* of a level corresponding to the voltage AVDC, based on the terminal-to-terminal voltage VB of the battery Bl detected by the voltage detector 36. The voltage control circuit 85 calculates the current command value IB*, for example, by performing proportional operation or proportional integral operation on AVDC.

[0163] The subtractor 86 calculates the deviation ΔIB = IB* - IB of the current command value IB* generated by the voltage control circuit 85 from the current value IB of the battery Bl detected by the current detector 37. The current control circuit 87 generates the voltage command value V* based on the deviation ΔIB of the current command value IB* from the current value IB.

[0164] ​The PWM circuit 88 is activated when the power failure signal PC is at the active level "H" (when the commercial AC power source 41 is out of operation), and outputs a signal for driving the four IGBTs included in the semiconductor switch 21, based on the voltage command value V*. The DC voltage converter 6 is controlled by the signal from the PWM circuit 88, and supplies the DC power of the battery Bl to the inverter 4.

[0165] The PWM circuit 88 is inactivated when the power failure signal PC is at the inactive level "L" (when the commercial AC power source 41 is normal), and does not perform the PWM control of the DC voltage converter 6. Further, when the commercial AC power source 41 is normal, the DC voltage converter 6 is controlled by the control section 81, and accumulates the DC power in the battery Bl.

[0166] <Operation of the uninterruptible power supply device>

[0167] Next, the operation of the uninterruptible power supply device 100 of Embodiment 1 will be described.

[0168] When the commercial AC power source 41 is normal, the switch 1 is turned on, and the three-phase AC power from the commercial AC power source 41 is supplied to the converter 3 via the switch 1 and the AC input filter 2, and is converted to DC power by the converter 3. The DC power is accumulated in the battery Bl by the DC voltage converter 6, and is converted to three-phase AC power by the inverter 4. The three-phase AC power generated by the inverter 4 is supplied to the load 42 via the AC output filter 5, and drives the load 42.

[0169] At this time, the converter 3 is controlled by the first control circuit 53 so that the DC voltage VDC = Ep + En of the sum of the terminal voltages Ep, En of the capacitors Cl, C2 becomes the reference DC voltage VDCR, and the DC voltage AE = Ep - En of the difference between the terminal voltages Ep, En of the capacitors Cl, C2 becomes 0.

[0170] When the commercial AC power source 41 is out of operation, basically, the switch 1 is turned off, and the operation of the converter 3 is stopped, and the DC power of the battery Bl is supplied to the inverter 4 via the DC voltage converter 6, and is converted to three-phase AC power of the commercial frequency by the inverter 4. The three-phase AC power generated by the inverter 4 is supplied to the load 42 via the AC output filter 5.

[0171] At this time, the DC voltage converter 6 is controlled by the control section 82 so that the DC voltage VDC = Ep + En of the sum of the terminal voltages Ep, En of the capacitors Cl, C2 becomes the reference DC voltage VDCR.

[0172] However, when the voltages Ep, En between the terminals of the capacitors Cl, C2 become unbalanced, the converter 3 is caused to operate. The converter 3 discharges the capacitor Cl and charges the capacitor C2 in the case of Ep > En, discharges the capacitor C2 and charges the capacitor Cl in the case of Ep < En, and reduces the direct current voltage ΔE = Ep - En of the difference between the voltages Ep, En between the terminals of the capacitors Cl, C2. In the case where the direct current voltage ΔE becomes 0, the operation of the converter 3 is stopped.

[0173] [Effect of Embodiment 1]

[0174] As explained above, in Embodiment 1, when the commercial AC power source 41 is powered off, the switch 1 is opened to electrically cut off the commercial AC power source 41 from the AC input filter 2, and the converter 3 is controlled in a manner to eliminate the direct current voltage ΔE = Ep - En of the difference between the voltages Ep, En between the terminals of the capacitors Cl, C2, to reduce the direct current voltage ΔE. Therefore, even in the case where the load current is small, the unbalance of the voltages Ep, En between the terminals of the capacitors Cl, C2 at the time when the commercial AC power source 41 is powered off can be eliminated.

[0175] Also, in Embodiment 1, each phase arm of the converter 3 is constituted by the three-level circuits 3A, 3B connected in parallel, and at the time when the commercial AC power source 41 is powered off, the three-level circuits 3A, 3B are caused to operate to discharge or charge the capacitors Cl, C2, thereby reducing the direct current voltage ΔE. At this time, the discharging and charging of the capacitors Cl, C2 are respectively realized by accumulating and releasing electromagnetic energy to the reactor 12 of the AC input filter 2. According to Embodiment 1, the capacitors Cl, C2 can be discharged or charged without using the capacitor 11 of the AC input filter 2 as a power buffer. Therefore, the balance control of the converter 3 at the time when the commercial AC power source 41 is powered off can be made simple.

[0176] In addition, according to Embodiment 1, it is not necessary to cause the operation for discharging the capacitor 11 of the AC input filter 2 in order to discharge or charge the capacitors Cl, C2, and therefore, at the time when the commercial AC power source 41 is powered off, the unbalance of the voltages Ep, En between the terminals of the capacitors Cl, C2 can be eliminated promptly.

[0177] [Embodiment 2]

[0178] In Embodiment 1, the configuration in which the three-level circuits 3A, 3B of each phase arm of the converter 3 are caused to operate to eliminate the unbalance of the voltages Ep, En between the terminals of the capacitors Cl, C2 is explained.

[0179] According to this configuration, it is possible to eliminate the imbalance of the terminal voltages Ep, En of the capacitors Cl, C2 in a short time when the commercial AC power source 41 is powered off. On the other hand, losses occur in each phase arm of the converter 3. Specifically, the losses of each phase arm are conduction losses (losses when the IGBT and diode are energized) and switching losses of the IGBT. Therefore, there is a concern that the operation efficiency of the uninterruptible power supply device 100 when the commercial AC power source 41 is powered off decreases.

[0180] Corresponding to such a concern, in Embodiment 2, the configuration is such that the number of phase arms of the converter 3 that operates when the commercial AC power source 41 is powered off is changed in accordance with the absolute value of the direct current voltage ΔE that is the difference between the terminal voltages Ep, En of the capacitors Cl, C2.

[0181] Figure 17 is a flowchart showing a modification example of the balance control of the converter 3 when the commercial AC power source 41 is powered off. Figure 5 The flowchart shown in Figure 17 is executed by the second control circuit 54 shown in

[0182] As shown in Figure 18 , first, by step S01, the second control circuit 54 compares the absolute value of the direct current voltage ΔE = Ep - En that is the difference between the terminal voltages Ep, En of the capacitors Cl, C2 with a first threshold voltage V1 that is determined in advance. The first threshold voltage V1 is a positive voltage.

[0183] In the case where the absolute value of ΔE is greater than the first threshold voltage V1 (when the "Yes" determination of S01), by step S04, the second control circuit 54 causes the R phase arm 3R, the S phase arm 3S, and the T phase arm 3T to operate. In S04, the three-level circuits 3A, 3B of the respective three phase arms 3R, 3T, 3S are controlled in such a manner that the direct current voltage ΔE disappears.

[0184] In the case where the absolute value of ΔE is equal to or less than the first threshold voltage V1 (when the "No" determination of S01), by step S02, the second control circuit 54 compares the absolute value of ΔE with a second threshold voltage V2 that is determined in advance. The second threshold voltage V2 is a positive voltage that is lower than the first threshold voltage V1.

[0185] In the case where the absolute value of ΔE is equal to or less than the first threshold voltage V1 and greater than the second threshold voltage V2 (when the "Yes" determination of S02), the second control circuit 54 causes, by step S05, two phase arms (for example, the R phase arm 3R and the S phase arm 3S) of the three phase arms to operate and causes the operation of the remaining one phase arm (for example, the T phase arm 3T) to stop. In S05, the three-level circuits 3A, 3B of the respective R phase arm 3R and S phase arm 3S are controlled in such a manner that the direct current voltage ΔE disappears.

[0186] If the absolute value of ΔE is below the second threshold voltage V2 (when S02 is determined to be "No"), the second control circuit 54 compares the absolute value of ΔE with 0 in step S03. If the absolute value of ΔE is below the second threshold voltage V2 but greater than 0 (when S02 is determined to be "Yes"), the second control circuit 54, in step S06, activates one phase arm (e.g., R-phase arm 3R) and stops the activation of the remaining two phase arms (e.g., S-phase arm 3S and T-phase arm 3T). In S06, the three-level circuits 3A and 3B of the R-phase arm 3R are controlled in a manner that makes the DC voltage ΔE disappear.

[0187] When the absolute value of ΔE is 0 (when S03 is "No"), the second control circuit 54 stops the operation of the three-phase arms 3R, 3S, and 3T through step S07.

[0188] As explained above, according to Embodiment 2, when the absolute value of the DC voltage ΔE exceeds the first threshold voltage V1, the DC voltage ΔE = Ep - En can be rapidly reduced by operating the three-phase arms 3R, 3S, and 3T of the converter 3. Furthermore, as the absolute value of the DC voltage ΔE decreases, the losses of the converter 3 can be reduced by decreasing the number of operating phase arms, thereby improving the operating efficiency of the uninterruptible power supply device 100 during a power outage of the commercial AC power supply 41.

[0189] [Implementation Method 3]

[0190] Figure 3 This is a circuit diagram showing the main parts of the uninterruptible power supply device according to Embodiment 3, which is related to... Figure 18 A comparison chart. (e.g.) Figure 19 As shown, the difference between Embodiment 3 and Embodiment 1 is that each phase arm 3R, 3S, and 3T of the converter 3 is composed of three-level circuits 3Ax and 3Bx. The circuit configurations of each phase arm 3R, 3S, and 3T of the converter 3 are the same, so the circuit configuration of the R phase arm 3R is described representatively.

[0191] The three-level circuit 3Ax includes IGBTs Q1A to Q4A and diodes D1A to D6A. IGBTs Q1A to Q4A are connected in series between DC lines L1 and L3. Diodes D1A to D4A are connected in anti-parallel to IGBTs Q1A to Q4A, respectively. Diode D5A is connected to the junction of IGBTs Q1A and Q2A and to DC line L2. Diode D6A is connected to the junction of IGBTs Q3A and Q4A and to DC line L.

[0192] The diodes D1A to D4A function as freewheeling diodes, and the diodes D5A, D6A function as clamping diodes. The input node 3a of the three-level circuit 3Ax is connected to the second terminal of the reactor 12RA, and to the connection point of the IGBTs Q2A, Q3A.

[0193] The three-level circuit 3Ax corresponds to an embodiment of the "first multi-level circuit". The IGBTs Q1A, Q2A and the diodes D1A, D2A constitute a "first switch", the IGBTs Q2A, Q3A and the diodes D2A, D3A, D5A, D6A constitute a "second switch", and the IGBTs Q3A, Q4A and the diodes D3A, D4A constitute a "third switch".

[0194] The three-level circuit 3Bx includes the IGBTs Q1B to Q4B and the diodes D1B to D6B. The IGBTs Q1B to Q4B are connected in series between the direct current lines L1, L3. The diodes D1B to D4B are connected in anti-parallel to the IGBTs Q1B to Q4B, respectively. The diode D5B is connected to the connection point of the IGBTs Q1B, Q2B and to the direct current line L2. The diode D6B is connected to the connection point of the IGBTs Q3B, Q4B and to the direct current line L.

[0195] The diodes D1B to D4B function as freewheeling diodes, and the diodes D5B, D6B function as clamping diodes. The input node 3b of the three-level circuit 3Bx is connected to the second terminal of the reactor 12RB, and to the connection point of the IGBTs Q2B, QBA.

[0196] The three-level circuit 3Bx corresponds to an embodiment of the "second multi-level circuit". The IGBTs Q1B, Q2B and the diodes D1B, D2B constitute a "fourth switch", the IGBTs Q2B, Q3B and the diodes D2B, D3B, D5B, D6B constitute a "fifth switch", and the IGBTs Q3B, Q4B and the diodes D3B, D4B constitute a "sixth switch".

[0197] The switching pattern of the IGBTs of each bridge circuit is composed of three patterns. Figure 19 is a diagram showing the switching pattern of the four IGBTs included in each bridge circuit. Figure 19 The operation of the bridge circuit 3Ax in each pattern is shown in (A) of FIG. 10.

[0198] Figure 19 (A) of FIG. 10 shows Pattern 1. In Pattern 1, the IGBTs Q1A, Q2A are on, the IGBTs Q3A, Q4A are off, and the capacitor Cl on the positive side is charged or discharged. Figure 19(B) shows Mode 2. In Mode 2, IGBTs Q2A, Q3A are turned on, and IGBTs Q1A, Q4A are turned off. The charge states of the positive-side capacitor Cl and the negative-side capacitor C2 are hardly changed. Figure 19 (C) shows Mode 3. In Mode 3, IGBTs Q3A, Q4A are turned on, and IGBTs Q1A, Q2A are turned off. The negative-side capacitor C2 is charged or discharged. In addition, in Figure 20 (A), (C) of FIG. 10, arrows indicate the directions of currents flowing at the time of charging. At the time of discharging, currents flow in the directions opposite to the arrows.

[0199] In Embodiment 3 as well as in Embodiment 1, the first control circuit 53 generates the PWM signals φ1A to φ4A, φ1B to φ4B in such a manner that the phases of the three-phase alternating voltages VR, VS, VT coincide with the phases of the three-phase alternating currents IR, IS, IT, the direct voltage VDC of the sum of the terminal-to-terminal voltages Ep, En of the capacitors Cl, C2 becomes the reference direct voltage VDCR, and the direct voltage ΔE of the difference between the terminal-to-terminal voltages Ep, En of the capacitors Cl, C2 becomes 0.

[0200] 1B to φ4B.

[0201] Further, in the case where the power-off signal PC is at the inactive level "L" level (when the commercial AC power supply 41 is normal), the first control circuit 53 is connected to the converter 3 through the switching circuit 55. Thus, the PWM signals φ1A to φ4A, φ1B to φ4B are supplied to the gates of the IGBTs Q1A to Q4A, Q1B to Q4B of the R-phase arm 3R, respectively, via the switching circuit 55. In addition, in each of the phase arms 3R, 3S, 3T of the converter 3, the three-level circuits 3Ax, 3Bx connected in parallel are driven in an interleaved manner. Thus, the fluctuations generated by each of the three-level circuits cancel each other out, and thus the same effects as in Embodiment 1 can be obtained.

[0202] In addition, in Embodiment 3 as well as in Embodiment 1, the second control circuit 54 controls the converter 3 in such a manner that the direct voltage ΔE becomes 0, based on the signal indicating the direct voltage ΔE from the subtracter 52.

[0203] Figure 20 (A) of FIG. 11 shows the waveforms of Ep, En. Figure 20 (A) of FIG. 11 shows the waveforms of Ep, En. Figure 20 (B) to (E) of FIG. 11 show the waveforms of the PWM signals φ1A to φ4A, φ1B to φ4B generated by the second control circuit 54. Figure 21

[0204] ​In the case where Ep > En (time tl), the PWM signals φ1A, φ2A are set to the "H" level and the "L" level at the prescribed frequency fc. The PWM signals φ3A, φ4A, φ1B, φ2B, φ4B are fixed to the "L" level, and the PWM signal φ3B is fixed to the "H" level.

[0205] Figure 22 and Figure 21 is an equivalent circuit diagram showing the operation of one phase of the converter 3 in the case where Ep > En. As shown in Figure 21 , when the PWM signals φ1A, φ2A are set to the "H" level and the PWM signal φ3B is set to the "H" level, the IGBTs Q1A, Q2A (first switches) are turned on, and the IGBT Q3B (fifth switch) is turned on. As a result, as shown by the arrows in Figure 22 , current flows from the positive electrode of the capacitor Cl via the DC line L1, the IGBTs Q1A, Q2A, the reactors 12RA, 12RB, the IGBT Q3B, the diode D6B, the DC line L2 to the negative electrode of the capacitor Cl. As a result, the capacitor Cl is discharged, and the terminal-to-terminal voltage Ep of the capacitor Cl decreases. At this time, electromagnetic energy is accumulated in the reactors 12RA, 12RB.

[0206] Next, when the PWM signals φ1A, φ2A are set to the "L" level, as shown in Figure 22 , the IGBTs Q1A, Q2A (first switches) are turned off. As a result, as shown by the arrows in Figure 23 , current flows from the reactor 12RA via the reactor 12RB, the IGBT Q3B, the diode D6B, the DC line L2, the capacitor C2, the DC line L3, the diodes D2A, D3A to the reactor 12RA. At this time, the electromagnetic energy of the reactors 12RA, 12RB is released, the capacitor C2 is charged, and the terminal-to-terminal voltage En of the capacitor C2 rises.

[0207] Thus, if the operation of setting the PWM signals φ1A, φ2A to the "H" level and the "L" level and turning on and off the IGBTs Q1A, Q2A (first switches) is repeated, ΔE = Ep - En gradually decreases. When ΔE = 0 (time t2), the PWM signals φ1A, φ2A, φ3B are fixed to the "L" level. That is, the IGBTs Q1A to Q4A, Q1B to Q4B are all turned off, and the operation of the converter 3 is stopped.

[0208] Figure 23 is a timing chart showing the operation of the second control circuit 54. Figure 23 shows the control of one phase (for example, the R-phase arm 3R) of the converter 3 in the case where Ep < En. Figure 23 (A) of shows the waveforms of Ep, En. Figure 24The waveforms of the PWM signals φ1A to φ4A, φ1B to φ4B generated by the second control circuit 54 are indicated by (B) to (E).

[0209] In the case where Ep < En (time t1), the PWM signals φ3A, φ4A are set to the "H" level and the "L" level at the prescribed frequency fc. The PWM signals φ1A, φ2A, φ1B, φ3B are fixed to the "L" level, and the PWM signal φ2B is fixed to the "H" level.

[0210] Figure 25 and Figure 24 is an equivalent circuit diagram showing the operation of one phase of the converter 3 in the case where Ep < En. As shown in Figure 24 , when the PWM signals φ3A, φ4A are set to the "H" level and the PWM signal φ2B is set to the "H" level, the IGBTs Q3A, Q4A (third switches) are turned on, and the IGBT Q2B (fifth switch) is turned on. As a result, as shown by the arrows in Figure 25 , current flows from the positive electrode of the capacitor C2 via the DC line L2, the diode D5B, the IGBT Q2B, the reactors 12RB, 12RA, the IGBTs Q3A, Q4A, the DC line L3 to the negative electrode of the capacitor C2. As a result, the capacitor C2 is discharged, and the terminal-to-terminal voltage En of the capacitor C2 decreases. At this time, electromagnetic energy is accumulated in the reactors 12RA, 12RB.

[0211] Next, when the PWM signals φ3A, φ4A are set to the "L" level, as shown in Figure 25 , the IGBTs Q3A, Q4A (third switches) are turned off. As a result, as shown by the arrows in Figure 20 , current flows from the reactor 12RB via the reactor 12RA, the diodes D2A, D1A, the DC line L1, the capacitor C1, the DC line L2, the diode D5B, the IGBT Q2B, the reactor 12RB to the reactor 12RA. At this time, the electromagnetic energy of the reactors 12RA, 12RB is released, the capacitor C1 is charged, and the terminal-to-terminal voltage Ep of the capacitor C1 rises.

[0212] In this way, if the operation of turning the PWM signals φ3A, φ4A to the "H" level and the "L" level and turning on and off the IGBTs Q3A, Q4A (third switches) is repeated, ΔE = Ep - En gradually decreases. When ΔE = 0 (time t2), the PWM signals φ3A, φ2B, φ4B are fixed to the "L" level. That is, all of the IGBTs Q1A to Q4A, Q1B to Q4B are turned off, and the operation of the converter 3 is stopped.

[0213] In the case where the power failure signal PC is an "H" level (when the commercial AC power source 41 is in power failure), the second control circuit 54 is connected to the converter 3 through the switching circuit 55. Thus, the PWM signals φ1A ~ φ4A, φ1B ~ φ4B are supplied to the gates of the IGBTs Q1A ~ Q4A, Q1B ~ Q4B of the R-phase arm 3R, respectively, via the switching circuit 55.

[0214] (Balancing control by the converter)

[0215] The balancing control of the converter 3 when the commercial AC power source 41 is normal is the same as that explained in Embodiment 1. That is, the first control circuit 53 is connected to the converter 3 through the switching circuit 55. In the case where Ep < En, the first control circuit 53 adds the positive voltage command value V1* to the voltage command values VR0*, VS0*, VT0* to generate the voltage command values VR*, VS*, VT*, and in the case where Ep > En, the first control circuit 53 adds the negative voltage command value V1* to the voltage command values VR0*, VS0*, VT0* to generate the voltage command values VR*, VS*, VT*. The PWM circuit 72 generates the PWM signals φ1A ~ φ4A, φ1B ~ φ4B by comparing the voltage command values VR*, VS*, VT* with the highs and lows of the triangular wave signals Cu1a, Cu1b, Cu2a, Cu2b.

[0216] The PWM circuit 72 supplies the generated PWM signals φ1A ~ φ4A, φ1B ~ φ4B to the gates of the IGBTs Q1A ~ Q4A, Q1B ~ Q4B of the three-level circuits 3Ax, 3Bx of the respective phase arms 3R, 3S, 3T via the switching circuit 55.

[0217] Next, the balancing control of the converter 3 when the commercial AC power source 41 is in power failure will be explained.

[0218] In the case where Ep > En, in order to attain the voltage balance of the capacitors C1, C2, as shown in FIG. 8, the second control circuit 54 performs an operation of turning on the IGBT Q3B of the three-level circuit 3Bx and turning on and off the IGBTs Q1A, Q2A of the three-level circuit 3Ax at a predetermined frequency fc. Figure 21

[0219] When the IGBTs Q1A, Q2A are turned on, as shown in FIG. 9, a current flows from the capacitor C1, the terminal-to-terminal voltage Ep of the capacitor C1 decreases, and electromagnetic energy is accumulated in the reactors 12RA, 12RB. When the IGBTs Q1A, Q2A are turned off, as shown in FIG. 10, the terminal-to-terminal voltage Ep of the capacitor C1 increases, and the electromagnetic energy accumulated in the reactors 12RA, 12RB is discharged. Figure 22 Figure 23 ​​As shown, the electromagnetic energy accumulated in the reactors 12RA, 12RB is released, the capacitor C2 is charged, and the voltage En between the terminals of the capacitor C2 rises. By turning the IGBTs Q1A, Q2A on and off at a predetermined frequency fc, ΔE = Ep - En gradually decreases. When ΔE = 0, the IGBTs Q1A to Q4A, Q1B to Q4B are turned off, and thus the operation of the converter 3 is stopped.

[0220] In the case of Ep < En, in order to achieve voltage balance of the capacitors C1, C2, as shown in FIG. 6B, the second control circuit 54 performs an operation of turning the IGBT Q2B of the three-level circuit 3Bx on and turning the IGBTs Q3A, Q4A of the three-level circuit 3Ax on and off at a predetermined frequency fc. Figure 24

[0221] When the IGBTs Q3A, Q4A are turned on, as shown in FIG. 7B, a current flows from the capacitor C2, the voltage En between the terminals of the capacitor C2 decreases, and electromagnetic energy is accumulated in the reactors 12RA, 12RB. When the IGBTs Q3A, Q4A are turned off, as shown in FIG. 7C, the electromagnetic energy accumulated in the reactors 12RA, 12RB is released, the capacitor C1 is charged, and the voltage Ep between the terminals of the capacitor C1 rises. By turning the IGBTs Q3A, Q4A on and off at a predetermined frequency fc, ΔE = Ep - En gradually decreases. When ΔE = 0, the IGBTs Q1A to Q4A, Q1B to Q4B are turned off, and thus the operation of the converter 3 is stopped. Figure 25 ​

[0222] In the embodiment 3, as in the embodiment 1, when the commercial AC power source 41 is powered off, the switch 1 is turned off to electrically cut off the commercial AC power source 41 from the AC input filter 2, and the converter 3 is controlled in a manner such that the difference between the voltages Ep, En between the terminals of the capacitors C1, C2, that is, the direct-current voltage ΔE = Ep - En disappears, to reduce the direct-current voltage ΔE. In addition, when the commercial AC power source 41 is powered off, each phase arm 3R, 3S, 3T of the converter 3 is configured by two three-level circuits 3Ax, 3Bx connected in parallel, and the three-level circuits 3Ax, 3Bx are operated to discharge or charge the capacitors C1, C2. Therefore, in the embodiment 3, the same effects as in the embodiment 1 can be obtained.

[0223] Further, by applying the configuration in which the number of phase arms of the converter 3 operated when the commercial AC power source 41 is powered off in accordance with the absolute value of the direct-current voltage ΔE is changed, as described in the embodiment 2, to the embodiment 3, the absolute value of the direct-current voltage ΔE can be rapidly reduced, and the loss of the converter 3 can be reduced.

[0224] [Other Configuration Examples]

[0225] ​​​In the above-described Embodiments 1 to 3, the configuration in which each phase arm of the converter 3 includes two three-level circuits 3A, 3B is described, but each phase arm of the converter 3 can include three or more three-level circuits. In this case, when the commercial AC power supply 41 is normal, three or more three-level circuits can be driven in an interleaved manner. In addition, when the commercial AC power supply 41 is out of service, by causing three or more three-level circuits to operate, the capacitors Cl, C2 can be discharged or charged.

[0226] In addition, in the present embodiment, the uninterruptible power supply device capable of being applied to a three-phase 4-wire type AC power supply and load is shown, but the present disclosure can also be applied to a three-phase 3-wire type AC power supply and load. In addition, the AC power supply and load are not limited to three phases, but can be single phase.

[0227] It should be considered that the present embodiment is illustrative and not limiting in all aspects. The scope of the present disclosure is not indicated by the above description, but by the claims, and is intended to include all modifications equivalent in meaning and scope to the claims.

[0228] Explanation of Reference Numerals

[0229] 1 switch, 2 AC input filter, 3 converter, 3R R phase arm, 3S S phase arm, 3T T phase arm, 4 inverter, 5 AC output filter, 6 DC voltage converter, 10 control device, 11, 11R, 11S, 11T, 19, 19U, 19V, 19W, Cl, C2 capacitor, 12, 12R, 12RA, 12RB, 12S, 12T, 18, 18U, 18V, 18W, 22, 22P, 22N reactor, 21 semiconductor switch, 31, 34 to 36 voltage detector, 32, 32R, 32S, 32T, 37 current detector, 33 outage detector, 41 commercial AC power supply, 42 load, 51, 68A to 68C, 71A to 71C adder, 52, 62, 66A to 66C, 84, 86 subtracter, 53 first control circuit, 54 second control circuit, 55 switching circuit, 60 voltage command generation circuit, 61, 83 reference voltage generation circuit, 63 DC voltage control circuit, 64 sine wave generation circuit, 65A to 65C multiplier, 67, 87 current control circuit, 70 balance control circuit, 72, 88 PWM circuit, 80 control circuit, 85 voltage control circuit, 90 oscillator, 91 to 94 triangle wave generator, 95 to 98 comparator, 100 uninterruptible power supply device, 102 CPU, 104 memory, 106 I / O circuit, 108 bus, 110, 112, 114, 116 buffer, 111, 113, 115, 117 NOT circuit, Bl battery, LI to L3 DC line, Cu1a, Cu1b, Cu2a, Cu2b triangle wave signal.

Claims

1. An uninterruptible power supply device, comprising: First to third DC lines; A first capacitor is connected between the first and second DC lines; The second capacitor is connected between the second and third DC lines; The switch has a first terminal that receives AC voltage supplied from an AC power source, and is turned on when the AC power source is normal and turned off when the AC power source is de-energized. An AC input filter, with its first terminal connected to the second terminal of the switch. The converter is connected between the second terminal of the AC input filter and the first to third DC lines. When the AC power supply is normal, it converts the AC power from the AC power supply into DC power and supplies it to the first to third DC lines. An inverter is connected between the first to third DC lines and the load to convert DC power from the first to third DC lines into AC power and supply it to the load. The first and second voltage detectors detect the voltage between the terminals of the first and second capacitors, respectively. as well as The control device controls the converter based on the detection values ​​of the first and second voltage detectors. The AC input filter includes: A first reactor, with its first terminal connected to the second terminal of the switch; and The second reactor has its first terminal connected to the second terminal of the switch. The converter includes: A first multi-level circuit is connected between the second terminal of the first reactor and the first to third DC lines, configured to convert AC voltage to and from the first to the third DC voltage; and The second multi-level circuit is connected between the second terminal of the second reactor and the first to third DC lines, and is configured to convert AC voltage to and from the first to the third DC voltage. The control device is, Based on the detection values ​​of the first and second voltage detectors, the sum of the voltages between the terminals of the first and second capacitors, i.e., the first voltage, and the difference between the voltages between the terminals of the first and second capacitors, i.e., the second voltage, are calculated. When the AC power supply is normal, the first and second multi-level circuits are controlled in such a way that the first voltage becomes the reference voltage and the second voltage disappears. When the AC power supply fails, the first and second multilevel circuits are controlled in a manner that causes the second voltage to disappear.

2. The uninterruptible power supply device according to claim 1, wherein, When the AC power supply fails, the control device... When the voltage between the terminals of the first capacitor is greater than the voltage between the terminals of the second capacitor, the first and second multilevel circuits are controlled in such a way that the first capacitor is discharged and the second capacitor is charged. When the voltage between the terminals of the first capacitor is less than the voltage between the terminals of the second capacitor, the first and second multilevel circuits are controlled in such a way that the second capacitor is discharged and the first capacitor is charged.

3. The uninterruptible power supply device according to claim 2, wherein, When the AC power supply fails, if the voltage between the terminals of the first capacitor is greater than the voltage between the terminals of the second capacitor, the control device is configured to alternately perform a first action to discharge the first capacitor and a second action to charge the second capacitor. In the first action, the control device controls the first and second multilevel circuits in such a way that current flows from the positive terminal of the first capacitor through the first DC line, the first multilevel circuit, the first and second reactors, the second multilevel circuit, and the second DC line to the negative terminal of the first capacitor. In the second operation, the control device controls the first and second multilevel circuits in such a way that current flows from the second terminal of the second reactor through the second multilevel circuit, the second DC line, the second capacitor, the third DC line, and the first multilevel circuit to the second terminal of the first reactor. The control device stops the first and second actions in response to the disappearance of the second voltage.

4. The uninterruptible power supply device according to claim 3, wherein, The first multilevel circuit includes: A first switch is connected between the first DC line and the second terminal of the first reactor; A second switch is connected between the second DC line and the second terminal of the first reactor; and A third switch is connected between the third DC line and the second terminal of the first reactor. The second multilevel circuit includes: The fourth switch is connected between the first DC line and the second terminal of the second reactor; The fifth switch is connected between the second DC line and the second terminal of the second reactor; and The sixth switch is connected between the third DC line and the second terminal of the second reactor. In the first action, the control device turns on the first and fifth switches and turns off the second, third, fourth, and sixth switches. In the second action, the control device turns on the fifth switch and turns off the first, second, third, fourth and sixth switches.

5. The uninterruptible power supply device according to claim 2, wherein, When the AC power supply fails, if the voltage between the terminals of the first capacitor is less than the voltage between the terminals of the second capacitor, the control device is configured to alternately perform a third action to discharge the second capacitor and a fourth action to charge the first capacitor. In the third operation, the control device controls the first and second multilevel circuits in such a manner that current flows from the positive terminal of the second capacitor through the second DC line, the second multilevel circuit, the second and first reactors, the first multilevel circuit, and the third DC line to the negative terminal of the first capacitor. In the fourth operation, the control device controls the first and second multilevel circuits in such a manner that current flows from the second terminal of the first reactor through the first multilevel circuit, the first DC line, the first capacitor, the second DC line, and the second multilevel circuit to the second terminal of the second reactor. The control device stops the third and fourth actions in response to the disappearance of the second voltage.

6. The uninterruptible power supply device according to claim 5, wherein, The first multilevel circuit includes: A first switch is connected between the first DC line and the second terminal of the first reactor; A second switch is connected between the second DC line and the second terminal of the first reactor; and A third switch is connected between the third DC line and the second terminal of the first reactor. The second multilevel circuit includes: The fourth switch is connected between the first DC line and the second terminal of the second reactor; The fifth switch is connected between the second DC line and the second terminal of the second reactor; and The sixth switch is connected between the third DC line and the second terminal of the second reactor. In the third action, the control device turns on the third and fifth switches and turns off the first, second, fourth, and sixth switches. In the fourth action, the control device turns on the fifth switch and turns off the first, second, third, fourth and sixth switches.

7. The uninterruptible power supply device according to any one of claims 1 to 6, wherein, The AC power supply is a three-phase AC power supply. The first and second reactors are respectively installed correspondingly to the AC power supply. The converter includes three-phase arms respectively arranged corresponding to the three phases of the AC power supply, and each of the three-phase arms includes the first and second multi-level circuits. When the AC power supply fails, the control device changes the number of phase arms that are activated based on the absolute value of the second voltage.

8. The uninterruptible power supply device according to claim 7, wherein, When the AC power supply fails, the control device reduces the number of phase arms that need to operate based on the decrease in the absolute value of the second voltage.

9. The uninterruptible power supply device according to any one of claims 1 to 6, wherein, When the AC power supply is normal, the control device performs interleaved driving on the first and second multi-level circuits.

10. The uninterruptible power supply device according to any one of claims 1 to 6, wherein, It also has: A DC-DC voltage converter is connected between the energy storage device and the first to third DC lines. When the AC power supply fails, it supplies DC power from the energy storage device to the first to third DC lines. When the AC power supply fails, the control device controls the DC voltage converter in such a way that the first voltage becomes the reference voltage.

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