DCR detection unit used in peak current mode DCM mode
By introducing a reverse current comparator, a peak current comparator, and a current compensation module in the peak current mode (DCM), the problems of DCR detection accuracy and efficiency are solved, achieving high signal-to-noise ratio signal detection and accurate current shutdown under wide load conditions, thus improving the performance of the switching power supply.
Patent Information
- Application Number
- CN202511068663.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-31
- Publication Date
- 2025-11-07
AI Technical Summary
The accuracy and efficiency of DCR detection in the current peak current mode DCM mode need to be improved, especially under the condition of large load current output, it is difficult to guarantee the accuracy of current limiting function and accurate turn-off at the zero crossing point of current valley.
By employing a reverse current comparator, a peak current comparator, and a current compensation module, and by configuring the ratio of the inductor L and its parasitic resistance R_dcr to the sampling terminals R and C, the amplitude of the AC signal of the inductor current is amplified, increasing the signal-to-noise ratio of the input signal. Furthermore, the current compensation module ensures the accuracy of the zero-crossing point of the current valley value under heavy load output.
It achieves efficient DCR detection over a wide load range, improves signal-to-noise ratio and dynamic response speed, ensures the accuracy of current reverse shutdown in DCM mode, and enhances the efficiency of switching power supplies and the accuracy of current limiting function.
Smart Images
Figure CN120908522A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of integrated circuits, and particularly relates to a DCR detection unit for peak current mode DCM mode. BACKGROUND
[0002] With the rapid development of automotive electronics and intelligent electronic devices, the performance, power consumption, and service life of power management chips are required to be harsh. As the most widely used control method of switching power supply, the peak current mode has the advantages of fast loop response, easy control loop design, etc. In order to improve the signal-to-noise ratio of the current detection signal and ensure the accuracy of the current limiting function, it is allowed to use the DCR power inductor of the pressure and the European Union to maximize the conversion efficiency, which has become the main research direction of the switching power supply design.
[0003] The error of the direct current resistance DCR of the inductor can be controlled within 5% under the current process, so the accuracy of this sampling method is higher than that of the MOS tube RDS sampling. In addition, this sampling method only adds one resistor and capacitor, and the circuit structure is simple and the cost is low. Since the added components hardly cause loss, this sampling method is very efficient. Especially in the case of large load current output, the efficiency of inductance DCR sampling is obviously better than that of external resistance sampling. SUMMARY
[0004] The purpose of the present application is to provide a DCR detection unit for peak current mode DCM mode, to solve the problems in the background art.
[0005] To solve the above technical problems, the present application provides a DCR detection unit for peak current mode DCM mode, comprising:
[0006] The reverse current comparator is used to close the synchronous rectifier tube when the current reverses zero in the DCM mode;
[0007] The peak current comparator compares the output of the external error amplifier with the sampled inductance current weighting coefficient to form a current loop and improve the dynamic response speed;
[0008] The current compensation module realizes the accuracy and efficiency of the peak current comparator and the reverse current comparator under the premise of high detection input signal-to-noise ratio.
[0009] In one embodiment, the reverse current comparator comprises a first PMOS tube, a second PMOS tube, a third NMOS tube, a first Schmitt trigger, and a first current detection readout circuit.
[0010] The source of the first PMOS tube and the source of the second PMOS tube are connected with VDD, the gate of the first PMOS tube and the gate of the second PMOS tube are connected with the drain of the second PMOS tube, the drain of the second PMOS tube is connected with the output end of the first current detection readout circuit, the positive input end of the first current detection readout circuit is the detection I senseN input level of the DRC detection unit, and the negative input end of the first current detection readout circuit is the detection I senseP input level of the DRC detection unit.
[0011] The drain of the first PMOS tube and the drain of the third NMOS tube are connected with the input end of the first Schmitt trigger, the source of the third NMOS tube is connected with GND, and the output of the first Schmitt trigger is a first reverse current comparator control signal.
[0012] In an embodiment, the peak current comparator comprises: a fourth NMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh NMOS tube, a second Schmitt trigger, a second current detection readout circuit, and a first resistor.
[0013] The source of the fifth PMOS tube and the source of the sixth PMOS tube are connected with VDD, the gate of the fifth PMOS tube and the gate of the sixth PMOS tube are connected with the drain of the sixth PMOS tube, the drain of the sixth PMOS tube and the drain of the seventh NMOS tube are connected with the output end of the second current detection readout circuit, the positive input end of the second current detection readout circuit is the detection I senseP input level of the DRC detection unit, and the negative input end of the second current detection readout circuit is the detection I senseN input level of the DRC detection unit.
[0014] The drain of the fifth PMOS tube and the drain of the fourth NMOS tube are connected with the input end of the second Schmitt trigger, the source of the fourth NMOS tube is connected with GND through the first resistor, the source of the seventh NMOS tube is connected with GND, the gate of the seventh NMOS tube is connected with the gate of the third NMOS tube, the output of the first Schmitt trigger is a second reverse current comparator control signal, and the gate of the fourth NMOS tube is connected with the output end of an external error amplifier.
[0015] In an embodiment, the current compensation module comprises: an eighth NMOS tube, a first fully differential low-pass filter, and a third current detection readout circuit.
[0016] The source of the eighth NMOS tube is connected with GND, the gate of the eighth NMOS tube is connected with the gate of the seventh NMOS tube, the drain of the eighth NMOS tube and the gate of the eighth NMOS tube are connected with the output end of the third current detection readout circuit, the positive input end of the third current detection readout circuit is connected with the positive output end of the first full-differential low-pass filter, the reverse input end of the third current detection readout circuit is connected with the reverse output end of the first full-differential low-pass filter, the positive input end of the first full-differential low-pass filter is the detection I senseP The reverse input end of the first full-differential low-pass filter is the detection I senseN The input stage.
[0017] In an embodiment, the detection I senseP The input stage is connected with the second end of the sampling resistance and the first end of the sampling capacitance; the detection I senseN The input stage is connected with the second end of the sampling capacitance and the second end of the parasitic resistance; the first end of the sampling resistance is connected with the first end of the inductor, and the second end of the inductor is connected with the first end of the parasitic resistance.
[0018] The application provides a DCR detection unit for a peak current mode DCM mode, peak current mode sampling is realized through DCR detection, and the proportion of an inductor L and its parasitic resistance R_dcr and a sampling end R and C is configured to improve the amplitude of an alternating current signal and increase the signal-to-noise ratio of a detection input signal. In order to ensure that a large load output current is not limited by a large detection peak current and the accuracy of current valley zero point turn-off in the DCM mode, a current compensation module is added. The system can realize wide load and high efficiency DCR detection. BRIEF DESCRIPTION OF DRAWINGS
[0019] Figure 1 is a structural schematic diagram of a DCR detection unit for a peak current mode DCM mode provided by the application.
[0020] Figure 2 is a structural schematic diagram of a reverse current comparator provided by the application.
[0021] Figure 3 is a schematic diagram of a reverse current comparator and a current zero-crossing point.
[0022] Figure 4 is a system block diagram of a peak current comparator.
[0023] Figure 5 is a schematic diagram of a peak current comparator and an error amplifier I ea .
[0024] Figure 6 This is a system block diagram of the current compensation module. Detailed Implementation
[0025] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the DCR detection unit for peak current mode DCM proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.
[0026] This invention provides a DCR detection unit for peak current mode DCM mode, used for detecting small DC resistances in current mode switching power supplies, and its structure is as follows. Figure 1 As shown, the system includes a reverse current comparator (IRVE), a peak current comparator (ICMP), and a current compensation module (Current_Compensation). The inverting input of the first current detection readout circuit CR1 in the reverse current comparator is connected to the non-inverting input of the second current detection readout circuit CR2 in the peak current comparator. This connection point is also connected to the non-inverting input of the first fully differential low-pass filter LPF1 in the current compensation module; simultaneously, this connection point serves as the DRC detection input. senseP Input terminal. The positive input terminal of the first current detection readout circuit CR1 in the reverse current comparator is connected to the inverting input terminal of the second current detection readout circuit CR2 in the peak current comparator. This connection point is also connected to the inverting input terminal of the first fully differential low-pass filter LPF1 in the current compensation module. Simultaneously, this connection point serves as the DRC detection input. senseN Input terminal. The gate of the third NMOS transistor M3 in the reverse current comparator is connected to the gate of the seventh NMOS transistor M7 in the peak current comparator. This connection point is connected to the gate of the eighth NMOS transistor M8 in the current compensation module.
[0027] In this invention, different L / R ratios are set. _dcr The ratio of L / R to RC _dcr The (RC) amplifies the peak-to-peak value of the AC signal of the inductor current, improving the input signal-to-noise ratio. Compared with the common peak current mode BUCK with DCM mode, it adds a current compensation module. The compensation current is set according to the ratio of the amplified peak-to-peak value, which can ensure that it is not limited by the large detection peak current when the load output is large and the accuracy of the zero-crossing turn-off of the current valley in DCM mode is guaranteed. The system can realize wide load and high efficiency DCR detection.
[0028] like Figure 2As shown, the reverse current comparator includes: a first PMOS transistor M1, a second PMOS transistor M2, a third NMOS transistor M3, a first Schmitt trigger sensor MMT1, and a first current detection and readout circuit CR1. The sources of both the first PMOS transistor M1 and the second PMOS transistor M2 are connected to VDD. The gates of both the first PMOS transistor M1 and the second PMOS transistor M2 are connected to the drain of the second PMOS transistor M2. The drain of the second PMOS transistor M2 is connected to the output of the first current detection and readout circuit CR1. The positive input of the first current detection and readout circuit CR1 is the DRC detection input. senseN The negative input terminal of the first current detection readout circuit CR1 in the input stage is the DRC detection I. senseP Input stage: The drains of the first PMOS transistor M1 and the third NMOS transistor M3 are both connected to the input of the first Schmitt trigger SMT1. The source of the third NMOS transistor M3 is connected to GND. The output of the first Schmitt trigger SMT1 is the reverse current comparator control signal VO1.
[0029] like Figure 4 As shown, the peak current comparator includes: a fourth NMOS transistor M4, a fifth PMOS transistor M5, a sixth PMOS transistor M6, a seventh NMOS transistor M7, a second Schmitt trigger SMT2, a second current detection and readout circuit CR2, and a first resistor R1. The sources of the fifth PMOS transistor M5 and the sixth PMOS transistor M6 are both connected to VDD. The gates of the fifth PMOS transistor M5 and the sixth PMOS transistor M6 are both connected to the drain of the sixth PMOS transistor M6. The drains of the sixth PMOS transistor M6 and the seventh NMOS transistor M7 are both connected to the output of the second current detection and readout circuit CR1. The positive input of the second current detection and readout circuit CR2 is the DRC detection input. senseP The negative input terminal of the second current detection readout circuit CR2 in the input stage is the DRC detection I. senseN Input stage: The drains of the fifth PMOS transistor M5 and the fourth NMOS transistor M4 are both connected to the input of the second Schmitt trigger SMT2. The source of the fourth NMOS transistor M4 is grounded through the first resistor R1. The source of the seventh NMOS transistor M7 is connected to GND. The output of the first Schmitt trigger SMT1 is the reverse current comparator control signal VO2.
[0030] like Figure 6As shown, the current compensation module comprises: an eighth NMOS transistor M8, a first full differential low-pass filter LPF1, and a third current detection readout circuit CR3.The source of the eighth NMOS transistor M8 is connected with GND, the gate of the eighth NMOS transistor M8 and the gate of the seventh NMOS transistor M7 are both connected with the gate of the third NMOS transistor M3, the drain of the eighth NMOS transistor M8 and the gate of the eighth NMOS transistor M8 are both connected with the output end of the third current detection readout circuit CR3, the positive input end of the third current detection readout circuit CR3 is connected with the positive output end of the first full differential low-pass filter LPF1, the reverse input end of the third current detection readout circuit CR3 is connected with the reverse output end of the first full differential low-pass filter LPF1, the positive input end of the first full differential low-pass filter LPF1 is connected with the DRC detection I senseP , the reverse input end of the first full differential low-pass filter LPF1 is the DRC detection I senseN .
[0031] The DCR detection unit provided by the application is based on a peak current module BUCK topology, and by adding a current compensation module, high signal-to-noise ratio signal detection and large load output are realized. Figure 2 As shown in the figure, the reverse current comparator is a schematic diagram for realizing detection of inductive current in the reverse direction, and the implementation manner is as follows: when the load is reduced to the critical conduction mode, there will be
[0032]
[0033] When entering the DCM mode, the following requirements are required:
[0034]
[0035] Wherein I O is the average output current, I pp is the peak-to-peak current, when , L is the inductance, R _dcr is the parasitic DC small resistance of the inductance, C is the sampling filter capacitor, and R is the sampling filter resistor; the left side of formula (2) is multiplied by the proportion K, and the following formula can be obtained:
[0036]
[0037] Wherein the left side of the formula is the DCR detection valley current read by the first current detection readout circuit CR1, as shown in the figure Figure 3 When it is close to (1-K)I O , the overcurrent comparator is reversed, the low measurement power tube is closed, and the inductive current is prevented from flowing in the reverse direction.
[0038] Figure 4 As shown in the figure, the peak current comparator is a schematic diagram for realizing detection of inductive current in the reverse direction, and the implementation manner is as follows: for , K is equal to 1, and the peak current module I eaThe relationship with the output current is as follows:
[0039]
[0040] As shown in Figure 5 When K>1, the following will occur:
[0041]
[0042] Substitute into equation (5):
[0043]
[0044] According to equation (7), the left side of the equation is the peak current of the sampling, and the right side of the equation is the output current of the error amplifier and the compensation current, which can dynamically increase the output swing of the error amplifier and improve the output current capability.
[0045] According to equation (4) and equation (7), the compensation current is -(K-1)I O , wherein I O is the average output current, Figure 6 The current compensation module filters the sampling signal through the first fully differential low-pass filter LPF1 to obtain an inductance average sampling current, and controls the output current proportion of the third current detection readout circuit CR3 to be (K-1) times I O .
[0046] In summary, the DCR detection unit for the peak current mode DCM of the application increases the current compensation module, ensures the accuracy of the wide load output range and the current reverse off in the DCM mode under the premise of realizing high signal-to-noise ratio signal detection.
[0047] The above description is only a description of the preferred embodiment of the application, and does not limit the scope of the application, and any modification made by the person skilled in the art according to the above disclosure is within the protection scope of the claims.
Claims
1. A DCR detection unit for use in peak current mode DCM, characterized by, The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter.
2. The DCR sensing unit for peak current mode DCM operation as claimed in claim 1 wherein, The application relates to a current control circuit for a synchronous rectification DC-DC converter. The source of the first PMOS tube and the source of the second PMOS tube are connected with VDD, the gate of the first PMOS tube and the gate of the second PMOS tube are connected with the drain of the second PMOS tube, the drain of the second PMOS tube is connected with the output end of the first current detection readout circuit, the positive input end of the first current detection readout circuit is the detection I senseN input stage, and the negative input end of the first current detection readout circuit is the detection I senseP input stage. The application relates to a current control circuit for a synchronous rectification DC-DC converter.
3. The DCR sensing unit for peak current mode DCM operation as claimed in claim 2, wherein, The application relates to a current control circuit for a synchronous rectification DC-DC converter. The source of the fifth PMOS tube and the source of the sixth PMOS tube are connected with VDD, the gate of the fifth PMOS tube and the gate of the sixth PMOS tube are connected with the drain of the sixth PMOS tube, the drain of the sixth PMOS tube and the drain of the seventh NMOS tube are connected with the output end of the second current detection readout circuit, the positive input end of the second current detection readout circuit is the detection I senseP input stage, and the negative input end of the second current detection readout circuit is the detection I senseN input stage. The application relates to a current control circuit for a synchronous rectification DC-DC converter.
4. The DCR sensing unit for peak current mode DCM operation as claimed in claim 3, wherein, The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC-DC converter. The application relates to a current control circuit for a synchronous rectification DC The source of the eighth NMOS tube is connected with GND, the gate of the eighth NMOS tube is connected with the gate of the seventh NMOS tube, the drain of the eighth NMOS tube and the gate of the eighth NMOS tube are connected with the output end of the third current detection readout circuit, the positive input end of the third current detection readout circuit is connected with the positive output end of the first fully differential low-pass filter, the negative input end of the third current detection readout circuit is connected with the negative output end of the first fully differential low-pass filter, and the positive input end of the first fully differential low-pass filter is the detection I senseP input stage, and the negative input end of the first fully differential low-pass filter is the detection I senseN input stage.
5. The DCR sensing unit for peak current mode DCM operation as claimed in claim 4, wherein, The DRC detection unit detects I senseP The input stage simultaneously connects the second end of the sampling resistor and the first end of the sampling capacitor; The DRC detection unit detects I senseN The second end of the sampling capacitor and the second end of the parasitic resistor are connected to the input stage; the first end of the sampling resistor is connected to the first end of the inductor, and the second end of the inductor is connected to the first end of the parasitic resistor.