Masking process correction method of mask plate pattern and chip

Abstract

The invention provides a mask process correction method of a mask plate graph and a chip, and relates to the technical field of integrated circuit manufacturing, and the method comprises the following steps: carrying out gridding processing on a mask design layout to obtain a first grid graph; obtaining a first edge grid corresponding to the graph edge of the mask design layout in the first grid graph to form a first graph edge contour line; obtaining a contour diagram of a pattern in a mask plate prepared by taking the mask design layout as a mask pattern; performing gridding processing with the same grid size as the mask design layout on the contour diagram to obtain a second grid diagram; obtaining a second edge grid corresponding to the pattern edge of the mask in the second grid chart to form a second pattern edge contour line; determining a mask process compensation amount based on the first pattern edge contour line, the second pattern edge contour line and the grid size; and correcting the mask design layout based on the mask process compensation amount to obtain a target mask pattern.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuit manufacturing, and particularly relates to a mask process correction method for mask layout and a chip. BACKGROUND

[0002] With the continuous progress of integrated circuit manufacturing process, the feature size of the chip is gradually reduced to the nanometer level. For example, for advanced processes of 7 nanometers and below, mask precision is crucial to the performance and yield of the chip. Small errors in the mask manufacturing process can cause pattern distortion in chip manufacturing, thereby affecting the function of the chip. There are various non-ideal factors in the mask manufacturing process, such as scattering effect during electron beam exposure, deviation of development and etching process, etc. These factors can cause deviation between the actual pattern of the mask and the design pattern. Mask process correction technology can significantly reduce errors in mask manufacturing by optimizing and correcting the mask pattern in advance, thereby improving the yield and performance of chip manufacturing.

[0003] In 14 nanometer and below technology nodes, mask process correction technology has become a key technology to improve the yield of chip manufacturing. Mask process correction technology needs to handle a large amount of computing tasks, especially in advanced process technology such as 7 nanometers and below. With the reduction of feature size, the complexity of mask pattern increases significantly, resulting in a large amount of time and computing resources consumed in the computing and optimization process. SUMMARY

[0004] In view of the above problems, the present disclosure provides a mask process correction method for mask layout and a chip, which at least partially solves the above technical problems.

[0005] An aspect of an embodiment of the present disclosure provides a mask process correction method for mask layout, comprising: performing grid processing on a mask design layout to obtain a first grid map; obtaining a first edge grid corresponding to the edge of the pattern of the mask design layout in the first grid map to form a first pattern edge contour line; obtaining a contour map of the pattern in a mask plate prepared by taking the mask design layout as a mask pattern; performing grid processing on the contour map with the same grid size as the mask design layout to obtain a second grid map; obtaining a second edge grid corresponding to the edge of the pattern of the mask plate in the second grid map to form a second pattern edge contour line; determining a mask process compensation amount based on the first pattern edge contour line, the second pattern edge contour line and the grid size; and correcting the mask design layout based on the mask process compensation amount to obtain a target mask layout.

[0006] According to an embodiment of the present disclosure, the mask design layout is grid processed to obtain a first grid map, including: dividing the mask design layout into a plurality of first grids; adding a first label to the first grid containing a pattern, and adding a second label to the first grid not containing a pattern to obtain the first grid map, the first label being different from the second label; performing grid processing on the contour map with the same grid size as the mask design layout to obtain a second grid map, including: dividing the contour map into a plurality of second grids with the same size as the first grid; adding a first label to the second grid containing a pattern, and adding a second label to the second grid not containing a pattern to obtain the second grid map, the first label being different from the second label.

[0007] According to an embodiment of the present disclosure, the first edge grid corresponding to the pattern edge of the mask design layout in the first grid map is obtained, including: determining the first grid as the first edge grid when the label of the first grid is the first label and the label of the grid adjacent to the first grid and located outside the first grid is the second label; and the second edge grid corresponding to the pattern edge of the mask layout in the second grid map is obtained, including: determining the second grid as the second edge grid when the label of the second grid is the first label and the label of the grid adjacent to the second grid and located outside the second grid is the second label.

[0008] According to an embodiment of the present disclosure, the mask process compensation amount is determined based on the first pattern edge contour line, the second pattern edge contour line and the grid size, including: calculating the process deviation between each pattern of the mask layout and the corresponding pattern in the mask design layout based on the first pattern edge contour line and the second pattern edge contour line to obtain the process deviation of each pattern in the mask design layout; setting at least two pattern optimization coefficients; determining the position compensation amount of the first edge grid of each pattern based on the respective pattern optimization coefficient, the process deviation of each pattern in the mask design layout and the grid size to obtain a plurality of position compensation amounts; and determining the target compensation amount from the plurality of position compensation amounts as the mask process compensation amount.

[0009] According to an embodiment of the present disclosure, the target compensation amount is determined from the plurality of position compensation amounts, including: correcting the mask design layout based on each group of position compensation amounts to obtain a plurality of corrected mask layout; taking the plurality of corrected mask layout as the input layout for preparing the mask layout to process a plurality of corrected mask layout; performing grid processing on the corrected mask layout and the contour map of the corrected mask layout with the same grid size to obtain a first corrected grid map and a second corrected grid map; for each corrected mask layout and the corresponding corrected mask layout, calculating the mean square error between the edge grid of the first corrected grid map and the corresponding edge grid in the second corrected grid map to obtain a plurality of mean square errors; and determining the position compensation amount corresponding to the mean square error less than the threshold value as the target compensation amount.

[0010] According to an embodiment of the present disclosure, the at least two pattern optimization coefficients are set, including: setting a plurality of pattern optimization coefficients in a gradient increasing manner.

[0011] Another aspect of the embodiment of the present disclosure provides a mask process correction method for a large-scale mask layout, including: dividing the large-scale mask layout into a plurality of local regions; inputting the plurality of local regions into a target model to output a target compensation amount of each local region; the target model is obtained by training a deep learning model based on data composed of a mask design layout and a target mask layout, and the target mask layout is obtained based on the method of the present disclosure; and correcting the large-scale mask layout based on the plurality of target compensation amounts to obtain a large-scale target mask layout.

[0012] According to an embodiment of the present disclosure, the inputting of the plurality of local regions into the target model and the outputting of the target compensation amount of each local region includes: extracting pixel features of the local regions and constructing a topological feature map between global edges, wherein the nodes in the topological feature map are edges of the local regions; fusing the pixel features of the local regions and the topological feature map between the global edges to obtain fused features; and determining the target compensation amount of each local region based on the fused features.

[0013] According to an embodiment of the present disclosure, the correcting of the large-scale mask layout based on the plurality of target compensation amounts to obtain the large-scale target mask layout includes: performing interpolation processing on the target compensation amounts of adjacent local regions to obtain mask process compensation amounts of the large-scale mask layout; and correcting the large-scale mask layout based on the mask process compensation amounts to obtain the large-scale target mask layout.

[0014] According to an embodiment of the present disclosure, the loss function for training the deep learning model is: a mean square error between a predicted compensation amount output by the deep learning model for a local region and a real compensation amount of the local region; and the method further includes: adjusting model parameters of the deep learning model based on the mean square error to obtain the target model.

[0015] According to an embodiment of the present disclosure, the method further includes: performing design rule checking on the large-scale target mask layout, and determining the large-scale target mask layout that meets the design rule as a final mask layout.

[0016] Another aspect of the embodiment of the present disclosure also provides a chip, which is obtained based on a mask processed by a target mask layout or a large-scale target mask layout, and the target mask layout or the large-scale target mask layout is obtained based on the method of the present disclosure.

[0017] The mask process correction method for a mask layout and the chip provided by the present disclosure have at least the following technical effects.

[0018] Under the conditions of fixed process parameters, etching equipment and one-time electron beam exposure, the pattern of the mask artwork is corrected based on the etching result of the mask artwork to compensate for the influence of process deviation, which can solve the problems of irregular etching shape and deviation of etching size from design size caused by scattering effect during electron beam exposure, development and etching process, such as line end shortening, corner rounding, line width variation and other defects.

[0019] Based on the calculation method of the edge profile, the target compensation amount of the mask process can be accurately determined, and a high-precision mask artwork can be obtained.

[0020] By setting different pattern optimization coefficients, a group of corrected mask artworks with gradient changes in target compensation amounts of the process can be obtained based on different position compensation amounts, and correction is completed in one experiment without iterative optimization. Based on the corrected mask artwork, the mask process is prepared, and the target mask artwork with pattern meeting the optimization requirements is confirmed in the corrected mask artwork with gradient changes in target compensation amounts of the process, thereby reducing the calculation resources and improving the correction efficiency.

[0021] By dividing the large-scale mask artwork into multiple local regions, the trained deep learning model is used to predict the process deviation of the large-scale artwork based on the mask artwork before and after optimization, and the artwork is quickly corrected in advance according to the geometric features, topological features and process features of the pattern in the input mask artwork, so that a high-precision mask artwork can be obtained. BRIEF DESCRIPTION OF DRAWINGS

[0022] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure, taken in conjunction with the accompanying drawings, in which:

[0023] Figure 1 A flowchart of a mask process correction method for a mask artwork according to an embodiment of the present disclosure is schematically shown.

[0024] Figure 2 The pattern structure of a part of a mask design artwork and the scanning electron microscope image of the pattern in the mask artwork corresponding to the part of the mask design artwork according to an embodiment of the present disclosure are schematically shown.

[0025] Figure 3 The profile image of the pattern in a part of a mask artwork and the coordinate image corresponding to the profile of the pattern in the part of the mask artwork according to an embodiment of the present disclosure are schematically shown.

[0026] Figure 4 The comparison result image of the profile image after the mask etching process based on the uncorrected mask design artwork and the mask design artwork and the result image obtained after etching type annotation based on the comparison result image according to an embodiment of the present disclosure are schematically shown.

[0027] Figure 5 An SEM image of a same location before and after optimization of a part of a mask design layout according to an embodiment of the present disclosure is shown schematically. A pattern structure after correction of a mask process compensation amount determined.

[0028] Figure 6 An SEM image of a same location before and after optimization of a part of a mask design layout according to an embodiment of the present disclosure is shown schematically. Figure 1 An SEM image of a same location before and after optimization of a part of a mask design layout according to an embodiment of the present disclosure is shown schematically.

[0029] Figure 7 An SEM image of a same location before and after optimization of a part of a mask design layout according to an embodiment of the present disclosure is shown schematically. Figure 6 A profile extraction comparison calculation diagram before and after optimization of a same dashed box region in a mask design layout according to an embodiment of the present disclosure is shown schematically.

[0030] Figure 8 An SEM image of a same location before and after optimization of a part of a mask design layout according to an embodiment of the present disclosure is shown schematically.

[0031] Figure 9 An SEM image of a same location before and after optimization of a part of a mask design layout according to an embodiment of the present disclosure is shown schematically. Figure 8 A profile extraction comparison calculation diagram before and after optimization of a same dashed box region in a mask design layout according to an embodiment of the present disclosure is shown schematically.

[0032] Figure 10 A flowchart of a mask process correction method of a mask layout according to another embodiment of the present disclosure is shown schematically. DETAILED DESCRIPTION

[0033] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that the description which follows is merely exemplary and is not intended to limit the scope of the present disclosure. In the following detailed description of embodiments of the present disclosure, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that one or more embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known structures and

[0034] The related mask process correction method relies on an accurate physical model to simulate various phenomena in the mask manufacturing process. However, the physical model may not fully accurately reflect the complex physical and chemical processes in the actual process in some cases, for example, in the development process, the miniaturization effect of the photoresist will cause a deviation between the simulation result and the actual result; in the etching process, the actual etching rate is affected by the mask pattern topology, density distribution, etc., so that the simulation etching result and the actual result exist deviation, the physical model needs to be further optimized to improve the accuracy of the mask. In addition, the mask manufacturing cost is high, especially the high-end mask, the manufacturing cost is extremely high, the mask process correction needs to ensure the accuracy while reducing the time and cost as much as possible.

[0035] Therefore, the embodiment of the present disclosure provides a mask process correction method for mask pattern, which can compensate the influence of process deviation by designing the shape of mask pattern under the condition of fixed process parameters, etching equipment and one-time electron beam exposure, solve the problem of irregular etching shape and deviation between etching size and design size caused by scattering effect during electron beam exposure, development and etching process.

[0036] Figure 1 The flowchart of the mask process correction method for mask pattern according to the embodiment of the present disclosure is schematically shown.

[0037] As shown in Figure 1 The mask process correction method for mask pattern of the present embodiment can include operations S110-S170.

[0038] In operation S110, the mask design layout is subjected to grid processing to obtain a first grid map.

[0039] In operation S120, the first edge grid corresponding to the pattern edge of the mask design layout in the first grid map is obtained to form a first pattern edge contour line.

[0040] In operation S130, the contour map of the pattern in the mask prepared by taking the mask design layout as the mask pattern is obtained.

[0041] In operation S140, the contour map is subjected to grid processing with the same grid size as the mask design layout to obtain a second grid map.

[0042] In operation S150, the second edge grid corresponding to the pattern edge of the mask in the second grid map is obtained to form a second pattern edge contour line.

[0043] In operation S160, the mask process compensation amount is determined based on the first pattern edge contour line, the second pattern edge contour line and the grid size.

[0044] At operation S170, the mask design layout is corrected based on the mask process compensation amount, to obtain a target mask layout.

[0045] According to an embodiment of the present disclosure, the pattern of the mask design layout can be designed according to the chip layout to be manufactured, and is theoretically the same as the pattern of the chip layout. The number of the pattern of the mask design layout can be one or multiple. The pattern shape of the mask design layout can be designed according to actual application requirements, and can be a regular pattern or an irregular pattern. The first grid map is composed of multiple grids, some of which contain patterns (which can be referred to as a pattern grid area), and some of which do not contain patterns (a blank grid area). The shape of the grid can be, for example, a square.

[0046] According to an embodiment of the present disclosure, in the case where the number of patterns in the mask design layout is multiple, for each pattern, the first edge grid containing the edge of the pattern is obtained, to obtain the first pattern edge contour line of the pattern.

[0047] According to an embodiment of the present disclosure, the mask design layout can be used to perform electron beam direct writing exposure, development, and plasma etching processes on a quartz substrate with electron beam glue to complete etching. After etching, a scanning electron microscope (SEM) image of the pattern in the prepared mask plate is collected, and the second pattern edge contour line can be obtained based on the SEM image.

[0048] Figure 2 The pattern structure of a part of the mask design layout and the scanning electron microscope image of the pattern in the mask plate corresponding to the part of the mask design layout according to an embodiment of the present disclosure are schematically shown.

[0049] As shown in Figure 2 Due to mask manufacturing process deviation, the pattern of the mask plate obtained after completing the mask etching process has defects such as line end shortening, corner rounding, and line width variation compared with the mask design layout, and mask process deviation correction is needed to design and compensate the pattern of the mask design layout.

[0050] According to an embodiment of the present disclosure, after the contour map is grid processed with the same grid size as the mask design layout, the grid size and shape of the second grid map and the first grid map are the same.

[0051] According to an embodiment of the present disclosure, since the first pattern edge contour line represents the edge of the pattern in the mask design layout, and the second pattern edge contour line represents the edge of the pattern in the mask plate obtained after etching the mask pattern based on the mask design layout, the method can compensate the mask process deviation of the pattern of the mask plate based on the etching result.

[0052] According to embodiments of this disclosure, since the number of graphics contained in the mask design layout may be multiple, it is necessary to determine the mask process compensation amount corresponding to each graphic based on the first graphic edge contour line and the second graphic edge contour line. Based on the mask process compensation amount corresponding to each graphic, each graphic in the mask design layout is corrected to obtain the target mask layout.

[0053] In some embodiments of this disclosure, the mask design layout is meshed to obtain a first mesh diagram, which may include:

[0054] The mask design layout is divided into multiple first grids.

[0055] A first label is added to the first grid that contains graphics, and a second label is added to the first grid that does not contain graphics, resulting in a first grid diagram. The first label and the second label are different.

[0056] For example, the mask design layout can be meshed with a grid size of D, such as 2nm, 5nm, or 10nm. The first label can be set to 1, and the second label can be set to 0. The meshed mask design layout can then be converted into a two-dimensional matrix, which can be represented as follows:

[0057]

[0058] Where x represents the x-coordinate of each grid cell, 0 M represents the number of horizontal grids in the first grid diagram; y represents the vertical coordinate of each grid, 0. N represents the number of vertical grids in the first grid diagram.

[0059] In embodiments of this disclosure, obtaining the first edge grid corresponding to the graphic edge of the mask design layout in the first mesh image may include:

[0060] If the label of the first grid is the first label, and the label of the grid adjacent to the first grid and located outside the first grid is the second label, then the first grid is determined as the first edge grid.

[0061] For example, obtain the edge grid of the graphic in the mask design layout. including the top edge ( ), lower edge ( ), left edge ( ) and right edge ( The image outline, composed of edge grids, is... ,in:

[0062] upper edge Grid in Conditions met: That is, the coordinates are The grid contains graphics, based on coordinates. After shifting the coordinates vertically upwards by one unit coordinate, the coordinates are: The grid does not contain graphics.

[0063] bottom edge Grid in Conditions met: That is, the coordinates are The grid contains graphics, based on coordinates. After shifting the coordinates vertically downwards by one unit coordinate, the coordinates are: The grid does not contain graphics.

[0064] left edge Grid in Conditions met: That is, the coordinates are The grid contains graphics, based on coordinates. After shifting horizontally outward by one unit coordinate, the coordinates are: The grid does not contain graphics.

[0065] right edge Grid in Conditions met: That is, the coordinates are The grid contains graphics, based on coordinates. After shifting horizontally outward by one unit coordinate, the coordinates are: The grid does not contain graphics.

[0066] In embodiments of this disclosure, the contour map is meshed to the same grid size as the mask design layout to obtain a second mesh map. This process may include: dividing the contour map into multiple second grids of the same size as the first grid; adding a first label to the second grids containing graphics and adding a second label to the second grids not containing graphics, thus obtaining the second mesh map. The first label and the second label are different.

[0067] Obtaining the second edge grid corresponding to the graphic edge of the mask in the second grid image can include: if the label of the second grid is the first label, and the label of the grid adjacent to the second grid and located outside the second grid is the second label, then the second grid is determined as the second edge grid.

[0068] Figure 3 The diagram schematically illustrates a contour view of a graphic in a portion of a mask region according to an embodiment of the present disclosure, and a coordinate graph corresponding to the contour of the graphic in the portion of the mask region.

[0069] like Figure 3As shown, after obtaining the SEM image of the mask plate, the contour extraction algorithm can be used to obtain the contour line H(m, n) of the SEM image of the pattern in the initial mask plate, and the contour map is processed by the same size grid according to the above method of extracting the first edge grid based on the mask design layout, and the grid (m, n) is determined as the mask plate contour line as the upper edge (m, n), the lower edge (m, n), the left edge (m, n) and the right edge (m, n) four sets. For specific details, please refer to the above determination process of the first edge grid, which will not be repeated here For specific details, please refer to the above determination process of the first edge grid, which will not be repeated here

[0070] In an embodiment of the present disclosure, the mask process compensation amount is determined based on the first pattern edge contour line, the second pattern edge contour line and the grid size, which can include:

[0071] The process deviation between each pattern of the mask plate and the corresponding pattern in the mask design layout is calculated based on the first pattern edge contour line and the second pattern edge contour line, and the process deviation of each pattern in the mask design layout is obtained.

[0072] At least two pattern optimization coefficients are set.

[0073] Based on the respective pattern optimization coefficient, the respective process deviation of each pattern in the mask design layout and the grid size, the position compensation amount of the first edge grid of each pattern is determined, and a plurality of position compensation amounts are obtained.

[0074] The target compensation amount is determined from the plurality of position compensation amounts as the mask process compensation amount.

[0075] For example, the process deviation of the edge contour of each pattern in the mask design layout caused by the mask process can be:

[0076] For the upper edge of the pattern , the process deviation of each grid , , );

[0077] For the lower edge of the pattern , the process deviation of each grid ,( , );

[0078] For the left edge of the pattern , the process deviation of each grid ,( , );

[0079] For the right edge of the pattern​​​ Process deviation of each grid

[0080] Figure 4 The comparison result figure of the profile map after the mask etching process is completed based on the uncorrected mask design layout and the mask design layout according to the embodiment of the present disclosure is schematically shown, and the result figure obtained after the etching type is labeled based on the comparison result figure.

[0081] Through the above calculation method, if , it means that the etching profile line of the initial mask at the grid is located at the outer edge of the initial design graph, and the etching is excessive (such as the solid grid in Figure 4 , if , it means that the etching profile line at the grid is consistent with the edge of the initial design graph; if , it means that the etching profile line at the grid is located at the inner edge of the initial design graph edge, and the etching is insufficient (such as the hollow grid in Figure 4 ).

[0082] After obtaining the process deviation, the number of grid required for optimization adjustment of the corresponding profile line grid can be calculated based on the process deviation and the grid size D:

[0083]

[0084] , wherein represents the floor function, represents the ceiling function, and i represents the number of the grid.

[0085] For each graph in the mask design layout, n graph optimization coefficients ε1, ε2, …, εn can be set. n If , , …, , the position compensation amount of each graph can be

[0086] For each image, the position after the edge grid correction processing can be obtained based on the position compensation amount, which can be as follows:

[0087] P1(x, y):

[0088] For the upper edge of the graph , the vertical coordinate of each grid after optimization processing is , and the horizontal coordinate is .

[0089] For the lower edge of the graph ​​​​y-coordinate of each grid after optimization x-coordinate of each grid after optimization ;

[0090] for the left edge of the figure x-coordinate of each grid after optimization y-coordinate of each grid after optimization ;

[0091] for the right edge of the figure x-coordinate of each grid after optimization y-coordinate of each grid after optimization ;

[0092] P2(x,y):

[0093] for the top edge of the figure y-coordinate of each grid after optimization x-coordinate of each grid after optimization ;

[0094] for the bottom edge of the figure y-coordinate of each grid after optimization x-coordinate of each grid after optimization ;

[0095] for the left edge of the figure x-coordinate of each grid after optimization y-coordinate of each grid after optimization ;

[0096] for the right edge of the figure x-coordinate of each grid after optimization y-coordinate of each grid after optimization ;

[0097] P n (x,y):

[0098] for the top edge of the figure y-coordinate of each grid after optimization x-coordinate of each grid after optimization ;

[0099] for the bottom edge of the figure y-coordinate of each grid after optimization x-coordinate of each grid after optimization ;

[0100] for the left edge of the figure x-coordinate of each grid after optimization y-coordinate of each grid after optimization ;

[0101] for the right edge of the figure each grid optimization processing horizontal coordinate , vertical coordinate .

[0102] Based on this, the most suitable set of position compensation amounts can be selected from the multiple sets of position compensation amounts as the target compensation amount, and further determined as the mask process compensation amount, to correct the mask design layout, to obtain a target mask layout.

[0103] In embodiments of the present disclosure, a plurality of pattern optimization coefficients with increasing gradients can be set The most suitable optimization coefficient is determined through mask process experiments, and the purpose of designing the optimization coefficient is to improve the robustness of the layout optimization to cope with process fluctuations. Different optimization coefficients are used for different process conditions.

[0104] Figure 5 The pattern structure diagram after correction of the mask process compensation amount determined based on different optimization coefficients according to embodiments of the present disclosure is schematically shown.

[0105] As Figure 5 shown, the optimization coefficients 0.5, 1 and 1.5 are determined, and three sets of optimized patterns with different optimization coefficients are designed for the same pattern in the mask, to obtain optimized design patterns P1(x,y), P2(x,y) and P3(x,y) respectively. The target design pattern is determined from P1(x,y), P2(x,y) and P3(x,y).

[0106] In embodiments of the present disclosure, determining the target compensation amount from the multiple sets of position compensation amounts comprises:

[0107] Respectively correct the mask design layout based on each set of position compensation amounts to obtain multiple corrected mask layouts.

[0108] Respectively take the multiple corrected mask layouts as input layouts for preparing mask plates, and process to obtain multiple corrected mask plates through a mask preparation process.

[0109] Grid the corrected mask layout and the contour map of the corrected mask plate with the same grid size to obtain a first corrected grid map and a second corrected grid map, respectively.

[0110] For each corrected mask layout and the corresponding corrected mask plate, calculate the mean square error between the edge grid of the first corrected grid map and the corresponding edge grid in the second corrected grid map to obtain multiple mean square errors.

[0111] The position compensation amount corresponding to the mean square error less than or equal to the threshold value is determined as the target compensation amount. ​

[0112] Exemplarily, after optimization of all patterns in the mask design layout, n sets of optimized pattern contour lines can be obtained, and for each pattern contour line H(m, n) in the n sets of pattern contour lines, the mean square error thereof with the mask design layout contour line H(m) is calculated to represent an error factor ER of mask manufacturing:

[0113]

[0114] wherein, is the i-th grid of the mask design layout contour line grid, is the i-th grid of the image contour line H(m, n) corresponding to the optimized design of the pattern and the image contour line H(m, n) after completion of the mask manufacturing process, N is the total grid number of the mask design layout contour line, the minimum error factor ERmin of the optimization target is determined, and which set of optimized patterns reaches the optimization target is determined according to the minimum error factor, so as to complete the optimization.

[0115] and the optimization is completed.

[0116] Therefore, the target mask layout corrected by the mask manufacturing process is obtained:

[0117]

[0118] wherein, is the mask design layout, is the pattern optimization coefficient corresponding to the mean square error less than or equal to the threshold value, is the deviation amount of the initial mask layout from the pattern contour line grid of the mask design layout.

[0119] Figure 6 The mask design layout according to the embodiment of the present disclosure is schematically shown. Figure 1 The SEM image comparison diagram of the same position before and after optimization of the partial area is schematically shown.

[0120] As shown in the above mask manufacturing process correction method, the mask manufacturing process deviation correction is performed, and the optimized patterns are significantly improved in terms of line end shortening, corner rounding, line width variation, etc. Figure 6

[0121] The contour extraction comparison calculation diagram of the same dashed box area in the mask design layout before and after optimization according to the embodiment of the present disclosure is schematically shown. Figure 7 Figure 6 As shown in the above mask manufacturing process correction method, the mask manufacturing process deviation correction is performed, and the optimized patterns are significantly improved in terms of line end shortening, corner rounding, line width variation, etc.

[0122] As shown in the above mask manufacturing process correction method, the mask manufacturing process deviation correction is performed, and the optimized patterns are significantly improved in terms of line end shortening, corner rounding, line width variation, etc. Figure 7 ​​​As shown, compared with the design line width of 50 nm, the maximum position offset of the left edge is changed from 14 nm before optimization to 3 nm after optimization, which is improved by 22%; the maximum position offset of the right edge is changed from 7 nm before optimization to 0 nm after optimization, which is improved by 14%.

[0123] Figure 8 A comparison diagram of SEM images before and after the same position optimization of another part of the mask design layout according to an embodiment of the present disclosure is schematically shown.

[0124] As Figure 8 shown, after the mask process correction using the mask process correction method described above, the optimized pattern is significantly improved in terms of line end shortening, corner rounding, line width variation, etc.

[0125] Figure 9 A comparison diagram of profile extraction before and after the same dashed box region optimization in the mask design layout according to an embodiment of the present disclosure is schematically shown. Figure 8

[0126] As Figure 9 shown, the comparison of SEM profile images before and after the optimization of regions A and B in the mask design layout can be obtained. For the longitudinal line A, the edge placement error (EPE) is improved from 21 nm before optimization to 1 nm after optimization; for the horizontal line B, the EPE is improved from 18 nm before optimization to 0 nm after optimization. Figure 6 The above results show that after the mask process correction method described above, the pattern fidelity and quality of the mask plate processing can be significantly improved, which has important reference value for the field.

[0127]

[0128] A flowchart of a mask process correction method of a mask plate layout according to another embodiment of the present disclosure is schematically shown. Figure 10 As

[0129] shown, the mask process correction method of the mask plate layout of the present embodiment can include operation S1010 to operation S1030. Figure 10 In operation S1010, the large-scale mask plate layout is divided into a plurality of local regions.

[0130] In operation S1020, the plurality of local regions are input into a target model, and the target compensation amount of each local region is output.

[0131] In operation S130, the large-scale mask plate layout is corrected based on the plurality of target compensation amounts, and a large-scale target mask plate layout is obtained.

[0132]

[0133] ​​According to an embodiment of the present disclosure, a square window with a size of w x w can be selected according to the input requirements of the mask design layout and the model. The large-scale layout is divided into a plurality of local regions. For example, the size of the mask design layout is W x H, which can be divided into ⌊W / w⌋ windows in the horizontal direction and ⌊H / w⌋ windows in the vertical direction. Wherein, ⌊·⌋ represents the floor function. The step length between adjacent windows is s (s < w), and for a large-scale layout M, the segmented local region can be represented as:

[0134]

[0135] Wherein, i and j represent the index of the window in the vertical and horizontal directions, respectively.

[0136] According to an embodiment of the present disclosure, the target model is obtained by training the deep learning model based on the data pair composed of the mask design layout and the target mask layout, and the target mask layout can be obtained based on the mask process correction method described above.

[0137] For example, the data pair composed of the mask design layout and the target mask layout can be used as the training set of the deep learning model, and the deviation data is obtained by extracting and calculating as described in the above embodiments. Feature parameters are extracted from the graphics of the training set, including geometric features: graphic area, perimeter, aspect ratio, contour curvature, local density; topological features: spacing between adjacent graphics, number of polygon edges; process features: etching direction sensitivity (horizontal / vertical edge), minimum graphic size. The displacement of the edge profile before and after optimization and the critical dimension change are used as the label of the graphics. The graphics are rotated, translated, and scaled to simulate the diversity in the layout, and Gaussian noise is added to simulate process fluctuations.

[0138] According to an embodiment of the present disclosure, the loss function for training the deep learning model is the mean square error between the predicted compensation amount output by the deep learning model for the local region and the true compensation amount of the local region. The method further comprises adjusting the model parameters of the deep learning model based on the mean square error to obtain the target model.

[0139] The loss function can be defined to measure the difference between the predicted compensation amount and the true compensation amount. The mean square error (MSE) is used as the loss function:

[0140]

[0141] Wherein, , is the true compensation amount of the local region i, and N is the number of local regions.

[0142] Further, the loss function can be based on

[0143]

[0144] performing model optimization, is the model parameter of the lth iteration training, is the model parameter of the (l+1)th iteration training, is the learning rate, is the gradient of the loss function with respect to the parameter.

[0145] In an embodiment of the present disclosure, inputting a plurality of local regions into a target model and outputting a target compensation amount of each local region can include:

[0146] extracting pixel features of the local region and a topological feature map between edges, wherein a node in the topological feature map is an edge of the local region.

[0147] fusing the pixel features and the topological feature map between edges to obtain fused features.

[0148] determining the target compensation amount of the local region based on the fused features.

[0149] For example, the target model of the embodiment of the present disclosure can adopt a hybrid model (CNN+GNN) based on a convolutional neural network and a graph neural network, which combines local pixel features and global topological relationships of a mask design layout. The image block of the local region of the mask design layout is taken as input to predict the compensation amount (Δx, Δy) of each edge. The difference between the predicted compensation amount and the true value is minimized using mean square error.

[0150] The target model can be divided into four parts: a convolutional neural network (CNN) for extracting pixel features of a local image block; a graph neural network (GNN) for modeling the topological relationship between global edges; a fusion module for combining local and global features for prediction; and a prediction module for predicting the target compensation amount of the edges of the graph. The specific process can be as follows:

[0151] First, the large-scale mask layout is divided into local regions, each region corresponding to an image block, forming an image block set, which is represented by a matrix as follows: , where h and w represent the height and width of the local image block, respectively.

[0152] Second, pixel features of the local region are extracted based on CNN (local features). The input of the CNN is the matrix of the mask design layout After the convolutional and pooling layers of the CNN, the feature map is obtained as follows:

[0153]

[0154] where C is the number of channels, and respectively represent the height and width of the feature map.

[0155] Next, the topological feature extraction of the local region is performed based on the GNN. The graph edges of the mask design layout are connected by the topological relationship of the layout As the nodes of the graph, the edge connection relationship is determined by the layout topology. The GNN updates the node features through the message passing mechanism. After K layers of GNN, the feature of node j is updated as:

[0156]

[0157] where N(j) is the neighbor node set of node j, and is the weight matrix and bias term of the k-th layer, is the activation function.

[0158] The local features extracted by the CNN are taken as the initial input:

[0159]

[0160] Next, the topological feature map between the pixel features and the edge is fused. The pixel features and the topological feature map between the edges can be spliced along the channel dimension. The feature map and the node feature matrix are converted into the same representation form and then fused.

[0161] Since the mask design layout is divided into N local regions, each local region corresponds to a node For each local region j, its fused fusion feature can be represented as:

[0162]

[0163]

[0164] wherein, is the feature map of the local region i extracted by the CNN, which is flattened into a vector, is the feature vector of the corresponding node extracted by the GNN. and are the weight matrix and the bias term, respectively.

[0165] Finally, the compensation amount is predicted. The fusion feature is input into the prediction module (the prediction module can adopt a multi-layer perception (MLP)), and the output is the compensation amount . The prediction process can be represented as:

[0166]

[0167] wherein the MLP comprises multiple fully connected layers and activation functions. and are weight matrix and bias term, respectively.

[0168] Since the mask design layout can contain multiple images, the output of the target model can be a compensation matrix with the same size as the local region:

[0169]

[0170] wherein f represents a prediction function of the target model, comprising convolutional layer and graph neural network layer operations. Based on this, the compensation of the mask design layout graph edge can be obtained.

[0171] In an embodiment of the present disclosure, based on the plurality of target compensation amounts, the large-scale mask layout is corrected to obtain a large-scale target mask layout, which can include:

[0172] The target compensation amounts of adjacent local regions are interpolated to obtain mask process compensation amounts of the large-scale mask layout.

[0173] Based on the mask process compensation amounts, the large-scale mask layout is corrected to obtain a large-scale target mask layout.

[0174] According to an embodiment of the present disclosure, the adjacent graph compensation results can be interpolated to avoid boundary effects, and the compensation results can be subjected to design rule checking (DRC) to ensure that the results after compensation meet the design rules.

[0175] For example, a bilinear interpolation method can be used. For a point (x, y) in the overlapping region, the compensation amount thereof can be calculated by interpolating the compensation amounts of the four adjacent points:

[0176]

[0177] wherein (x,y) are the four adjacent points around the point (x, y), and the corresponding compensation amounts thereof are , , , , , , , and .

[0178] After the mask design layout is compensated based on the compensation amounts, the compensated layout can be subjected to DRC to ensure that the results after compensation meet the design rules. The DRC check is represented as:

[0179]

[0180] wherein, represents the target mask layout after mask process compensation. The prediction result of =1 is taken as the final layout of mask process correction of the large-scale layout, so as to complete the correction.

[0181] Based on the mask process correction method of the above mask layout, the embodiments of the present disclosure further provide a chip, which is obtained by mask processing based on a target mask layout or a large-scale target mask layout, and the target mask layout or the large-scale target mask layout is obtained based on the above method.

[0182] It should be noted that the specific implementation details and the technical effects brought by the chip embodiments are the same as or similar to those of the above method embodiments, and will not be described here.

[0183] The above describes the embodiments of the present disclosure. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present disclosure. Although each embodiment is described above, this does not mean that the measures in each embodiment cannot be used advantageously in combination. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various alternatives and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A mask process correction method for a mask pattern, characterized by, The method comprises the following steps: performing grid processing on a mask design layout to obtain a first grid map; obtaining a first edge grid corresponding to the edge of a pattern in the mask design layout in the first grid map, to form a first pattern edge contour line; obtaining a contour map of a pattern in a mask plate prepared by taking the mask design layout as a mask pattern; performing grid processing on the contour map with the same grid size as the mask design layout to obtain a second grid map; obtaining a second edge grid corresponding to the edge of a pattern in the mask plate in the second grid map, to form a second pattern edge contour line; determining a mask process compensation amount based on the first pattern edge contour line, the second pattern edge contour line and the grid size; correcting the mask design layout based on the mask process compensation amount to obtain a target mask plate layout.

2. The method of claim 1, wherein, The grid processing on the mask design layout to obtain the first grid map comprises the following steps: dividing the mask design layout into a plurality of first grids; adding a first label to the first grid containing a pattern and adding a second label to the first grid not containing a pattern to obtain the first grid map, wherein the first label is different from the second label; The grid processing on the contour map with the same grid size as the mask design layout to obtain the second grid map comprises the following steps: dividing the contour map into a plurality of second grids with the same size as the first grid size; adding the first label to the second grid containing a pattern and adding the second label to the second grid not containing a pattern to obtain the second grid map, wherein the first label is different from the second label.

3. The method of claim 2, wherein, The obtaining of the first edge grid corresponding to the edge of the pattern in the mask design layout in the first grid map comprises the following steps: in the case that the label of the first grid is the first label and the label of the grid adjacent to the first grid and located outside the first grid is the second label, the first grid is determined as the first edge grid; The obtaining of the second edge grid corresponding to the edge of the pattern in the mask plate in the second grid map comprises the following steps: in the case that the label of the second grid is the first label and the label of the grid adjacent to the second grid and located outside the second grid is the second label, the second grid is determined as the second edge grid.

4. The method according to any one of claims 1 to 3, characterized in that, The determination of the mask process compensation amount based on the first pattern edge contour line, the second pattern edge contour line and the grid size comprises the following steps: calculating the process deviation between each pattern of the mask plate and the corresponding pattern in the mask design layout based on the first pattern edge contour line and the second pattern edge contour line to obtain the process deviation of each pattern in the mask design layout; setting at least two pattern optimization coefficients; determining the position compensation amount of the first edge grid of each pattern based on the pattern optimization coefficient, the process deviation of each pattern in the mask design layout and the grid size respectively to obtain a plurality of groups of position compensation amounts; determining a target compensation amount from the plurality of groups of position compensation amounts as the mask process compensation amount.

5. The method of claim 4, wherein, The determination of the target compensation amount from the plurality of groups of position compensation amounts comprises the following steps: correct the mask design layout based on each set of position compensation amount respectively, to obtain a plurality of corrected mask layout; respectively take the plurality of corrected mask layout as an input layout for preparing a mask, to obtain a plurality of corrected mask; perform grid processing on the corrected mask layout and the profile of the corrected mask with the same grid size, to obtain a first corrected grid and a second corrected grid respectively; for each corrected mask layout and the corresponding corrected mask, calculate the mean square error between the edge grid of the first corrected grid and the corresponding edge grid in the second corrected grid, to obtain a plurality of mean square error; determine the position compensation amount corresponding to the mean square error less than or equal to the threshold value as the target compensation amount.

6. The method of claim 4, wherein, The setting at least two pattern optimization coefficients includes: setting a plurality of pattern optimization coefficients with gradient increasing.

7. A method of mask process correction for large mask artwork, characterized by, including: segmenting the large-scale mask layout into a plurality of local regions; inputting the plurality of local regions into a target model to output the target compensation amount of each local region; the target model is obtained by training a deep learning model based on the data composed of the mask design layout and the target mask layout, the target mask layout is obtained based on the method of any one of claims 1-6; correct the large-scale mask layout based on a plurality of target compensation amounts to obtain a large-scale target mask layout.

8. The method of claim 7, wherein, The inputting the plurality of local regions into a target model to output the target compensation amount of each local region includes: extracting the pixel features of the local region and constructing a topological feature map between global edges, the nodes in the topological feature map are the edges of the local region; fuse the pixel features of the local region and the topological feature map between global edges to obtain fused features; determine the target compensation amount of each local region based on the fused features.

9. The method according to claim 7 or 8, characterized in that, The correction of the large-scale mask layout based on a plurality of target compensation amounts to obtain a large-scale target mask layout includes: interpolate the target compensation amounts of adjacent local regions to obtain the mask process compensation amount of the large-scale mask layout; correct the large-scale mask layout based on the mask process compensation amount to obtain the large-scale target mask layout.

10. A chip, characterized by The chip is prepared based on the mask prepared by the target mask layout or the large-scale target mask layout, the target mask layout is obtained based on the method of any one of claims 1-6, and the large-scale target mask layout is obtained based on the method of any one of claims 8-9.

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