Packaging structure, preparation method thereof and electronic equipment

Abstract

The embodiment of the invention discloses a packaging structure, a preparation method thereof and electronic equipment, relates to the field of semiconductors, and aims to reduce interference among a plurality of chips without additionally increasing the size of the packaging structure. The packaging structure comprises a substrate, a first chip, a first packaging layer, a second chip and a second packaging layer. The first chip is arranged on one side of the substrate; the first chip is coupled to the substrate. The first packaging layer is arranged on the side, away from the substrate, of the first chip and wraps the first chip. The second chip is arranged on the side, away from the first chip, of the first packaging layer in the stacking direction of the substrate and the first chip; the second chip is coupled to the substrate. The second packaging layer is arranged on one side, far away from the first packaging layer, of the second chip along the stacking direction of the substrate and the first chip, and wraps the second chip on the substrate; wherein the second packaging layer wraps the first packaging layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor technology, and in particular, but not exclusively, to a packaging structure and a preparation method thereof, and an electronic device. BACKGROUND

[0002] With the development of mobile terminals and wearable electronic products, more and more challenges are brought to the layout of the mainboard of the electronic products. In order to solve this problem, the application of integrating various different chips into one packaging template is more and more widely used. With the increase of the number of packaged chips, the structure of realizing coupling between adjacent chips and the arrangement mode of multiple chips are important factors affecting the performance of the packaged chips. SUMMARY

[0003] Therefore, embodiments of the present application provide a packaging structure and a preparation method thereof, and an electronic device to solve at least one problem in the prior art, which can reduce the crosstalk of the signal lines of adjacent chips, improve the performance of the packaging structure, and does not additionally increase the size of the packaging structure.

[0004] The technical scheme of the embodiments of the present application is implemented as follows:

[0005] In a first aspect, the embodiments of the present application provide a packaging structure. The packaging structure includes a substrate, a first chip, a first packaging layer, a second chip and a second packaging layer. The first chip is arranged on one side of the substrate; the first chip is coupled with the substrate. The first packaging layer is arranged on the side of the first chip away from the substrate, and covers the first chip. The second chip is arranged on the side of the first packaging layer away from the first chip along the stacking direction of the substrate and the first chip; the second chip is coupled with the substrate. The second packaging layer is arranged on the side of the second chip away from the first packaging layer along the stacking direction of the substrate and the first chip, and covers the second chip on the substrate; wherein the second packaging layer covers the first packaging layer.

[0006] In some examples, the first chip is coupled with the substrate through a first conductive line; the first packaging layer covers the first conductive line. The second chip is coupled with the substrate through a second conductive line; the second conductive line is located between the first packaging layer and the second packaging layer.

[0007] In some examples, the first packaging layer includes a top surface located on the side of the first chip away from the substrate, and a side wall extending to the substrate along the edge of the top surface and surrounding the first chip; the included angle between the top surface and the side wall is an obtuse angle.

[0008] In some examples, the substrate includes a plurality of groups of pins; the first chip is coupled with one group of the pins; the second chip is coupled with one group of the pins. The pins coupled with the first chip are related to a number and / or size of the first conductive lines of the first chip along a dimension parallel to a plane where the substrate is located; the pins coupled with the second chip are related to a number and / or size of the second conductive lines of the second chip along the dimension parallel to the plane where the substrate is located. The thickness of the first encapsulation layer and the dimension parallel to the plane where the substrate is located are related to the number and / or size of the first conductive lines of the first chip and the number and / or size of the second conductive lines of the second chip.

[0009] In some examples, a plurality of the second chips are arranged at a side of the first encapsulation layer away from the first chip. The pins coupled with the first chip include first pins and second pins; some of the second chips are coupled with the first pins, and some of the second chips are coupled with the second pins.

[0010] In some examples, the second chip is connected with the first encapsulation layer by a chip adhesive film.

[0011] In some examples, the packaging structure further includes a third chip and a third encapsulation layer. The third chip is arranged at a side of the second encapsulation layer away from the second chip along a stacking direction of the substrate and the first chip; the third chip is coupled with the substrate. The third encapsulation layer is arranged at a side of the third chip away from the third chip and encapsulates the third chip on the substrate. The third encapsulation layer encapsulates the second encapsulation layer.

[0012] In some examples, the packaging structure further includes a fourth chip arranged between the first encapsulation layer and the first chip. The fourth chip is coupled with the substrate through the first chip; wherein the first chip is coupled with the substrate through first conductive lines.

[0013] In the packaging structure, the first encapsulation layer encapsulates the first chip, the second chip is arranged on the first encapsulation layer, and the second chip is encapsulated on the substrate by using the second encapsulation layer, so that the structure of the stacked chips encapsulated by the packaging layers is realized. The second encapsulation layer encapsulates the first encapsulation layer, and the first chip and the second chip are encapsulated into an integral structure, instead of arranging the encapsulated chips in layers after the chips are independently encapsulated. In this way, the packaging structure realized by the application can improve the stable encapsulation effect of the first chip and the second chip, and by respectively encapsulating different chips by different encapsulation layers, the different chips can be separated, especially the conductive lines of the stacked chips, which facilitates the layout design of the lines, reduces the process difficulty of the conductive lines of the multiple chips, and can reduce the interference between the stacked multiple chips (especially, the chip transmitting sensitive signals can be separated from other chips to avoid crosstalk, so that better performance is achieved).

[0014] In a second aspect, the embodiments of the application provide an electronic device. The electronic device includes one or more packaging structures according to any of the above examples, and a housing. The housing surrounds the one or more packaging structures.

[0015] In a third aspect, the embodiments of the application provide a preparation method of a packaging structure. The preparation method includes: providing a substrate; arranging a first chip on the substrate, the first chip being coupled to the substrate; forming a first encapsulation layer on a side of the first chip away from the substrate, the first encapsulation layer encapsulating the first chip; arranging a second chip on a side of the first encapsulation layer away from the substrate, the second chip being coupled to the substrate; and forming a second encapsulation layer on a side of the second chip away from the first encapsulation layer in a stacking direction of the substrate and the first chip, the second encapsulation layer encapsulating the second chip on the substrate to obtain an encapsulated substrate, wherein the second encapsulation layer encapsulates the first encapsulation layer.

[0016] In some examples, before the second chip is arranged on the side of the first encapsulation layer away from the substrate, the method further includes grinding a surface of the first encapsulation layer.

[0017] The arrangement of the second chip on the side of the first encapsulation layer away from the substrate includes connecting the second chip and the first encapsulation layer by using a chip bonding film.

[0018] In some examples, the arrangement of the second chip on the side of the first encapsulation layer away from the substrate further includes forming a second conductive line in an extension direction of a sidewall of the first encapsulation layer, the second conductive line being coupled to a pin on the substrate.

[0019] In some examples, the disposing the first chip on the substrate includes forming a first conductive wire coupled with the first chip and the substrate.

[0020] The forming the first encapsulation layer away from the substrate side of the first chip includes disposing a thickness and a dimension along a plane parallel to a plane where the substrate is located of the first encapsulation layer based on a number and / or a dimension of the second conductive wire and a number and / or a dimension of the first conductive wire.

[0021] In some examples, the providing the substrate includes disposing a plurality of groups of pins on the substrate; wherein a dimension along a plane parallel to a plane where the substrate is located of a pin coupled with the second chip is disposed based on a number and / or a dimension of the second conductive wire; and a dimension along a plane parallel to a plane where the substrate is located of a pin coupled with the first chip is disposed based on a number and / or a dimension of the first conductive wire.

[0022] In some examples, after the forming the second encapsulation layer, the method further includes cutting the encapsulated substrate to obtain a plurality of encapsulation structures. One of the plurality of encapsulation structures includes a structure that encapsulates the first chip and the second chip stacked in layers with the first encapsulation layer and the second encapsulation layer, respectively; and a dimension of the encapsulation structure is similar to a dimension of the second encapsulation layer along a plane parallel to a plane where the substrate is located.

[0023] The method for preparing the encapsulation structure described above is used to prepare the encapsulation structure provided in any of the examples described above. The method for preparing the encapsulation structure has the same beneficial effects as the encapsulation structure provided in any of the examples described above, and will not be described again here. BRIEF DESCRIPTION OF DRAWINGS

[0024] In the drawings, like reference numerals can be used to describe like parts throughout the several views. Like reference numerals with different letter suffixes can represent different instances of the like parts. The drawings illustrate generally, by way of example, various embodiments discussed in the present document.

[0025] Figure 1 Structure diagram of the encapsulation structure provided for the implementation of the present application Figure 1 ;

[0026] Figure 2 Structure diagram of the encapsulation structure provided for the implementation of the present application Figure 2 ;

[0027] Figure 3 Structure diagram of the encapsulation structure provided for the implementation of the present application Figure 3 ;

[0028] Figure 4 Structure diagram of the encapsulation structure provided for the implementation of the present application Figure 4;

[0029] Figure 5 Structure diagram of a packaging structure provided for implementation of the present application Figure 5 ;

[0030] Figure 6 Structure diagram of a packaging structure provided for implementation of the present application Figure 6 ;

[0031] Figure 7 Structure diagram of a packaging structure provided for implementation of the present application Figure 7 ;

[0032] Figure 8 Structure diagram of an electronic device provided for implementation of the present application

[0033] Figure 9 Preparation method flow diagram of a packaging structure provided for implementation of the present application Figure 1 ;

[0034] Figure 10 (a)~(e) in Figure 10 Preparation process flow diagram of a packaging structure provided for implementation of the present application

[0035] Figure 11 Preparation method flow diagram of a packaging structure provided for implementation of the present application Figure 2 ;

[0036] Figure 12 Preparation method flow diagram of a packaging structure provided for implementation of the present application Figure 3 ;

[0037] Figure 13 Preparation method flow diagram of a packaging structure provided for implementation of the present application Figure 4 ;

[0038] Figure 14 Preparation method flow diagram of a packaging structure provided for implementation of the present application Figure 5 . DETAILED DESCRIPTION

[0039] The technical solutions of the present application are further described in detail below in combination with the accompanying drawings and specific embodiments.

[0040] In the embodiments of the present application, the terms “first”, “second”, etc. are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0041] In the embodiments of the present application, the term “A is in contact with B” includes the case where A is in direct contact with B, or the case where A is indirectly in contact with B with other components interposed between A and B.

[0042] It should be understood that the reference herein to “some embodiments” or “some examples” means that a particular feature, structure, or characteristic relating to an embodiment is included in at least one embodiment of the application. Therefore, the appearances of “in some embodiments” or “in some examples” at various places throughout the specification are not necessarily referring to the same embodiment. In addition, such particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the sequence of the processes described above does not mean the order of execution, and the order of execution of the processes should be determined according to their functions and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the application. The sequence of the embodiments of the application described above is only for description, and does not represent the advantages or disadvantages of the embodiments.

[0043] It should be noted that the terms “comprises”, “comprising”, or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, an element defined by the phrase “comprising a” does not exclude the existence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0044] It can be understood that the meanings of “on”, “over”, and “above” in the present application should be interpreted in the broadest way, such that “on” not only means the meaning of “on” with no intervening features or layers therebetween (i.e. directly on), but also includes the meaning of “on” with intervening features or layers therebetween.

[0045] It should be noted that although the present specification is described in terms of embodiments, not every embodiment contains only one independent technical solution, and the description manner of the specification is only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be properly combined to form other embodiments that those skilled in the art can understand.

[0046] Quad Flat Package (QFP) is a surface mount package. Its pins are drawn from four sides, in the form of a gull wing (L), which allows the pins to be arranged compactly around the package. The pin count of QFP packages is generally more than 100, and is suitable for large-scale or very large-scale integrated circuits, such as microprocessors, digital signal processors, etc. The base materials of QFP packages are ceramic, metal and plastic, among which plastic packages account for the vast majority due to low cost and mature technology. In addition, QFP packages have small size and reduced parasitic parameters, which are suitable for high-frequency applications.

[0047] With the demand for higher integration, the more functions a single chip needs to implement, the more dies QFP needs to accommodate, while generating more packaging risks, including too close to the patch, cross-wire, and so on, and performance problems (too close to the device, signal crosstalk caused by wire).

[0048] It should be noted that Chip and Die can refer to the same structure (the names can be interchangeable), or Die can be an unencapsulated Chip. Different levels of chip structures can be set according to requirements, for example, Chip, Die and Wafer are three different levels of chip structures. The examples provided in this application are described in the name of "chip", which does not limit whether "chip" is a Chip or Wafer structure.

[0049] Also, in the packaging structure provided in this application, "first chip", "second chip", "third chip" and "fourth chip" are described as a kind of chip in the same positional relationship in the packaging structure, and chips in different positional relationships are distinguished by different names. Different kinds of chips can be the same or different in function, which can be set according to actual needs.

[0050] To solve the above technical problems, as shown in Figures 1 to 7 The application provides a packaging structure 100, which can set a layered chip packaging structure, improve the layout of the chip, reduce the interference between multiple chips, and does not increase the size of the packaging structure.

[0051] As shown in Figure 1 The packaging structure 100 includes a substrate 110, a first chip 120, a first packaging layer 130, a second chip 140 and a second packaging layer 150.

[0052] The first chip 120 is arranged on one side of the substrate 110; the first chip 120 is coupled to the substrate 110.

[0053] The first packaging layer 130 is arranged on the side of the first chip 120 away from the substrate 110, and covers the first chip 120.

[0054] The second chip 140 is arranged on the side of the first packaging layer 130 away from the first chip 120 along the stacking direction of the substrate 110 and the first chip 120; the second chip 140 is coupled to the substrate 110.

[0055] The second encapsulation layer 150 is arranged on the side of the second chip 140 away from the first encapsulation layer 130 along the stacking direction of the substrate 110 and the first chip 120, and encapsulates the second chip 140 on the substrate 110; and the second encapsulation layer 150 encapsulates the first encapsulation layer 130.

[0056] In the encapsulation structure 100, the first chip 120 is encapsulated by the first encapsulation layer 130, the second chip 140 is arranged on the first encapsulation layer 130, and the second chip 140 is encapsulated on the substrate 110 by the second encapsulation layer 150, so as to realize the structure of the encapsulation-stacked multiple chips, which is conducive to reducing the size of the encapsulation structure 100. The second encapsulation layer 150 encapsulates the first encapsulation layer 130, and the first chip 120 and the second chip 140 are encapsulated into an integral structure, instead of the mode of independently encapsulating the chips by the encapsulation layer and then stacking the encapsulated chips. In this way, the encapsulation structure 100 realized by the present application can improve the stable encapsulation effect of the first chip 120 and the second chip 140; and by respectively encapsulating different chips by different encapsulation layers, the different chips can be separated, especially the conductive lines of the stacked multiple chips, which is conducive to the layout design of the lines, reduces the process difficulty of the conductive lines of the multiple chips, and can reduce the interference between the stacked multiple chips (especially, the chip transmitting sensitive signals can be separated from other chips to avoid crosstalk, so as to achieve better performance).

[0057] In some examples, as shown in Figure 2 The first chip 120 is coupled to the substrate 110 by the first conductive line 121. The first encapsulation layer 130 encapsulates the first conductive line 121.

[0058] The second chip 140 is coupled to the substrate 110 by the second conductive line 141. The second conductive line 141 is located between the first encapsulation layer 130 and the second encapsulation layer 150.

[0059] For example, the first encapsulation layer 130 encapsulates the first conductive line 121 and separates the first conductive line 121 from the second conductive line 141, which can reduce the signal interference between the first conductive line 121 and the second conductive line 141, reduce the interference between the stacked first chip 120 and the second chip 140, and improve the performance of the encapsulation structure 100. Moreover, the first conductive line 121 is formed in the space surrounded by the first encapsulation layer 130, which is independent in space and is conducive to the layout design of the first conductive line 121, reducing the risk of wire bonding of the first conductive line 121. Similarly, the second conductive line 141 is formed in the second encapsulation layer 140, which is independent in space and is conducive to the layout design of the second conductive line 141, reducing the risk of wire bonding of the second conductive line 141.

[0060] In some examples, as shown in Figure 2As shown, the first encapsulation layer 130 includes a top surface 131 on a side of the first chip 120 away from the substrate 110, and a sidewall 132 extending from an edge of the top surface 131 to the substrate 110 and surrounding the first chip 120; an included angle between the top surface 131 and the sidewall 132 is obtuse.

[0061] In an example, the second conductive wire 141 can be formed in a wire bonding manner and coupled the second chip 140 and the substrate 110, and the included angle between the top surface 131 and the sidewall 132 of the first encapsulation layer 130 is obtuse, which can reduce the probability of the end of the included angle between the top surface 131 and the sidewall 132 of the first encapsulation layer 130 being sharp and causing the second conductive wire 141 to be broken, and improve the yield of the second conductive wire 141.

[0062] In some examples, as shown in FIG. 1, the substrate 110 includes a plurality of groups of pins 111. The first chip 120 is coupled to one group of pins 111. The second chip 140 is coupled to one group of pins 111. Figure 3 As shown, the substrate 110 includes a plurality of groups of pins 111. The first chip 120 is coupled to one group of pins 111. The second chip 140 is coupled to one group of pins 111.

[0063] The pins 111 coupled to the first chip 120 along a dimension parallel to a plane on which the substrate 110 lies are related to a number and / or a size of the first conductive wires 121 of the first chip 120. The pins 111 coupled to the second chip 140 along a dimension parallel to a plane on which the substrate 110 lies are related to a number and / or a size of the second conductive wires 141 of the second chip 140. The thickness and the dimension L2 of the first encapsulation layer 130 along a dimension parallel to a plane on which the substrate 110 lies are related to the number and / or the size of the first conductive wires 121 of the first chip 120 and the number and / or the size of the second conductive wires 141 of the second chip 140.

[0064] For example, based on the number and / or size of the first conductive lines 121 of the first chip 120, the first encapsulation layer 130 is set along a dimension parallel to the substrate 110 to ensure that the first encapsulation layer 130 can cover the first chip 120 on the substrate 110. Then, based on the number and size of the second conductive lines 141 of the second chip 140 (e.g., the spacing between multiple second conductive lines 141, and the linewidth of the second conductive lines 141, etc.), the initial first encapsulation layer 131 can be thinned by grinding, and the slope of the sidewalls of the first encapsulation layer 131 can be adjusted to reduce the dimension L2 of the first encapsulation layer 131 along the plane parallel to the substrate 110. This can reduce the size of the structure after encapsulating the first chip 120, and achieve the overall size of the encapsulation structure 100 without additionally increasing the size of the stacked first chip 120 and second chip 140. Wherein, without increasing the overall size of the package structure 100 of the first chip 120 and the second chip 140, the dimension L1 of the pin 111 coupled to the first chip 120 along the plane parallel to the substrate 110 can be adjusted, and the dimension L1 of the pin 111 coupled to the second chip 140 along the plane parallel to the substrate 110 can be adjusted to ensure the performance of the transmission signals of the first chip 120 and the second chip 140.

[0065] In this way, based on the number and size of the first conductive lines 121 of the first chip 120 and the number and size of the second conductive lines 141 of the second chip 140, the pins 111 on the substrate 110 can be adjusted along the dimension L1 parallel to the plane where the substrate 110 is located. This allows for good coupling performance between the first chip 120 and the second chip 140 and the substrate 110, while also adjusting the size of the first packaging layer 130 without additionally increasing the size of the packaging structure 100.

[0066] It should be noted that, Figure 3 In the package structure 100 shown, the first chip 120 and the second chip 140 are coupled to pins 111 on the substrate 110. Because multiple sets of pins 111 are disposed on the surface of the substrate 110, from... Figure 3 The pins shown in the diagram represent multiple pins located on the surface of substrate 110 (on the same layer), and are not limited to two specific pins. Therefore, the coupling of the first chip 120 and the second chip 140 to pins 111 on substrate 110 can be with the same set of pins on substrate 110 or with different sets of pins on substrate 110. The examples provided in this application do not limit this, and the configuration can be tailored to specific examples.

[0067] In some examples, such as Figure 4 As shown, a plurality of second chips 140 are spaced apart on the side of the first package layer 130 away from the first chip 120. The pins 111 coupled to the first chip 120 include a first pin 111A and a second pin 111B.

[0068] Part of the second chip 140 is coupled with the first pin 111A, and another part of the second chip 140 is coupled with the second pin 111B.

[0069] As shown in the example, Figure 4 The packaging structure 100 can include a plurality of second chips 140. The plurality of second chips 140 are arranged on the first packaging layer 130 in a spaced manner. The size of the first chip 120 and the size of the second chip 140 can be combined, for example, the size of the first chip 120 is greater than the size of the second chip 140. The first chip 120 is arranged closer to the substrate 110. After packaging the first chip 120, the first packaging layer 130 has a larger size in the direction parallel to the plane of the substrate 110, which is beneficial to provide a flat surface to arrange the plurality of second chips 140.

[0070] Part of the second chip 140 is coupled with the first pin 111A, and another part of the second chip 140 is coupled with the second pin 111B, which is beneficial to realize that the plurality of second chips 140 are coupled with the first chip 120 on the same group of pins. In this way, based on the size and number of the second chip 140 and the first chip 120, the relative position relationship between the second chip 140 and the first chip 120 can be adjusted, so that the stability of the packaging structure 100 is better.

[0071] It can be understood that a plurality of chips in the same position relationship are named the same name. For example, the "first chip" refers to a type of chip that is covered by the first packaging layer 130 on the substrate 110. The "second chip" refers to a type of chip that is arranged on the surface of the first packaging layer 130 and is covered by the second packaging layer 150 on the substrate 110. The second chip 140 can be arranged in multiple, and the first chip 120 can also be arranged in multiple. The examples provided by the present application do not limit this, and the actual demand can be adjusted.

[0072] In some examples, the second chip 140 is connected to the first packaging layer 130 through a chip bonding film. For example, the chip bonding film can well adapt to various packaging processes. It can be compatible with packaging processes such as plastic packaging, ceramic packaging, etc. During different packaging processes, the chip bonding film will not degrade in performance due to high temperature, chemical reagents and other environmental factors, and can stably play its bonding and protection role.

[0073] In some examples, as shown in the example, Figure 5 The packaging structure 100 further includes a third chip 160 and a third packaging layer 170.

[0074] The third chip 160 is disposed on a side of the second package layer 150 away from the second chip 140 in a stacking direction of the substrate 110 and the first chip 120; and the third chip 160 is coupled with the substrate 110.

[0075] The third package layer 170 is disposed on a side of the third chip 160 away from the second chip 140, and covers the third chip 160 on the substrate 110. The third package layer 170 covers the second package layer 150.

[0076] As shown in the example, Figure 5 The package structure 100 can include a plurality of chips stacked. It can be understood that the plurality of chips in the same positional relationship are named the same name. For example, the "third chip" refers to a type of chip disposed on the surface of the second package layer 150 and covered by the third package layer 170 on the substrate 110. In this way, the number of layers of the package structure 100 can be set, and the number of chips in the same layer can be set, which is beneficial to reduce the size of the package structure 100.

[0077] In some examples, as shown in the example, Figure 6 and Figure 7 The package structure 100 further includes a fourth chip 180 disposed between the first package layer 130 and the first chip 120. The fourth chip 180 is coupled with the substrate 110 through the first chip 120; and the first chip 120 is coupled with the substrate 110 through the first conductive wire 121.

[0078] As shown in the example, Figure 6 The fourth chip 180 is coupled with the first chip 120 through the lead wire 181. Or as shown in the example, Figure 7 The fourth chip 180 is coupled with the first chip 120 through the solder pad. In this way, the fourth chip 180 is directly coupled with the first chip 120, rather than being directly coupled with the pin on the substrate 110 through the first chip, which is beneficial to reduce the size factor affecting the pin on the substrate 110, and reduce the size of the package structure 100 along the plane parallel to the plane where the substrate 110 is located. Moreover, the functions of the first chip 120 and the fourth chip 180 can be combined in terms of relevance, and the first package layer 130 can be directly encapsulated with the stacked first chip 120 and the fourth chip 180, which is beneficial to reduce the stacking thickness of the plurality of chips of the package structure 100.

[0079] Similarly, a fifth chip (not shown in the figure) stacked with the second chip 140 can also be disposed between the second package layer 150 and the first package layer 130, and the fifth chip is coupled with the substrate 110 through the second chip 140. Thus, the size factor affecting the pin on the substrate 110 is reduced, and the size of the package structure 100 along the plane parallel to the plane where the substrate 110 is located is reduced; and the stacking thickness of the plurality of chips of the package structure 100 is reduced.

[0080] In some embodiments, as shown in Figure 8 The embodiments of the present application provide an electronic device 200. The electronic device 200 comprises one or more packaging structures 100 as described in any of the above examples, and a housing 210. The housing 210 encloses the one or more packaging structures 100.

[0081] For example, the electronic device 200 can include, but is not limited to, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having the packaging structure 100 therein.

[0082] In some embodiments, as shown in Figures 9 to 14 The embodiments of the present application provide a method for manufacturing a packaging structure 100.

[0083] As shown in Figure 9 The manufacturing method comprises S100-S500.

[0084] S100: As shown in (a) of Figure 10 A substrate 110 is provided. For example, the substrate 110 can be a layer structure comprising a plurality of layers of dielectric material and conductive material, and a circuit structure.

[0085] S200: As shown in (b) of Figure 10 A first chip 120 is disposed on the substrate 110; the first chip 120 is coupled to the substrate 110. For example, the first chip 120 can be bonded or adhered to the substrate 110.

[0086] S300: As shown in (c) of Figure 10 A first encapsulation layer 130 is formed on a side of the first chip 120 away from the substrate 110; the first encapsulation layer 130 covers the first chip 120. For example, the first encapsulation layer 130 can comprise a plastic encapsulation material.

[0087] S400: As shown in (d) of Figure 10 A second chip 140 is disposed on a side of the first encapsulation layer 130 away from the substrate 110; the second chip 140 is coupled to the substrate 110.

[0088] S500: As shown in (e) of Figure 10As shown in (e), a second encapsulation layer 150 is formed on the side of the second chip 140 away from the first encapsulation layer 130 along the stacking direction of the substrate 110 and the first chip 120. The second encapsulation layer 150 covers the second chip 140 on the substrate 110 to obtain a packaged substrate. The second encapsulation layer 150 covers the first encapsulation layer 130. For example, the second encapsulation layer 150 may include a molding compound.

[0089] For example, such as Figure 1 As shown, the second encapsulation layer 150 encapsulates both the second chip 140 and the first encapsulation layer 130 covering the first chip 120 on the substrate 110.

[0090] The above-described structure employs a first encapsulation layer 130 to cover the first chip 120, a second chip 140 disposed on the first encapsulation layer 130, and a second encapsulation layer 150 to cover the second chip 140 on the substrate 110, achieving a multi-chip encapsulation structure that helps reduce the size of the encapsulation structure 100. Specifically, the second encapsulation layer 150 covers the first encapsulation layer 130, encapsulating the first chip 120 and the second chip 140 into a single structure; rather than using separate encapsulation layers to encapsulate the chips and then stacking the encapsulated chips. Thus, the encapsulation structure 100 implemented in this application improves the robust encapsulation effect of the first chip 120 and the second chip 140; and by encapsulating different stacked chips with different encapsulation layers, different chips can be separated, especially the conductive lines of the stacked chips, facilitating circuit layout design, reducing the manufacturing difficulty of the conductive lines of multiple chips, and reducing interference between the stacked chips (especially, chips transmitting sensitive signals can be isolated to avoid crosstalk with other chips, achieving better performance).

[0091] In some examples, such as Figure 11 As shown, before step S400 above, the method further includes step S310.

[0092] S310: Grind the surface of the first encapsulation layer 130. For example, a chemical mechanical polishing process is used to grind the first encapsulation layer 130, making the surface of the first encapsulation layer 130 away from the first chip 120 flat. This facilitates subsequent bonding of the second chip 140 and improves the bonding stability between the second chip 140 and the first encapsulation layer 130. Furthermore, it can also reduce the thickness of the first encapsulation layer 130, making it easier to adjust the thickness of the first encapsulation layer 130 according to the number of second conductive lines 141 on the second chip 140, thus achieving the effect of not increasing the size of the encapsulation structure 100.

[0093] Continue reading Figure 11 The above step S400 includes S410.

[0094] S410: connect the second chip 140 and the first packaging layer 130 by using a chip bonding film.

[0095] For example, the chip bonding film can avoid the problem of separation of the second chip 140 and the first packaging layer 130 due to performance degradation caused by high temperature, chemical reagents and other environmental factors, and improve the stability of the bonding between the chip and the packaging layer.

[0096] In some examples, as shown in Figure 12 The above step S400 further includes S410.

[0097] S420: form the second conductive wire 141 along the extension direction of the side wall 132 of the first packaging layer 130, and the second conductive wire 141 is coupled to the pin 111 on the substrate 110.

[0098] For example, the second conductive wire 141 can be formed by wire bonding and coupled to the substrate 110. As shown in Figure 2 The angle between the top surface 131 and the side wall 132 of the first packaging layer 130 is obtuse, and the second conductive wire 141 is formed along the extension direction of the side wall 132 of the first packaging layer 130, which can reduce the probability of disconnection of the second conductive wire 141 caused by the sharp end of the angle between the top surface 131 and the side wall 132 of the first packaging layer 130, and improve the yield of the second conductive wire 141.

[0099] In some examples, as shown in Figure 13 The above step S200 includes S210.

[0100] S210: form the first conductive wire 121 coupled to the first chip 120 and the substrate 110. For example, the first conductive wire 121 can be formed by wire bonding.

[0101] Referring back to Figure 13 The above step S300 includes S320.

[0102] S320: based on the number and / or size of the second conductive wire 141 and the number and / or size of the first conductive wire 121, set the thickness and the size L2 parallel to the plane on which the substrate 110 is located of the first packaging layer 130.

[0103] For example, the second chip 140 is coupled to the pin 111 by a plurality of second conductive wires 141, and the number of the second conductive wires 141, the line width of the second conductive wires 141, the spacing between adjacent second conductive wires 141, and the like; similarly, the first chip 120 is coupled to the pin 111 by a plurality of first conductive wires 121, and the number of the first conductive wires 121, the line width of the first conductive wires 121, the spacing between adjacent first conductive wires 121, and the like; the thickness of the first packaging layer 130 and the size L2 of the first packaging layer 130 along the plane parallel to the plane where the substrate 110 is located (as shown in Figure 3

[0104] For example, the second chip 140 is coupled to the pin 111 by a plurality of second conductive wires 141, and the number of the second conductive wires 141, the line width of the second conductive wires 141, the spacing between adjacent second conductive wires 141, and the like; similarly, the first chip 120 is coupled to the pin 111 by a plurality of first conductive wires 121, and the number of the first conductive wires 121, the line width of the first conductive wires 121, the spacing between adjacent first conductive wires 121, and the like; the thickness of the first packaging layer 130 and the size L2 of the first packaging layer 130 along the plane parallel to the plane where the substrate 110 is located (as shown in

[0105] In some examples, as shown in Figure 14 The step S100 includes S110.

[0106] S110: A plurality of groups of pins 111 are arranged on the substrate 110; wherein, based on the number and / or size of the second conductive wires 141, the size L1 of the pin 111 coupled to the second chip 140 along the plane parallel to the plane where the substrate 110 is located is set; and, based on the number and / or size of the first conductive wires 121, the size L1 of the pin 111 coupled to the first chip 120 along the plane parallel to the plane where the substrate 110 is located is set.

[0107] For example, as shown in Figure 3 The first chip 120 is coupled to a group of pins 111, and the second chip 140 is coupled to a group of pins 111. For example, the number of wires required by different pins of the first chip 120 can be different, and the size L1 of different pins 111 can be set to be different according to the number of first conductive wires 121 coupled to different pins 111 on the substrate 110. Similarly, the number of wires required by different pins of the second chip 140 can be different, and the size L1 of different pins 111 can be set to be different according to the number of second conductive wires 141 coupled to different pins 111 on the substrate 110. The examples provided by the present application do not make specific limitations thereon, and can be adjusted according to actual needs. ​

[0108] In another example, the first chip 120 and the second chip 140 can be coupled with the same group of pins 111 on the substrate 110. One end of the pin 111 coupled with both the first chip 120 and the second chip 140 extends into the inside of the first packaging layer 130 and is coupled with the first conductive wire 121 of the first chip 120, and the other end extends along the first packaging layer 130 in the direction of the second packaging layer 150 and is coupled with at least the second conductive wire 141 of the second chip 140 (for example, it can extend outside the second packaging layer 150), so as to facilitate the coupling of the packaging structure 100 with other electronic elements through the target pin 111. For example, according to the number of the first conductive wire 121 and the second conductive wire 141 coupled with different pins 111 on the substrate 110, the size L1 of different pins 111 can be different, and the examples provided in the present application do not make specific limitations thereon, and the actual needs can be adjusted.

[0109] In some examples, as shown in Figure 14 After the above step S500, the method further includes S700.

[0110] S700: cutting the packaged substrate to obtain a plurality of packaging structures 100. One packaging structure 100 in the plurality of packaging structures 100 includes a structure in which the first chip 120 and the second chip 140 are respectively packaged by the first packaging layer 130 and the second packaging layer 150; the size of the packaging structure 100 is similar to the size of the second packaging layer 150 along the plane parallel to the plane where the substrate 110 is located.

[0111] It can be understood that a plurality of packaging structures 100 can be prepared on the substrate, and each packaging structure 100 is an independent structure. The size of the packaging structure 100 along the plane parallel to the plane where the substrate 110 is located can be the size within a predetermined area on the substrate 110. In this way, the effect that the pin 111 provided on the substrate 110 is coupled with both the first chip 120 and the second chip 140 in the packaging structure 100 can be achieved. In this way, the size and thickness of the first packaging layer 130 can be inversely deduced according to the size of the packaging structure 100 along the plane parallel to the plane where the substrate 110 is located; the size L1 of the pin 111 provided on the substrate 110 along the plane parallel to the plane where the substrate 110 is located can be inversely deduced based on the number and size of the first conductive wire 121 of the first chip 120 and the number and size of the second conductive wire 141 of the second chip 140 (see Figure 3 ).

[0112] In an example, the first packaging layer 130 and the second chip 140 wrapped with the first chip 120 are packaged by the second packaging layer 150 to obtain the packaging structure 100. The size of the packaging structure 100 can be predetermined, and based on this, the size of the second packaging layer 150 along the plane parallel to the plane where the substrate 110 is located is similar.

[0113] The thickness of the first encapsulation layer 130, the thickness of the second encapsulation layer 150, and the number of chips in the encapsulation structure 100 can be set as Figure 4 ~As shown in the encapsulation structure 100, the stacking relationship of the plurality of chips and the number of each layer of chips can improve the performance of the encapsulation structure 100 without increasing the size of the encapsulation structure 100, under the condition of meeting the functions of the plurality of chips integrated in the encapsulation structure 100. Figure 7

[0114] Based on the preparation method of the encapsulation structure 100 provided in the above examples, the substrate 110 can also be subjected to local sinking treatment, for example, etching the area where the first chip 120 is arranged to obtain a groove, and the groove depth can be equal to the thickness of the first chip 120. In this way, it is beneficial to reduce the wire bonding risk of the first conductive wire 121 and improve the yield of the first conductive wire 121 during the process of coupling the first chip 120 to the pin 111 on the substrate 110 through the first conductive wire 121.

[0115] In addition, the first conductive wire 121 and the second conductive wire 141 are prepared by wire bonding. The problem of wire bonding arc height of the first conductive wire 121, the distance from the inner side of the top surface of the first encapsulation layer 130 to the surface where the first chip 120 contacts the substrate 110 is the thickness of the first chip 120 (and the thickness of the adhesive between the first chip 120 and the substrate 110), the value of the wire bonding arc height of the first conductive wire 121, and the interval threshold value between the wire bonding arc height of the first conductive wire 121 and the first encapsulation layer 130. The sum of the three. Similarly, after the second chip 140 and the second conductive wire 141 are arranged on the side of the first encapsulation layer 130 away from the substrate 110, a plurality of chips and encapsulation layers can be arranged under the condition of meeting the thickness requirement of the encapsulation structure 100. The examples provided in the present application do not limit this.

[0116] The above is only an embodiment of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.​

Claims

1. A package structure, characterized by, The package structure comprises: a substrate; a first chip disposed on one side of the substrate; the first chip is coupled with the substrate; a first encapsulation layer disposed on a side of the first chip away from the substrate and covering the first chip; a second chip disposed on a side of the first encapsulation layer away from the first chip along a stacking direction of the substrate and the first chip; the second chip is coupled with the substrate; a second encapsulation layer disposed on a side of the second chip away from the first encapsulation layer along the stacking direction of the substrate and the first chip and covering the second chip on the substrate; wherein the second encapsulation layer covers the first encapsulation layer.

2. The package structure of claim 1, wherein, The first chip is coupled with the substrate through a first conductive line; the first encapsulation layer covers the first conductive line. The second chip is coupled with the substrate through a second conductive line; the second conductive line is located between the first encapsulation layer and the second encapsulation layer.

3. The package structure of claim 2, wherein, The first encapsulation layer comprises a top surface located on a side of the first chip away from the substrate and a side wall extending from an edge of the top surface to the substrate and surrounding the first chip; an included angle between the top surface and the side wall is obtuse.

4. The package structure of claim 2, wherein, The substrate comprises a plurality of pins; the first chip is coupled with a group of the pins; the second chip is coupled with a group of the pins; The pins coupled with the first chip along a dimension parallel to a plane where the substrate is located are related to a number and / or a dimension of the first conductive lines of the first chip; the pins coupled with the second chip along a dimension parallel to the plane where the substrate is located are related to a number and / or a dimension of the second conductive lines of the second chip; The thickness and the dimension parallel to the plane where the substrate is located of the first encapsulation layer are related to the number and / or the dimension of the first conductive lines of the first chip and the number and / or the dimension of the second conductive lines of the second chip.

5. The package structure of claim 4, wherein, A plurality of the second chips are spaced apart on a side of the first encapsulation layer away from the first chip; The pins coupled with the first chip comprise first pins and second pins; part of the second chips are coupled with the first pins and another part of the second chips are coupled with the second pins.

6. The package structure of claim 1, wherein, The second chip is connected with the first encapsulation layer through a chip bonding film.

7. The package structure of claim 1, wherein, The package structure further comprises: a third chip disposed on a side of the second encapsulation layer away from the second chip along the stacking direction of the substrate and the first chip; the third chip is coupled with the substrate; a third encapsulation layer disposed on a side of the third chip away from the third chip and covering the third chip on the substrate; The third encapsulation layer covers the second encapsulation layer.

8. The package structure of claim 1, wherein, The package structure further comprises a fourth chip disposed between the first encapsulation layer and the first chip; The fourth chip is coupled with the substrate through the first chip; wherein the first chip is coupled with the substrate through a first conductive line.

9. An electronic device, comprising: The package structure comprises: one or more package structures according to any one of claims 1-8; a housing surrounding the one or more package structures.

10. A method for preparing a packaging structure, characterized in that, The package structure comprises: providing a substrate; disposing a first chip on the substrate; The first chip is coupled with the substrate; A first encapsulation layer is formed on a side of the first chip away from the substrate; The first encapsulation layer covers the first chip; A second chip is arranged on a side of the first encapsulation layer away from the substrate; the second chip is coupled with the substrate; A second encapsulation layer is formed on a side of the second chip away from the first encapsulation layer along a stacking direction of the substrate and the first chip, the second encapsulation layer covers the second chip on the substrate to obtain an encapsulated substrate; and the second encapsulation layer covers the first encapsulation layer.

11. The method of claim 10, wherein, Before the second chip is arranged on the side of the first encapsulation layer away from the substrate, the method further comprises: Grinding a surface of the first encapsulation layer; The second chip is arranged on the side of the first encapsulation layer away from the substrate, comprising: The second chip is connected with the first encapsulation layer by using a chip bonding film.

12. The method of claim 11, wherein, The second chip is arranged on the side of the first encapsulation layer away from the substrate, further comprising: A second conductive wire is formed along an extension direction of a sidewall of the first encapsulation layer, the second conductive wire is coupled with a pin on the substrate.

13. The method of claim 12, wherein, The first chip is arranged on the substrate, comprising: A first conductive wire coupled with the first chip and the substrate is formed; The first encapsulation layer is formed on the side of the first chip away from the substrate, comprising: Based on the number and / or size of the second conductive wire and the number and / or size of the first conductive wire, the thickness and the size parallel to the plane where the substrate is located of the first encapsulation layer are set.

14. The method of claim 13, wherein, The substrate is provided, comprising: A plurality of pins are arranged on the substrate; wherein, based on the number and / or size of the second conductive wire, the size parallel to the plane where the substrate is located of the pin coupled with the second chip is set; and, based on the number and / or size of the first conductive wire, the size parallel to the plane where the substrate is located of the pin coupled with the first chip is set.

15. The preparation method according to claim 10, characterized in that, The method further comprises: The encapsulated substrate is cut to obtain a plurality of encapsulation structures; one encapsulation structure in the plurality of encapsulation structures comprises a structure in which the first chip and the second chip are encapsulated by the first encapsulation layer and the second encapsulation layer respectively; and the size of the encapsulation structure is close to the size parallel to the plane where the substrate is located of the second encapsulation layer.

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