Power device and method of manufacturing the same

Abstract

The application provides a power device and a preparation method thereof, which comprises the following steps: forming a P-type layer and an N-type layer on an N-type substrate; forming a groove; ion implantation to form an N-type source region; forming a gate oxide layer in the groove; forming a first polysilicon layer, a thick oxide layer and a second polysilicon layer in the groove; depositing a dielectric layer; forming a source contact region, the source contact region exposing part of the N-type source region and part of the P-type layer; forming an insulating layer; forming a gate contact region, the gate contact region extending into the first polysilicon layer; forming a drain contact region, the drain contact region exposing the N-type layer; forming a source electrode, a gate electrode and a drain electrode, the source electrode being in contact with the N-type source region and the P-type epitaxial layer at the same time. The application can simultaneously mount the source electrode, the gate electrode and the drain electrode to a heat dissipation substrate, greatly optimizes the heat dissipation path and reduces the source path inductance; the connection between the P-type layer and the N-type source region is formed in the device through the groove, which can effectively simplify the process, avoid additional lead-out process and effectively save the manufacturing cost.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit design and manufacturing, and in particular relates to a power device and its fabrication method. Background Technology

[0002] In traditional vertical power MOSFET structures, the drain is typically fabricated on the back side of the semiconductor wafer, while the source and gate are fabricated on the front side. While this structure is mature, it has limitations in high-frequency, high-power-density applications: 1) A single back-side drain for heat dissipation cannot meet the heat dissipation requirements of high-power-density applications; 2) The source needs to be wire-bonded, which introduces significant parasitic inductance, leading to severe voltage overshoot and switching losses during switching.

[0003] To overcome these problems, the industry has proposed "source-down" packaging technology. One key implementation method is to place the source, gate, and drain electrodes on the same plane, which facilitates package interconnection and heat dissipation. However, how to bring out the electrodes inside the device structure without sacrificing the device's electrical performance (such as on-resistance and breakdown voltage), and ensure the feasibility and reliability of manufacturing, remains a challenge for current technology.

[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a power device and its fabrication method, which solves the problem that the source-facing packaging method in the prior art is difficult to achieve the lead-out of each electrode inside the device structure while ensuring the feasibility and reliability of manufacturing.

[0006] To achieve the above and other related objectives, the present invention provides a method for fabricating a power device. The method includes: providing an N-type substrate; forming a P-type layer and an N-type layer on the N-type substrate; etching to form a trench, the trench penetrating the N-type layer and extending into the P-type layer; forming a barrier layer in the trench that partially blocks the P-type layer; forming an N-type source region below the trench by ion implantation, the N-type source region extending from the lower part of the trench into the N-type substrate; removing the barrier layer; forming a gate oxide layer in the trench; forming a gate stack structure of a first polysilicon layer, a thick oxide layer, and a second polysilicon layer in the trench, the thick oxide layer also forming a sidewall between the second polysilicon layer and the trench; and depositing a layer on the N-type layer. A dielectric layer is deposited; in a first region, the dielectric layer and gate stack structure are etched to form a source contact region, exposing a portion of the N-type source region and a portion of the P-type layer; an insulating layer is formed on the sidewalls of the gate stack structure in the source contact region; in a second region, the dielectric layer and gate stack structure are etched to form a gate contact region, which penetrates the second polysilicon layer and the thick oxide layer and extends into the first polysilicon layer; in a third region, the dielectric layer is etched to remove the drain contact region, exposing the N-type layer; a metal layer is deposited on the dielectric layer and in the source, gate, and drain contact regions, and the metal layer is patterned to form the source, gate, and drain, respectively, with the source simultaneously contacting the N-type source region and the P-type epitaxial layer.

[0007] Optionally, forming a P-type layer and an N-type layer on an N-type substrate includes: growing a P-type epitaxial layer on an N-type substrate by an epitaxial process; and growing an N-type epitaxial layer on a P-type epitaxial layer by an epitaxial process.

[0008] Optionally, the resistivity of the P-type epitaxial layer is 0.1 ohm·cm to 0.4 ohm·cm, and the thickness is 0.2 μm to 1.5 μm; the resistivity of the N-type epitaxial layer is 0.1 ohm·cm to 10 ohm·cm, and the thickness is 0.5 μm to 10 μm.

[0009] Optionally, the trench depth is 1.5μm~12μm, the distance between the bottom of the trench and the N-type substrate is 0.1μm~0.6μm, and the trench width is 0.8μm~6μm.

[0010] Optionally, the N-type source region extends from the bottom surface and part of the side surface of the trench into the N-type substrate. The N-type source region is formed by implanting N-type ions into the bottom of the trench to at least invert the P-type epitaxial layer below the trench into an N-type source region. The N-type ions are phosphorus or arsenic, the ion implantation energy is 20 keV to 800 keV, and the ion implantation dose is 1e12cm. -2 ~1e16cm -2 .

[0011] Optionally, forming the gate stack structure includes: filling a trench with a first polysilicon layer and etching the first polysilicon layer to a depth within the trench to expose the top of the trench, wherein the top surface of the etched first polysilicon layer is higher than the interface between the N-type layer and the P-type layer; forming a thick oxide layer on the surface of the first polysilicon layer and the top sidewall of the trench; depositing a second polysilicon layer on the top of the trench and planarizing the second polysilicon layer to remove the second polysilicon layer on the surface of the N-type layer.

[0012] Optionally, the thickness of the gate oxide layer is 100 Å to 1200 Å, the thickness of the thick oxide layer is 700 Å to 2000 Å, and the top surface of the first polysilicon layer is 0.1 μm to 1 μm higher than the interface between the N-type layer and the P-type layer.

[0013] Optionally, the depth of the gate contact region extending into the first polysilicon layer is 0 μm to 0.5 μm.

[0014] Optionally, the thickness of the metal layer is 0.5μm to 8μm, and the top surface heights of the source, gate, and drain are the same.

[0015] Optionally, the width of the P-type layer exposed in the source contact region is 0.1 μm to 20 μm, and the width of the N-type source region exposed in the source contact region is 0.1 μm to 20 μm.

[0016] Optionally, the height difference between the upper surface of the second polysilicon layer and the surface of the N-type epitaxial layer is 0 μm to 0.2 μm.

[0017] The present invention also provides a power device, comprising: an N-type substrate on which a P-type layer and an N-type layer are formed; a trench extending through the N-type layer and into the P-type layer; an N-type source region formed below a portion of the trench, extending from the lower part of the trench into the N-type substrate, wherein a P-type layer adjacent to the N-type source region is also retained below the trench; a gate oxide layer formed in the trench; a gate stack structure formed in the trench, the gate stack structure comprising a first polysilicon layer, a thick oxide layer, and a second polysilicon layer, wherein the thick oxide layer is also formed on a sidewall between the second polysilicon layer and the trench; and a dielectric layer formed on the N-type layer. The source contact region is formed by etching the dielectric layer and gate stack structure of the first region, exposing part of the N-type source region and part of the P-type layer; an insulating layer is formed on the sidewall of the gate stack structure of the source contact region; the gate contact region is formed by etching the dielectric layer and gate stack structure of the second region, penetrating the second polysilicon layer and the thick oxide layer and extending into the first polysilicon layer; the drain contact region is formed by etching the dielectric layer of the third region, exposing the N-type layer; the source, gate, and drain are formed in the source contact region, gate contact region, and drain contact region, respectively, with the source simultaneously contacting the N-type source region and the P-type epitaxial layer.

[0018] Optionally, the P-type layer and the N-type layer are respectively a P-type epitaxial layer and an N-type epitaxial layer. The resistivity of the P-type epitaxial layer is 0.1 ohm·cm to 0.4 ohm·cm and the thickness is 0.2 μm to 1.5 μm. The resistivity of the N-type epitaxial layer is 0.1 ohm·cm to 10 ohm·cm and the thickness is 0.5 μm to 10 μm.

[0019] Optionally, the thickness of the gate oxide layer is 100 Å to 1200 Å, the thickness of the thick oxide layer is 700 Å to 2000 Å, and the top surface of the first polysilicon layer is 0.1 μm to 1 μm higher than the interface between the N-type layer and the P-type layer.

[0020] Optionally, the thickness of the source, gate, and drain is 0.5μm to 8μm, and the top surface height of the source, gate, and drain is the same.

[0021] Optionally, the width of the P-type layer exposed in the source contact region is 0.1 μm to 20 μm, and the width of the N-type source region exposed in the source contact region is 0.1 μm to 20 μm.

[0022] As described above, the power device and its fabrication method of the present invention have the following beneficial effects:

[0023] Unlike traditional methods that form P-type bulk regions through ion implantation, this invention forms P-type layers through epitaxial growth. Epitaxial growth allows for precise control over the thickness, doping concentration, and uniformity of the P-type layer, while avoiding lattice damage and defects that may be caused by high-energy ion implantation. This results in a more uniform and reliable bulk region, which is beneficial for improving the breakdown voltage and avalanche tolerance of the device, and enhancing the long-term reliability and consistency of the device.

[0024] This invention achieves a co-planar layout of the source, gate, and drain by etching and filling a specific area with metal, directly connecting from the front side of the device downwards to the N-type source region. Firstly, this invention eliminates the need for back-side grinding and metallization processes, simplifying the packaging process. Secondly, by implementing a "source-down" packaging structure, the source, gate, and drain can be simultaneously mounted to a heat dissipation substrate, greatly optimizing the heat dissipation path and reducing source path inductance. Thirdly, the connection between the P-type layer (body region) and the N-type source region is formed inside the device through trenches, effectively simplifying the process, avoiding additional lead-out processes, and significantly reducing manufacturing costs.

[0025] This invention employs a two-layer shielding gate structure, connecting the first and second polysilicon layers simultaneously through a contact hole. The first polysilicon layer connected to the lower layer serves as a control gate, enabling faster control of the switching of power devices. When the device is turned on, the second polysilicon layer can accumulate charge carriers on the surface of the thick oxide layer to reduce the on-resistance of the device. During reverse voltage withstand, it can adjust the depletion and field strength distribution in the N-type layer, thereby improving the voltage withstand capability of the device. Attached Figure Description

[0026] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.

[0027] Figure 1 The diagram shown is a schematic representation of the surface layout structure of a power device according to an embodiment of the present invention.

[0028] Figures 2-14 The diagrams shown below illustrate the structural features of each step in the fabrication method of the power device according to an embodiment of the present invention. Figure 14 The diagram shown is a structural schematic of a power device according to an embodiment of the present invention.

[0029] Component labeling description: N-type substrate 101, P-type layer 102, N-type layer 103, trench 104, barrier layer 105, N-type source region 106, gate oxide layer 107, first polysilicon layer 108, thick oxide layer 109, second polysilicon layer 110, dielectric layer 111, source contact region 112, insulating layer 113, gate contact region 114, drain contact region 115, source 116, gate 117, drain 118. Detailed Implementation

[0030] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0031] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0032] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0033] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0034] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0035] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0036] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0037] like Figures 1-14 As shown, where, Figure 1 The diagram shows the surface layout of the power device. Figures 2-14 The figures shown are schematic diagrams of the cross-sectional structures at sections A-A', B-B', and C-C', respectively. This embodiment provides a method for fabricating a power device, the method comprising:

[0038] like Figure 2 As shown, step 1) is performed first, an N-type substrate 101 is provided, and a P-type layer 102 and an N-type layer 103 are formed on the N-type substrate 101.

[0039] In one embodiment, the N-type substrate 101 can be a heavily doped N-type silicon substrate with a resistivity of less than 0.01 ohm·cm.

[0040] In one embodiment, forming a P-type layer 102 and an N-type layer 103 on an N-type substrate 101 includes the following steps:

[0041] Step 1-1): A P-type epitaxial layer is grown on an N-type substrate 101 using an epitaxial process. The dopant can be boron (B). The resistivity of the P-type epitaxial layer is 0.1 ohm·cm to 0.4 ohm·cm, for example, 0.1 ohm·cm, 0.2 ohm·cm, 0.3 ohm·cm, or 0.4 ohm·cm, and the thickness is 0.2 μm to 1.5 μm, for example, 0.2 μm, 0.5 μm, 1.0 μm, or 1.5 μm. Unlike the traditional method of forming a P-type bulk region through ion implantation, this invention forms the P-type layer 102 through epitaxial growth. Epitaxial growth allows for precise control of the thickness, doping concentration, and uniformity of the P-type layer 102, while avoiding lattice damage and defects that may be caused by high-energy ion implantation. This results in a more uniform and reliable bulk region, which is beneficial for improving the breakdown voltage and avalanche tolerance of the device, and enhancing the long-term reliability and consistency of the device.

[0042] Steps 1-2) involve growing an N-type epitaxial layer on a P-type epitaxial layer using an epitaxial process, where the dopant can be phosphorus (P) or arsenic (As).

[0043] In one embodiment, the resistivity of the N-type epitaxial layer is 0.1 ohm·cm to 10 ohm·cm, for example, it can be 0.1 ohm·cm, 1 ohm·cm, 5 ohm·cm or 10 ohm·cm, and the thickness is 0.5 μm to 10 μm, for example, it can be 0.5 μm, 2 μm, 5 μm or 10 μm.

[0044] like Figure 3 As shown, then step 2) is performed to etch and form trench 104, which penetrates the N-type layer 103 and extends into the P-type layer 102.

[0045] In one embodiment, the depth of the trench 104 is 1.5 μm to 12 μm, and the depth of the trench 104 can be, for example, 2 μm, 5 μm, 8 μm or 12 μm. The distance between the bottom of the trench 104 and the N-type substrate 101 is 0.1 μm to 0.6 μm, for example, 0.1 μm, 0.3 μm, 0.5 μm, 0.6 μm, etc. The width of the trench 104 is 0.8 μm to 6 μm, for example, 0.8 μm, 2 μm, 4 μm, 6 μm, etc.

[0046] like Figures 4-5 As shown, then step 3) is performed, forming a barrier layer 105 in the trench 104 to block the P-type layer 102, and forming an N-type source region 106 below the trench 104 by ion implantation. The N-type source region 106 extends from the lower part of the trench 104 into the N-type substrate 101, and the barrier layer 105 is removed.

[0047] In one embodiment, forming a barrier layer 105 in the trench 104 to block a portion of the P-type layer 102 includes: fabricating photoresist by spin coating, and then forming a patterned photoresist layer by exposure and development processes to serve as the barrier layer 105.

[0048] In one embodiment, the N-type source region 106 extends from the bottom surface and part of the side surface of the trench 104 into the N-type substrate 101. The N-type source region 106 is formed by implanting N-type ions (e.g., phosphorus, arsenic, etc.) into the bottom of the trench 104 to at least invert the P-type epitaxial layer below the trench 104 into the N-type source region 106. The N-type ions are phosphorus or arsenic, the ion implantation energy is 20 keV to 800 keV, and the ion implantation dose is 1e12cm. -2 ~1e16cm -2 .

[0049] like Figure 6 As shown, then step 4) is performed to form a gate oxide layer 107 in the trench 104 by means of thermal oxidation, atomic layer deposition or plasma-enhanced chemical vapor deposition; in some embodiments, the thickness of the gate oxide layer 107 is 100 Å to 1200 Å, for example, it can be 100 Å, 300 Å, 500 Å, 800 Å, 1200 Å, etc.

[0050] like Figures 7-9 As shown, step 5 is then performed, forming a gate stack structure of a first polysilicon layer 108, a thick oxide layer 109, and a second polysilicon layer 110 in the trench 104. The thick oxide layer 109 is also formed on the sidewall between the second polysilicon layer 110 and the trench 104.

[0051] In one embodiment, forming the gate stack structure includes:

[0052] A first polysilicon layer 108 is filled into the trench 104 and etched to a depth within the trench 104 to expose the top of the trench 104. The top surface of the etched first polysilicon layer 108 is higher than the interface between the N-type layer 103 and the P-type layer 102 to form a gate 117 structure, so that the first polysilicon layer 108 can control the formation of a continuous channel when a suitable voltage is applied. For example, the top surface of the etched first polysilicon layer 108 is 0.1 μm to 1 μm higher than the interface between the N-type layer 103 and the P-type layer 102, for example, it can be 0.1 μm, 0.3 μm, 0.5 μm, 1 μm, etc.

[0053] A thick oxide layer 109 is formed on the surface of the first polysilicon layer 108 and the top sidewall of the trench 104 by means of thermal oxidation process, plasma-enhanced chemical vapor deposition process, etc.; in one embodiment, the thickness of the thick oxide layer 109 is 700 Å to 2000 Å, for example, it can be 700 Å, 1000 Å, 1500 Å, 2000 Å, etc.

[0054] A second polysilicon layer 110 is deposited on top of the trench 104, and the second polysilicon layer 110 is planarized to remove the second polysilicon layer 110 from the surface of the N-type layer 103. In one embodiment, the height difference between the upper surface of the second polysilicon layer 110 and the surface of the N-type epitaxial layer is 0 μm to 0.2 μm.

[0055] like Figure 10 As shown, then step 6) is performed to deposit a dielectric layer on the N-type layer 103; for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a stack of the above materials can be deposited on the N-type layer 103 as a dielectric layer using a process such as plasma-enhanced chemical vapor deposition.

[0056] like Figure 10 As shown, step 7) is then performed, etching the dielectric layer and gate stack structure in the first region to form source contact region 112, which exposes a portion of the N-type source region 106 and a portion of the P-type layer 102.

[0057] In one embodiment, the width of the P-type layer 102 exposed by the source contact region 112 is 0.1μm to 20μm, for example, it can be 0.1μm, 5μm, 10μm, 20μm, etc., and the width of the N-type source region 106 exposed by the source contact region 112 is 0.1μm to 20μm, for example, it can be 0.1μm, 5μm, 10μm, 20μm, etc.

[0058] like Figure 11 As shown, then step 8) is performed to form an insulating layer 113 on the sidewall of the gate stack structure in the source contact region 112.

[0059] For example, an insulating layer 113 can be formed on the sidewalls and bottom of the gate stack structure in the source contact region 112 by thermal oxidation or plasma-enhanced chemical vapor deposition. Then, the bottom insulating layer 113 can be removed by etching to expose the N-type source region 106 and part of the P-type layer 102.

[0060] like Figure 12 As shown, step 9) is then performed, etching the dielectric layer and gate stack structure in the second region to form a gate contact region 114, which penetrates the second polysilicon layer 110 and the thick oxide layer 109 and extends into the first polysilicon layer 108.

[0061] In one embodiment, the depth of the gate contact region 114 extending into the first polysilicon layer 108 is 0 μm to 0.5 μm, for example, it can be 0 μm, 0.1 μm, 0.2 μm, 0.5 μm, etc. This invention employs a two-layer shielded gate structure, connecting the first polysilicon layer 108 and the second polysilicon layer 110 simultaneously through a contact hole. The first polysilicon layer 108, connected to the lower layer, serves as a control gate, enabling faster control of the power device's switching. When the device is turned on, the second polysilicon layer 110 can accumulate charge carriers on the surface of the thick oxide layer 109 to reduce the device's on-resistance. During reverse voltage withstand, it can adjust the depletion and field strength distribution in the N-type layer 103, thereby improving the device's withstand voltage capability.

[0062] like Figure 13 As shown, then step 10) is performed, etching away the dielectric layer in the third region to form a drain contact region 115, which exposes the N-type layer 103.

[0063] like Figure 14 As shown, in step 11), a metal layer is deposited on the dielectric layer and in the source contact region 112, gate contact region 114, and drain contact region 115. The metal layer is patterned to form the source 116, gate 117, and drain 118, respectively. The source 116 is simultaneously in contact with the N-type source region 106 and the P-type epitaxial layer. This invention achieves a co-planar layout of the source 116, gate 117, and drain 118 by etching and filling metal in a specific area, directly connecting from the front side of the device downwards to the N-type source region 106. On the one hand, the present invention can eliminate the back-side grinding and metallization process, simplifying the packaging process; on the other hand, by realizing the "source 116 facing down" packaging structure, the present invention can simultaneously mount the source 116, gate 117, and drain 118 to the heat dissipation substrate, greatly optimizing the heat dissipation path and reducing the inductance of the source 116 path; thirdly, the connection between the P-type layer 102 (body region) and the N-type source region 106 is formed inside the device through the trench 104, which can effectively simplify the process, avoid additional lead-out processes, and effectively save manufacturing costs.

[0064] In one embodiment, the thickness of the metal layer is 0.5μm to 8μm. For example, the thickness of the metal layer can be 0.5μm, 1μm, 2μm, 5μm, 8μm, etc., and the top surface heights of the source 116, gate 117 and drain 118 are the same.

[0065] like Figure 1 and Figure 14As shown, this embodiment also provides a power device, which can be fabricated by the power device fabrication method of the above embodiments. The power device includes: an N-type substrate 101, on which a P-type layer 102 and an N-type layer 103 are formed; a trench 104, which penetrates the N-type layer 103 and extends into the P-type layer 102; an N-type source region 106, formed below a portion of the trench 104, extending from the lower part of the trench 104 into the N-type substrate 101, and a P-type layer 102 adjacent to the N-type source region 106 is also retained below the trench 104; a gate oxide layer 107, formed in the trench 104; and a gate stack structure, formed in the trench 104, the gate stack structure including a first polysilicon layer 108, a thick oxide layer 109, and a second polysilicon layer 110, wherein the thick oxide layer 109 is also formed on the side between the second polysilicon layer 110 and the trench 104. The structure includes: a wall; a dielectric layer 111 formed on an N-type layer 103; a source contact region 112 formed by etching the dielectric layer 111 and the gate stack structure in the first region, exposing a portion of the N-type source region 106 and a portion of the P-type layer 102; an insulating layer 113 formed on the sidewall of the gate stack structure in the source contact region 112; a gate contact region 114 formed by etching the dielectric layer 111 and the gate stack structure in the second region, penetrating the second polysilicon layer 110 and the thick oxide layer 109 and extending into the first polysilicon layer 108; a drain contact region 115 formed by etching the dielectric layer in the third region, exposing the N-type layer 103; a source electrode 116, a gate electrode 117, and a drain electrode 118 formed in the source contact region 112, the gate contact region 114, and the drain contact region 115, respectively, with the source electrode 116 simultaneously contacting the N-type source region 106 and the P-type epitaxial layer.

[0066] In one embodiment, the P-type layer 102 and the N-type layer 103 are a P-type epitaxial layer and an N-type epitaxial layer, respectively. The resistivity of the P-type epitaxial layer is 0.1 ohm·cm to 0.4 ohm·cm, and the thickness is 0.2 μm to 1.5 μm. The resistivity of the N-type epitaxial layer is 0.1 ohm·cm to 10 ohm·cm, and the thickness is 0.5 μm to 10 μm.

[0067] In one embodiment, the thickness of the gate oxide layer 107 is 100 Å to 1200 Å, the thickness of the thick oxide layer 109 is 700 Å to 2000 Å, and the top surface of the first polysilicon layer 108 is 0.1 μm to 1 μm higher than the interface between the N-type layer 103 and the P-type layer 102.

[0068] In one embodiment, the thickness of the source 116, gate 117, and drain 118 is 0.5μm to 8μm, and the top surface heights of the source 116, gate 117, and drain 118 are the same.

[0069] In one embodiment, the width of the P-type layer 102 exposed by the source contact region 112 is 0.1 μm to 20 μm, and the width of the N-type source region 106 exposed by the source contact region 112 is 0.1 μm to 20 μm.

[0070] As described above, the power device and its fabrication method of the present invention have the following beneficial effects:

[0071] Unlike traditional methods that form P-type bulk regions through ion implantation, this invention forms the P-type layer 102 through epitaxial growth. Epitaxial growth allows for precise control over the thickness, doping concentration, and uniformity of the P-type layer 102, while avoiding lattice damage and defects that may be caused by high-energy ion implantation. This results in a more uniform and reliable bulk region, which is beneficial for improving the breakdown voltage and avalanche tolerance of the device, and enhancing the long-term reliability and consistency of the device.

[0072] This invention achieves a co-planar layout of the source 116, gate 117, and drain 118 by etching and filling a specific area with metal, directly connecting from the front side of the device downwards to the N-type source region 106. Firstly, this invention eliminates the need for back-side grinding and metallization processes, simplifying the packaging process. Secondly, by implementing a "source 116 facing down" packaging structure, the source 116, gate 117, and drain 118 can be simultaneously mounted to a heat dissipation substrate, greatly optimizing the heat dissipation path and reducing the inductance of the source 116 path. Thirdly, the connection between the P-type layer 102 (body region) and the N-type source region 106 is formed inside the device through trenches 104, effectively simplifying the process, avoiding additional lead-out processes, and effectively saving manufacturing costs.

[0073] This invention employs a two-layer shielding gate structure, and connects the first polysilicon layer 108 and the second polysilicon layer 110 simultaneously through a contact hole. The first polysilicon layer 108 connected to the lower layer serves as a control gate, enabling faster control of the switching of power devices. When the device is turned on, the second polysilicon layer 110 can accumulate charge carriers on the surface of the thick oxide layer 109 to reduce the on-resistance of the device. During reverse voltage withstand, it can adjust the depletion and field strength distribution in the N-type layer 103, thereby improving the voltage withstand capability of the device.

[0074] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0075] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a power device, characterized in that, The preparation method includes: An N-type substrate is provided, on which a P-type layer and an N-type layer are formed; Trenches are formed by etching, the trenches penetrating the N-type layer and extending into the P-type layer; A barrier layer is formed in the trench to block a portion of the P-type layer. An N-type source region is formed below the trench by ion implantation. The N-type source region extends from the lower part of the trench into the N-type substrate. The barrier layer is then removed. A gate oxide layer is formed in the trench; A gate stack structure consisting of a first polysilicon layer, a thick oxide layer, and a second polysilicon layer is formed in the trench, and the thick oxide layer is also formed on the sidewall between the second polysilicon layer and the trench. A dielectric layer is deposited on the N-type layer; The dielectric layer and the gate stack structure are etched in a first region to form a source contact region, the source contact region exposing a portion of the N-type source region and a portion of the P-type layer; An insulating layer is formed on the sidewall of the gate stack structure in the source contact region; The dielectric layer and the gate stack structure are etched in the second region to form a gate contact region, which penetrates the second polysilicon layer and the thick oxide layer and extends into the first polysilicon layer. The dielectric layer is etched away in the third region to form a drain contact region, which exposes the N-type layer. A metal layer is deposited on the dielectric layer and in the source contact region, gate contact region and drain contact region. The metal layer is patterned to form the source, gate and drain respectively. The source is in contact with both the N-type source region and the P-type layer.

2. The method for fabricating a power device according to claim 1, characterized in that: Forming a P-type layer and an N-type layer on the N-type substrate includes: A P-type epitaxial layer is grown on the N-type substrate using an epitaxial process. An N-type epitaxial layer is grown on the P-type epitaxial layer using an epitaxial process.

3. The method for fabricating the power device according to claim 2, characterized in that: The resistivity of the P-type epitaxial layer is 0.1 ohm·cm to 0.4 ohm·cm, and the thickness is 0.2 μm to 1.5 μm. The resistivity of the N-type epitaxial layer is 0.1 ohm·cm to 10 ohm·cm, and the thickness is 0.5 μm to 10 μm.

4. The method for fabricating a power device according to claim 1, characterized in that: The trench has a depth of 1.5μm to 12μm, a distance of 0.1μm to 0.6μm between the bottom of the trench and the N-type substrate, and a width of 0.8μm to 6μm.

5. The method for fabricating a power device according to claim 1, characterized in that: The N-type source region extends from the bottom and part of the side of the trench into the N-type substrate. The N-type source region is formed by implanting N-type ions into the bottom of the trench to at least invert the P-type epitaxial layer below the trench into an N-type source region. The N-type ions are phosphorus or arsenic, the ion implantation energy is 20 keV to 800 keV, and the ion implantation dose is 1e12cm. -2 ~1e16cm -2 .

6. The method for fabricating a power device according to claim 1, characterized in that: The formation of the gate stack structure includes: The trench is filled with a first polysilicon layer and the first polysilicon layer is etched to a depth within the trench to expose the top of the trench. The top surface of the etched first polysilicon layer is higher than the interface between the N-type layer and the P-type layer. A thick oxide layer is formed on the surface of the first polysilicon layer and on the top sidewall of the trench; A second polysilicon layer is deposited on top of the trench, and the second polysilicon layer is planarized to remove the second polysilicon layer from the surface of the N-type layer.

7. The method for fabricating a power device according to claim 1, characterized in that: The thickness of the gate oxide layer is 100 Å to 1200 Å, the thickness of the thick oxide layer is 700 Å to 2000 Å, and the top surface of the first polysilicon layer is 0.1 μm to 1 μm higher than the interface between the N-type layer and the P-type layer.

8. The method for fabricating a power device according to claim 1, characterized in that: The depth of the gate contact area extending into the first polysilicon layer is 0 μm to 0.5 μm.

9. The method for fabricating a power device according to claim 1, characterized in that: The thickness of the metal layer is 0.5μm to 8μm, and the top surfaces of the source, gate, and drain are at the same height.

10. The method for fabricating a power device according to claim 1, characterized in that: The width of the P-type layer exposed in the source contact region is 0.1 μm to 20 μm, and the width of the N-type source region exposed in the source contact region is 0.1 μm to 20 μm.

11. The method for fabricating a power device according to claim 1, characterized in that: The height difference between the upper surface of the second polycrystalline silicon layer and the surface of the N-type layer is 0 μm ~ 0.2 μm.

12. A power device, characterized in that, The power device includes: An N-type substrate, wherein a P-type layer and an N-type layer are formed on the N-type substrate; The trench penetrates the N-type layer and extends into the P-type layer; An N-type source region is formed below a portion of the trench, the N-type source region extending from the lower part of the trench into the N-type substrate, and a P-type layer adjacent to the N-type source region is also retained below the trench; A gate oxide layer is formed in the trench; A gate stack structure is formed in the trench, the gate stack structure including a first polysilicon layer, a thick oxide layer and a second polysilicon layer, the thick oxide layer also being formed on the sidewall between the second polysilicon layer and the trench; A dielectric layer is formed on the N-type layer; The source contact region is formed by etching the dielectric layer and the gate stack structure of the first region, and the source contact region exposes part of the N-type source region and part of the P-type layer; An insulating layer is formed on the sidewall of the gate stack structure in the source contact region; The gate contact region is formed by etching the dielectric layer and the gate stack structure of the second region. The gate contact region penetrates the second polysilicon layer and the thick oxide layer and extends into the first polysilicon layer. The drain contact region is formed by etching the dielectric layer of the third region, and the drain contact region exposes the N-type layer; The source, gate, and drain are formed in the source contact region, gate contact region, and drain contact region, respectively, and the source is in contact with both the N-type source region and the P-type layer.

13. The power device according to claim 12, characterized in that: The P-type layer and N-type layer are respectively a P-type epitaxial layer and an N-type epitaxial layer. The resistivity of the P-type epitaxial layer is 0.1 ohm·cm to 0.4 ohm·cm and the thickness is 0.2 μm to 1.5 μm. The resistivity of the N-type epitaxial layer is 0.1 ohm·cm to 10 ohm·cm and the thickness is 0.5 μm to 10 μm.

14. The power device according to claim 12, characterized in that: The thickness of the gate oxide layer is 100 Å to 1200 Å, the thickness of the thick oxide layer is 700 Å to 2000 Å, and the top surface of the first polysilicon layer is 0.1 μm to 1 μm higher than the interface between the N-type layer and the P-type layer.

15. The power device according to claim 12, characterized in that: The thickness of the source, gate, and drain is 0.5μm to 8μm, and the top surface height of the source, gate, and drain is the same.

16. The power device according to claim 12, characterized in that: The width of the P-type layer exposed in the source contact region is 0.1 μm to 20 μm, and the width of the N-type source region exposed in the source contact region is 0.1 μm to 20 μm.

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