Display panel

Abstract

The invention relates to a display panel. Wherein the anode layer is arranged on the array substrate and comprises a plurality of anodes; the pixel definition layer is arranged on the anode layer, a plurality of pixel openings corresponding to the anodes and retaining walls arranged around the pixel openings are formed in the pixel definition layer, the side faces of the anodes are located in the coverage range of the retaining walls, the pixel openings are arranged in the first direction and the second direction, and the first direction and the second direction intersect with each other; the bottom surface of one side, close to the array substrate, of each pixel opening comprises a first bottom surface and a second bottom surface connected to at least one side of the first bottom surface in the first direction, and the width of one side, away from the first bottom surface, of the second bottom surface in the second direction is smaller than that of one side, close to the first bottom surface, of the second bottom surface in the second direction; the height of the retaining wall between every two adjacent pixel openings in the first direction is smaller than that of the retaining wall between every two adjacent pixel openings in the second direction; the process can be simplified, and the process cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel. BACKGROUND

[0002] Display technology is constantly updated, and display devices are developing towards multifunction and digitization. With the gradual maturity of printing technology, in the future, it will become a mainstream trend of display technology together with evaporation technology.

[0003] At present, bank1 and bank2 are formed in the pixel definition layer, and the anode and the pixel area are defined by the longitudinal bank1 and the transverse bank2. The function of bank1 is to edge the anode to prevent corrosion and other adverse phenomena of the anode. The height of bank2 is greater than that of bank1, and its function is to isolate different color inks to prevent color mixing. The height of bank1 is smaller, which can be beneficial to realize the overflow of the same ink and improve the film forming uniformity.

[0004] However, bank1 and bank2 need to be patterned respectively to realize the limitation of the pixel area, which leads to complex process and high cost. SUMMARY

[0005] The embodiments of the present application provide a display panel which can simplify the process and reduce the cost.

[0006] The embodiments of the present application provide a display panel, which comprises:

[0007] An array substrate;

[0008] An anode layer disposed on the array substrate and comprising a plurality of anodes;

[0009] A pixel definition layer disposed on the anode layer, the pixel definition layer is formed with a plurality of pixel openings corresponding to the plurality of anodes and a barrier wall disposed around the pixel openings, and the side surface of the anode is located in the coverage range of the barrier wall. The plurality of pixel openings are arranged along a first direction and a second direction, and the first direction and the second direction intersect.

[0010] The bottom surface of the pixel opening near the array substrate side comprises a first bottom surface and a second bottom surface connected to at least one side of the first bottom surface along the first direction. The width of the second bottom surface away from the first bottom surface along the second direction is less than the width of the second bottom surface close to the first bottom surface along the second direction. The height of the barrier wall between the two adjacent pixel openings along the first direction is less than the height of the barrier wall between the two adjacent pixel openings along the second direction.

[0011] In an embodiment of the present application, the second bottom surface has a first end away from the first bottom surface, the minimum distance between the first end and the side surface of the anode along the first direction has a first value, and the minimum distance between the second bottom surface except the first end and the side surface of the anode along the first direction has a second value, the first value being less than or equal to the second value.

[0012] In an embodiment of the present application, for two second bottom surfaces oppositely arranged between two adjacent pixel openings along the first direction, one of the second bottom surfaces has its first end aligned with the first end of the other second bottom surface along the first direction.

[0013] In an embodiment of the present application, for two second bottom surfaces oppositely arranged between two adjacent pixel openings along the first direction, the distance between the two aligned first ends is greater than or equal to 0.5 microns and less than or equal to 1 micron.

[0014] In an embodiment of the present application, the minimum distance between the first end and the side surface of the anode along the first direction is 0.

[0015] In an embodiment of the present application, the width of the second bottom surface along the second direction gradually decreases away from the first bottom surface connected thereto.

[0016] In an embodiment of the present application, a plurality of anodes are arranged along the first direction and the second direction, the anodes include first sub-anodes and second sub-anodes connected to at least one side of the first sub-anodes along the first direction, and the width of the second sub-anodes away from the first sub-anodes along the second direction is less than the width of the second sub-anodes close to the first sub-anodes along the second direction.

[0017] In an embodiment of the present application, the first bottom surface is aligned with the first sub-anodes along the thickness direction of the display panel, and the second bottom surface is aligned with the second sub-anodes along the thickness direction of the display panel.

[0018] In an embodiment of the present application, the barrier wall includes first sub-walls between two adjacent pixel openings along the first direction and second sub-walls between two adjacent pixel openings along the second direction, the height of the first sub-walls is less than the height of the second sub-walls, and the first sub-walls are integrally arranged with the second sub-walls.

[0019] In an embodiment of the present application, the second bottom surface has a first end away from the first bottom surface, and the first sub-wall has a thickness on a side close to the first end that is less than a thickness on a side away from the first end.

[0020] And / or, the first sub-wall has a width on a side close to the first end in the first direction that is less than a width on a side away from the first end in the first direction.

[0021] In an embodiment of the present application, the first sub-wall has a first surface on a side away from the array substrate, and the second sub-wall has a second surface on a side away from the array substrate, and the second surface has a surface contact angle that is greater than a surface contact angle of the first surface.

[0022] The present application provides a display panel, by reducing the width of the second bottom surface of at least one end of the bottom surface of the pixel opening, so that the width of the end of the second bottom surface away from the first bottom surface is smaller; since the width of the end of the second bottom surface away from the first bottom surface is smaller, its influence on the coverage of the anode side surface is also smaller, thereby without affecting the coverage of the side surface of the anode, the distance between the end of the second bottom surface away from the first bottom surface and the side surface of the anode can be reduced, that is, the distance between the two adjacent pixel openings in the first direction is closer; therefore, in the process of forming the pattern of the pixel opening by the pixel definition layer, the film layer in the region of the pixel opening is removed, and the film layer close to the pixel opening is removed or thinned; since the distance between the adjacent pixel openings is reduced, the barrier wall between the adjacent pixel openings is also thinned synchronously; to form barrier walls with different heights in the same process, so that the height of the barrier wall between the two pixel openings adjacent in the first direction is less than the height of the barrier wall between the two pixel openings adjacent in the second direction; thereby on the basis of meeting the edge covering of the barrier wall to the anode, realizing the overflow of the ink in the first direction and blocking the color mixing of the ink in the second direction, the process can be simplified and the process cost can be reduced.

[0023] Other features and advantages of the present application will be described in detail in the following specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0025] For a more complete understanding of the present application and the advantages thereof, reference is now made to the following descriptions taken in connection with the accompanying drawings in which:

[0026] Figure 1 A structure diagram of a pixel definition layer provided for an embodiment is shown in the following figure;

[0027] Figure 2 A structure diagram of a pixel definition layer provided for an embodiment is shown in the following figure;

[0028] Figure 3 A structure diagram of a pixel definition layer provided for an embodiment is shown in the following figure; Figure 2 A structure diagram of a pixel definition layer provided for an embodiment is shown in the following figure;

[0029] Figure 4 A structure diagram of a pixel definition layer provided for an embodiment is shown in the following figure;

[0030] Figure 5 A structure diagram of a pixel definition layer provided for an embodiment is shown in the following figure;

[0031] Figure 6 A structure diagram of a pixel definition layer provided for an embodiment is shown in the following figure;

[0032] Figure 7 A structure diagram of a pixel definition layer provided for an embodiment is shown in the following figure; Figure 2 A structure diagram of a pixel definition layer provided for an embodiment is shown in the following figure;

[0033] Figure 8 A structure diagram of a pixel definition layer provided for an embodiment is shown in the following figure; Figure 2 A structure diagram of a pixel definition layer provided for an embodiment is shown in the following figure.

[0034] Explanation of reference signs:

[0035] 1, first barrier wall; 2, second barrier wall; 3, pixel region;

[0036] 10, array substrate; 20, anode layer; 21, anode; 211, first sub-anode; 213, second sub-anode; 30, pixel definition layer; 31, pixel opening; 311, first bottom surface; 312, second bottom surface; 3121, first end; 32, barrier wall; 321, first sub-wall; 3210, first surface; 322, second sub-wall; 3220, second surface; 40, light emitting layer; 41, light emitting part; 411, first light emitting part; 412, second light emitting part; 413, third light emitting part; 42, connecting part. DETAILED DESCRIPTION

[0037] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative effort are within the protection scope of the present application.

[0038] Please refer to Figure 1 At present, a display panel defines a plurality of pixel regions 3 by setting a first barrier wall 1 in a transverse direction and a second barrier wall 2 in a longitudinal direction, so that ink can be formed in the plurality of pixel regions 3 in an inkjet printing process; wherein the pixel region 3 is provided with an anode, and the first barrier wall 1 and the second barrier wall 2 also need to cover the edges of the anode to avoid corrosion of the anode in the subsequent process; in addition, the ink will be blocked by the first barrier wall 1, but the ink will flow between the two adjacent first barrier walls 1 to improve the film uniformity of the printing layer in the pixel region 3. However, the patterns of the first barrier wall 1 and the second barrier wall 2 are different, the heights are different, and the hydrophilicity and hydrophobicity are also different, and usually two photomask processes are needed to realize, resulting in a complex process and high cost.

[0039] Please refer to Figure 2 and Figure 3 The embodiment of the present application provides a display panel, which comprises an array substrate 10, an anode layer 20 and a pixel definition layer 30; the anode layer 20 is arranged on the array substrate 10 and comprises a plurality of anodes 21; the pixel definition layer 30 is arranged on the anode layer 20, a plurality of pixel openings 31 corresponding to the plurality of anodes 21 and a barrier wall 32 arranged around the pixel openings 31 are formed in the pixel definition layer 30, and the side surface of the anode 21 is located in the coverage range of the barrier wall 32, the plurality of pixel openings 31 are arranged along a first direction X and a second direction Y, and the first direction X and the second direction Y intersect.

[0040] Wherein, the bottom surface of the pixel opening 31 close to the side of the array substrate 10 comprises a first bottom surface 311 and a second bottom surface 312 connected to at least one side of the first bottom surface 311 along the first direction X, the width W1 of the second bottom surface 312 away from the first bottom surface 311 along the second direction Y is less than the width W2 of the second bottom surface 312 close to the first bottom surface 311 along the second direction Y, and the height of the barrier wall 32 located between the two adjacent pixel openings 31 along the first direction X is less than the height of the barrier wall 32 located between the two adjacent pixel openings 31 along the second direction Y.

[0041] In the application process, the width of the second bottom surface 312 of at least one end of the bottom surface of the pixel opening 31 is reduced, so that the width W1 of the end of the second bottom surface 312 away from the first bottom surface 311 is smaller. Since the width W1 of the end of the second bottom surface 312 away from the first bottom surface 311 is smaller, its coverage of the side surface of the anode 21 is also smaller, and the distance between the end of the second bottom surface 312 away from the first bottom surface 311 and the side surface of the anode 21 can be reduced, that is, the distance between the two adjacent pixel openings 31 in the first direction X is made smaller. Therefore, in the process of forming the pattern of the pixel opening 31 in the pixel definition layer 30, the film layer in the area of the pixel opening 31 is removed, and the film layer near the pixel opening 31 is removed or thinned. Since the distance between the adjacent pixel openings 31 is reduced, the barrier wall 32 between the adjacent pixel openings 31 is also thinned. In the same process, barrier walls 32 with different heights are formed, so that the height of the barrier wall 32 between the two adjacent pixel openings 31 in the first direction X is smaller than the height of the barrier wall 32 between the two adjacent pixel openings 31 in the second direction Y. Further, on the basis of meeting the edge covering of the barrier wall 32 to the anode 21, realizing the overflow of the ink in the first direction X and blocking the color mixing of the ink Y in the second direction, the process can be simplified and the process cost can be reduced.

[0042] Specifically, please refer to Figure 2 and Figure 3 The display panel includes an array substrate 10, an anode layer 20, a pixel definition layer 30 and a printing layer 40 arranged on the array substrate 10 in sequence.

[0043] In some embodiments, the array substrate 10 includes a substrate and a thin film transistor layer arranged on the substrate.

[0044] In some embodiments, the substrate can be a hard substrate, such as a glass substrate; or the substrate can be a flexible substrate, such as a substrate formed of polyimide. When the substrate is a flexible substrate, the substrate can be formed of multiple sub-substrates made of the same material, such as polyimide, and the adjacent sub-substrates are bonded by an adhesive sub-layer.

[0045] In some embodiments, the thin film transistor layer includes a thin film transistor, the thin film transistor includes a semiconductor on the substrate, the semiconductor can be formed of polycrystalline silicon or metal oxide (such as indium gallium zinc oxide). The semiconductor is divided into a channel region and a source region and a drain region formed on both sides of the channel region. The thin film transistor layer further includes a first gate insulating layer covering the semiconductor. The thin film transistor further includes a first gate formed on the first gate insulating layer, the first gate overlaps with the channel region. The first gate can be formed of multiple layers or a single layer including a low-resistance material such as Al, Ti, Mo, Cu, Ni, or an alloy thereof, or a material with high corrosion resistance. The thin film transistor layer further includes a second gate insulating layer covering the first gate. The thin film transistor further includes a second gate on the second gate insulating layer, the second gate overlaps with the first gate, and the second gate can be formed of multiple layers or a single layer including a low-resistance material such as Al, Ti, Mo, Cu, Ni, or an alloy thereof, or a material with high corrosion resistance. The thin film transistor layer further includes a first interlayer insulating layer formed on the second gate. The first interlayer insulating layer and the first gate insulating layer and the second gate insulating layer include a source contact hole and a drain contact hole, and the source region and the drain region are respectively exposed through the source contact hole and the drain contact hole.

[0046] The thin film transistor further includes a source and a drain arranged in the same layer, both the source and the drain are formed on the first interlayer insulating layer, the source is connected with the source region through the source contact hole, and the drain is connected with the drain region through the drain contact hole. The source and the drain can be formed of multiple layers or a single layer including a low-resistance material such as Al, Ti, Mo, Cu, Ni, or an alloy thereof, or a material with high corrosion resistance. For example, the source and the drain can be a triple layer of Ti / Cu / Ti, Ti / Ag / Ti, Ti / Al / Ti, or Mo / Al / Mo, or other single layer or multi-layer structures.

[0047] In some embodiments, the thin film transistor layer further includes a planar layer on the side of the first interlayer insulating layer away from the substrate, the planar layer covers the source and the drain.

[0048] In some embodiments, the anode layer 20 is arranged on the array substrate 10, i.e., on the flat upper surface; the anode layer 20 includes a plurality of anodes 21 arranged at intervals, each anode 21 can be connected with the source or the drain of the corresponding thin film transistor to realize signal transmission.

[0049] Further, the plurality of anodes 21 can be arranged along a first direction X and a second direction Y, and the first direction X and the second direction Y intersect; in some embodiments, the first direction X and the second direction Y intersect, i.e., the plurality of anodes 21 are arranged in multiple rows and multiple columns.

[0050] In some embodiments, the pixel definition layer 30 is disposed on the anode layer 20, and the pixel definition layer 30 is formed with a plurality of pixel openings 31 and a barrier wall 32 disposed around each pixel opening 31; wherein the plurality of pixel openings 31 are correspondingly disposed with the plurality of anodes 21, for example, one-to-one correspondingly disposed.

[0051] That is, the plurality of pixel openings 31 are also arranged along the first direction X and the second direction Y, and each pixel opening 31 exposes the surface of the corresponding anode 21 away from the array substrate 10.

[0052] In the embodiments of the present application, the side surface of the anode 21 is located in the coverage range of the barrier wall 32, that is, the side surface of the plurality of anodes 21 is located in the coverage range of the barrier wall 32, so as to avoid the anode 21 from being corroded in subsequent processes or use.

[0053] In some embodiments, the printing layer 40 is disposed on the pixel definition layer 30, and the printing layer 40 includes a plurality of printing portions 41, and the plurality of printing portions 41 are correspondingly disposed with the plurality of pixel openings 31; that is, the plurality of printing portions 41 are also arranged along the first direction X and the second direction Y.

[0054] Wherein, each printing portion 41 is located in the corresponding pixel opening 31 and on the side of the corresponding anode 21 away from the array substrate 10.

[0055] In some embodiments, the plurality of printing portions 41 can include a plurality of first printing portions 411, a plurality of second printing portions 412, and a plurality of third printing portions 413; wherein each plurality of first printing portions 411 can be arranged in a row along the first direction X, each plurality of second printing portions 412 can be arranged in a row along the first direction X, and each plurality of third printing portions 413 can be arranged in a row along the first direction X; and the plurality of rows of first printing portions 411, the plurality of rows of second printing portions 412, and the plurality of rows of third printing portions 413 can be alternately arranged along the second direction Y; for example, along the second direction Y, they can be arranged in the following order: a row of first printing portions 411, a row of second printing portions 412, a row of third printing portions 411, a row of first printing portions 411, a row of second printing portions 412, a row of third printing portions 411, a row of first printing portions 411, a row of second printing portions 412, a row of third printing portions 411, and so on, and can be arranged according to this rule.

[0056] In some embodiments, the printing unit 41 can include at least one of a hole injection layer, a hole transport layer and a light emitting layer disposed in the pixel opening 31; wherein the hole injection layer is between the hole transport layer and the anode, the hole transport layer is on the side of the hole injection layer away from the anode, and the light emitting layer is on the side of the hole transport layer away from the hole injection layer; and the hole injection layer, the hole transport layer and the light emitting layer can be prepared by an inkjet printing process; when the printing unit 41 contains the light emitting layer, the printing unit 41 has a light emitting function.

[0057] It can be understood that the display panel can further include an electron transport layer and an electron injection layer disposed in sequence on the side of the printing layer 40 away from the array substrate 10, and the electron transport layer and the electron injection layer can be prepared by an evaporation process.

[0058] In some embodiments, the light emitting color of the first printing unit 411, the light emitting color of the second printing unit 412 and the light emitting color of the third printing unit 413 are different from each other and are each independently selected from any one of red, green and blue; or the light emitting color of the light emitting layer in the pixel opening 31 corresponding to the first printing unit 411, the light emitting color of the light emitting layer in the pixel opening 31 corresponding to the second printing unit 412 and the light emitting color of the light emitting layer in the pixel opening 31 corresponding to the third printing unit 413 are different from each other and are each independently selected from any one of red, green and blue.

[0059] In some embodiments, the same ink is simultaneously printed to form a film for each row of the first printing unit 411, and the ink can flow between the plurality of pixel openings 31 arranged in the first direction X corresponding to the same row of the first printing unit 411, i.e., overflow, to improve the film forming uniformity of the first printing unit 411; similarly, the same ink is simultaneously printed to form a film for each row of the second printing unit 412, and the ink can flow between the plurality of pixel openings 31 arranged in the first direction X corresponding to the same row of the second printing unit 412, i.e., overflow, to improve the film forming uniformity of the second printing unit 412; the same ink is simultaneously printed to form a film for each row of the third printing unit 413, and the ink can flow between the plurality of pixel openings 31 arranged in the first direction X corresponding to the same row of the third printing unit 413, i.e., overflow, to improve the film forming uniformity of the third printing unit 413.

[0060] In addition, each row of the first printing part 411 and the adjacent row of the second printing part 412 are formed by different inks, so that the two need to be blocked by the barrier wall 32 to avoid ink color mixing; similarly, each row of the first printing part 411 and the adjacent row of the third printing part 413 are formed by different inks, so that the two need to be blocked by the barrier wall 32 to avoid ink color mixing; each row of the second printing part 411 and the adjacent row of the third printing part 413 are formed by different inks, so that the two need to be blocked by the barrier wall 32 to avoid ink color mixing.

[0061] Further, in some embodiments, the display panel can further include a cathode layer and an encapsulation layer disposed on the printing layer 40. The cathode layer can continuously cover the plurality of printing parts 41 away from the anode 21, and the encapsulation layer can cover the cathode layer away from the printing layer 40, so as to block water and oxygen and improve the stability and service life of the display panel.

[0062] In the embodiments of the present application, by improving and designing the pixel opening 31, the barrier wall 32 and the anode 21, the display panel can simplify the process and reduce the cost on the basis of ensuring the original function.

[0063] Specifically, in the embodiment of the present application, the bottom surface of the pixel opening 31 close to the side of the array substrate 10 comprises a first bottom surface 311 and a second bottom surface 312 connected to at least one side of the first bottom surface 311 along the first direction X, the width W1 of the second bottom surface 312 away from the first bottom surface 311 along the second direction Y is smaller than the width W2 of the second bottom surface 312 close to the first bottom surface 311 along the second direction Y; that is, the width of the bottom surface of the pixel opening 31 is reduced on at least one side along the first direction X; so that the width W1 of the second bottom surface 312 away from the first bottom surface 311 is smaller; since the width W1 of the second bottom surface 312 away from the first bottom surface 311 is smaller, its coverage of the side surface of the anode 21 is also smaller, thereby reducing the distance between the second bottom surface 312 away from the first bottom surface 311 and the side surface of the anode 21 without affecting the coverage of the side surface of the anode 21, that is, making the distance between the two adjacent pixel openings 31 along the second direction Y closer; therefore, during the patterning process of the pixel definition layer 30 to form the pixel opening 31, the film layer in the area of the pixel opening 31 is removed, and the film layer close to the pixel opening 31 is removed or thinned; since the distance between the adjacent pixel openings 31 is reduced, the barrier wall 32 between the adjacent pixel openings 31 is also thinned synchronously; that is, the height of the barrier wall 32 between the two adjacent pixel openings 31 along the first direction X is smaller than the height of the barrier wall 32 between the two adjacent pixel openings 31 along the second direction Y; thereby forming barrier walls 32 with different heights in the same process, so that the height of the barrier wall 32 between the two adjacent pixel openings 31 along the first direction X is smaller than the height of the barrier wall 32 between the two adjacent pixel openings 31 along the second direction Y; thereby simplifying the process and reducing the process cost on the basis of meeting the edge covering of the barrier wall 32 to the anode 21, realizing the overflow of the ink along the first direction X and blocking the color mixing of the ink Y along the second direction.

[0064] It should be noted that the bottom surface of the pixel opening 31 close to the side of the array substrate 10 defined in the embodiment of the present application can be regarded as the bottom surface of the pixel opening 31, that is, the bottom surface of the pixel opening 31 close to the side of the array substrate 10 can be regarded as the surface of the anode 21 exposed by the pixel opening 31.

[0065] In the embodiment of the present application, the principle of thinning the adjacent barrier wall 32 during the patterning process of the pixel opening 31 is as follows: when the mask is used to pattern the pixel definition layer 30 to form the pixel opening 31, the opening in the mask can correspond to the area of the pixel opening 31, thereby causing partial exposure at the position adjacent to the pixel opening 31 during the exposure and development process, and then being removed during the development process to achieve thinning.

[0066] Please combineFigure 2 、 Figure 3 、 Figure 4 and Figure 5 In the embodiments of the present application, the width of the end side of the anode 21 along the first direction X can be reduced to match the shape of the pixel opening 31.

[0067] The anode 21 includes a first sub-pole 211 and a second sub-pole 212 connected to at least one side of the first sub-pole 211 along the first direction X, and the width of the side of the second sub-pole 212 away from the first sub-pole 211 along the second direction Y is smaller than the width of the side of the second sub-pole 212 close to the first sub-pole 211 along the second direction Y.

[0068] The first bottom surface 311 is arranged in position along the thickness direction of the display panel with the first sub-pole 211, and the second bottom surface 312 is arranged in position along the thickness direction of the display panel with the second sub-pole 212.

[0069] In some embodiments, the second bottom surface 312 has a first end 3121 away from the first bottom surface 311, the minimum distance L between the first end 3121 and the side of the anode 21 along the first direction X has a first value, and the minimum distance L between the part of the second bottom surface 312 other than the first end 3121 and the side of the anode 21 along the first direction X has a second value, the first value being smaller than or equal to the second value; that is, in the embodiments of the present application, the first end 3121 of the second bottom surface 312 is extended towards the side of the second sub-pole 212, so that the first end 3121 is closer to the side of the second sub-pole 212, and thus it is easier to thin the barrier wall 32 between the two adjacent pixel openings 31 along the first direction X in the patterning process of the pixel opening 31.

[0070] In some embodiments, the minimum distance L between the first end 3121 and the side of the anode 21 along the first direction X is 0; thus, the barrier wall 32 between the two adjacent pixel openings 31 along the first direction X can be thinned to the greatest extent, so that the ink can pass through the barrier wall 32 between the two adjacent pixel openings 31 along the first direction X in the printing process to achieve overflow and improve the film uniformity of the ink.

[0071] In some embodiments, the width of the second bottom surface 312 along the second direction X gradually decreases away from the first bottom surface 311.

[0072] In some embodiments, the shape of the anode 21 can be circular or elliptical, and the shape of the pixel opening 31 can be polygonal, for example, the first bottom surface 311 is quadrangular, the second bottom surface 312 is triangular, one side of the triangle is connected to one side of the first bottom surface 311, and one corner of the triangle away from the first bottom surface 311 can be regarded as the first end 3121.

[0073] Please combine Figure 2 , Figure 3 , Figure 6 , Figure 7 and Figure 8 , for the two second bottom surfaces 312 between the two adjacent pixel openings 31 along the first direction X and oppositely arranged, one of the first ends 3121 of the second bottom surface 312 and the first end 3121 of the other second bottom surface 312 are aligned and oppositely arranged along the first direction X; thereby facilitating the reduction of the distance between the two second bottom surfaces 312, and facilitating the thinning of the barrier wall 32 between the two second bottom surfaces 312.

[0074] In some embodiments, for the two second bottom surfaces 312 between the two adjacent pixel openings 31 along the first direction X and oppositely arranged, the spacing between the two aligned first ends 3121 is greater than or equal to 0.5 microns and less than or equal to 1 micron; the embodiments of the present application can thin the barrier wall 32 between the two second bottom surfaces 312 synchronously during the formation of the pixel openings 31 by setting the spacing between the two first ends 3121 to be small enough, so as to realize the height differentiation of the barrier wall 32 in the same process, which can save the process and reduce the cost.

[0075] In some embodiments, the barrier wall 32 includes a first sub-wall 321 located between the two adjacent pixel openings 31 along the first direction X and a second sub-wall 322 located between the two adjacent pixel openings 31 along the second direction Y, the height of the first sub-wall 321 is less than the height of the second sub-wall 322, and the first sub-wall 321 and the second sub-wall 322 are integrally arranged.

[0076] In some embodiments, please combine Figure 2 , Figure 3 , and Figure 7 , the printing layer 40 further includes a connecting portion 42 connected between the two adjacent printing portions 41 along the first direction X, and the connecting portion 42 is located on the surface of at least part of the first sub-wall 321; that is, the embodiments of the present application can make the ink flow on the first sub-wall 321 by reducing the thickness of the first sub-wall 321, thereby realizing the overflow of the ink and improving the film forming uniformity of the ink.

[0077] In some embodiments, between the two adjacent pixel openings 31 along the first direction X, the thickness of the first sub-wall 321 on the side close to the first end 3121 is less than the thickness of the first sub-wall 321 on the side away from the first end 3121; further, the thickness of the first sub-wall 321 gradually decreases in the direction close to the first end 3121, as shown in Figure 8 .

[0078] It should be noted that,Figure 8 The position of the first end 3121 is shown by a dashed line in FIG. 12, but the position is only used to represent the position of the first end 3121 in the direction parallel to the plane, and cannot represent the position of the first end 3121 in the direction perpendicular to the plane; and Figure 8 The first end 3121 cannot be exposed in the sectional view of FIG. 13, and the embodiment of the present application is used to illustrate the structural change of the first sub-wall 321. Figure 8 The position of the first end 3121 is shown by a dashed line in FIG. 13.

[0079] In some embodiments, between two adjacent pixel openings 31 along the first direction X, the width of the first sub-wall 321 along the first direction X on the side close to the first end 3121 is smaller than the width of the first sub-wall 321 along the first direction X on the side away from the first end 3121; and further, the width of the first sub-wall 321 along the first direction X gradually decreases in the direction close to the first end 3121, as shown in FIG. 14. Figure 6

[0080] In some embodiments, the distance between two adjacent second sub-walls 322 along the second direction Y is greater than or equal to 10 microns and less than or equal to 16 microns.

[0081] In an embodiment, in the process of the pixel definition layer 30, a hydrophobic element is formed on the side of the pixel definition layer 30 away from the array substrate 10, so that the surface contact angle is increased, and the pixel definition layer 30 can be hydrophobic, while other parts of the pixel definition layer 30 can be hydrophilic; and then the ink flow can be effectively blocked from the pixel opening 31; but in the patterning process of the pixel definition layer 30, the part of the barrier wall 32 close to the top between two adjacent pixel openings 31 along the first direction X is removed, that is, the hydrophobic surface is removed, so that the surface of the first sub-wall 321 formed away from the array substrate 10 is hydrophilic; which can be beneficial to the overflow of the ink along the first direction X, and improve the film uniformity of the ink; and compared with the technology shown in FIG. 15, different processes are required to make the first barrier wall 1 and the second barrier wall 2 have different hydrophobicity, and the embodiment of the present application can further simplify the process and reduce the cost. Figure 1

[0082] In some embodiments, the hydrophobic element can be fluorine element; for example, the fluorine element in the material can float to the surface of the pixel definition layer 30 in the coating and film forming process of the pixel definition layer 30, so that the side of the pixel definition layer 30 away from the array substrate 10 has the hydrophobic element; or the hydrophobic element can be additionally formed on the surface of the side of the pixel definition layer 30 away from the array substrate 10.

[0083] In some embodiments, the hydrophobic element can be fluorine element; for example, the fluorine element in the material can float to the surface of the pixel definition layer 30 in the coating and film forming process of the pixel definition layer 30, so that the side of the pixel definition layer 30 away from the array substrate 10 has the hydrophobic element; or the hydrophobic element can be additionally formed on the surface of the side of the pixel definition layer 30 away from the array substrate 10. Figure 2 Figure 3 Figure 8 ​​​​The first sub-wall 321 has a first surface 3210 away from the array substrate 10, and the second sub-wall 322 has a second surface 3220 away from the array substrate 10, and the surface contact angle of the second surface 3220 is greater than the surface contact angle of the first surface 3210.

[0084] In some embodiments, the surface contact angle of the first surface 3210 can be less than 90°, and the first surface 3210 is hydrophilic, so as to facilitate the overflow of the ink along the first direction X and improve the film uniformity; and the surface contact angle of the second surface 3220 can be greater than 90°, and the second surface 3220 is hydrophobic, so as to facilitate the blocking of the ink by the second sub-wall 322 along the second direction Y, and reduce the probability of ink color mixing.

[0085] In summary, in the embodiments of the present application, the width of the second bottom surface 312 of the at least one end of the bottom surface of the pixel opening 31 is reduced, so that the width W1 of the end of the second bottom surface 312 away from the first bottom surface 311 is smaller. Since the width W1 of the end of the second bottom surface 312 away from the first bottom surface 311 is smaller, the coverage of the side surface of the anode 21 is also smaller, and thus the distance between the end of the second bottom surface 312 away from the first bottom surface 311 and the side surface of the anode 21 can be reduced, i.e., the distance between the two adjacent pixel openings 31 along the first direction X is smaller. Therefore, during the patterning process of the pixel definition layer 30 to form the pixel opening 31, the film layer near the pixel opening 31 is removed or thinned. Since the distance between the adjacent pixel openings 31 is reduced, the barrier wall 32 between the adjacent pixel openings 31 is also thinned. In the same process, the barrier wall 32 with different heights is formed, so that the height of the barrier wall 32 between the two adjacent pixel openings 31 along the first direction X is smaller than the height of the barrier wall 32 between the two adjacent pixel openings 31 along the second direction Y. Thus, on the basis of meeting the edge covering of the barrier wall 32 to the anode 21, the overflow of the ink along the first direction X and the blocking of the ink Y along the second direction, the process can be simplified and the process cost can be reduced.

[0086] In addition, the present application also provides a display device, and the display device comprises the display panel as described in the above embodiments.

[0087] It can be understood that the display device has the same display panel as the above embodiments, and thus the display device has the same beneficial effects as the display panel, which will not be described here.

[0088] In the description of the application, the terms "first", "second", etc. are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0089] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0090] The embodiments, implementation manners and related technical features of the present application can be combined or replaced with each other without conflict.

[0091] The above is only the preferred embodiment of the present application, and does not limit the present application in any form. Any simple modification, equivalent change and modification made to the above embodiment in accordance with the technical essence of the present application without departing from the technical solution content of the present application still falls within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized by, The display panel comprises: an array substrate; an anode layer disposed on the array substrate and comprising a plurality of anodes; a pixel definition layer disposed on the anode layer, the pixel definition layer having a plurality of pixel openings corresponding to the plurality of anodes and a barrier wall disposed around the pixel openings, and a side surface of the anode being within a coverage range of the barrier wall, the plurality of pixel openings being arranged along a first direction and a second direction intersecting the first direction; wherein a bottom surface of the pixel opening on a side close to the array substrate comprises a first bottom surface and a second bottom surface connected to at least one side of the first bottom surface along the first direction, a width of the second bottom surface away from the first bottom surface along the second direction being less than a width of the second bottom surface close to the first bottom surface along the second direction, and a height of the barrier wall between two adjacent pixel openings along the first direction being less than a height of the barrier wall between two adjacent pixel openings along the second direction.

2. The display panel of claim 1, wherein, The second bottom surface has a first end away from the first bottom surface, a minimum distance between the first end and the side surface of the anode along the first direction having a first value, and a minimum distance between a part of the second bottom surface other than the first end and the side surface of the anode along the first direction having a second value, the first value being less than or equal to the second value.

3. The display panel of claim 2, wherein, For two second bottom surfaces oppositely arranged between two adjacent pixel openings along the first direction, the first end of one of the second bottom surfaces is aligned with and oppositely arranged to the first end of the other second bottom surface along the first direction.

4. The display panel of claim 3, wherein, For two second bottom surfaces oppositely arranged between two adjacent pixel openings along the first direction, a distance between the two first ends arranged in alignment is greater than or equal to 0.5 microns and less than or equal to 1 micron.

5. The display panel of claim 2, wherein, The minimum distance between the first end and the side surface of the anode along the first direction is 0.

6. The display panel of claim 1, wherein, The width of the second bottom surface along the second direction gradually decreases in a direction away from the first bottom surface connected thereto.

7. The display panel of any one of claims 1 to 6, wherein, The plurality of anodes are arranged along the first direction and the second direction, the anode comprising a first sub-anode and a second sub-anode connected to at least one side of the first sub-anode along the first direction, and a width of the second sub-anode away from the first sub-anode along the second direction being less than a width of the second sub-anode close to the first sub-anode along the second direction; wherein the first bottom surface is aligned with the first sub-anode along a thickness direction of the display panel, and the second bottom surface is aligned with the second sub-anode along the thickness direction of the display panel.

8. The display panel of any one of claims 1 to 6, wherein, The barrier wall comprises a first sub-wall between two adjacent pixel openings along the first direction and a second sub-wall between two adjacent pixel openings along the second direction, a height of the first sub-wall being less than a height of the second sub-wall, and the first sub-wall and the second sub-wall being integrally arranged.

9. The display panel of claim 8, wherein, The second bottom surface has a first end away from the first bottom surface, and a thickness of the first sub-wall on a side close to the first end is less than a thickness of the first sub-wall on a side away from the first end. And / or, a width of the first sub-wall on the side close to the first end along the first direction is less than a width of the first sub-wall on the side away from the first end along the first direction.

10. The display panel of claim 8, wherein, A side of the first sub-wall away from the array substrate has a first surface, and a side of the second sub-wall away from the array substrate has a second surface, and a surface contact angle of the second surface is greater than a surface contact angle of the first surface.

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