Connection body of mask and supporting part and manufacturing method thereof

Abstract

The invention relates to a connector of a mask and a support part and a manufacturing method thereof. The connector of the mask and the supporting part is used for a forming process of OLED pixels on a semiconductor wafer, and comprises the components of the supporting part which comprises an edge part and a grid part; and a mask connected to the support portion and including a plurality of unit portions on which a mask pattern is formed, the lower portion of the support portion being further formed with an anti-deformation portion.

Description

Technical Field

[0001] This invention relates to a connector between a mask and a support, and a method for manufacturing the same. More specifically, it relates to a connector between a mask and a support used in forming pixels on a semiconductor wafer and capable of precisely forming ultra-high resolution mask patterns, and a method for manufacturing the same. Background Technology

[0002] As a technique for forming pixels in OLED manufacturing, the FMM (Fine Metal Mask) method is mainly used. This method involves attaching a thin-film metal mask (Shadow Mask) tightly to the substrate and depositing organic matter at the desired location.

[0003] In existing OLED manufacturing processes, after fabricating the mask film, the mask is soldered to the OLED pixel deposition frame. However, there is a problem of difficulty in aligning large-area masks during the fixing process. In addition, due to the thinness and large area of ​​the mask film, there is a problem of mask sagging or twisting under load during the soldering and fixing process to the frame.

[0004] In the manufacturing process of ultra-high-definition OLEDs, even tiny alignment errors below 1μm can lead to pixel deposition failure. Therefore, it is necessary to develop technologies that can prevent mask sagging or twisting and ensure accurate alignment.

[0005] In addition, microdisplays used in VR (virtual reality) devices have recently attracted attention. To present images to users in VR devices, microdisplays need to be significantly smaller than existing displays, and they must achieve high image quality within a tiny frame. Therefore, it is necessary to create a mask pattern significantly smaller than the masks used in existing ultra-high-definition OLED manufacturing processes, and to perform finer alignment of the mask before pixel deposition. Summary of the Invention

[0006] Technical issues

[0007] Therefore, the present invention is proposed to solve the many problems in the prior art as described above, and aims to provide a connector for a mask and support portion capable of realizing ultra-high image quality pixels of a micro display and a method for manufacturing the same.

[0008] Furthermore, the present invention aims to provide a mask-support connector and its manufacturing method that can improve the stability of pixel deposition by accurately aligning the mask.

[0009] However, the above-mentioned technical problems are merely exemplary, and the scope of the present invention is not limited thereto.

[0010] Technical solution

[0011] The above-mentioned objective of the present invention can be achieved by a connector between a mask and a support portion, which is used in the process of forming OLED pixels on a semiconductor wafer and includes: a support portion, which includes an edge portion and a grid portion; a mask, which is connected to the support portion and includes a plurality of unit portions having a mask pattern formed thereon, and the lower part of the support portion further has an anti-deformation portion formed thereon.

[0012] At least a portion of the mask may be arranged in a groove formed by a recess in the support portion.

[0013] The support portion and the mask may have a circular shape. The grid portion may include: a plurality of first grid portions that extend along a first direction and are connected at both ends to the edge portion; and a plurality of second grid portions that extend along a second direction different from the first direction and intersect with the first grid portions, and are connected at both ends to the edge portion.

[0014] The mask may include: a dummy portion connected to the edge portion; a plurality of unit portions arranged in the center of the mask rather than in the dummy portion, and including a plurality of mask patterns; and a dividing portion arranged in the center of the mask rather than in the dummy portion, and arranged between the plurality of unit portions, the dividing portion being supported on the grid portion.

[0015] The anti-deformation portion is formed at the lower part of the edge portion, the lower part of the first grid portion, and the lower part of the second grid portion.

[0016] The material of the mask can be the same as the material of the anti-deformation part.

[0017] The thickness of the mask can be the same as the thickness of the anti-deformation part, or the thickness of the anti-deformation part can be greater.

[0018] The overall volume of the mask and the overall volume of the anti-deformation part can be between 70% and 130% of each other.

[0019] The support portion can be formed from a silicon wafer, and the mask and the anti-deformation portion can be formed on the silicon wafer using electroforming.

[0020] A connecting portion may be sandwiched between the support portion and the mask, or between the support portion and the anti-deformation portion, wherein the connecting portion comprises Ni and Si, or comprises Fe, Ni and Si.

[0021] Furthermore, the above-mentioned objective of the present invention is achieved by a method for manufacturing a connector between a mask and a support portion, which is used in the process of forming OLED pixels on a semiconductor wafer. The method includes the following steps: (a) preparing a support portion, the support portion being a conductive substrate, including a first surface and a second surface opposite to the first surface; (b) forming a mask on the first surface of the support portion by electroforming; (c) forming an anti-deformation portion on the second surface of the support portion by electroforming; (d) performing heat treatment on the support portion, the anti-deformation portion, and the mask; and (e) forming an edge portion and a grid portion on the second surface of the support portion by etching the support portion.

[0022] In step (e), edge anti-deformation portion and grid anti-deformation portion can be formed by etching the anti-deformation portion.

[0023] Invention Effects

[0024] According to the present invention configured as described above, it has the effect of achieving ultra-high image quality pixels for microdisplays.

[0025] Furthermore, according to the present invention, the stability of pixel deposition is improved by accurately aligning the mask.

[0026] Furthermore, according to the present invention, all portions of the mask maintain a uniform pressure level.

[0027] Of course, the scope of the present invention is not limited to the effects described above. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the connection between the mask and the support portion according to an embodiment of the present invention.

[0029] Figure 2 yes Figure 1 A schematic diagram of the side section of A-A'.

[0030] Figure 3 These are a top view and a side cross-sectional view of a mask according to an embodiment of the present invention, specifically E-E'.

[0031] Figure 4 This is a top view of a support portion according to an embodiment of the present invention.

[0032] Figures 5 to 11 This is a schematic diagram of the manufacturing process of the connector between the mask and the support according to the first embodiment of the present invention.

[0033] Figures 12 to 16This is a schematic diagram of the manufacturing process of the connector between the mask and the support according to the second embodiment of the present invention.

[0034] Figure 17 This is a top view and a side cross-sectional view of a mask according to another embodiment of the present invention, specifically E-E' or F-F'.

[0035] Figure 18 This is a top view of a support portion according to another embodiment of the present invention.

[0036] Figure 19 This is a schematic diagram of the mask planarization process and the dummy groove portion of the grid portion according to an embodiment of the present invention.

[0037] Figure 20 These are a top view and a side cross-sectional view of the mask pattern and the dummy groove portion of the grid portion according to an embodiment of the present invention.

[0038] Figure 21 This is a schematic diagram of an OLED pixel deposition apparatus employing a connection between a mask and a support portion according to an embodiment of the present invention.

[0039] Figure 22 yes Figure 8 A schematic diagram illustrating the phenomena that may occur during the heat treatment process.

[0040] Figure 23 This is a side cross-sectional schematic diagram of the connection body between the mask and the support according to the third embodiment of the present invention.

[0041] Figure 24 This is a schematic diagram illustrating phenomena that may occur during the heat treatment process according to the third embodiment of the present invention.

[0042] Figure 25 This is a side cross-sectional schematic diagram of the connection body between the mask and the support according to the fourth embodiment of the present invention.

[0043] [Explanation of Labels in the Attached Image]

[0044] 10: Connector between the mask and the support

[0045] 20: Mask

[0046] 30: Support section

[0047] 31: Edge

[0048] 33, 35: First grid section, second grid section

[0049] 40: Connecting part

[0050] 50: Deformation-resistant part

[0051] 1000: OLED pixel deposition device

[0052] C, SR, DM: Unit section, division section, virtual section

[0053] H: Heat treatment

[0054] P: Mask pattern

[0055] PS: Flattening

[0056] TR, DTR: Groove section, Dummy groove section Detailed Implementation

[0057] The present invention will now be described in detail with reference to the accompanying drawings, which illustrate examples of specific embodiments in which the invention may be practiced. These embodiments are described in detail to enable those skilled in the art to fully implement the invention. Various embodiments of the invention should be understood to be different from each other but not mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented as other embodiments without departing from the spirit and scope of the invention. Furthermore, the position or arrangement of individual components in each disclosed embodiment should be understood to be subject to change without departing from the spirit and scope of the invention. Therefore, the following detailed description is not intended to limit the invention; the scope of the invention is defined only by the appended claims and all their equivalents, provided that it can be properly explained. Similar reference numerals in the drawings denote the same or similar functions in various respects, and for convenience, lengths, areas, thicknesses, etc., and their shapes may be exaggerated.

[0058] Hereinafter, in order to enable those skilled in the art to readily implement the present invention, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0059] Figure 1 This is a schematic diagram of the connection body 10 between the mask and the support portion according to an embodiment of the present invention. Figure 2 yes Figure 1 A schematic diagram of the side section of A-A'. Figure 3 These are top views and side cross-sectional views of a mask 20 according to an embodiment of the present invention, specifically E-E'. Figure 4 This is a top view of the support portion 30 according to an embodiment of the present invention.

[0060] Recently, the microdisplays used in VR (virtual reality) devices can display targets such as semiconductor wafers and silicon wafers up to 1900 (refer to...) Figure 21 Instead of using a large substrate for pixel deposition, microdisplays, because the image is placed in front of the user, have a screen size of approximately 1 to 2 inches compared to large-area displays. Furthermore, due to their proximity to the user's eyes, higher resolution is necessary.

[0061] Therefore, the object of the present invention is to provide a mask and support connector 10 and a method for manufacturing the same, which is not used in a pixel formation process on a large-area target substrate with a side length exceeding 1000m, but in a pixel formation process on a semiconductor wafer target substrate 1900 of 200mm, 300mm, or 450mm and can form ultra-high quality pixels.

[0062] For example, current QHD image quality achieves a pixel size of approximately 30 to 50 μm with a PPI of 500 to 600. For 4K UHD and 8K UHD high-definition images, even higher resolutions are achieved, such as 860 PPI or 1600 PPI. Microdisplays directly applied to VR devices or inserted into VR devices aim for ultra-high image quality of approximately 2000 PPI or higher, with pixel sizes of approximately 5 to 10 μm. Semiconductor wafers and silicon wafers, by utilizing technologies developed in semiconductor processes, can undergo finer and more precise processes compared to glass substrates, thus enabling their use as substrates for high-resolution microdisplays. The present invention is characterized by providing a connector 10 for a mask and support portion that can be formed on these semiconductor wafers.

[0063] Reference Figure 1 and Figure 2 The present invention is characterized in that, in order to use a semiconductor wafer as a target substrate 1900 (refer to...) Figure 21 In the pixel deposition process, the mask 20 has a shape corresponding to the semiconductor wafer (or silicon wafer). It should be noted that "the shape of the mask 20 corresponding to the semiconductor wafer" means that the mask 20 and the semiconductor wafer have the same size and shape, or although they have different sizes and shapes, they are at least coaxial, and this even includes a state where the mask pattern P is arranged within the shape of the semiconductor wafer. Another feature is that the mask 20 corresponding to the shape of the semiconductor wafer is integrally connected to the support portion 30, which acts as a frame, thereby ensuring accurate mask alignment.

[0064] The connector 10 between the mask and the support may include a mask 20 and a support 30. The mask 20 may be connected to one side of the support 30. The support 30 can serve as a frame for supporting the mask 20.

[0065] Reference Figures 1 to 3The mask 20 may include unit parts C, dividing parts SR, and dummy parts DM. The portion of the mask 20 that does not contact the support part 30 and forms the mask pattern P is designated as unit part C; the portion arranged between unit parts C is designated as dividing parts SR; and the portion attached to the support part 30 is designated as dummy part DM. Unit parts C, dividing parts SR, and circular dummy parts DM are designated with different names and reference numerals depending on their formation location. However, unit parts C, dividing parts SR, and dummy parts DM are not separate areas but are made of the same material and integrally connected. In other words, unit parts C, dividing parts SR, and circular dummy parts DM are parts of the mask 20 formed simultaneously during the electroforming process. In the following description, unit parts C, dividing parts SR, and dummy parts DM may be used interchangeably with mask 20.

[0066] The mask 20 is preferably made of Invar or SuperInvar alloy. Alternatively, the mask 20 may also be made of nickel (Ni), cobalt (Co), titanium (Ti), chromium (Cr), tungsten (W), molybdenum (Mo), or a combination thereof, or an electroformable alloy capable of forming a support portion 30′ (or a conductive substrate 30′, see reference). Figure 5 The mask 20 may be a metallic material containing silicon and silicides. Alternatively, the mask 20 may also include a superinvar alloy containing Co in a ternary or higher configuration. The mask 20 may be circular to correspond to a circular semiconductor wafer. The mask 20 may have a size equal to or greater than that of a semiconductor wafer, such as 200 mm, 300 mm, or 450 mm.

[0067] To accommodate large-area substrates, existing photomasks come in quadrilateral and polygonal shapes. Furthermore, to correspond with these masks, frames also have quadrilateral or polygonal shapes. Since the mask includes angular corners, there is a problem of stress concentration at the corners. This stress concentration causes only a portion of the mask to be subjected to different forces, potentially leading to mask distortion or deformation, which further results in pixel alignment failure. In particular, stress concentration at the mask corners should be avoided in ultra-high image quality exceeding 2000 PPI.

[0068] Therefore, a key feature of this invention is that the mask 20 is circular in shape, excluding corners. That is, the dummy portion DM of the mask 20 is circular in shape, excluding corners. Because it lacks corners, the problem of applying different forces to specific parts of the mask 20 can be solved, allowing pressure to be evenly distributed along the circular edge. Therefore, the mask 20 does not twist or deform, which helps in accurate pixel alignment and has the advantage of achieving mask patterns P with a PPI of 2000 or higher. This invention achieves pixel deposition of approximately 5 to 10 μm by corresponding a circular semiconductor wafer (or silicon wafer) with a low coefficient of thermal expansion and performing a pixel deposition process with a circular mask 20 where pressure is evenly distributed along the edge.

[0069] The unit section C can be formed with multiple mask patterns P. Each mask pattern P has multiple pixel patterns P corresponding to R, G, and B. The sides of the mask patterns P can be oblique, tapered, or gradually widening from top to bottom. A large number of mask patterns P are clustered together to form a display unit section C. The display unit section C is a display area with a diagonal length of approximately 1 to 2 inches. Alternatively, the display unit section C can also be an area corresponding to multiple displays.

[0070] The mask pattern P can have a roughly conical shape, and the pattern width can be several to tens of μm, preferably about 5 to 10 μm (resolution above 2000 PPI).

[0071] The mask 20 may include multiple unit parts C. The multiple unit parts C may be arranged at a predetermined interval in a first direction (x-axis direction) and a second direction perpendicular to the first direction (y-axis direction). Figure 1 The illustration shows twenty-one unit sections C arranged along a first direction and a second direction, but is not limited to this. Dividing sections SR may be arranged between the unit sections C. The unit sections C and the dividing sections SR are portions arranged at the center of the mask 20, not the dummy section DM.

[0072] The dummy part DM has a circular edge or a shape corresponding to a semiconductor wafer, and can define the appearance shape of the mask 20. The dummy part DM can be connected to the support part 30. Specifically, the dummy part DM can be attached to at least a portion of the edge part 31 of the support part 30. The dummy part DM and the edge part 31 can be attached to each other based on the connection part 40 formed between them.

[0073] Reference Figure 1 , Figure 2 and Figure 4The support portion 30 may include an edge portion 31, a plurality of first grid portions 33, and a plurality of second grid portions 35. Although the edge portion 31, first grid portions 33, and second grid portions 35 are designated with different names and reference numerals, they are not separate areas but are made of the same material and integrally connected. In the following description, the edge portion 31, first grid portions 33, and second grid portions 35 may be used interchangeably with the support portion 30.

[0074] The support portion 30 is preferably made of silicon; more preferably, the support portion 30 may be formed of a silicon wafer and may be made of monocrystalline silicon. In order to be compatible with the target substrate 1900 (see reference 1900)... Figure 21 Corresponding to a circular semiconductor wafer, the edge portion 31 of the support portion 30 can be circular in shape. In order to connect the mask 20 to the upper part, the support portion 30 can be at least larger than or equal to the shape of the mask 20.

[0075] The edge portion 31 can define the external shape of the support portion 30. The edge portion 31 can be circular. Other shapes are also possible as long as they facilitate electroforming of the mask 20 and the support portion 30 corresponds to the semiconductor wafer and can be used for OLED pixel processes.

[0076] Multiple first grid sections 33 extend in a first direction and are connected at both ends to edge sections 31. Furthermore, multiple second grid sections 35 extend in a second direction different from the first direction and intersect with the first grid sections 33, and are also connected at both ends to edge sections 31. For example, the first direction is the x-axis direction, and the second direction is the y-axis direction; the first and second directions may be perpendicular to each other. The first grid sections 33 are spaced apart and arranged parallel to each other, and the second grid sections 35 are also spaced apart and arranged parallel to each other. Moreover, the first grid sections 33 and second grid sections 35 intersect, and the intersecting portions form a mesh-like free space CR. This free space CR serves as the space for arranging the unit sections C of the mask 20 and is referred to as the unit region CR (see reference). Figure 4 ).

[0077] The thickness of the support portion 30 can be greater than the thickness of the mask 20. To achieve a mask pattern P with a resolution higher than 2000 PPI (pixels per inch), the mask 20 can be formed with a thickness of approximately 2 μm to 12 μm. If the thickness of the mask 20 is greater than this, it may be difficult to ensure that the width or spacing of the mask pattern P, which has an overall tapered shape, meets the required resolution.

[0078] The support portion 30 has the rigidity to support the mask 20, and considering the ease of forming the edge portion 31 and the grid portions 33, 35, the reduction of shadow effects, and the maneuverability, it can be formed with a thickness of about 50 μm to 200 μm.

[0079] As an example, the edge portion 31 and the first grid portion 33 / second grid portion 35 in the support portion 30 can have the same thickness. By thinning the silicon wafer, the thickness of the edge portion 31, the first grid portion 33 and the second grid portion 35 can be approximately 50 μm to 200 μm.

[0080] As another example, the thickness of the edge portion 31 in the support portion 30 can be greater than the thickness of the first grid portion 33 / second grid portion 35. The edge portion 31 acts as a frame on the connector 10 between the mask 20 and the support portion 30, having rigidity to support the mask 20, and its thickness can be greater than that of the first grid portion 33 and the second grid portion 35 to prevent the support portion 30 from deforming or bending as a whole. As an example, when a silicon wafer is used directly, the thickness of the edge portion 31 can be approximately 700 μm to 1000 μm, and when the predetermined thickness is reduced, it can be approximately 500 μm to 1000 μm.

[0081] The thickness of the first grid portion 33 and the second grid portion 35 is at least sufficient to support the mask 20, and a unit region CR for allowing organic matter 1600 to pass through is required between the first grid portion 33 and the second grid portion 35 (refer to...). Figure 4 To prevent the organic material 1600 from exhibiting a shadow effect based on the thickness of the first grid portion 33 and the second grid portion 35, it is preferable that the thickness is greater than that of the mask 20 and less than that of the edge portion 31. As an example, the thickness of the first grid portion 33 and the second grid portion 35 can be approximately 50 μm to 200 μm.

[0082] Furthermore, the mask-support connector 10 of the present invention is characterized in that at least a portion of the mask 20 is arranged in a groove TR formed by the recess of the support 30. The groove TR has two side surfaces SS [ref]. Figure 5 In the state of ], it can be a trench formed by depression. It can be understood that it also includes a step shape formed by depression in the state of having only one side SS. Figure 2 The mask and support connector 10:10-1 shows an example of a groove portion TR having a lower surface 37a and a side surface 37b and being in the form of a step 37. Furthermore, Figure 20 (b) shows an example of a second grid section 35 having a groove section with a tapered sloping shape on the side.

[0083] From another perspective, it is understandable that in the mask and support connector 10 of the present invention, the upper surface of the support 30 and the upper surface of the mask 20 are located on the same horizontal plane. A portion of the mask 20 is arranged in the groove TR formed by the recess of the support 30, so that the upper surfaces of the support 30 and the mask 20 have the same horizontal plane. In particular, referring to... Figure 2The dummy part DM of the mask 20 and the edge part 31 of the support part 30 can share the same upper surface.

[0084] As described above, the connector 10 between the mask and the support portion arranges or accommodates at least a portion of the mask 20 in the groove portion TR of the support portion 30, thereby enabling the groove portion TR to more firmly anchor the mask 20. As a result, the alignment of the mask 20 and the alignment of the mask pattern P / unit portion C can be more accurate, thereby enabling ultra-high image quality pixels.

[0085] Re-reference Figure 2 A connecting portion 40 may be sandwiched between the mask 20 and the support portion 30. The connecting portion 40 may be formed on the lower surface BS and the side surface SS of the groove portion TR [ref]. Figure 5 At least a portion of the support portion 30 is between the support portion 30 and the mask 20. The mask 20 can be connected to the support portion 30 by means of a clamping connection portion 40. The edge portion 31 of the support portion 30 can be connected to the dummy portion DM of the mask 20, and the first grid portion 33 and the second grid portion 35 of the support portion 30 can be connected to the dividing portion SR of the mask 20. That is, the dividing portion SR can be supported on the first grid portion 33 and the second grid portion 35.

[0086] According to one embodiment, the connecting portion 40 can be heat-treated H (refer to the above) while the mask 20 is stacked on the support portion 30. Figure 8 The connecting portion 40 can be provided as an intermetallic compound synthesized from the components of the mask 20 and the support portion 30. Through the synthesis of the Fe and Ni components of the mask 20 and the Si component of the support portion 30, the connecting portion 40 can be provided as a silicide containing Ni and Si, or containing Fe, Ni and Si, or containing Fe and Ni. Based on the bonding force of the intermetallic compound, the mask 20 and the support portion 30 can be connected to each other by clamping the connecting portion 40.

[0087] Furthermore, according to one embodiment, in order to form the mask 20 onto the support portion 30 with higher adhesion, the connecting portion 40 may further include an adhesion layer [or an auxiliary connecting portion (not shown)] serving as an adhesion medium. For example, when the support portion 30 is a silicon wafer, compared to a mask 20 made of Invar alloy, super Invar alloy, or similar materials being directly bonded to the support portion 30, a state where an auxiliary connecting portion made of Ni, Cu, or similar materials is used as a medium for bonding exhibits higher adhesion. Therefore, the auxiliary connecting portion may include at least one of Ni, Cu, Ti, Au, Ag, Al, Sn, In, Bi, Zn, Sb, Ge, and Cd. To enhance the adhesion between the support portion 30 and the mask 20, or between the support portion 30 and the connecting portion 40, the auxiliary connecting portion is preferably sandwiched with a relatively thin thickness. To ensure that the electromagnetic field formed for electroforming the mask 20 onto the support portion 30 is not affected, the auxiliary connecting portion may be formed with a relatively thin thickness of 0.01 μm to 0.2 μm. Within the aforementioned thickness range, the electromagnetic field forming channel used in electroforming can simultaneously provide a thickness for enhancing adhesion.

[0088] The connecting portion 40 may be formed on the lower surface of the mask 20 or on the side surface between the mask patterns P. Alternatively, the connecting portion 40 may be partially or completely removed during the formation of the edge portion 31, the first grid portion 33, and the second grid portion 35 on the support portion 30. For ease of explanation, Figure 2 and Figure 3 The thickness of the connecting portion 40 is exaggerated in the illustration. The connecting portion 40 has a very thin thickness [less than 1 μm, preferably less than 0.1 μm] compared to the thickness of the mask 20 or the width of the mask pattern P. Even if part or all of the connecting portion 40 is removed, it will hardly affect the thickness of the mask 20 or the width of the mask pattern P.

[0089] Furthermore, like the mask 20, the support portion 30 also has a rounded edge, eliminating corners and thus resolving the issue of applying different forces to specific parts of the support portion 30. Additionally, pressure can be evenly distributed along the rounded edge. Therefore, the support portion 30 helps prevent twisting or deformation. Connecting a circular mask 20 to this circular support portion 30 doubles the pressure distribution effect. Moreover, the first grid portion 33 and the second grid portion 35 of the support portion 30 are arranged below the dividing portion SR of the mask 20, providing overall support for the mask 20 and preventing sagging of the unit portion C and the dividing portion SR in the very thin mask 20. As a result, the mask 20 and the support portion 30 do not twist, and accurate pixel alignment is facilitated, achieving a high resolution of over 2000 PPI.

[0090] Additionally, refer to again Figure 3The crystal orientation CO of the 100-facet or 111-facet of the silicon wafer may not be parallel to the length direction of the first grid portion 33 or the second grid portion 35. The first grid portion 33 and the second grid portion 35 are formed along the X-axis or Y-axis direction, and the crystal orientation CO of the 100-facet or 111-facet of the silicon wafer of the support portion 30 may have a preset angle other than 0° or 180°, and is not parallel to the X-axis or Y-axis direction (0° or 180° angle). From another perspective, the crystal orientation CO of the 100-facet or 111-facet of the silicon wafer may be at a preset angle other than 0° or 180° with the direction in which multiple unit portions C are arranged, i.e., the X-axis or Y-axis direction. Compared to other crystallization directions, silicon wafers are more likely to break along the 100 or 111 crystallization direction. By arranging the unit portion C and the dividing portion SR of the mask 20 corresponding to the first grid portion 33 and the second grid portion 35 in a way that is staggered from the crystallization direction CO, it has the advantages of reducing the risk of breakage of the connector 10 between the mask 20 and the support portion 30 and increasing the overall rigidity.

[0091] Figures 5 to 11 This is a schematic diagram illustrating the manufacturing process of the mask and support connector 10 according to the first embodiment of the present invention. Although the following illustration shows the form of the mask and support connector 10-2 with the mask 20 arranged on the upper surface of the edge portion 31, it should be noted that this manufacturing process also includes manufacturing... Figure 2 The process shown is to form a groove in the shape of a step 37 on the edge portion 31 and to arrange a mask and support in the shape of a mask 20 on its upper part.

[0092] Reference Figure 5 Prepare the support portion 30'. To enable electroforming, the support portion 30' can be a conductive substrate 30' made of a conductive material. To achieve both conductivity and low resistance, a 10-fold [electroforming process] can be performed on the support portion 30' (or the conductive substrate 30'). 19 cm- 3 The above-mentioned high concentration of doping. Doping can be performed on the entire support portion 30' or only on the surface portion of the support portion 30'. According to one embodiment, the surface resistivity of the support portion 30' can be 5 × 10⁻⁶. -4 Up to 1×10 -2 ohm·cm. The support part 30′ can be used as a cathode electrode during the electroforming process.

[0093] Unlike metals with metal oxides on their surface or polycrystalline silicon with grain boundaries, doped monocrystalline silicon, due to the absence of defects, has the advantage of forming a uniform electromagnetic field across its surface during electroforming, enabling the formation of a uniform electroplated film (or mask 20). The mask 20, made from a uniform electroplated film, can further improve the image quality of OLED pixels. Furthermore, it eliminates the need for additional processes to remove or eliminate defects, resulting in reduced processing costs and increased production efficiency.

[0094] Then, a patterned insulating portion M1 can be formed on one side of the support portion 30'. The insulating portion M1, as a protruding (bump) portion formed on one side of the support portion 30', can have insulating properties to prevent the formation of an electroplated film (or mask 20). Therefore, the insulating portion M1 can be formed from any one of photoresist, silicon oxide, or silicon nitride. The insulating portion M1 can be formed on the support portion 30' by deposition or other methods. Thermal oxidation and thermal nitridation methods can also be used with the support portion 30' as a substrate. Photoresist can also be formed by printing or other methods.

[0095] The width md of the insulating portion M1 can correspond to the upper width of the mask pattern P. The upper width of the mask pattern P, serving as the end portion through which the organic material 1600 passes during OLED pixel deposition, determines the pixel resolution. When aiming for ultra-high image quality at approximately 2000 PPI or higher, the pixel size is approximately 5-10 μm; therefore, the width md of the insulating portion M1 can also be approximately 5-10 μm. Furthermore, as described later, by forming a trench TR in the support portion 30', the insulating portion M1 can be formed with a relatively thin thickness within the range used to form the trench TR. Considering that the trench TR corresponds to the thickness of the mask 20 (approximately 2-12 μm), the insulating portion M1 can be formed with a relatively thin thickness of approximately 0.5-2 μm. Therefore, it has the advantage of easily forming the insulating portion M1 and reducing material usage.

[0096] Then, EC1 can be etched onto the support portion 30'. EC1 can be etched onto the surface of the first side (or top side) of the support portion 30' exposed between the patterns of the insulating portion M1. EC1 can be etched using either dry etching or wet etching. Wet etching has the advantage of unidirectional etching characteristics, while dry etching has the advantage of anisotropic characteristics and the ability to precisely etch to the desired width. Alternatively, laser etching using femtosecond or picosecond lasers, which allows for precision etching, can also be performed. For laser etching, the process of forming the first insulating portion M1 can be omitted.

[0097] Based on etching EC1, a recessed trench TR can be formed on the first surface (or top surface) of the support portion 30'. The depth h of the trench TR can approximately correspond to the thickness of the mask 20 to be formed. As an example, the depth h of the trench TR can be approximately 2~12 μm.

[0098] Multiple groove portions TR can be formed by patterning. The groove portions TR can be reverse-formed on the support portion 30' corresponding to the unit portion C, corresponding to the mask pattern P. In other words, the portion of the unit portion C where the groove portions TR are not formed can later be used as the mask pattern P. On the support portion 30' corresponding to the dummy portion DM, as shown... Figure 2 As shown, grooves in the form of steps 37: 37a, 37b can also be formed, as well as grooves TR with two sides, or grooves TR can be omitted. Grooves TR are not formed on the support portion 30′ corresponding to the dividing portion SR, or they can be formed as shown... Figure 19 and Figure 20 The dummy trench section DTR is shown.

[0099] The trench portion TR may include a lower surface BS and a side surface SS. The side surface SS may be tilted to have a vertical or preset angle. When using wet etching EC1, since wet etching has the characteristic of unidirectional etching, the side surface SS may be tilted to have a preset angle. That is, the side surface SS of the trench portion TR may be formed in a tapered shape. Considering the crystal orientation of the support portion 30' of the monocrystalline silicon material, the tapered angle of the trench portion TR may be formed to correspond to the etching direction during etching.

[0100] Then, refer to Figure 6 Electroforming can be performed on the support portion 30' to form a mask 20': 20'a. The support portion 30' is used as a cathode, and an anode (not shown) is prepared opposite it. The anode (not shown) can be immersed in a plating solution (not shown), and the support portion 30' can be fully or partially immersed in the plating solution (not shown). Since the insulating portion M1 has insulating properties, an electroplated film may not be formed on the portion corresponding to the insulating portion M1. In particular, an electroplated film is formed in the trench portion TR to form the mask 20'. The mask 20' is formed with a thickness that fills the trench portion TR and does not exceed the upper part of the insulating portion M1. In other words, the mask 20' can be electroformed so that the upper end of the mask 20' is higher than the height of the first surface (or upper surface) of the support portion 30' and lower than the height of the upper end of the insulating portion M1.

[0101] Furthermore, to ensure that the mask 20′ has a similar coefficient of thermal expansion (CTE) to the silicon material of the support portion 30′, its composition can be controlled. In the connector 10 between the mask and the support portion, the support portion 30 acts as a framework for the silicon material. The mask 20 should have a similar coefficient of thermal expansion to the support portion 30 to prevent sagging of the mask 20 on the support portion 30, which serves as the framework. Additionally, the alignment error (PPA) between the unit portion C and the mask pattern P can be minimized on the support portion 30.

[0102] Therefore, in order to make the coefficient of thermal expansion of the silicon support portion 30′ and the mask 20′ after heat treatment H (described later) approximately (3.5±1)×10⁻⁶, -6 The composition of mask 20' can be controlled at a temperature of / ℃. Even for mask 20' made of Invar alloy, it can be electroformed with different Fe and Ni ratios to control the coefficient of thermal expansion to a level that is closest to the silicon support portion 30'. Alternatively, in order to ensure that mask 20' is tightly connected to support portion 30' according to process temperature conditions, the coefficient of thermal expansion of mask 20' can be controlled to be greater than or less than the coefficient of thermal expansion of support portion 30'.

[0103] Furthermore, during the heat treatment H and etching EC2 processes described later, the mask 20′ formed by electroforming should be firmly bonded to the support portion 30′ without peeling off. Several solutions can be considered for this purpose.

[0104] As one approach, firstly, the native oxide of the support portion 30' undergoing electroforming can be controlled. An oxide can be formed on the surface of the support portion 30' made of silicon wafer material. Because a uniform electromagnetic field cannot be generated on the surface of this oxide, the electroplated film (mask 20') cannot be formed uniformly, and the adhesion between the formed electroplated film (mask 20') and the support portion 30' remains low. Therefore, the electroforming process is preferably performed after the process of removing the native oxide.

[0105] As an alternative, another film can be further formed between the electroplated film (mask 20') and the support portion 30' as an adhesive medium. In addition to the barrier film described later, films or combinations of films with adhesive strength on both sides can be used.

[0106] As an alternative, the surface of the support portion 30' can be pretreated before electroforming. Physical or chemical treatments can be used to ensure that the electroplated film (mask 20') formed during the electroforming process adheres more strongly to the support portion 30'. Furthermore, by controlling the gold plating method during the electroforming process, the electroplated film (mask 20') can be made to have strong adhesion when formed on the support portion 30'.

[0107] Additionally, refer to Figure 7 To ensure that the mask 20′:20′b has a similar coefficient of thermal expansion to the silicon material of the support 30′, the mask layer 20′b can be composed of a stack of at least two electroplated layers. In this case, the first mask layer 23′ can be formed of a metallic material capable of forming a silicide with the support 30′. When the first mask layer 23′ is formed by electroforming, it can be formed of materials with high adhesion to the support 30′, such as Ni, Co, Ti, Cr, W, and Mo. When the second mask layer 21′ is formed by electroforming, it can be formed of materials with low coefficients of thermal expansion, such as Invar alloys or super Invar alloys. Since the first and second mask layers have different coefficients of thermal expansion, the coefficient of thermal expansion of the mask 20′ can be controlled by adjusting the thickness ratio of the first and second mask layers. The thickness ratio of the first and second mask layers can be controlled by adjusting the electroforming time.

[0108] Furthermore, during electroforming, by adjusting the current density, the masks 20' and 20'b can form at least two layers with different compositions. For example, the mask 20'b may include a first mask layer 23' of pure Ni or a Ni-rich alloy layer and a second mask layer 21' of an Invar alloy layer. First, by applying a first current density, the first mask layer 23' can be formed on at least a portion of the lower surface BS and the side surface SS of the trench TR. The first mask layer 23' is pure Ni or an alloy layer containing more than 60 wt% Ni. Then, by applying a second current density different from the first current density, the second mask layer 21' can be formed on the first mask layer 23'. The second mask layer 21' is an FeNi alloy layer (Invar layer) containing 36 wt% to 42 wt% Ni. The second current density may be less than the first current density. For example, if the first current density is applied in an electroplating bath environment capable of forming an FeNi alloy, a Ni-rich layer can be electroplated; as the current density changes to the second current density, a layer with an increased Fe proportion can be electroplated.

[0109] However, the thickness of the first mask layer 23′ should be less than the thickness of the second mask layer 21′. The first mask layer 23′ is preferably formed to ensure a certain degree of adhesion to the support portion 30′ in order to align with the second mask layer 21′, which has a lower coefficient of thermal expansion. Therefore, the thickness of the first mask layer 23′ is preferably 2% to 20% of the thickness of the second mask layer 21′.

[0110] The Ni in the first mask 23' is more conducive to silicide formation when heat-treated at a relatively low temperature below Invar. Furthermore, the Ni in the first mask 23' has excellent adhesion to Invar, thus acting as an adhesive medium between the silicon material support portion 30' and the second mask 21'. Moreover, it has the advantage of being able to form silicides by clamping a Ni-rich first mask 23' and heat-treating it at a temperature below 400°C [ref]. Figure 8 The advantages of forming the connecting part 40.

[0111] As another example, mask 20'b can be configured with a lower layer and an upper layer containing pure Ni or Ni-rich alloy layers, and an Invar alloy layer sandwiched in the middle layer. In this case, during electroforming, by applying a first current density, a lower layer (first mask layer) can be formed on at least a portion of the lower surface BS and side surface SS of the trench portion TR by applying a first current density. An intermediate layer (second mask layer) can be formed by applying a FeNi alloy layer (Invar layer) containing 36 wt% to 42 wt% Ni by applying a second current density different from the first current density. An upper layer (third mask layer) can be formed by applying a first current density (or a third current density) different from the second current density. The second current density can be less than the first current density (or the third current density). The thickness of the third mask layer can correspond to the thickness of the first mask layer.

[0112] At this point, the upper layer, consisting of pure Ni or an alloy layer containing more than 60 wt% Ni, contains more Ni than the FeNi alloy layer (Invar layer), thus offering the advantage of reduced oxidation during the heat treatment process H described later. Furthermore, in the planarization PS process described later, removing the upper layer first offers the advantage of protecting the intermediate layers.

[0113] in addition, Figure 6 and Figure 7Before electroforming the masks 20': 20'a, 20'b, auxiliary connecting portions (not shown) can be further formed on at least a portion of the trench portion TR. For example, when the support portion 30 is a silicon wafer, compared to a mask 20 made of Invar alloy, super Invar alloy, or similar materials being directly bonded to the support portion 30, a state where the connecting portion 40, made of materials such as Ni or Cu, is used as a medium for bonding exhibits higher adhesion. Therefore, the auxiliary connecting portion may contain at least one of Ni, Cu, Ti, Au, Ag, Al, Sn, In, Bi, Zn, Sb, Ge, and Cd. When the material of the auxiliary connecting portion is not easily electroformed, it can be formed by sputtering or brazing. When the auxiliary connecting portion is formed by electroforming, it can be formed from materials such as Ni, Cu, Ti, Au, Ag, and Al, which have high adhesion to the support portion 30'. Alternatively, when the auxiliary connection is formed by sputtering or brazing, it can be made of materials such as Sn, In, Bi, Zn, Sb, Ge, and Cd, which have high adhesion to the support portion 30′. The auxiliary connection can be formed with a relatively thin thickness of 0.01 μm to 0.2 μm.

[0114] Then, refer to Figure 8 The mask 20' and support 30' can be heat-treated H. Before or after heat treatment H, the insulation part M1 can be removed. The heat treatment can be performed at temperatures ranging from 100°C to 800°C. For example, ... Figure 6 When the mask 20' is formed directly on the support portion 30', heat treatment can be performed at a temperature of 300°C to 800°C. As another example, such as... Figure 7 As shown, when the first mask layer 23′ is formed between the second mask layer 21′ and the support portion 30′, the heat treatment H can be performed at a temperature of about 100°C to 800°C, more preferably, at a low temperature range of about 100°C to 400°C. During the heat treatment H, a preset pressure can also be applied to perform the heat treatment with less heat.

[0115] Typically, Invar alloy sheets formed by electroforming have a higher coefficient of thermal expansion than those formed by rolling. Therefore, heat treatment of the Invar alloy sheet can reduce the coefficient of thermal expansion, but this heat treatment process can also cause some deformation. If only the separately existing mask 20 is heat-treated, some deformation may occur in the mask pattern P. Therefore, if heat treatment H is performed while the support 30' is bonded to the mask 20', it is possible to prevent minor deformation of the mask pattern P caused by heat treatment.

[0116] Furthermore, in this invention, the mask 20' is adapted to be accommodated within the groove TR formed by the recess of the support portion 30'. If heat treatment H is performed in this state, a special effect is achieved where the side surface SS and the lower surface BS of the groove TR prevent deformation of the mask 20' in the horizontal direction. Furthermore, in this invention, by accommodating the mask 20' within the groove TR, the contact area between the support portion 30' and the mask 20' is further ensured, which facilitates the formation of the connecting portion 40 based on heat treatment H.

[0117] Furthermore, the coefficients of thermal expansion of the Invar alloy sheet and the silicon wafer produced by electroforming are almost the same, approximately 3 to 4 ppi. Therefore, even when heat treatment H is performed, since the thermal expansion of the mask 20′ and the support 30′ is almost the same, misalignment due to expansion will not occur, thus preventing minor deformation of the mask pattern P.

[0118] Furthermore, a feature of this invention is that the mask 20′ and the support portion 30′ are connected by a heat treatment H. During the heat treatment H, a connection portion 40 can be formed between the mask 20′ and the support portion 30′. The connection portion 40 can be provided as an intermetallic compound synthesized from the components of the mask 20′ and the support portion 30′. As the Fe and Ni components of the mask 20′ and the Si components of the support portion 30′ are synthesized, the connection portion 40 can be provided as a silicide containing Ni and Si, or containing Fe, Ni and Si, or containing Fe and Ni. Based on the bonding force of the intermetallic compound, the mask 20′ and the support portion 30′ can be connected to each other by clamping the connection portion 40.

[0119] Furthermore, according to one embodiment, the heat treatment H process can be performed in multiple steps. As a 2-step heat treatment, Ni2Si is formed in a low-temperature region (approximately 250 to 350°C), and the mask 20 is bonded to the support 30', followed by gradual heating to a high-temperature region (approximately 450 to 650°C) and heat treatment. Since the Invar alloy mask formed by electroforming has a microcrystalline and / or amorphous structure, rapid heating during heat treatment can cause the Invar alloy mask to detach or separate from the silicon wafer support 30' due to volume shrinkage. Therefore, it is preferable to bond the Invar alloy mask to the silicon wafer support 30' at a low temperature, and then gradually heat to a high temperature for heat treatment.

[0120] Furthermore, according to one embodiment, a reducing atmosphere should be maintained during heat treatment H. The reducing atmosphere can be H2, Ar, or N2; preferably, dry N2 gas is used to prevent oxidation of the Invar alloy mask. To prevent oxidation of the Invar alloy mask, the O2 concentration needs to be controlled to be less than 100 ppm. Alternatively, a vacuum atmosphere of less than 10⁻² torr can be formed. Heat treatment H can be performed for 30 minutes to 2 hours.

[0121] By forming an adhesive layer of Ni silicide, (Ni, Fe)Si silicide, etc., on the interface of the mask 20' formed on the silicon wafer support 30' by electroforming, the mask 20' and the support 30' can be connected by clamping the adhesive layer 40.

[0122] In addition, to control the reaction between Ni, Fe-Ni, and Si during heat treatment H, a barrier film (not shown) can be formed on the support portion 30' before electroforming the mask 20'. The barrier film prevents uncontrolled penetration of components of the electroplated film from the mask 20' (for example, Ni, Fe-Ni) into the silicon support portion 30'. Furthermore, to enable electroplating on the surface, the barrier film preferably has electrical conductivity. Therefore, the barrier film can comprise materials such as titanium nitride (TiN), titanium or titanium nitride (Ti / TiN), tungsten carbide (WC), tungsten titanate (WTi), and graphene. Thin film formation processes such as barrier film deposition can be used without restriction. The barrier film can form a uniform silicide by controlling the reaction between Fe, Ni, and Si, and utilize appropriate adhesion to allow the mask 20 and the connector 40 to adhere. Furthermore, the barrier film may be composed of a film or a combination of films, which, when the mask 20' is electroformed onto the support 30', provide a preset adhesive force or adhesion force so that the mask 20' and the support 30' do not separate.

[0123] The thickness (silicide thickness) of the connecting part 40 can be controlled between 10 and 300 nm by adjusting the temperature and time to connect the support part 30′ and the mask 20′.

[0124] Furthermore, when the aforementioned auxiliary connecting portion (not shown) is further sandwiched, during the heat treatment H, the auxiliary connecting portion between the mask 20' and the support portion 30' acts as a connecting medium between the mask 20' and the support portion 30' through a phase transformation based on the melting into a liquid state and then resolidifying into a solid state during heat treatment. The auxiliary connecting portion can be used as an adhesion layer or a glue layer. From another perspective, the metal composition of the auxiliary connecting portion can diffuse into the mask 20' and the support portion 30', or conversely, the composition of the mask 20' and the support portion 30' can diffuse into the auxiliary connecting portion, or the composition can diffuse into each other, thereby changing the interface state of the mask 20', the support portion 30', and the auxiliary connecting portion and achieving connection.

[0125] In addition, considering the connection strength between the mask 20' and the support 30', the heat treatment process can be omitted.

[0126] Then, refer to Figure 9 The mask 20' can be planarized (PS). Planarization (PS) refers to simultaneously mirroring one side (top) of the mask 20' and removing a portion of the upper part of the mask 20', thereby reducing its thickness (20'->20). Planarization (PS) can be achieved using methods such as lapping, polishing, and buffing.

[0127] After planarization (PS), the mask 20 and the support portion 30' can at least share the same upper surface. The mask 20 is planarized (PS) in the groove portion (TR) state that is recessed and accommodated in the support portion 30', so that the upper surface can be shared with the support portion 30'.

[0128] in addition, Figure 8 Heat treatment H and Figure 9 The order of planarizing the PS can be reversed. First, the mask 20' can be planarized and its thickness reduced (20'->20), and then the connecting part 40 can be generated by heat treatment H.

[0129] Then, refer to Figure 10 The support portion 30' can be etched EC2. The EC2 etching can be performed on the reverse side (second side) of the first (top) surface of the support portion 30' connected to the mask 20. The EC2 etching can be performed on the portion of the support portion 30' corresponding to the unit portion C of the mask 20. The portion corresponding to the dividing portion SR of the mask 20 may not be etched. Optionally, before etching EC2 on the support portion 30', a thickness reduction process can be performed on all or the center of the lower surface (second surface) of the support portion 30'.

[0130] The support portion 30 after EC2 etching can be shaped to include an edge portion 31, a first grid portion 33, and a second grid portion 35. To clearly present the edge portion 31, the first grid portion 33, and the second grid portion 35 on the support portion 30, EC2 etching is preferably performed using a dry etching method with anisotropic etching characteristics. Since the support portion 30′ is a silicon wafer, existing semiconductor-related technologies and MEMS (Micro-Electro Mechanical Systems)-related technologies can be used to etch EC2.

[0131] To impart etching resistance, an insulating portion M2 can be formed on the lower surface of the support portion 30', except for the portion corresponding to the unit portion C. The insulating portion M2 can be photoresist formed by printing methods, or it can be silicon oxide or silicon nitride formed by methods such as thermal oxidation or thermal nitridation, acting as a hard mask. Alternatively, a metal acting as a mask can be used during etching. The exposed portions of the lower surface of the support portion 30' not covered by the insulating portion M2 can be etched (EC2).

[0132] Furthermore, in this invention, the connecting portion 40 formed between the support portion 30' and the mask 20 can act as a stopper during the EC2 etching process. During the EC2 etching process from the second surface of the support portion 30' towards the first surface, the EC2 etching stops when it reaches the connecting portion 40. Therefore, it has the effect of preventing damage to the mask 20 or the mask pattern P during the EC2 etching process.

[0133] The mask 20 is housed within the trench TR, thus maintaining its shape during the EC2 etching process. The portion between adjacent trench TRs in the support 30' disappears after the EC2 etching process. This free space can be provided as a mask pattern P for the mask 20. If the side surface SS of the trench TR includes an inclined shape or a conical shape, the side surface of the mask pattern P can also have a corresponding inclined shape or conical shape.

[0134] Secondly, refer to Figure 11 After removing the insulating part M2 and performing subsequent processes such as cleaning, the manufacturing of the mask and support assembly 10:10-2 can be completed. The support part 30 includes an edge part 31, a first grid part 33, and a second grid part 35, and the mask 20 is connected to the support part 30 with a connecting part 40 sandwiched in the middle. The unit part C of the mask 20 does not require the support of the support part 30, and the lower part is an open area, which can be used as an organic material source 1600 in the OLED pixel deposition process (refer to...). Figure 21 The movement path is used.

[0135] Figures 12 to 16 This is a schematic diagram of the manufacturing process of the mask and support connector 10 according to the second embodiment of the present invention.

[0136] First, such as Figure 5 A support portion 30' can be prepared, and a patterned insulating portion M1 can be formed on one side of the support portion 30'. In addition, by etching the ECl support portion 30', a plurality of recessed groove portions TR can be formed on the first side (or the top side).

[0137] Then, refer to Figure 12 The insulating part M2 can be removed and cleaned. Furthermore, pretreatment processes for electroforming can be performed. The support part 30' has multiple grooves TR formed on it.

[0138] Then, refer to Figure 13 Electroforming can be performed on the support portion 30' to form a mask 20″. The mask 20″ can be formed to fill the groove portion TR and also cover the rest of the support portion 30' outside the groove portion TR. In other words, the mask 20″ can be electroformed so that its upper end is higher than the height of the first surface (or upper surface) of the support portion 30'. The mask 20″: 20″a can also be made using the same method. Figure 6 It is formed by the electroforming method described herein.

[0139] As another example, see Figure 14 Alternatively, it can be used Figure 7 The method for forming the first mask layer 23' and the second mask layer 21' described herein causes the mask 20″: 20″b to be formed as a stack having at least two electroplated layers 21″, 23″.

[0140] Then, refer to Figure 15 The mask 20″ and the support 30′ can be heat-treated H. Before or after the heat treatment H, the insulation part M1 can be removed. Figure 8 The heat treatment method H described above can also be used. During the heat treatment H process, a connecting part 40 can be formed between the mask 20″ and the support 30′. The connecting part 40 can be provided as an intermetallic compound synthesized from the components of the mask 20′ and the support 30′.

[0141] The mask 20″ is adapted to be accommodated in the groove TR formed by the recess of the support 30′. Therefore, during the heat treatment H process, the mask 20″ can be prevented from deforming in the horizontal direction, further ensuring the contact area between the support 30′ and the mask 20″, which is more conducive to the formation of the connecting part 40.

[0142] Then, refer to Figure 16The mask 20″ can be planarized (PS). By mirroring one side (top) of the mask 20″ and removing a portion of the upper part of the mask 20″, the thickness can be reduced (20'->20). The portion of the mask 20″ above the upper surface of the support 30' can be removed.

[0143] After planarization (PS), the mask 20 and the support portion 30' can at least share the same upper surface. When the mask 20 is recessed and accommodated in the groove portion (TR) of the support portion 30', it can share the upper surface with the support portion 30'.

[0144] in addition, Figure 15 Heat treatment H and Figure 16 The planarization PS sequence can be reversed. First, the mask 20' is planarized PS and its thickness is reduced (20'->20), and then the connection part 40 can be generated by heat treatment H.

[0145] As described above, in this invention, after the mask 20 is formed on the support portion 30 by electroforming, the support portion 30 is processed to form a frame without applying additional physical stretching to the mask 20, thus eliminating the risk of mask misalignment. Therefore, it achieves ultra-high image quality pixels of over 2000 PPI while ensuring accurate mask alignment and improving the stability of pixel deposition.

[0146] Figure 17 This is a top view of a mask 20 and a side cross-sectional view of E-E' or FF' according to another embodiment of the present invention. Figure 18 This is a top view of the support portion 30 according to another embodiment of the present invention.

[0147] Figure 3 The edges of the mask 20 are circular, but the unit portions C, including the mask pattern P, can be quadrilateral. When the unit portions C are arranged along the first and second directions approximately at the center of the mask 20, the distances from each unit portion C to the edge of the circular mask 20 will be different. From another perspective, the contact area between each unit portion C and the dummy portion DM can be different. Therefore, uneven pressure levels may occur in different regions of the unit portions C and the dummy portion DM of the mask 20.

[0148] In addition, a mask pattern P is formed in the unit portion C to penetrate the mask 20. On the contrary, no penetrating pattern is formed in the dummy portion DM. Therefore, the dummy portion DM is less deformed under pressure, while the unit portion C shows greater deformation under the same pressure. In order to achieve an ultra-high-definition OLED pixel with a resolution of 500 to 600 PPI or more, preferably 2000 PPI or more, the connection body 10 between the mask and the support portion should form the mask pattern P finely without changing its position. Therefore, it is necessary to adjust the pressure levels applied to the unit portion C and the dummy portion DM evenly. This also applies to the unit region CR and the dummy unit region DCR of the support portion 30.

[0149] Referring again to Figure 17 , the present invention is characterized in that the dummy portion DM includes a plurality of dummy unit portions DC. The dummy unit portions DC can be arranged along the first direction (x-axis direction) of the unit portion C and the second direction (y-axis direction) perpendicular to the first direction with a preset interval. The preset interval between the dummy unit portion DC and the unit portion C can correspond to the preset interval between the unit portion C and the unit portion C. A dividing portion SR can also be arranged between the dummy unit portion DC and the unit portion C.

[0150] The length of at least one side of the dummy unit portion DC can correspond to the length of one side of the unit portion C. The unit portion C is quadrilateral, and the edge sides C1 and C2 of the unit portion C can be composed of straight lines perpendicular to each other. If the unit portion C is square, the lengths of C1 and C2 are the same; if it is rectangular, the lengths of C1 and C2 are different. The dummy unit portion DC is arranged along the first direction and the second direction in the extension direction of the unit portion C, but due to the characteristics of being arranged at the edge of the mask 20, it cannot be quadrilateral. The dummy unit portion DC can be a shape with at least some sides having curvature. From another perspective, two to four of the edge sides DC1, DC2, and DC3 of the dummy unit portion DC can be straight lines, and some sides can be curves. Figure 17 In, for example, two sides DC1 and DC2 of the dummy unit portion DC located in the upper left side are straight lines, and the DC3 side is composed of two straight lines and one curve. Again, for example, the dummy unit portion DC located on the rightmost or leftmost side and the dummy unit portion DC located on the uppermost or lowermost side are composed of straight lines with a shape approximately like ′匚′ on three sides, and the right side is composed of a curve.

[0151] In addition, a plurality of dummy patterns DP can be formed in the dummy unit portion DC. As Figure 17As shown, the shape of the dummy part pattern DP can be the same as the shape of the mask pattern P. For example, it can have a shape with sloping sides, a tapered shape, or a shape where the pattern width gradually widens from top to bottom. Multiple dummy part patterns DP can form a dummy part unit DC by forming a cluster. The dummy part pattern DP can have a generally tapered shape, and the pattern width can be formed from a few μm to tens of μm, preferably about 5 μm to 10 μm (resolution of 2000 PPI or higher).

[0152] Furthermore, the dummy pattern DP can be formed at a predetermined depth even if it does not penetrate the mask 20 in the thickness direction, as long as it maintains pressure uniformity throughout the entire area of ​​the mask 20. Moreover, the dummy pattern DP does not need to have the same shape and size as the mask pattern P, as long as it maintains pressure uniformity throughout the entire area of ​​the mask 20; it can also have a shape larger than the mask pattern P and other than a conical shape. However, the more similar the shape is to the mask pattern P, the higher the uniformity of the pressure level will be.

[0153] Alternatively, the dummy part pattern DP can also be formed on the dummy part DM of the mask 20 in the form of cutting off a predetermined area. The dummy part pattern DP may not be multiple, and may be a continuously connected shape rather than being formed in a regular repetitive manner. For example, the dummy part pattern DP may also be provided in the form of retaining only the unit part C of the mask 20 and cutting off the remaining part.

[0154] Reference Figure 18 Multiple dummy unit regions DCR can be formed on the support portion 30. The dummy unit regions DCR can be arranged along a first direction (x-axis direction) and a second direction perpendicular to the first direction (y-axis direction), and are spaced at a predetermined interval from the unit regions CR. The predetermined interval between the dummy unit regions DCR and the unit regions CR can correspond to the predetermined interval between unit regions CR. A first grid portion 33 and a second grid portion 35 can also be arranged between the dummy unit regions DCR and the unit regions CR. The dummy unit regions DCR perform the same function as the dummy unit portion DC described above; therefore, the description of the dummy unit portion DC described above will be used instead.

[0155] Figure 19 This is a schematic diagram of the mask planarization process and the dummy groove portion of the grid portion according to an embodiment of the present invention. Figure 20 These are (a) a top view and (b) a side cross-sectional view of G-G' of the mask pattern and the dummy groove portion of the grid portion according to an embodiment of the present invention.

[0156] like Figure 19 As shown in (a), Figure 9Ideally, after the planarization PS process, the top surface of the mask 20 and the top surface of the support 30' should be completely at the same level.

[0157] However, as Figure 19 As shown in (b), if planarization PS such as polishing and buffing is performed, the upper surface of mask 20 and the upper surface of support 30' will not have the same height on the same horizontal plane. The upper part of mask 20 is subjected to concave twisting grinding DS1 and DS2, which can form a more recessed shape. At this time, the part of mask 20 located in unit section C is for forming mask pattern P, and the width of the groove TR is a narrower width of several μm corresponding to mask pattern P. Therefore, the depth of the recess DS1 is relatively shallow. Conversely, the part of mask 20 located in dividing section SR is not for mask pattern P but is for support on the first grid section 33 and the second grid section 35. Therefore, it has a wider width of several hundred μm to several mm. As a result of planarization PS on the wider width, the depth of the recess DS2 is relatively deep. If the recess DS2 is deep, the thickness of mask 20 in dividing section SR becomes thinner, the rigidity becomes weaker, it is easy to deform, and it may even affect the alignment of unit section C.

[0158] Therefore, as Figure 19 As shown in (c), a dummy groove portion DTR can be formed in the region on the support portion 30 where the first grid portion 33 and the second grid portion 35 are formed. The width of the dummy groove portion DTR can be formed from a few μm to several hundred μm, and preferably it can be formed to be the same size as the groove portion TR, that is, a width that is narrower by a few μm. Thus, even when performing planarization PS, the degree of depression can be uniformly formed on the unit portion C or the dividing portion SR, so that the dividing portion SR and the first grid portion 33 and the second grid portion 35 can share the same upper surface.

[0159] Reference Figure 20 , Figure 20 Figure (b) illustrates the configuration of the dividing portion SR of the mask 20 housed within the dummy groove portion DTR of the second grid portion 35. The dividing portion SR is fixed to the dummy groove portion DTR, and the upper portion 35a of the second grid portion 35 can penetrate the dividing portion SR and be anchored therethrough. Thus, the dummy groove portion DTR can provide an effect that improves the adhesion to the dividing portion SR.

[0160] Figure 21 This is a schematic diagram of an OLED pixel deposition apparatus 1000 employing a connector 10 for a mask and a support portion according to an embodiment of the present invention.

[0161] Reference Figure 21The OLED pixel deposition apparatus 1000 includes: a magnetic plate 1300 which houses a magnet 1310 and is equipped with a cooling water pipe 1350; and a deposition source supply unit 1500 which supplies an organic source 1600 from the lower part of the magnetic plate 1300.

[0162] A target substrate 1900, such as glass, for depositing an organic source 1600 can be inserted between the magnetic plate 1300 and the deposition source supply unit 1500. A mask-support connector 10 is arranged close to or very close to the target substrate 1900, which is used to deposit the organic source 1600 according to different pixels. The magnet 1310 generates a magnetic field, and the attraction of the magnetic field allows the mask-support connector 10 to adhere tightly to the target substrate 1900.

[0163] The deposition source supply unit 1500 can travel back and forth along the left and right paths to provide an organic source 1600. The organic source 1600 provided by the deposition source supply unit 1500 passes through the mask pattern P formed in the connector 10 of the mask and support and is deposited on one side of the target substrate 1900. The organic source 1600 that passes through the mask pattern P of the connector 10 of the mask and support and is deposited can be used as a pixel 1700 of the OLED.

[0164] The mask pattern P is formed obliquely on its sides (forming a conical shape), thus preventing uneven deposition of OLED pixels 1700 caused by the shadow effect based on the organic source 1600 passing along the oblique direction.

[0165] As described above, after electroforming the mask 20 onto the support portion 30′ (or conductive substrate 30′), the present invention processes and connects the mask 20 and the support portion 30′ to form the support portion 30 as a frame without applying additional physical stretching to the mask 20. Therefore, there is no risk of mask misalignment. Thus, the present invention achieves ultra-high image quality pixels of 2000 PPI or higher while ensuring accurate mask 20 alignment and improving the stability of pixel deposition.

[0166] Figure 22 yes Figure 8 A schematic diagram illustrating the phenomena that may occur during the heat treatment process.

[0167] like Figure 8 As shown above, when heat treatment H is performed on a laminated body in which a mask 20' is formed on the support portion 30', a connection portion 40 can be formed between the mask 20' made of Invar alloy material and the support portion 30' made of silicon material. However, due to the difference in their coefficients of thermal expansion, the mask 20' and the support portion 30' have different degrees of expansion and contraction, and therefore may bend towards the side that contracts more after heat treatment H.

[0168] Reference Figure 22When heat-treating the Invar alloy mask 20' and the silicon support portion 30', the difference in their coefficients of thermal expansion can lead to different degrees of stretching. For example, when the stretching of the support portion 30' is longer and the stretching of the mask 20' is relatively shorter, the mask 20' may be subjected to an inward force F1, while the support portion 30' may be subjected to an outward force F2. Because of the connecting portion 40, when the mask 20' and the support portion 30' are connected, the forces F1 and F2 may be applied alternately, potentially resulting in a downward curved bending phenomenon. Alternatively, when the stretching of the mask 20' is longer and the stretching of the support portion 30' is relatively shorter, the applied forces are opposite to those in the above example, potentially resulting in an upward curved bending phenomenon.

[0169] If the bending phenomenon described above occurs, it may be detrimental to the uniform alignment of the mask pattern P. Therefore, a bending-resistant structure is proposed below.

[0170] Figure 23 This is a side cross-sectional schematic diagram of the connector 10:10-3 between the mask and the support part according to the third embodiment of the present invention. Figure 24 This is a schematic diagram illustrating phenomena that may occur during the heat treatment process according to the third embodiment of the present invention.

[0171] Figure 23 The connecting body 10:10-3 of the mask and support shown is... Figures 1 to 3 The connecting body 10:10-1 between the mask and the support is substantially the same in terms of the structure of the mask 20, the support 30, and the connecting part 40, so its detailed description is omitted.

[0172] Reference Figure 23 The connector 10:10-3 between the mask and the support is characterized in that a deformation-resistant portion 50 is further formed on the lower part of the support 30. The deformation-resistant portion 50 can be formed on the lower part of the support 30 by electroforming. Preferably, the material of the deformation-resistant portion 50 is substantially the same as that of the mask 20, and can be Invar or super Invar. Alternatively, the deformation-resistant portion 50 may also include nickel (Ni), cobalt (Co), titanium (Ti), chromium (Cr), tungsten (W), molybdenum (Mo), or combinations thereof, alloys thereof, which are electroformable and can form the support 30′ [or, conductive substrate 30′, see reference]. Figure 5 The silicon-containing metallic material and silicides. Alternatively, the deformation-resistant part 50 may also include a superinvar alloy material with a ternary or higher Co composition.

[0173] In this embodiment, by forming a mask 20' on the upper part of the support 30 and an anti-deformation part 50 on the lower part of the support 30, bending can be prevented during the heat treatment process. Figure 8 Before the heat treatment H, an electroforming process can be performed on the upper part of the support portion 30' to form a mask 20', and an electroplated film for constituting the anti-deformation portion 50 can be further formed on the lower part of the support portion 30'. That is, in the above-mentioned Figure 6 and Figure 7 In the process, the mask 20' is electroformed to simultaneously or sequentially form the anti-deformation part 50 on the lower part of the support part 30'.

[0174] like Figure 24 As shown, if heat treatment H is performed afterward, since the material of the mask 20' is substantially the same as the material of the anti-deformation part 50, the degree of thermal expansion and contraction of the upper and lower surfaces of the support part 30' can be uniformly controlled. A second connecting part 45, similar to the connecting part 40, can also be formed between the anti-deformation part 50 and the support part 30'.

[0175] For example, when the stretch of the support portion 30' is relatively long while the stretch of the mask 20' and the anti-deformation portion 50 is relatively short, an inward force F1 can be applied to the mask 20', an inward force F3 can be applied to the anti-deformation portion 50, and an outward force F2 can be applied to the support portion 30'. Because a connecting portion 40 or a second connecting portion 45 is formed, when the mask 20' and the support portion 30', and the support portion 30' and the anti-deformation portion 50 are interconnected, forces F1, F3, and F2 may be applied alternately. However, since forces F1 and F3 are applied inward from the upper and lower parts of the support portion 30', forces F1 and F3 cancel each other out, thereby preventing bending. As another example, when the stretching of the mask 20' or the anti-deformation part 50 is longer while the stretching of the support part 30' is relatively shorter, the applied force is opposite to that in the above example. In this case, the forces F1 and F3 cancel each other out, thereby preventing bending. Thus, by further forming the anti-deformation part 50, it is possible to have the effect of preventing the connection body 10:10-3 between the mask and the support part from bending.

[0176] In addition, such as Figure 10 As described above, the edge portion 31, the first grid portion 33, and the second grid portion 35 can be formed by etching EC2 on the lower part of the support portion 30'. By etching EC2 on the lower part, the remaining portion of the anti-deformation portion 50, except for the portions corresponding to the edge portion 31, the first grid portion 33, and the second grid portion 35, is also etched away. As a result of etching EC2, the lower part of the support portion 30 is left with the edge anti-deformation portion 51 and the grid anti-deformation portion [the first grid portion 33 and the second grid portion 35] of the anti-deformation portion 50.

[0177] Since a significant portion of the anti-deformation part 50 is etched away by EC2, the force F1 exerted by the upper mask 20 on the support part 30 may be greater than the force F3 exerted by the anti-deformation part 50 on the support part 30. Therefore, the thickness T4 of the anti-deformation part 50 is preferably electroformed to be greater than the thickness T3 of the mask 20. Only when the overall volume of the anti-deformation part 50 is at least the same as the overall volume of the mask 20 can uniform forces F1 and F3 be applied to the upper and lower surfaces of the support part 30, with forces F1 and F3 canceling each other out, thereby preventing bending. For example, the thickness T4 of the anti-deformation part 50 can be approximately 30% to 300% larger than the thickness T3 of the mask 20. For example, even if forces F1 and F3 do not completely cancel each other out, within the range that does not cause bending of the support part 30, the overall volume of the mask 20 and the overall volume of the anti-deformation part 50 can be in the range of 70% to 130% of each other.

[0178] Figure 25 This is a side cross-sectional schematic diagram of the connector 10:10-4 between the mask and the support part according to the fourth embodiment of the present invention.

[0179] Reference Figure 25 This embodiment is an example of the mask and support body 10:10-4 where a groove TR is not formed on the support 30', but rather an insulating part (not shown) such as photoresist is formed, and then the mask 20' is immediately formed by electroforming. The mask 20' can be formed on the flat upper surface of the support 30' by electroforming.

[0180] In this embodiment, as Figure 8 The steps involve heat-treating the mask 20' formed by electroforming on the support portion 30' to form the connecting portion 40. For example... Figure 23 As mentioned above, the difference in the coefficient of thermal expansion during heat treatment H can cause bending. Therefore, in this embodiment, the anti-deformation part 50 can also be formed at the lower part of the support 30' by electroforming before heat treatment H is performed. The structure and function of the anti-deformation part 50 are as follows. Figures 23 to 24 As described in [the text].

[0181] As described above, the present invention has illustrated and explained preferred embodiments, but the present invention is not limited to the above embodiments. Various modifications and alterations can be made by those skilled in the art without departing from the spirit of the present invention. All such modifications and alterations should be considered to fall within the scope of the present invention and the appended claims.

Claims

1. A connector between a mask and a support, used in a process of forming OLED pixels on a semiconductor wafer, comprising: The support portion includes an edge portion and a grid portion; A mask, which is connected to the support and includes multiple unit parts formed with a mask pattern. The lower part of the support is further formed with an anti-deformation part.

2. The connector between the mask and the support as described in claim 1, wherein, At least a portion of the mask is arranged in a groove formed by a depression in the support portion.

3. The connector between the mask and the support as described in claim 1, wherein, The support and the mask are circular in shape. The grid portion includes: a plurality of first grid portions extending along a first direction and connected at both ends to the edge portion; and a plurality of second grid portions extending along a second direction different from the first direction and intersecting with the first grid portions, and connected at both ends to the edge portion.

4. The connector between the mask and the support as described in claim 3, wherein, The mask includes: A dummy part, which is connected to the edge portion; The plurality of unit portions are arranged at the center of the mask rather than at the dummy portion, and include a plurality of mask patterns; The dividing section is located at the center of the mask rather than at the dummy section, and is arranged between the plurality of unit sections. The dividing section is supported on the grid section.

5. The connector between the mask and the support as described in claim 3, wherein, The anti-deformation portion is formed at the lower part of the edge portion, the lower part of the first grid portion, and the lower part of the second grid portion.

6. The connector between the mask and the support as described in claim 1, wherein, The material of the mask is the same as the material of the anti-deformation part.

7. The connector between the mask and the support as described in claim 1, wherein, The thickness of the mask is the same as the thickness of the anti-deformation part, or the thickness of the anti-deformation part is greater.

8. The connector between the mask and the support as described in claim 1, wherein, The overall volume of the mask and the overall volume of the anti-deformation part are each between 70% and 130% of the other.

9. The connector between the mask and the support as described in claim 1, wherein, The support portion is formed from a silicon wafer, and the mask and the anti-deformation portion are formed on the silicon wafer by electroforming.

10. The connector between the mask and the support as described in claim 9, wherein, A connecting portion may be provided between the support portion and the mask or between the support portion and the anti-deformation portion. The connecting portion may contain Ni and Si, or Fe, Ni and Si.

11. A method for manufacturing a connector between a mask and a support, the connector being used in a process of forming OLED pixels on a semiconductor wafer, the method comprising the following steps: (a) Prepare a support portion, the support portion being a conductive substrate, including a first surface and a second surface opposite to the first surface; (b) A mask is formed on the first surface of the support using an electroforming method; (c) An anti-deformation part is formed on the second surface of the support by electroforming; (d) Heat treatment is performed on the support, the anti-deformation part and the mask; (e) An edge portion and a grid portion are formed by etching the support portion on the second surface of the support portion.

12. The method for manufacturing the connector between the mask and the support as described in claim 11, wherein, In step (e), edge anti-deformation portion and grid anti-deformation portion are formed by etching the anti-deformation portion.

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