Palladium plating composition, method for manufacturing substrate for semiconductor package using same, and substrate for semiconductor package manufactured by method

Abstract

The present invention relates to a palladium plating composition, a method for manufacturing a substrate for semiconductor encapsulation using the same, and a substrate for semiconductor encapsulation manufactured by the method. The present invention provides a palladium plating composition for electroless plating on a copper substrate of a substrate for semiconductor encapsulation by nickel-free plating, a method for manufacturing a substrate for semiconductor encapsulation using the same, and a substrate for semiconductor encapsulation manufactured by the method.

Description

Technical Field

[0001] The present invention relates to a palladium plating composition for electroless plating of a copper substrate for semiconductor packaging, a method for manufacturing a semiconductor packaging substrate using the same, and a semiconductor packaging substrate manufactured by the method. Background Technology

[0002] In the manufacturing of electronic components, the steps that form circuits on a semiconductor wafer are called front-end processes, while the steps that assemble the wafer into a state that can be used in an actual product are called back-end processes or packaging processes.

[0003] In the field of semiconductor packaging, new packaging technologies that are thinner and smaller have been developed, replacing wire bonding or flip chip bonding technologies.

[0004] Among them, wire bonding technology is a method of bonding thin metal wires to pads. That is, it is a technology that connects the internal chip and the external environment. Structurally, the wires act as a bridge connecting the bonding pads of the chip (first bonding) and the pads of the carrier (second bonding).

[0005] Furthermore, there are three ways to connect the leads to the pads: heat bonding by heating and pressing the bonding pads and the capillary (a capillary-shaped lead moving tool); bonding by applying ultrasonic waves to the capillary without using heat; and a combination of heat and ultrasonic waves.

[0006] First, the thermoforming method is as follows: the temperature of the chip's bonding pads is raised to about 200°C beforehand, and the temperature of the tip of the cleaver is also raised to form the lead into a ball shape. Pressure is then applied to the bonding pads by the cleaver to attach the lead.

[0007] Furthermore, the ultrasonic method involves applying ultrasonic waves to the pads by attaching leads to them and using a wedge (a lead-moving tool similar to a cleaver, which does not form a ball) to adhere the leads to the pads. This method offers advantages in terms of both process and material cost.

[0008] However, since ultrasound is used instead of heat and pressure, it has the disadvantage of being easy to operate but having poor tensile strength (the force that the lead wire can withstand when pulled after wiring) after bonding.

[0009] Furthermore, the most commonly used method in semiconductor manufacturing is thermo-ultrasonic bonding, which combines the advantages of thermoforming and ultrasonic bonding. This method applies heat, pressure, and ultrasonic waves to a bonding tool to achieve optimal bonding conditions. Back-end semiconductor processes prioritize bond strength over cost, and therefore, even though it is more expensive, thermo-ultrasonic bonding using gold wire is primarily employed.

[0010] Furthermore, flip-chip bonding technology involves placing the semiconductor chip face down and connecting electrically conductive metal protrusions to the bonding pads. Because flip-chip bonding faces the substrate without leads, it has the following characteristics: reduced size, reduced power consumption, reduced ambient noise, faster signal transmission due to shorter distances, and stronger bonding.

[0011] The materials used for metal protrusions are primarily solder and gold (Au). Metal protrusions refer to conductive metal protrusions used to connect chips to the circuit board via tape-and-reel automatic bonding (TAB) or flip chip (FC) methods, or to directly connect them to the circuit board via ball grid array (BGA) or chip scale package (CSP).

[0012] Solder protrusions will form spherical shapes through surface tension after the reflow soldering process. Gold protrusions, as one type of metal protrusion, will be formed into cuboids with length, width, and height through electroplating gold.

[0013] The wafers with gold protrusions will be used for TCP (tape carrier package), COG (Chip on Glass) packaging, and COF (chip on Film) packaging, and will be used in products such as televisions, monitors, networks, mobile devices, tablets, and automotive DIC (Digital Image Correlation).

[0014] Because of its excellent physical and chemical properties such as conductivity, oxidation resistance, and chemical resistance, gold plating is used in a variety of applications in the fields of microelectronics and optoelectronics, including RDL (redistribution layer), pattern plating, conformal via coating, X-ray mask, MEMS (microelectromechanical systems), and gold bumping.

[0015] Currently, although a nickel plating layer is formed on the semiconductor packaging substrate as described above, the high plating thickness of the nickel plating layer makes it difficult to use for fine pitch, and it has the problem of cracking due to the poor flexibility of nickel metal.

[0016] Furthermore, in existing methods of electroless palladium plating after nickel plating on copper surfaces, if nickel plating is omitted in order to perform electroless palladium plating, pitting and pinholes will occur due to localized corrosion of the copper surface. Additionally, copper ions dissolve in the electroless palladium plating bath, leading to the problem of easy decomposition of the plating bath.

[0017] Therefore, through diligent efforts and extensive research, the applicant has obtained a palladium plating composition for electroless plating on a copper substrate of a semiconductor packaging substrate, a method for manufacturing a semiconductor packaging substrate using the same, and a semiconductor packaging substrate manufactured by the method, thereby completing the present invention.

[0018] Existing technical documents

[0019] Patent documents

[0020] Korean Patent No. 10-1852658 (Patent Publication Date: April 26, 2018) Summary of the Invention

[0021] Technical issues

[0022] Therefore, the object of the present invention is to provide a palladium plating composition for electroless plating on a copper substrate of a semiconductor packaging substrate.

[0023] Furthermore, the object of the present invention is to provide a method for manufacturing a semiconductor packaging substrate using a palladium plating composition to form a fine-pitch chemical palladium immersion gold (EPIG) plating layer.

[0024] Furthermore, the object of the present invention is to provide a semiconductor packaging substrate manufactured by a method for manufacturing a semiconductor packaging substrate using a palladium plating composition to form a fine-pitch chemical palladium impregnation gold plating layer.

[0025] The problems to be solved by the present invention are not limited to those mentioned above. Those skilled in the art to which this invention pertains can clearly understand other problems not mentioned through the following description.

[0026] Technical solution

[0027] To address the aforementioned problems, according to an embodiment of the present invention, a palladium plating composition is provided for use in a semiconductor packaging substrate. This palladium plating composition is characterized by comprising: a palladium compound; a plating uniformity enhancer; a reducing agent; a plating film improver; a metal ion complexing agent; a plating wetting agent; a pH adjuster; and deionized water. The palladium plating composition is chemically plated onto a copper substrate of the semiconductor packaging substrate using a nickel-free electroplating method. When the palladium plating composition is applied to a microcircuit with a pitch of 4–50 μm on the semiconductor packaging substrate and measured under the circuit diffusion rate evaluation conditions described in evaluation condition 1 below, the circuit diffusion rate is 0.001–8 volume percentages.

[0028] Evaluation Condition 1

[0029] Circuit diffusivity (volume percentage) = (diffusion width (μm) / circuit width (μm)) × 100

[0030] According to another embodiment of the present invention, a palladium plating composition is provided, characterized in that when the palladium plating composition is used on the semiconductor packaging substrate and measured under the solder ball welding strength evaluation conditions of evaluation condition 2 below, the solder ball welding strength is 700 to 850 gf.

[0031] Evaluation Condition 2

[0032] Measurement method: Ball pull test.

[0033] Solder balls: Arp 0.45ΦSAC305 (Sn-3.0Ag-0.5Cu),

[0034] Reflow Soldering: Multi-functional Reflow Soldering Machine (BTU, VIP-70)

[0035] Reflow soldering conditions: Maximum 260°C.

[0036] According to another embodiment of the present invention, a palladium plating composition is provided, characterized in that when the above-mentioned palladium plating composition is used on the above-mentioned semiconductor packaging substrate and evaluated under the solder diffusion evaluation conditions of the following evaluation condition 3, the solder ball diffusion is (width + length) / 2 of the diffused solder ball, and the solder ball diffusion length is 700 to 950 μm.

[0037] Evaluation Condition 3

[0038] Evaluation by reflow soldering the solder balls.

[0039] Solder ball diameter: 300μm

[0040] Solder ball type: SAC 305 (solder balls with 96.5% by weight tin (Sn), 3% by weight silver (Ag), and 0.5% by weight copper (Cu)).

[0041] Reflow soldering conditions: Preheat at 130–200°C for 80–120 seconds, then bond (solder) at 240–260°C for 20–60 seconds.

[0042] According to another embodiment of the present invention, a palladium plating composition is provided, characterized in that, when the palladium plating composition is used on the semiconductor packaging substrate and measured under the lead bond strength evaluation conditions of evaluation condition 4 below, the average lead bond strength is 9 to 15 gf.

[0043] Evaluation Condition 4

[0044] Wire bonding machine: HB-16, W-4626 from 3H Corporation; Leads: 1mil-Au

[0045] Stage temperature: 165℃

[0046] The bond strength was determined by taking the average strength value after tensile testing of 30 specimens. The evaluation was conducted by identifying the break point of the lead wire to distinguish between the "Good Mode" and the "Failure Mode," where the bond interface was damaged.

[0047] According to another embodiment of the present invention, a palladium plating composition is provided, characterized in that, when the palladium plating composition is used on the semiconductor packaging substrate to measure the interlayer blank area before heat treatment, the interlayer blank area before heat treatment is 0 to 5% by volume.

[0048] According to another embodiment of the present invention, a palladium plating composition is provided, characterized in that, when the palladium plating composition is used on the semiconductor packaging substrate to measure the interlayer blank area after heat treatment, the interlayer blank area after heat treatment is 0 to 5% by volume.

[0049] According to another embodiment of the present invention, a palladium plating composition is provided, characterized in that when the palladium plating composition is used on the semiconductor packaging substrate to perform a peel test to determine the adhesion of the plating to confirm whether the substrate metal and the plating are separated and attached to the tape, the substrate metal and the plating do not separate.

[0050] According to another embodiment of the present invention, a palladium plating composition is provided, characterized in that when the palladium plating composition is used in the semiconductor packaging substrate, a gold plating layer is also formed on the palladium plating layer, the thickness of the gold plating layer being 0.03 to 0.50 μm.

[0051] According to another embodiment of the present invention, a palladium plating composition is provided, characterized in that when the palladium plating composition is used in the semiconductor packaging substrate, the palladium plating thickness is 0.03 to 0.50 μm.

[0052] According to one embodiment of the present invention, the palladium plating composition for semiconductor packaging substrates, relative to 100 weight percent of the above, may contain: 0.01 to 1 weight percent of a palladium compound (palladium content); 0.5 to 5 weight percent of a plating uniformity enhancer; 0.1 to 5 weight percent of a reducing agent; 0.1 to 3 weight percent of a plating film improver; 0.1 to 5 weight percent of a metal ion complexing agent; 0.001 to 0.5 weight percent of a plating wetting agent; 1 to 10 weight percent of a pH adjuster; and the remainder being deionized water.

[0053] According to one embodiment of the present invention, the above-mentioned palladium compound, as a water-soluble palladium compound, can be used as a palladium metal supplement for pure palladium plating solution.

[0054] According to one embodiment of the present invention, the palladium compound can be palladium chloride, palladium sulfate, palladium tetrachloride, palladium acetate, palladium ammonium chloride, ethylenediamine palladium, or pyrimidinone palladium.

[0055] According to one embodiment of the present invention, the above-mentioned coating uniformity enhancer can improve the coating uniformity and conductivity of palladium metal.

[0056] According to one embodiment of the present invention, the coating uniformity enhancer may be glycolic acid, lactic acid, tartaric acid, malic acid, aminosuccinic acid, citric acid, gluconic acid, oxalic acid, malonic acid, ascorbic acid, hydrochloric acid, or citric acid.

[0057] According to one embodiment of the present invention, the reducing agent described above can promote precipitation by imparting reducing properties to palladium metal.

[0058] According to one embodiment of the present invention, the reducing agent may be phosphonic acid, ammonium phosphite, sodium phosphite, potassium phosphite, ammonium phosphite, ammonium formate, sodium formate, potassium formate, calcium formate, or formaldehyde.

[0059] According to one embodiment of the present invention, the above-mentioned coating modifier can form a high-purity palladium coating, providing excellent heat resistance and enhancing the adhesion between coatings.

[0060] According to an embodiment of the present invention, the above-mentioned coating modifier may be 1,3-dihydro-2H-imidazolium, 1,3-dimethyl-3,4,5,6-tetrahydro-2(1H)-pyrimidinone, 4(s)-4-hydroxy-3,4-dihydro-2(1H)-pyrimidinone, 1,3-dihydro-2H-imidazolium-2-one, 1-methyl-tetrahydro-2(1H)-pyrimidinone, or 4-amino-2(1H)-pyrimidinone.

[0061] According to an embodiment of the present invention, the above-mentioned metal ion complexing agent can prevent metal ion precipitation by dissolving, coordinating and complexing metal ions in the plating solution.

[0062] According to an embodiment of the present invention, the metal ion complexing agent may be ethylenediaminetetraacetic acid (EDTA), diethylenetriaminepentaacetic acid (DTPA), triethylenetetraaminehexaacetic acid, propylenediaminetetraacetic acid, N-(2-hydroxyethyl)ethylenediaminetriacetic acid, 1,3-diamino-2-hydroxypropane-N,N,Nˊ,Nˊ-tetraacetic acid, bis-(hydroxyphenyl)-ethylenediaminediacetic acid, diaminocyclohexanetetraacetic acid, ethylene glycol-bis((β-aminoethyl ether)-N,Nˊ-tetraacetic acid), alkylene polyamine polyacetic acid, N,N,Nˊ,Nˊ-tetra-(2-hydroxypropyl)ethylenediamine, ethylenediamine, triethylenetetraamine, diethylenetriamine, tetra(aminoethyl)ethylenediamine or polyamines and their sodium, potassium or ammonium salts.

[0063] According to one embodiment of the present invention, the above-mentioned plating wetting agent can adjust the wettability between the plating solution and the metal surface and make the size of the plated particles smaller.

[0064] According to one embodiment of the present invention, the above-mentioned coating wetting agent may be polyethylene glycol, polyoxyethylene ether, polyoxyethylene alkylamino ether, polynaphthalene ethyl ether, polyethylene glycol, polypropylene glycol or polypropylene.

[0065] According to one embodiment of the present invention, the pH adjuster described above can be a pH adjuster used to maintain the pH of the plating solution.

[0066] According to one embodiment of the present invention, the pH adjuster may be hydrochloric acid, sulfuric acid, nitric acid, boric acid, sodium hydroxide or potassium hydroxide.

[0067] According to an embodiment of the present invention, the palladium plating composition may further include a bombardment gold plating composition for plating bombardment gold on the copper substrate of the semiconductor packaging substrate before plating palladium.

[0068] According to an embodiment of the present invention, the above-described impact gold plating composition may comprise: a gold compound; a gold ion complexing agent; a conductivity enhancer; a secondary material erosion inhibitor; a secondary material erosion auxiliary inhibitor; a plating solution wetting agent; and deionized water.

[0069] According to one embodiment of the present invention, the above-mentioned gold compound, as a water-soluble gold compound, can be a gold supplement for the AuStrike plating solution.

[0070] According to one embodiment of the present invention, the gold compound may be potassium gold cyanide, potassium gold cyanide, potassium gold chloride, potassium gold chloride, potassium gold sulfite, sodium gold sulfite, potassium gold thiosulfate, or sodium gold thiosulfate.

[0071] According to an embodiment of the present invention, the above-mentioned metal ion complexing agent can prevent metal ion precipitation by dissolving, coordinating and complexing metal ions in the plating solution.

[0072] According to an embodiment of the present invention, the gold ion complexing agent may be ethylenediaminetetraacetic acid, diethylenetriaminepentaacetic acid, triethylenetetraaminehexaacetic acid, propylenediaminetetraacetic acid, N-(2-hydroxyethyl)ethylenediaminetriacetic acid, 1,3-diamino-2-hydroxypropane-N,N,Nˊ,Nˊ-tetraacetic acid, bis-(hydroxyphenyl)-ethylenediaminediacetic acid, diaminocyclohexanetetraacetic acid, ethylene glycol-bis((β-aminoethyl ether)-N,Nˊ-tetraacetic acid), alkylene polyamine polyacetic acid, N,N,Nˊ,Nˊ-tetra-(2-hydroxypropyl)ethylenediamine, ethylenediamine, triethylenetetraamine, diethylenetriamine, tetra(aminoethyl)ethylenediamine or polyamines and their sodium, potassium or ammonium salts.

[0073] According to one embodiment of the present invention, the above-mentioned conductivity enhancer can improve the metal deposition properties by increasing the conductivity of the plating solution.

[0074] According to one embodiment of the present invention, the above-mentioned conductivity enhancer may be oxalic acid, malonic acid, phosphoric acid, pyrophosphate, succinic acid, glutaric acid, adipic acid, pimelic acid, octanoic acid, azelaic acid, sebacic acid, undecanoic acid, dodecanoic acid, 3,3-dimethylvaleric acid, cyclopentanedicarboxylic acid or cyclohexanedicarboxylic acid and their alkali metal salts, alkaline earth metal salts or ammonium salts.

[0075] According to one embodiment of the present invention, the corrosion inhibitor of the secondary material described above can inhibit the elution of the secondary metal, prevent the redeposition of the secondary metal, and inhibit the corrosion of the metal.

[0076] According to an embodiment of the present invention, the erosion inhibitor of the above-mentioned secondary material may be imidazole carboxylic acid, imidazole dicarboxylic acid, pyridine carboxylic acid, pyridine dicarboxylic acid, pyrimidine carboxylic acid, pyrimidine dicarboxylic acid, pyridazine carboxylic acid, pyridazine dicarboxylic acid, pyrazine carboxylic acid, pyrazine dicarboxylic acid and mixtures thereof, 2-imidazole carboxylic acid, imidazole-4-carboxylic acid, imidazole-2,4-dicarboxylic acid, imidazole-4,5-dicarboxylic acid, glycolic acid, lactic acid, hydroxybutyric acid, hydroxyvalerate, hydroxy-n-valerate, hydroxyhexanoic acid, hydroxymonocarboxylic acid, hydroxysuccinic acid, hydroxybutyric acid, citric acid or α-hydroxydicarboxylic acid.

[0077] According to an embodiment of the present invention, when impact gold is directly plated on a copper surface, the aforementioned secondary material erosion aid inhibitor can prevent localized erosion phenomena such as holes and pinholes.

[0078] According to one embodiment of the present invention, the above-mentioned secondary material erosion auxiliary inhibitor may be 2-amino-9H-purine-6(H)-one, 3,7-dihydro-purine-2,6-dione, 2-mercaptopyrimidine, 2-amino-5-mercapto-1,3,4-thiadiazole, 2-mercaptobenzoxazole, 2-mercaptobenzothiazole or 2-mercaptobenzimidazole.

[0079] According to one embodiment of the present invention, the above-mentioned plating wetting agent can adjust the wettability between the plating solution and the metal surface and make the size of the plated particles smaller.

[0080] According to one embodiment of the present invention, the above-mentioned coating wetting agent may be polyethylene glycol, polyoxyethylene ether, polyoxyethylene alkylamino ether, polynatyl ethyl ether, polyethylene glycol or polypropylene.

[0081] According to one embodiment of the present invention, the above-described impact gold plating composition, relative to 100 weight percent, may contain: 0.005 to 1.0 weight percent of a gold compound (gold content); 0.5 to 5 weight percent of a gold ion complexing agent; 0.1 to 10 weight percent of a conductivity enhancer; 0.1 to 2 weight percent of a secondary material erosion inhibitor; 0.01 to 1.0 weight percent of a secondary material erosion auxiliary inhibitor; 0.001 to 0.5 weight percent of a plating solution wetting agent; and the remainder being deionized water.

[0082] Furthermore, according to another embodiment of the present invention, a method for manufacturing a semiconductor packaging substrate is provided, characterized by comprising: step (a-1), degreasing a copper substrate using a degreasing solution; step (a-2), etching the degreased copper substrate using an etching solution; step (a-3), forming an impact gold plating layer on the etched copper substrate using an impact gold plating composition; step (a-4), forming a palladium plating layer on the impact gold plating layer using a palladium plating composition for semiconductor packaging substrates; and step (a-5), plating gold onto the palladium plating layer using a gold plating composition for semiconductor packaging substrates to manufacture a semiconductor packaging substrate having a gold plating layer. When the palladium plating composition is used on a microcircuit in the 4-50 μm pitch range of the semiconductor packaging substrate and measured under the circuit diffusion rate evaluation conditions of evaluation condition 1 below, the circuit diffusion rate is 0.001-8 volume percentages.

[0083] Evaluation Condition 1

[0084] Circuit diffusivity (volume percentage) = (diffusion width (μm) / circuit width (μm)) × 100

[0085] According to another embodiment of the present invention, a method for manufacturing a semiconductor packaging substrate is provided, characterized in that when the palladium plating composition of the above-described semiconductor packaging substrate manufacturing method is used on the above-described semiconductor packaging substrate and measured under the solder ball welding strength evaluation conditions of the following evaluation condition 2, the solder ball welding strength is 660 to 850 gf.

[0086] Evaluation Condition 2

[0087] Measurement method: Solder ball pull-out test

[0088] Solder balls: Arpmetal 0.45ΦSAC305 (Sn-3.0Ag-0.5Cu)

[0089] Reflow Soldering: Multi-functional Reflow Soldering Machine (BTU, VIP-70)

[0090] Reflow soldering conditions: Maximum 260℃

[0091] According to another embodiment of the present invention, a method for manufacturing a semiconductor packaging substrate is provided, characterized in that when the palladium plating composition of the above-described semiconductor packaging substrate manufacturing method is applied to the above-described semiconductor packaging substrate and evaluated under the solder diffusion evaluation conditions of the following evaluation condition 3, the solder ball diffusion is (width + length) / 2 of the diffused solder ball, and the solder ball diffusion length is 700 to 950 μm.

[0092] Evaluation Condition 3

[0093] Evaluation by reflow soldering the solder balls.

[0094] Solder ball diameter: 300μm

[0095] Solder ball type: SAC 305 (solder ball with 96.5% wt tin, 3% wt silver and 0.5% wt copper)

[0096] Reflow soldering conditions: Preheat at 130–200°C for 80–120 seconds, then bond (solder) at 240–260°C for 20–60 seconds.

[0097] According to another embodiment of the present invention, a method for manufacturing a semiconductor packaging substrate is provided, characterized in that when the palladium plating composition of the above-described semiconductor packaging substrate manufacturing method is used on the above-described semiconductor packaging substrate and measured under the lead bonding strength evaluation conditions of the following evaluation condition 4, the average lead bonding strength is 9 to 15 gf.

[0098] Evaluation Condition 4

[0099] Wire bonding machine: HB-16, W-4626 from 3H Corporation; Leads: 1mil-Au

[0100] Stage temperature: 165℃

[0101] The bond strength was determined by taking the average strength value after performing tensile tests on 30 specimens. The evaluation was conducted by identifying the breakage point of the lead wire to distinguish between a good mode and a bad mode where the bond interface failed.

[0102] According to another embodiment of the present invention, a method for manufacturing a semiconductor packaging substrate is provided, characterized in that, when the palladium plating composition of the above-described semiconductor packaging substrate manufacturing method is used on the above-described semiconductor packaging substrate to measure the interlayer blank area before heat treatment, the interlayer blank area before heat treatment is 0 to 5% by volume.

[0103] According to another embodiment of the present invention, a method for manufacturing a semiconductor packaging substrate is provided, characterized in that, when the palladium plating composition of the above-described semiconductor packaging substrate manufacturing method is used on the above-described semiconductor packaging substrate to measure the interlayer blank area after heat treatment, the interlayer blank area after heat treatment is 0 to 5% by volume.

[0104] According to another embodiment of the present invention, a method for manufacturing a semiconductor packaging substrate is provided, characterized in that when the palladium plating composition of the above-described semiconductor packaging substrate manufacturing method is used to perform a peel test on the semiconductor packaging substrate to determine the adhesion of the plating layer to confirm whether the base metal and the plating layer are separated and adhered to the tape, the base metal and the plating layer do not separate.

[0105] According to another embodiment of the present invention, a method for manufacturing a semiconductor packaging substrate is provided, characterized in that, when the gold plating composition of the above-described semiconductor packaging substrate manufacturing method is used on the semiconductor packaging substrate, the gold plating thickness is 0.03 to 0.50 μm.

[0106] According to another embodiment of the present invention, a method for manufacturing a semiconductor packaging substrate is provided, characterized in that, when the palladium plating composition of the above-described semiconductor packaging substrate manufacturing method is used in the above-described semiconductor packaging substrate, the palladium plating thickness is 0.03 to 0.50 μm.

[0107] According to one embodiment of the present invention, the thickness of the above-mentioned impact gold plating layer can be 2 to 30 nm.

[0108] According to one embodiment of the present invention, before the above-described step (a-1) of degreasing the copper substrate using a degreasing solution, a pretreatment step may be included using a pretreatment solution for removing the pre-washed material from the copper substrate.

[0109] According to an embodiment of the present invention, the above-described step (a-2) of etching a degreased copper substrate using an etching solution may further include a step of acid treatment using an acid treatment solution for removing etching residues.

[0110] According to an embodiment of the present invention, in the above step (a-3) of forming an impact gold plating layer on an etched copper substrate using an impact gold plating composition, a post-treatment step is further included, which uses a post-treatment solution to prevent the diffusion of fine-pitch particles.

[0111] Furthermore, according to another embodiment of the present invention, a semiconductor packaging substrate manufactured by the above-described semiconductor packaging substrate manufacturing method is provided.

[0112] The effects of the invention

[0113] According to the present invention, a palladium plating composition is provided for electroless plating of a copper substrate of a semiconductor packaging substrate, wherein the palladium plating has excellent physical properties.

[0114] Furthermore, the present invention provides a method for manufacturing a semiconductor packaging substrate using a palladium plating composition to form a fine-pitch chemical palladium impregnation gold plating layer, which has excellent process stability and is environmentally friendly.

[0115] Furthermore, the present invention provides a semiconductor packaging substrate manufactured by a method for forming a fine-pitch chemical palladium impregnation gold plating layer using a palladium plating composition. The semiconductor packaging substrate has excellent physical properties and is economical.

[0116] The effects of the present invention are not limited to those described above. It should be understood that all effects inferred from the structure of the invention as described in the detailed description of the invention or the claims should be included. Attached Figure Description

[0117] Figure 1 This is a process flow diagram of a method for manufacturing a semiconductor packaging substrate according to an embodiment of the present invention.

[0118] Figure 2 This is a photograph of a semiconductor packaging substrate for evaluation according to an embodiment of the present invention.

[0119] Figure 3 This is a scanning electron microscope (SEM) image of the coating on a semiconductor packaging substrate according to an embodiment of the present invention.

[0120] Figure 4 An optical microscope photograph showing the appearance of the palladium plating on a semiconductor packaging substrate according to an embodiment of the present invention.

[0121] Figure 5An optical microscope photograph showing the appearance of the gold plating on a semiconductor packaging substrate according to an embodiment of the present invention.

[0122] Figure 6 A scanning electron microscope image showing whether there is interlayer local erosion (holes) in the plating layer of a semiconductor packaging substrate before heat treatment according to an embodiment of the present invention.

[0123] Figure 7 This is a scanning electron microscope image showing whether there is interlayer localized erosion (holes) in the plating layer of a semiconductor packaging substrate after heat treatment according to an embodiment of the present invention.

[0124] Figure 8 A scanning electron microscope image showing the soldering test process of a semiconductor packaging substrate according to an embodiment of the present invention.

[0125] Figure 9 An optical photograph illustrating the solder ball diffusion properties of a semiconductor packaging substrate according to an embodiment of the present invention.

[0126] Figure 10 This is a schematic diagram illustrating a wire bonding measurement method for a semiconductor packaging substrate according to an embodiment of the present invention.

[0127] Figure 11 A scanning electron microscope image of the circuit diffusion rate of a semiconductor packaging substrate according to an embodiment of the present invention is shown. Detailed Implementation

[0128] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0129] The advantages, features, and methods of implementing the invention will become clear from the accompanying drawings and detailed embodiments described below.

[0130] However, the present invention is not limited to the embodiments disclosed below, but can be implemented in many other forms. The following embodiments are only used to make the disclosure of the present invention complete, and are provided only to enable those skilled in the art to fully understand the scope of the present invention. The present invention is defined only by the scope of the claims.

[0131] Furthermore, in describing the present invention, detailed descriptions of relevant prior art or other technologies will be omitted when it is determined that such technologies may unnecessarily obscure the essence of the present invention.

[0132] The present invention will now be described in detail.

[0133] Palladium plating composition

[0134] The present invention provides a palladium plating composition for electroless plating on a copper substrate of a semiconductor packaging substrate using a nickel-free electroplating method.

[0135] This invention provides a palladium plating composition for a semiconductor packaging substrate, comprising: a palladium compound; a plating uniformity enhancer; a reducing agent; a plating film improver; a metal ion complexing agent; a plating wetting agent; a pH adjuster; and deionized water. The palladium plating composition is chemically plated onto a copper substrate of the semiconductor packaging substrate using a nickel-free electroplating method. When the palladium plating composition is applied to a microcircuit with a pitch of 4–50 μm on the semiconductor packaging substrate and measured under the circuit diffusion rate evaluation conditions described in Evaluation Condition 1 below, the circuit diffusion rate can be 0.001–8 volume percentages.

[0136] Evaluation Condition 1

[0137] Circuit diffusivity (volume percentage) = (diffusion width (μm) / circuit width (μm)) × 100

[0138] The present invention provides a palladium plating composition for electroless plating on a copper substrate of a semiconductor packaging substrate using a nickel-free electroplating method, and the palladium plating has excellent physical properties.

[0139] In the manufacturing of electronic components, the steps that form circuits on a semiconductor wafer are called front-end processes, while the steps that assemble the wafer into a state that can be used in an actual product are called back-end processes or packaging processes.

[0140] In the field of semiconductor packaging, new packaging technologies that are thinner and smaller have been developed, replacing wire bonding or flip chip bonding technologies.

[0141] Among them, wire bonding technology is a method of bonding thin metal wires to pads. That is, it is a technology that connects the internal chip and the external environment. Structurally, the wires act as a bridge connecting the bonding pads of the chip (first bonding) and the pads of the carrier (second bonding).

[0142] Furthermore, there are three ways to connect the leads to the pads: heat bonding by heating and pressing the bonding pads and the wedge (a capillary-shaped lead moving tool); bonding by applying ultrasonic waves to the wedge without using heat; and a combination of heat and ultrasonic waves.

[0143] First, the thermoforming method is as follows: the temperature of the chip's bonding pads is raised to about 200°C in advance, and the temperature of the tip (end) of the wedge is also raised to make the lead into a ball shape, thereby applying pressure to the bonding pads through the wedge to attach the lead.

[0144] Furthermore, the ultrasonic method involves applying ultrasonic waves to the pads by attaching leads to a wedge (a lead-moving tool similar to a cleaver, which does not form a ball) to adhere the leads to the pads. This method offers advantages in terms of both process and material cost.

[0145] However, since ultrasound is used instead of heat and pressure, it has the disadvantage of being easy to operate but having poor tensile strength (the force that the lead wire can withstand when pulled after wiring) after bonding.

[0146] Furthermore, the most commonly used method in semiconductor manufacturing is thermo-ultrasound, which combines the advantages of thermoforming and ultrasonic bonding. Bonding is achieved under optimal conditions by applying heat, pressure, and ultrasonic waves to a bonding pad. Back-end semiconductor processes prioritize bond strength over cost, and therefore, even though it is more expensive, thermo-ultrasound primarily uses gold wire bonding.

[0147] Furthermore, flip-chip bonding technology involves placing the semiconductor chip face down and connecting electrically conductive metal protrusions to the bonding pads. Because flip-chip bonding faces the substrate without leads, it has the following characteristics: reduced size, reduced power consumption, reduced ambient noise, faster signal transmission due to shorter distances, and stronger bonding.

[0148] The materials used for metal protrusions are primarily solder and gold. Metal protrusions refer to conductive metal protrusions used to connect chips to circuit boards via tape-and-reel bonding or flip-chip bonding, or to directly connect ball grid arrays, chip-level packaging, etc., to circuit boards.

[0149] Solder protrusions will form spherical shapes through surface tension after the reflow soldering process. Gold protrusions, as one type of metal protrusion, will be formed into cuboids with length, width, and height through electroplating gold.

[0150] The wafers with gold protrusions will be used for tape-on packaging, crystal-glass bonding packaging, and thin-film flip-chip packaging, and will be used in products such as televisions, monitors, networks, mobile devices, tablets, and automotive digital imaging products.

[0151] Because of its excellent physical and chemical properties such as conductivity, oxidation resistance, and chemical resistance, gold plating is used in a variety of applications in microelectronics and optoelectronics, including redistribution layers, pattern plating, conformal via coatings, X-ray masks, microelectromechanical systems (MEMS), and gold bumps.

[0152] Currently, although a nickel plating layer is formed on the semiconductor packaging substrate as described above, the high plating thickness of the nickel plating layer makes it difficult to use for fine pitch, and it has the problem of cracking due to the poor flexibility of nickel metal.

[0153] Furthermore, in existing methods of electroless palladium plating after nickel plating on copper surfaces, if nickel plating is omitted in order to perform electroless palladium plating, pitting and pinholes will occur due to localized corrosion of the copper surface. Additionally, copper ions dissolve in the electroless palladium plating bath, leading to the problem of easy decomposition of the plating bath.

[0154] Therefore, through diligent efforts and extensive research, the applicant has obtained a palladium plating composition for electroless plating on a copper substrate of a semiconductor packaging substrate, a method for manufacturing a semiconductor packaging substrate using the same, and a semiconductor packaging substrate manufactured by the method, thereby completing the present invention.

[0155] The palladium plating composition described above can be chemically plated on the copper substrate of the semiconductor packaging substrate in a nickel-free electroplating manner.

[0156] In this case, the semiconductor packaging substrate of the present invention can be a semiconductor packaging substrate without forming a nickel plating layer.

[0157] Therefore, since the aforementioned semiconductor packaging substrate does not form a nickel plating layer belonging to the back film, it results in less signal loss and less diffusion of micro-circuits in high-frequency communication, making it easier to handle fine pitches and preventing cracks.

[0158] The palladium plating composition described above is chemically plated on the copper substrate of the semiconductor packaging substrate in a nickel-free electroplating manner. When the palladium plating composition is used on a microcircuit with a pitch of 4 to 50 μm on the semiconductor packaging substrate and measured under the circuit diffusion rate evaluation conditions of evaluation condition 1 below, the circuit diffusion rate can be 0.001 to 8 volume percentages.

[0159] Evaluation Condition 1

[0160] Circuit diffusivity (volume percentage) = (diffusion width (μm) / circuit width (μm)) × 100

[0161] Moreover, the aforementioned circuit diffusion rate can be obtained by measuring the diffusion volume using a scanning electron microscope.

[0162] If the diffusion rate of the circuit is within the above range, the semiconductor packaging substrate can be used for fine pitch.

[0163] In this case, preferably, the circuit diffusion rate can be 0.001 to 7.8 volume percentages, more preferably, it can be 0.001 to 7.5 volume percentages.

[0164] Furthermore, when the above-mentioned palladium plating composition is used on the above-mentioned semiconductor packaging substrate and measured under the following evaluation condition 2 for solder ball welding strength evaluation, the solder ball welding strength can be 700 to 850 gf.

[0165] Evaluation Condition 2

[0166] Measurement method: Ball pull test.

[0167] Solder balls: Arp 0.45ΦSAC305 (Sn-3.0Ag-0.5Cu),

[0168] Reflow Soldering: Multi-functional Reflow Soldering Machine (BTU, VIP-70)

[0169] Reflow soldering conditions: Maximum 260℃

[0170] Furthermore, the aforementioned solder ball bonding strength is used in flip chip bonding technology to evaluate the bonding strength between the semiconductor packaging substrate and the solder bumps.

[0171] When measuring the semiconductor packaging substrate using the solder ball welding strength evaluation condition 2, if the solder ball welding strength is within the above range, the bonding strength between the semiconductor packaging substrate and the solder bump is excellent, thereby enabling the packaging process to be well realized.

[0172] In this case, preferably, the welding strength of the aforementioned welding ball can be 710 to 850 gf, more preferably, it can be 720 to 850 gf.

[0173] Furthermore, when the above-mentioned palladium plating composition is used on the above-mentioned semiconductor packaging substrate and evaluated under the solder diffusion evaluation conditions of evaluation condition 3 below, the solder ball diffusion is (width + length) / 2 of the diffused solder ball, and the solder ball diffusion length can be 700 to 950 μm.

[0174] Evaluation Condition 3

[0175] Evaluation by reflow soldering the solder balls.

[0176] Solder ball diameter: 300μm

[0177] Solder ball type: SAC 305 (solder ball with 96.5% wt tin, 3% wt silver and 0.5% wt copper)

[0178] Reflow soldering conditions: Preheat at 130–200°C for 80–120 seconds, then bond (solder) at 240–260°C for 20–60 seconds.

[0179] Furthermore, the aforementioned solder ball diffusion is used in flip chip bonding technology to evaluate the diffusion properties of solder bumps.

[0180] When measuring the semiconductor packaging substrate using the solder ball diffusion evaluation condition 3, if the solder ball diffusion length is within the above range, the bonding strength between the semiconductor packaging substrate and the solder bump is excellent, thereby enabling the packaging process to be well realized.

[0181] In this case, preferably, the diffusion length of the solder ball can be 700-945 μm, more preferably, it can be 700-940 μm.

[0182] Furthermore, when the above-mentioned palladium plating composition is used on the above-mentioned semiconductor packaging substrate and measured under the following evaluation condition 4 for wire bonding strength evaluation, the average wire bonding strength can be 9 to 15 gf.

[0183] Evaluation Condition 4

[0184] Wire bonding machine: HB-16, W-4626 from 3H Corporation; Leads: 1mil-Au

[0185] Stage temperature: 165℃

[0186] The bond strength was determined by taking the average strength value after performing tensile tests on 30 specimens. The evaluation was conducted by identifying the breakage point of the lead wire to distinguish between a good mode and a bad mode where the bond interface failed.

[0187] Furthermore, the aforementioned wire bonding strength is used in wire bonding technology to evaluate the bonding strength between the semiconductor packaging substrate and the wires.

[0188] When measuring the semiconductor packaging substrate using the lead bonding strength evaluation condition 4, if the lead bonding strength is within the above range after aging heat treatment at 165°C, the bonding strength between the semiconductor packaging substrate and the lead is excellent, thereby enabling the packaging process to be well realized.

[0189] In this case, preferably, the wire bonding strength can be 9 to 14.8 gf, more preferably, it can be 9 to 14.5 gf.

[0190] Furthermore, when the palladium plating composition described above is used on the semiconductor packaging substrate to measure the interlayer blank area before heat treatment, the interlayer blank area before heat treatment can be 0 to 5% by volume.

[0191] Furthermore, the blank area between the plating layers before heat treatment is the area of ​​the pores (voids between plating layers) on the surface of the copper substrate of the semiconductor packaging substrate before heat treatment, which is used to evaluate the corrosion or solder brittleness rate of the copper substrate and is measured by scanning electron microscope images.

[0192] If the blank area between the plating layers before the heat treatment is within the above range, the electrical connection between the semiconductor chip and the semiconductor packaging substrate will be excellent.

[0193] In this case, preferably, the blank area between the coating layers before the heat treatment can be 0 to 4.8% by volume, more preferably, it can be 0 to 4.5% by volume.

[0194] Furthermore, when the palladium plating composition described above is used in the semiconductor packaging substrate to measure the blank area between plating layers after heat treatment, the blank area between plating layers after heat treatment can be 0 to 5% by volume.

[0195] Furthermore, the blank area between the plating layers after the heat treatment is the area of ​​the pores (tiny pores between plating layers) on the surface of the copper substrate before the heat treatment of the semiconductor packaging substrate. It is used to evaluate the corrosion or solder brittleness rate of the copper substrate and is measured by scanning electron microscope images.

[0196] If the blank area between the plating layers after the heat treatment is within the above range, the electrical connection between the semiconductor chip and the semiconductor packaging substrate will be excellent.

[0197] In this case, preferably, the blank area between the coating layers after the above heat treatment can be 0 to 4.8% by volume, more preferably, it can be 0 to 4.5% by volume.

[0198] Furthermore, when the above-mentioned palladium plating composition is used in the above-mentioned semiconductor packaging substrate to perform a peel test on the tape to determine the adhesion of the plating to confirm whether the base metal and the plating are separated and attached to the tape, the base metal and the plating may not separate.

[0199] Furthermore, when the above-mentioned palladium plating composition is used in the above-mentioned semiconductor packaging substrate, a gold plating layer is also formed on the palladium plating layer, and the thickness of the gold plating layer can be 0.03 to 0.50 μm.

[0200] Preferably, the thickness of the gold plating layer can be 0.03 to 0.40 μm, more preferably, it can be 0.03 to 0.30 μm.

[0201] Furthermore, when the above-mentioned palladium plating composition is used in the above-mentioned semiconductor packaging substrate, the palladium plating thickness can be 0.03 to 0.50 μm.

[0202] Preferably, the thickness of the palladium coating can be 0.03 to 0.40 μm, more preferably, it can be 0.03 to 0.30 μm.

[0203] Furthermore, relative to 100% by weight of the above-mentioned palladium plating composition for semiconductor packaging substrates, it may contain: 0.01 to 1% by weight of a palladium compound (palladium content); 0.5 to 5% by weight of a plating uniformity enhancer; 0.1 to 5% by weight of a reducing agent; 0.1 to 3% by weight of a plating film improver; 0.1 to 5% by weight of a metal ion complexing agent; 0.001 to 0.5% by weight of a plating wetting agent; 1 to 10% by weight of a pH adjuster; and the remainder being deionized water.

[0204] Among them, the above-mentioned palladium compound, as a water-soluble palladium compound, can be used as a palladium metal supplement for pure palladium plating solution.

[0205] In this case, the palladium compound mentioned above can be palladium chloride, palladium sulfate, palladium tetrachloride, palladium acetate, palladium ammonium chloride, palladium ethylenediamine, or palladium pyrimidinone.

[0206] Furthermore, if the content of the palladium compound (palladium content) is within the above range, a palladium coating can be formed uniformly.

[0207] In this case, preferably, the content of the palladium compound (palladium content) can be 0.01 to 0.98 weight percentages, more preferably, it can be 0.01 to 0.95 weight percentages.

[0208] Furthermore, the aforementioned coating uniformity enhancer can improve the coating uniformity and conductivity of palladium metal.

[0209] The coating uniformity enhancer can be glycolic acid, lactic acid, tartaric acid, malic acid, aminosuccinic acid, citric acid, gluconic acid, oxalic acid, malonic acid, ascorbic acid, hydrochloric acid, or citric acid.

[0210] Furthermore, if the above-mentioned coating uniformity enhancer is within the above-mentioned range, the palladium coating can be made smooth.

[0211] In this case, preferably, the content of the coating uniformity enhancer can be 0.5 to 4.98% by weight, more preferably, it can be 0.5 to 4.95% by weight.

[0212] Furthermore, the aforementioned reducing agents can impart reducing properties to palladium metal to promote precipitation.

[0213] The reducing agent mentioned above can be phosphonic acid, ammonium phosphite, sodium phosphite, potassium phosphite, ammonium phosphite, ammonium formate, sodium formate, potassium formate, calcium formate, or formaldehyde.

[0214] Furthermore, if the content of the reducing agent is within the above range, a palladium coating can be formed uniformly.

[0215] Preferably, the content of the reducing agent can be 0.1 to 4.98% by weight, more preferably, it can be 0.1 to 4.95% by weight.

[0216] Furthermore, the aforementioned coating modifier can achieve high-purity palladium coating, providing excellent heat resistance and enhancing the adhesion between coating layers.

[0217] In this case, the above-mentioned coating modifier can be 1,3-dihydro-2H-imidazolium, 1,3-dimethyl-3,4,5,6-tetrahydro-2(1H)-pyrimidinone, 4(s)-4-hydroxy-3,4-dihydro-2(1H)-pyrimidinone, 1,3-dihydro-2H-imidazolium-2-one, 1-methyl-tetrahydro-2(1H)-pyrimidinone, or 4-amino-2(1H)-pyrimidinone.

[0218] Furthermore, if the content of the above-mentioned coating modifier is within the above range, a palladium coating can be formed smoothly.

[0219] Preferably, the content of the coating improvement agent can be 0.1 to 2.98% by weight, more preferably, it can be 0.1 to 2.95% by weight.

[0220] Furthermore, the aforementioned metal ion complexing agent can prevent metal ion precipitation by dissolving, coordinating, and complexing metal ions in the plating solution.

[0221] In this case, the aforementioned metal ion complexing agent can be ethylenediaminetetraacetic acid, diethylenetriaminepentaacetic acid, triethylenetetraaminehexaacetic acid, propylenediaminetetraacetic acid, N-(2-hydroxyethyl)ethylenediaminetriacetic acid, 1,3-diamino-2-hydroxypropane-N,N,Nˊ,Nˊ-tetraacetic acid, bis-(hydroxyphenyl)-ethylenediaminediaacetic acid, diaminocyclohexanetetraacetic acid, ethylene glycol-bis((β-aminoethyl ether)-N,Nˊ-tetraacetic acid), alkylene polyamine polyacetic acid, N,N,Nˊ,Nˊ-tetra-(2-hydroxypropyl)ethylenediamine, ethylenediamine, triethylenetetraamine, diethylenetriamine, tetra(aminoethyl)ethylenediamine, or polyamines and their sodium, potassium, or ammonium salts.

[0222] Furthermore, if the content of the aforementioned metal ion complexing agent is within the above-mentioned range, a palladium coating can be formed uniformly.

[0223] Preferably, the content of the metal ion complexing agent can be 0.1 to 4.98% by weight, more preferably, it can be 0.1 to 4.95% by weight.

[0224] Furthermore, the aforementioned plating wetting agent can adjust the wettability between the plating solution and the metal surface and refine the size of the plated particles.

[0225] The aforementioned coating wetting agent can be polyethylene glycol, polyoxyethylene ether, polyoxyethylene alkylamino ether, polynatyl ethyl ether, polyethylene glycol, polypropylene glycol, or polypropylene.

[0226] Furthermore, if the content of the above-mentioned coating wetting agent is within the above-mentioned range, a palladium coating can be formed smoothly.

[0227] Preferably, the content of the above-mentioned coating wetting agent can be 0.001 to 0.498% by weight, more preferably, it can be 0.001 to 0.495% by weight.

[0228] Furthermore, the aforementioned pH adjuster can be used to maintain the pH of the plating solution.

[0229] In this case, the pH adjuster mentioned above can be hydrochloric acid, sulfuric acid, nitric acid, boric acid, sodium hydroxide, or potassium hydroxide.

[0230] Furthermore, if the content of the pH adjuster is within the above range, a palladium coating can be formed uniformly.

[0231] Preferably, the content of the pH adjuster can be 1 to 9.8% by weight, more preferably, it can be 1 to 9.5% by weight.

[0232] Furthermore, the aforementioned direct gold plating composition may also include a bomb gold plating composition for plating bomb gold before directly plating palladium onto the copper substrate of the aforementioned semiconductor packaging substrate.

[0233] The aforementioned impact gold plating composition may include: a gold compound; a gold ion complexing agent; a conductivity enhancer; an erosion inhibitor for secondary materials; an auxiliary erosion inhibitor for secondary materials; a plating solution wetting agent; and deionized water.

[0234] The aforementioned impact gold plating composition can be a chemical impact gold plating composition.

[0235] In this case, the above-mentioned chemically impacted gold plating composition may contain a gold cyanide compound or a cyanide-free gold compound.

[0236] Moreover, the impact gold plating layer formed on the aforementioned copper substrate can act as a catalyst for the formation of subsequent gold plating layers.

[0237] Furthermore, the impact gold plating formed on the copper substrate can suppress the corrosion or pores (tiny pores between plating layers) of the copper substrate.

[0238] The thickness of the impact gold plating layer formed by the above-mentioned impact gold plating composition can be 2 to 30 nm.

[0239] If the thickness of the impact gold plating layer formed on the copper substrate deviates from the above range, erosion or voids (micropores between plating layers) will occur on the copper substrate of the semiconductor packaging substrate.

[0240] In this case, preferably, the thickness of the impact gold plating layer formed on the copper substrate can be 2 to 28 nm, more preferably, it can be 2 to 25 nm.

[0241] Furthermore, the palladium plating layer formed on the aforementioned impact gold plating layer can be formed from a palladium plating composition.

[0242] The palladium plating composition described above can be a chemical palladium plating composition.

[0243] Furthermore, the palladium plating formed on the aforementioned impact gold plating layer can serve to electrically connect the semiconductor chip to the copper substrate through wire bonding or flip chip bonding processes.

[0244] Furthermore, the palladium plating formed on the aforementioned impact gold plating layer can inhibit the erosion or dissolution of the aforementioned copper substrate and suppress corrosion.

[0245] Moreover, the thickness of the palladium coating formed on the aforementioned impact gold coating can be 0.03 to 0.50 μm.

[0246] If the thickness of the palladium plating layer formed by the impact gold plating layer deviates from the above range, the copper substrate of the semiconductor packaging substrate will be eroded or dissolved, resulting in corrosion.

[0247] In this case, preferably, the thickness of the palladium coating formed by the impact gold coating can be 0.03 to 0.40 μm, more preferably, it can be 0.03 to 0.30 μm.

[0248] Furthermore, the gold plating layer formed on the palladium plating layer can be formed from a gold plating composition.

[0249] The gold plating composition can be a chemical gold plating composition.

[0250] Furthermore, the gold plating layer formed on the palladium plating layer can serve to electrically connect the semiconductor chip to the copper substrate through the bonding wire process or the flip chip bonding process.

[0251] Furthermore, the gold plating layer formed on the palladium plating layer can inhibit the erosion or dissolution of the copper substrate, thus suppressing corrosion.

[0252] Furthermore, the thickness of the gold plating layer formed on the palladium plating layer can be 0.03 to 0.50 μm.

[0253] If the thickness of the gold plating layer formed by the palladium plating layer deviates from the above range, the copper substrate of the semiconductor packaging substrate will be eroded or dissolved, resulting in corrosion.

[0254] In this case, preferably, the thickness of the gold plating layer formed on the palladium plating layer can be 0.03 to 0.40 μm, more preferably, it can be 0.03 to 0.30 μm.

[0255] Furthermore, relative to 100% by weight of the above-mentioned impact gold plating composition, it may contain: 0.005 to 1.0% by weight of a gold compound (gold content); 0.5 to 5% by weight of a gold ion complexing agent; 0.1 to 10% by weight of a conductivity enhancer; 0.1 to 2% by weight of a secondary material erosion inhibitor; 0.01 to 1.0% by weight of a secondary material erosion auxiliary inhibitor; 0.001 to 0.5% by weight of a plating solution wetting agent; and the remainder being deionized water.

[0256] Among them, the above-mentioned gold compound, as a water-soluble gold compound, can be a gold supplement for gold impact plating solution.

[0257] In this case, the gold compound can be potassium gold cyanide, potassium gold cyanide, potassium gold chloride, potassium gold chloride, potassium gold sulfite, sodium gold sulfite, potassium gold thiosulfate, or sodium gold thiosulfate.

[0258] Furthermore, if the content of the aforementioned gold compound (gold content) is within the above range, a uniform impact gold plating layer can be formed, which can be well deposited with the subsequent palladium plating layer.

[0259] In this case, preferably, the content of the gold compound (gold content) can be 0.005 to 0.998 weight percentages, more preferably, it can be 0.005 to 0.995 weight percentages.

[0260] Furthermore, the aforementioned gold ion complexing agent can prevent the precipitation of metal ions by dissolving, coordinating, and complexing metal ions in the plating solution.

[0261] The gold ion complexing agent mentioned above can be ethylenediaminetetraacetic acid, diethylenetriaminepentaacetic acid, triethylenetetraaminehexaacetic acid, propylenediaminetetraacetic acid, N-(2-hydroxyethyl)ethylenediaminetriacetic acid, 1,3-diamino-2-hydroxypropane-N,N,Nˊ,Nˊ-tetraacetic acid, bis-(hydroxyphenyl)-ethylenediaminediaacetic acid, diaminocyclohexanetetraacetic acid, ethylene glycol-bis((β-aminoethyl ether)-N,Nˊ-tetraacetic acid), alkylene polyamine polyacetic acid, N,N,Nˊ,Nˊ-tetra-(2-hydroxypropyl)ethylenediamine, ethylenediamine, triethylenetetraamine, diethylenetriamine, tetra(aminoethyl)ethylenediamine or polyamines and their sodium, potassium or ammonium salts.

[0262] Moreover, if the content of the gold ion complexing agent is within the above range, a smooth impact gold plating layer can be formed, which can be well deposited with the subsequent palladium plating layer.

[0263] In this case, preferably, the content of the gold ion complexing agent can be 0.5 to 4.98% by weight, more preferably, it can be 0.5 to 4.95% by weight.

[0264] Furthermore, the aforementioned conductivity enhancer can improve the metal deposition properties by increasing the conductivity of the plating solution.

[0265] The aforementioned conductivity enhancer may be oxalic acid, malonic acid, phosphoric acid, pyrophosphate, succinic acid, glutaric acid, adipic acid, pimelic acid, octanoic acid, azelaic acid, sebacic acid, undecanoic acid, dodecanoic acid, 3,3-dimethylvaleric acid, cyclopentanedicarboxylic acid or cyclohexanedicarboxylic acid and their alkali metal salts, alkaline earth metal salts or ammonium salts.

[0266] Furthermore, if the content of the aforementioned conductivity enhancer is within the above range, a uniform impact gold plating layer can be formed, which can be well deposited with the subsequent palladium plating layer.

[0267] In this case, preferably, the content of the conductivity enhancer can be 0.1 to 9.98% by weight, more preferably, it can be 0.1 to 90.95% by weight.

[0268] Furthermore, the corrosion inhibitors of the aforementioned secondary materials can inhibit the dissolution of secondary metals and prevent metal re-precipitation, thereby inhibiting metal corrosion.

[0269] The erosion inhibitors of the aforementioned secondary materials may be imidazole carboxylic acid, imidazole dicarboxylic acid, pyridine carboxylic acid, pyridine dicarboxylic acid, pyrimidine carboxylic acid, pyrimidine dicarboxylic acid, pyridazine carboxylic acid, pyridazine dicarboxylic acid, pyrazine carboxylic acid, pyrazine dicarboxylic acid and mixtures thereof, 2-imidazole carboxylic acid, imidazole-4-carboxylic acid, imidazole-2,4-dicarboxylic acid, imidazole-4,5-dicarboxylic acid, glycolic acid, lactic acid, hydroxybutyric acid, hydroxyvalerate, hydroxy-n-valerate, hydroxyhexanoic acid, hydroxymonocarboxylic acid, hydroxysuccinic acid, tartaric acid, citric acid or α-hydroxydicarboxylic acid.

[0270] Furthermore, if the content of the erosion inhibitor of the aforementioned secondary material is within the above range, an impact gold plating layer can be smoothly formed, which can be well deposited with the subsequent palladium plating layer.

[0271] In this case, preferably, the content of the erosion inhibitor of the secondary material can be 0.1 to 1.98% by weight, more preferably, it can be 0.1 to 1.95% by weight.

[0272] Furthermore, when impact gold is directly plated on a copper surface, the aforementioned secondary material corrosion inhibitor can prevent localized corrosion phenomena such as pores and pinholes.

[0273] Among them, the aforementioned secondary material erosion auxiliary inhibitors can be 2-amino-9H-purine-6(H)-one, 3,7-dihydro-purine-2,6-dione, 2-mercaptopyrimidine, 2-amino-5-mercapto-1,3,4-thiadiazole, 2-mercaptobenzoxazole, 2-mercaptobenzothiazole or 2-mercaptobenzoimidazole.

[0274] Moreover, if the content of the aforementioned secondary material erosion-aiding inhibitor is within the above range, an impact gold plating layer can be smoothly formed, which can be well deposited with the subsequent palladium plating layer.

[0275] In this case, preferably, the content of the secondary material erosion-aiding inhibitor can be 0.01 to 0.998% by weight, more preferably, it can be 0.01 to 0.995% by weight.

[0276] Furthermore, the aforementioned plating wetting agent can adjust the wettability between the plating solution and the metal surface and refine the size of the plated particles.

[0277] The aforementioned coating wetting agent can be polyethylene glycol, polyoxyethylene ether, polyoxyethylene alkylamino ether, polynatyl ethyl ether, polyethylene glycol, polypropylene glycol, or polypropylene.

[0278] Furthermore, if the content of the above-mentioned plating wetting agent is within the above range, an impact gold plating layer can be formed uniformly, which can be well deposited with the subsequent palladium plating layer.

[0279] In this case, preferably, the content of the above-mentioned coating wetting agent can be 0.001 to 0.498 weight percentages, more preferably, it can be 0.001 to 0.495 weight percentages.

[0280] Manufacturing method of substrate for semiconductor packaging

[0281] The present invention provides a semiconductor packaging substrate for forming a fine-pitch chemical palladium-impregnated gold plating layer using a palladium plating composition.

[0282] The method for manufacturing a semiconductor packaging substrate of the present invention includes: step (a-1), degreasing a copper substrate using a degreasing solution; step (a-2), etching the degreased copper substrate using an etching solution; step (a-3), forming an impact gold plating layer on the etched copper substrate using an impact gold plating composition; step (a-4), forming a palladium plating layer on the impact gold plating layer using a palladium plating composition for semiconductor packaging substrates; and step (a-5), plating gold onto the palladium plating layer using a gold plating composition for semiconductor packaging substrates to manufacture a semiconductor packaging substrate having a gold plating layer. When the palladium plating composition is used on a microcircuit in the 4-50 μm pitch range of the semiconductor packaging substrate and measured under the circuit diffusion rate evaluation conditions of evaluation condition 1 below, the circuit diffusion rate is 0.001-8 volume percentages.

[0283] Evaluation Condition 1

[0284] Circuit diffusivity (volume percentage) = (diffusion width (μm) / circuit width (μm)) × 100

[0285] This invention provides a method for manufacturing a semiconductor packaging substrate using a palladium plating composition to form a fine-pitch chemical palladium impregnation gold plating layer, which has excellent process stability and is environmentally friendly.

[0286] In this case, the semiconductor packaging substrate of the present invention can be a semiconductor packaging substrate without forming a nickel plating layer.

[0287] Therefore, since the aforementioned semiconductor packaging substrate does not form a nickel plating layer belonging to the back film, it results in less signal loss and less diffusion of micro-circuits in high-frequency communication, making it easier to handle fine pitches and preventing cracks.

[0288] Furthermore, the copper substrate can be a copper metal substrate selected from printed circuit boards (PCBs) or glass substrates.

[0289] Furthermore, the oxide film on the surface of the aforementioned copper substrate can be appropriately removed using a reducing agent.

[0290] Moreover, the thickness of the aforementioned copper substrate can be 0.005 to 10 mm.

[0291] If the thickness of the copper substrate is within the aforementioned range, it facilitates the conduction of electrical signals on the semiconductor packaging substrate.

[0292] In this case, preferably, the thickness of the copper substrate can be 0.005 to 9.8 mm, more preferably, it can be 0.01 to 9.8 mm.

[0293] Furthermore, in the above step (a-1) of using a degreasing solution to degrease the copper substrate, the degreasing solution can be a solvent degreasing solution, an acidic degreasing solution, an alkaline degreasing solution, a plating wetting agent degreasing solution, an electrolytic degreasing solution, or an ultrasonic degreasing solution.

[0294] Specifically, the degreasing solution can be at least one of ACIDCLEAN 620, ACIDCLEAN 420 and ACIDCLEAN 820 selected from MK Chem&Tech.

[0295] The degreasing solution can remove contaminants that adhere to the copper substrate during the manufacturing process.

[0296] Furthermore, in the above step (a-2) of etching the degreased copper substrate using an etching solution, the etching solution may be an etching solution containing phosphoric acid, an etching solution containing nitric acid, an etching solution containing both phosphoric acid and nitric acid, an etching solution containing sulfuric acid, an etching solution containing hydrochloric acid, or an etching solution containing both sulfuric acid and hydrochloric acid.

[0297] Specifically, the etching solution can be at least one of MKS-1200, MKS-4000, MKS-6000, FSE-200 and MKS-4000N selected from MK Chem&Tech.

[0298] The etching solution described above can be used to finely etch the surface of the degreased copper substrate.

[0299] Furthermore, in the above step (a-3) of forming an impact gold plating layer on an etched copper substrate using an impact gold plating composition, the impact gold plating layer formed on the etched copper substrate can be formed by the impact gold plating composition.

[0300] The aforementioned impact gold plating composition can be a chemical impact gold plating composition.

[0301] In this case, the above-mentioned chemically bombarded gold plating composition may contain gold cyanide compounds or cyanide-free gold compounds and purine or pyrimidine compounds having carbonyl oxygen.

[0302] Moreover, the impact gold plating layer formed on the etched copper substrate can act as a catalyst for the subsequent formation of the palladium plating layer.

[0303] Furthermore, the impact gold plating layer formed on the etched copper substrate can suppress the erosion or pores (micropores between plating layers) of the copper substrate.

[0304] Moreover, the thickness of the impact gold plating layer formed on the etched copper substrate can be 2 to 30 nm.

[0305] If the thickness of the impact gold plating layer formed on the etched copper substrate deviates from the above range, erosion or voids (micropores between plating layers) will occur on the copper substrate of the semiconductor packaging substrate.

[0306] In this case, preferably, the thickness of the impact gold plating layer formed on the etched copper substrate can be 2 to 28 nm, more preferably, it can be 2 to 25 nm.

[0307] Furthermore, in the above step (a-4) of forming a palladium plating layer in a gold impactor using a palladium plating composition for semiconductor packaging substrates, the palladium plating layer formed in the gold impactor can be formed by the palladium plating composition.

[0308] The palladium plating composition described above can be a chemical palladium plating composition.

[0309] Furthermore, the palladium plating layer formed by the aforementioned impact gold plating layer can inhibit the erosion or dissolution of the aforementioned copper substrate, thus suppressing corrosion.

[0310] Furthermore, the thickness of the palladium coating formed on the aforementioned impact gold coating can be 0.03–0.50 μm.

[0311] If the thickness of the palladium plating layer formed by the impact gold plating layer deviates from the above range, the copper substrate of the semiconductor packaging substrate will be eroded or dissolved, resulting in corrosion.

[0312] In this case, preferably, the thickness of the palladium coating formed by the impact gold coating can be 0.03 to 0.40 μm, more preferably, it can be 0.03 to 0.30 μm.

[0313] Furthermore, in the above-described step (a-5) of manufacturing a semiconductor packaging substrate having a gold plating layer by plating a palladium plating layer with gold using a gold plating composition for semiconductor packaging substrate, the gold plating layer formed on the palladium plating layer can be formed by the gold plating composition.

[0314] The gold plating composition can be a chemical gold plating composition.

[0315] In this case, the above-mentioned chemical gold plating composition may contain a gold cyanide compound or a cyanide-free gold compound.

[0316] Furthermore, the gold plating layer formed on the palladium plating layer can serve to electrically connect the semiconductor chip to the copper substrate through the bonding wire process or the flip chip bonding process.

[0317] Furthermore, the gold plating layer formed on the palladium plating layer can inhibit the erosion or dissolution of the copper substrate, thus suppressing corrosion.

[0318] Furthermore, the thickness of the gold plating layer formed on the palladium plating layer can be 0.03 to 0.50 μm.

[0319] If the thickness of the gold plating layer formed by the palladium plating layer deviates from the above range, the copper substrate of the semiconductor packaging substrate will be eroded or dissolved, resulting in corrosion.

[0320] In this case, preferably, the thickness of the gold plating layer formed on the palladium plating layer can be 0.03 to 0.40 μm, more preferably, it can be 0.03 to 0.30 μm.

[0321] When the above-mentioned palladium plating composition is used in a microcircuit with a pitch of 4 to 50 μm on the above-mentioned semiconductor packaging substrate and measured under the circuit diffusion rate evaluation conditions of evaluation condition 1 below, the circuit diffusion rate can be 0.001 to 8 volume percentages.

[0322] Moreover, the aforementioned circuit diffusion rate can be obtained by measuring the diffusion volume using a scanning electron microscope.

[0323] If the diffusion rate of the circuit is within the above range, the semiconductor packaging substrate can be used for fine pitch.

[0324] In this case, preferably, the circuit diffusion rate can be 0.001 to 7.8 volume percentages, more preferably, it can be 0.001 to 7.5 volume percentages.

[0325] Furthermore, when the above-mentioned palladium plating composition is used on the above-mentioned semiconductor packaging substrate and measured under the following evaluation condition 2 for solder ball welding strength evaluation, the solder ball welding strength can be 660 to 850 gf.

[0326] Evaluation Condition 2

[0327] Measurement method: Solder ball pull-out test.

[0328] Solder balls: Arp 0.45ΦSAC305 (Sn-3.0Ag-0.5Cu),

[0329] Reflow Soldering: Multi-functional Reflow Soldering Machine (BTU, VIP-70)

[0330] Reflow soldering conditions: Maximum 260℃

[0331] Furthermore, the aforementioned solder ball bonding strength is used in flip chip bonding technology to evaluate the bonding strength between the semiconductor packaging substrate and the solder bumps.

[0332] When measuring the semiconductor packaging substrate using the solder ball welding strength evaluation condition 2, if the solder ball welding strength is within the above range, the bonding strength between the semiconductor packaging substrate and the solder bump is excellent, thereby enabling the packaging process to be well realized.

[0333] In this case, preferably, the welding strength of the aforementioned welding ball can be 710 to 850 gf, more preferably, it can be 720 to 850 gf.

[0334] Furthermore, when the above-mentioned palladium plating composition is used on the above-mentioned semiconductor packaging substrate and evaluated under the solder diffusion evaluation conditions of evaluation condition 3 below, the solder ball diffusion is (width + length) / 2 of the diffused solder ball, and the solder ball diffusion length can be 700 to 950 μm.

[0335] Evaluation Condition 3

[0336] Evaluation by reflow soldering the solder balls.

[0337] Solder ball diameter: 300μm

[0338] Solder ball type: SAC 305 (solder ball with 96.5% wt tin, 3% wt silver and 0.5% wt copper)

[0339] Reflow soldering conditions: Preheat at 130–200°C for 80–120 seconds, then bond (solder) at 240–260°C for 20–60 seconds.

[0340] Furthermore, the aforementioned solder ball diffusion is used in flip chip bonding technology to evaluate the diffusion properties of solder bumps.

[0341] When measuring the semiconductor packaging substrate using the solder ball diffusion evaluation condition 3, if the solder ball diffusion length is within the above range, the bonding strength between the semiconductor packaging substrate and the solder bump is excellent, thereby enabling the packaging process to be well realized.

[0342] In this case, preferably, the diffusion length of the solder ball can be 700-945 μm, more preferably, it can be 700-940 μm.

[0343] Furthermore, when the above-mentioned palladium plating composition is used on the above-mentioned semiconductor packaging substrate and measured under the following evaluation condition 4 for wire bonding strength evaluation, the average wire bonding strength can be 9 to 15 gf.

[0344] Evaluation Condition 4

[0345] Wire bonding machine: HB-16, W-4626 from 3H Corporation; Leads: 1mil-Au

[0346] Stage temperature: 165℃

[0347] The bond strength was determined by taking the average strength value after performing tensile tests on 30 specimens. The evaluation was conducted by identifying the breakage point of the lead wire to distinguish between a good mode and a bad mode where the bond interface failed.

[0348] Furthermore, the aforementioned wire bonding strength is used in wire bonding technology to evaluate the bonding strength between the semiconductor packaging substrate and the wires.

[0349] When measuring the semiconductor packaging substrate using the lead bonding strength evaluation condition 4, if the lead bonding strength is within the above range after aging heat treatment at 165°C, the bonding strength between the semiconductor packaging substrate and the lead is excellent, thereby enabling the packaging process to be well realized.

[0350] In this case, preferably, the wire bonding strength can be 9 to 14.8 gf, more preferably, it can be 9 to 14.5 gf.

[0351] Furthermore, when the palladium plating composition described above is used on the semiconductor packaging substrate to measure the interlayer blank area before heat treatment, the interlayer blank area before heat treatment can be 0 to 5% by volume.

[0352] Furthermore, the blank area between the plating layers before heat treatment is the area of ​​the pores (tiny pores between plating layers) on the surface of the copper substrate of the semiconductor packaging substrate before heat treatment, which is used to evaluate the corrosion or solder brittleness rate of the copper substrate and is measured by scanning electron microscope images.

[0353] If the blank area between the plating layers before the heat treatment is within the above range, the electrical connection between the semiconductor chip and the semiconductor packaging substrate will be excellent.

[0354] In this case, preferably, the blank area between the coating layers before the heat treatment can be 0 to 4.8% by volume, more preferably, it can be 0 to 4.5% by volume.

[0355] Furthermore, when the palladium plating composition described above is used in the semiconductor packaging substrate to measure the blank area between plating layers after heat treatment, the blank area between plating layers after heat treatment can be 0 to 5% by volume.

[0356] Furthermore, the blank area between the plating layers after the heat treatment is the area of ​​the pores (tiny pores between plating layers) on the surface of the copper substrate before the heat treatment of the semiconductor packaging substrate. It is used to evaluate the corrosion or solder brittleness rate of the copper substrate and is measured by scanning electron microscope images.

[0357] If the blank area between the plating layers after the heat treatment is within the above range, the electrical connection between the semiconductor chip and the semiconductor packaging substrate will be excellent.

[0358] In this case, preferably, the blank area between the coating layers after the above heat treatment can be 0 to 4.8% by volume, more preferably, it can be 0 to 4.5% by volume.

[0359] Furthermore, when the above-mentioned palladium plating composition is used in the above-mentioned semiconductor packaging substrate to perform a peel test on the tape to determine the adhesion of the plating to confirm whether the base metal and the plating are separated and attached to the tape, the base metal and the plating may not separate.

[0360] Furthermore, before the above-mentioned step (a-1) of degreasing the copper substrate using a degreasing solution, a pretreatment step may be included using a pretreatment solution for removing the pre-washed material from the copper substrate.

[0361] The pretreatment solution can be a solvent pretreatment solution, an acidic pretreatment solution, an alkaline pretreatment solution, a plating wetting agent pretreatment solution, an electrolytic pretreatment solution, or an ultrasonic pretreatment solution.

[0362] Specifically, the degreasing solution can be at least one of ACIDCLEAN 620, ACIDCLEAN 420 and ACIDCLEAN 820 selected from MK Chem&Tech.

[0363] Furthermore, in the above step (a-2) of etching the degreased copper substrate using an etching solution, an acid treatment step may also be included, which uses an acid treatment solution to remove etching residues.

[0364] The acid treatment solution can be at least one selected from 2-10% by weight (wt%) of sulfuric acid aqueous solution, 2-10% by weight of phosphoric acid aqueous solution and 2-10% by weight of hydrochloric acid aqueous solution.

[0365] Furthermore, in the above step (a-3) of forming an impact gold plating layer on an etched copper substrate using an impact gold plating composition, a post-treatment step may also be included, which uses a post-treatment solution to prevent the diffusion of fine-pitch particles.

[0366] The post-treatment liquid can be selected from at least one of water washing liquid, anti-discoloration liquid, hydrogen catalytic removal liquid and rust inhibitor.

[0367] Specifically, the post-treatment solution can be at least one selected from NEOZEN APD-100, POST-DIP PR and 2-10% by weight aqueous sulfuric acid solution from MK Chem&Tech.

[0368] Figure 1 This is a process flow diagram of a method for manufacturing a semiconductor packaging substrate according to an embodiment of the present invention.

[0369] Reference Figure 1 In the method for manufacturing a substrate for semiconductor packaging, after degreasing a copper substrate with a degreasing solution (step S110), an etching solution is used to etch the degreased copper substrate (step S120).

[0370] Then, an impact gold plating layer is formed on the etched copper substrate using the impact gold plating composition (step S130).

[0371] Next, a palladium plating layer is formed on the above-mentioned impact gold plating layer using a palladium plating composition for semiconductor packaging substrates (step S140).

[0372] Then, a semiconductor packaging substrate with a gold plating layer is manufactured by plating gold onto the palladium plating layer using a gold plating composition for semiconductor packaging substrates (S150).

[0373] Semiconductor packaging substrate manufactured by a semiconductor packaging substrate manufacturing method

[0374] The present invention provides a semiconductor packaging substrate manufactured by a method for forming a fine-pitch chemical palladium impregnation gold plating layer using a palladium plating composition.

[0375] The present invention provides a semiconductor packaging substrate manufactured by the above-described method for manufacturing a semiconductor packaging substrate.

[0376] The present invention provides a semiconductor packaging substrate manufactured by a method of forming a fine-pitch chemical palladium impregnation gold plating layer using a palladium plating composition. The semiconductor packaging substrate has excellent physical properties and is economical.

[0377] The present invention will now be described in detail through embodiments. However, these embodiments are for more specific illustration of the invention, and the scope of the invention is not limited to these embodiments. The embodiments described below can be appropriately modified and altered by those skilled in the art within the scope of the invention.

[0378] Example

[0379] Examples 1-4: Manufacturing a semiconductor packaging substrate with a chemical palladium-impregnated gold plating layer

[0380] The printed circuit board used in this embodiment is an SMD type FR-4 substrate. Figure 2 Part (A) to Figure 2 Part (C) is a photograph showing the evaluation substrate used in this invention.

[0381] A 50 μm thick copper substrate (circuit spacing 50 μm) was degreased for 5 minutes at 45°C using MK Chem&Tech's ACID CLEAN 620 as the degreaser, and then etched for 2 minutes at 27°C using MK Chem&Tech's MKS-3000 as the etching solution.

[0382] Then, using a bombardment gold plating composition (MK Chem&Tech's NEOZEN SG) containing a gold cyanide compound and a purine compound with carbonyl oxygen, chemical bombardment gold was performed on the above-etched copper substrate at a temperature of 80°C for 5 minutes to a thickness of 10 nm.

[0383] Then, a substrate is manufactured on the above-mentioned impact gold coating using a palladium plating composition with the composition described in Table 2.

[0384] Then, a semiconductor packaging substrate with a gold plating film having a thickness of 0.10 μm is manufactured by electroless plating on the palladium film using a gold plating composition for semiconductor packaging substrates containing a gold cyanide compound (NEOZEN TG from MK Chem&Tech).

[0385] The manufacturing process of the test substrate is shown in Table 1 below. The simplified structure and thickness of the test substrate after palladium and gold plating are also shown. Figure 2 The image is shown in the scanning electron microscope.

[0386] Table 1

[0387]

[0388] *The reagents used in Table 1 are products of MK Chem&Tech Ltd.

[0389] *There are three water washing stages between each process.

[0390] Table 2

[0391]

[0392] Comparative example

[0393] Comparative Examples 1 to 2

[0394] Prepare a chemical palladium plating solution in deionized water according to the composition, content and conditions shown in Table 2 above, and process the substrate according to the process conditions and sequence in Table 1 above.

[0395] Comparative Example 3

[0396] Except for not plating with impact gold, the substrate was processed according to the process conditions and sequence in Table 1 above in the same way as in Comparative Example 1.

[0397] Comparative Example 3 above failed to form a palladium coating normally, resulting in insufficient coating quality.

[0398] Experimental Example

[0399] Experimental Example 1: Palladium plating thickness analysis and palladium plating appearance evaluation on semiconductor packaging substrates with chemical palladium impregnation gold plating.

[0400] The thicknesses of the palladium coatings in Examples 1 to 4 and Comparative Examples 1 to 2 were measured using an X-ray fluorescence spectrometry (XRF) coating analysis device, as shown in Table 3 below.

[0401] The thickness of the palladium coating in Examples 1 to 4 was measured to be 0.11–0.96 μm.

[0402] Furthermore, the thickness of the palladium coating in Comparative Examples 1 to 2 was measured to be 0.72 to 0.84 μm.

[0403] Furthermore, the palladium-plated specimens were observed using an optical microscope to check for any abnormal appearances such as spots or discoloration. The results are shown in Table 3 below. Figure 4 As shown.

[0404] Among them, as shown in Table 3 below and Figure 4 As shown, the palladium coatings of Examples 1 to 4 and Comparative Examples 1 to 2 all have good appearance.

[0405] Experimental Example 2: Analysis of Gold Plating Thickness and Evaluation of Gold Plating Appearance on Semiconductor Packaging Substrates with Chemical Palladium Impregnation Gold Plating

[0406] The thickness of the gold plating in Examples 1 to 4 and Comparative Examples 1 to 2 was measured using an X-ray fluorescence spectrometry coating analysis device, as shown in Table 3 below.

[0407] The thickness of the gold plating in Examples 1 to 4 was measured to be 0.11–0.13 μm.

[0408] Furthermore, the thickness of the gold plating in Comparative Examples 1 to 2 was measured to be 0.12 to 0.14 μm.

[0409] Furthermore, the appearance of the gold-plated test pieces was observed using an optical microscope to check for any abnormalities such as spots or discoloration. The results are shown in Table 3 below. Figure 5 As shown.

[0410] Among them, as shown in Table 3 below and Figure 5 As shown, the gold plating of Examples 1 to 4 and Comparative Examples 1 to 2 all have good appearance.

[0411] Experimental Example 3: Measurement of localized interlayer erosion (voids) in a semiconductor packaging substrate with a chemical palladium-impregnated gold plating layer before heat treatment.

[0412] After processing a 20 μm cross-section using a FEI HELIOS 6001FIB instrument, the localized interlayer erosion (porosity) of the coatings before heat treatment in Examples 1 to 4 and Comparative Examples 1 to 2 was observed using a scanning electron microscope, as shown in Table 3 below. Figure 6 As shown in Table 3 below, the results confirming whether there is localized corrosion in the coating before heat treatment are as follows. Figure 6 As shown.

[0413] Among them, as shown in Table 3 below and Figure 6 As shown, the coatings in Examples 1 to 4 above did not exhibit localized erosion before heat treatment.

[0414] Conversely, as shown in Table 3 below and Figure 6 As shown, the coatings of Comparative Examples 1 to 2 before heat treatment showed localized erosion.

[0415] Experimental Example 4: Measurement of localized interlayer erosion (voids) in a semiconductor packaging substrate with a chemical palladium-impregnated gold plating layer after heat treatment.

[0416] After heat-treating the plated specimens in an oven at 175°C for 24 hours, a 20μm cross-section was processed using a FEI HELIOS 6001FIB instrument. The localized interlayer erosion (porosity) of the heat-treated plating in Examples 1 to 4 and Comparative Examples 1 to 2 was observed using a scanning electron microscope, as shown in Table 3 below. Figure 7 As shown, the results confirming whether there is localized corrosion in the coating after heat treatment are presented in Table 3 below. Figure 7 As shown.

[0417] Among them, as shown in Table 3 below and Figure 7 As shown, the coatings in Examples 1 to 4 above did not exhibit localized erosion after heat treatment.

[0418] Conversely, as shown in Table 3 below and Figure 7 As shown, the coatings of Comparative Examples 1 to 2 exhibited localized erosion after heat treatment.

[0419] Experiment Example 5: Determination of Coating Adhesion

[0420] To determine the adhesion of the gold plating, a tape peel test was conducted to confirm whether the base metal of Examples 1 to 4 and Comparative Examples 1 to 2 separated from the plating and adhered to the tape. The results are shown in Table 3 below.

[0421] Among them, the coatings of Examples 1 to 4 above exhibit good adhesion.

[0422] In contrast, the coating of Comparative Example 1 showed good adhesion, but in Comparative Example 2, part of the base metal separated from the coating.

[0423] Experiment Example 6: Determining the Welding Strength of Solder

[0424] The tensile strength and failure mode of the solder balls of Examples 1 to 4 and Comparative Examples 1 to 2 were tested using a DAGE 4000 instrument under the following evaluation conditions 2. The tensile speed (PullSpeed) was set to 5000 μm / sec to determine the strength of the specimens after plating. A total of 30 experiments were performed to obtain the average value, and the results are shown in Table 3 below. Figure 8 This is a scanning electron microscope image of a solder ball in a soldering state.

[0425] Evaluation Condition 2

[0426] Measurement method: Ball pull test.

[0427] Solder balls: Arp 0.45ΦSAC305 (Sn-3.0Ag-0.5Cu),

[0428] Reflow Soldering: Multi-functional Reflow Soldering Machine (BTU, VIP-70)

[0429] Reflow soldering conditions: Maximum 260℃

[0430] Among them, the solder welding strength of Examples 1 to 4 is 739.4 to 749.2 gf.

[0431] Conversely, the solder welding strength of Comparative Examples 1 to 2 was 678.6 to 688.4 gf.

[0432] Experiment Example 7: Determination of solder ball diffusivity

[0433] After applying a thin film of flux to the plated test pieces of Examples 1 to 4 and Comparative Examples 1 to 2, 0.3ΦSAC305 (Sn-3.0Ag-0.5Cu) solder balls from Alpha Corporation were placed on the plates and reflow soldered. The length of the diffused solder balls was measured as (width + length) / 2. The results are shown in Table 3 below. Figure 9 As shown.

[0434] The solder diffusion of Examples 1 to 4 is 867–894 μm.

[0435] In contrast, the solder diffusion of Comparative Examples 1 to 2 was 640–690 μm.

[0436] Experiment Example 8: Determining Wire Bond Strength

[0437] To evaluate the bonding strength and failure mode of the wire bonds in Examples 1 to 4 and Comparative Examples 1 to 2, a DAGE 4000 instrument was used. The tensile speed was set to 1000 μm / sec. Figure 10 As shown, the fracture modes of the leads are divided into 5 stages. The bonding strength is obtained by taking the average strength value after tensile testing of 30 specimens. The good mode and the bad mode of bonding interface failure are distinguished by identifying the fracture point of the leads. The results are shown in Table 3 below.

[0438] In the above-mentioned Examples 1 to 4, the wire bonding strength is 12.6 to 13.9 g.

[0439] In contrast, the wire bonding strength of Comparative Examples 1 to 2 was 6.4 to 8.2 g.

[0440] Experiment Example 9: Determining the circuit diffusion rate

[0441] To determine the diffusion rate of the gold plating, scanning electron microscopy was used to observe circuits with a space of less than 20 μm after plating to confirm whether there was circuit diffusion in Examples 1 to 4 and Comparative Examples 1 to 2. The results are shown in Table 3 below. Figure 11 As shown.

[0442] In the above embodiments 1 to 4, the circuit diffusion rate is 0% by volume, meaning that no circuit diffusion occurred at all.

[0443] In contrast, the circuit diffusion rate of Comparative Examples 1 to 2 was 10 to 15% by volume, indicating significant circuit diffusion.

[0444] Table 3

[0445]

[0446] This concludes the description of specific embodiments of the palladium plating composition of the present invention, the method for manufacturing a semiconductor packaging substrate using the same, and the semiconductor packaging substrate manufactured by the method. However, it is self-evident that various modifications may exist without departing from the scope of the present invention.

[0447] Therefore, the scope of the present invention is not limited to the illustrated embodiments, but should be determined by the appended claims and equivalent scopes.

[0448] That is, the embodiments described are illustrative at all levels and should be understood as not limiting. The scope of the invention is presented by the appended claims, rather than by a detailed description, and should be interpreted as including all modifications or variations of the implementation derived from the meaning, scope, and equivalent concepts of the claims.

Claims

1. A palladium plating composition for use in semiconductor packaging substrates, characterized in that, Include: Palladium compounds; Coating uniformity enhancer; reducing agent; Coating and film improvement agents; Metal ion complexing agents; Coating wetting agent; pH adjuster; and Deionized water The palladium plating composition is chemically plated onto the copper substrate of the semiconductor packaging substrate using a nickel-free electroplating method. When the palladium plating composition is used in microcircuits with a 4-50 μm pitch on the semiconductor packaging substrate and measured under the circuit diffusion rate evaluation conditions of evaluation condition 1 below, the circuit diffusion rate is 0.001-8 volume percentage. Evaluation Criterion 1: Circuit diffusion rate (volume percentage) = (diffusion width (μm) / circuit width (μm)) × 100.

2. The palladium plating composition according to claim 1, characterized in that, When the palladium plating composition is used on the semiconductor packaging substrate and measured under the solder ball strength evaluation conditions of evaluation condition 2 below, the solder ball strength is 700-850 gf. Evaluation condition 2: Measurement method: Solder ball pull-out test. Solder balls: Arpmetal 0.45ΦSAC305, Sn-3.0Ag-0.5Cu, Reflow soldering: BTU's VIP-70 multi-function reflow soldering machine. Reflow soldering conditions: Maximum 260℃.

3. The palladium plating composition according to claim 1, characterized in that, When the palladium plating composition is used on the semiconductor packaging substrate and evaluated under the solder diffusion evaluation conditions of evaluation condition 3 below, the solder ball diffusion is (width + length) / 2 of the diffused solder ball, and the solder ball diffusion length is 700 to 950 μm. Evaluation condition 3: The solder balls were reflow soldered for evaluation. Solder ball diameter: 300μm Solder ball type: SAC 305, a solder ball containing 96.5% by weight of tin, 3% by weight of silver, and 0.5% by weight of copper. Reflow soldering conditions: Preheat at 130–200°C for 80–120 seconds, then bond at 240–260°C for 20–60 seconds, i.e., soldering.

4. The palladium plating composition according to claim 1, characterized in that, When the palladium plating composition is used on the semiconductor packaging substrate and measured under the lead bond strength evaluation conditions described in evaluation condition 4 below, the average lead bond strength is 9 to 15 gf. Evaluation Criterion 4: Wire bonding machine: HB-16, W-4626 from 3H Corporation; Leads: 1mil-Au. Stage temperature: 165℃ The bond strength was determined by taking the average strength value after performing tensile tests on 30 specimens. The bond strength was evaluated by identifying the break point of the lead wire to distinguish between good and bad modes where the bond interface was damaged.

5. The palladium plating composition according to claim 1, characterized in that, When the palladium plating composition is used on the semiconductor packaging substrate to measure the interlayer blank area before heat treatment, the interlayer blank area before heat treatment is 0 to 5% by volume.

6. The palladium plating composition according to claim 1, characterized in that, When the palladium plating composition is used on the semiconductor packaging substrate to measure the blank area between plating layers after heat treatment, the blank area between plating layers after heat treatment is 0 to 5% by volume.

7. The palladium plating composition according to claim 1, characterized in that, When the palladium plating composition is used on the semiconductor packaging substrate to perform a peel test on the adhesive tape to determine the adhesion of the plating to confirm whether the base metal and the plating are separated and adhered to the adhesive tape, the base metal and the plating do not separate.

8. The palladium plating composition according to claim 1, characterized in that, When the palladium plating composition is used in the semiconductor packaging substrate, a gold plating layer is also formed on the palladium plating layer, and the thickness of the gold plating layer is 0.03 to 0.50 μm.

9. The palladium plating composition according to claim 1, characterized in that, When the palladium plating composition is used in the semiconductor packaging substrate, the palladium plating thickness is 0.03 to 0.50 μm.

10. The palladium plating composition according to any one of claims 1 to 9, characterized in that, The coating uniformity enhancer improves the coating uniformity and conductivity of palladium metal.

11. The palladium plating composition according to any one of claims 1 to 9, characterized in that, The coating modifier forms a high-purity palladium coating, providing excellent heat resistance and enhancing the adhesion between coating layers.

12. The palladium plating composition according to any one of claims 1 to 9, characterized in that, The palladium plating composition for semiconductor packaging substrates comprises, relative to 100 weight percent: Palladium compounds, i.e., palladium content, are present in a concentration of 0.01 to 1% by weight. 0.5–5% by weight of coating uniformity enhancer; 0.1–5% by weight of reducing agent; 0.1–3% by weight of coating modifier; 0.1–5% by weight of metal ion complexing agent; 0.001 to 0.5% by weight of coating wetting agent; 1-10% by weight of pH adjuster; and The remaining amount of deionized water.

13. The palladium plating composition according to any one of claims 1 to 9, characterized in that, The palladium plating composition further comprises a bombardment gold plating composition for plating bombardment gold on a copper substrate prior to plating palladium on the semiconductor packaging substrate.

14. The palladium plating composition according to claim 13, characterized in that, The impact gold plating composition comprises: Gold compounds; Gold ion complexing agent; Conductivity enhancer; Erosion inhibitors for secondary materials; Secondary material erosion auxiliary inhibitor; Coating solution wetting agent; and Deionized water.

15. The palladium plating composition according to claim 14, characterized in that, When impact gold is directly plated on a copper surface, the secondary material erosion aid inhibitor prevents localized erosion phenomena, including pores and pinholes.

16. The palladium plating composition according to claim 14, characterized in that, The impact gold plating composition comprises, relative to 100% by weight, the following: Gold compounds ranging from 0.005 to 1.0% by weight, i.e., gold content; 0.5–5% by weight of gold ion complexing agent; 0.1 to 10% by weight of conductivity enhancer; 0.1–2 wt% of erosion inhibitors for secondary materials; Secondary material erosion-aiding inhibitors, ranging from 0.01 to 1.0% by weight; 0.001 to 0.5% by weight of plating solution wetting agent; and The remaining amount of deionized water.

17. A method for manufacturing a substrate for semiconductor packaging, characterized in that, include: Step (a-1): Degrease the copper substrate using a degreasing solution; Step (a-2): Etch the degreased copper substrate using an etching solution; Step (a-3): An impact gold plating layer is formed on the etched copper substrate using an impact gold plating composition; Step (a-4): A palladium plating layer is formed on the impacted gold plating layer using a palladium plating composition for semiconductor packaging substrates; and Step (a-5): A semiconductor packaging substrate with a gold plating layer is manufactured by plating gold onto the palladium plating layer using a gold plating composition for semiconductor packaging substrates. When the palladium plating composition is used in microcircuits with a 4-50 μm pitch on the semiconductor packaging substrate and measured under the circuit diffusion rate evaluation conditions of evaluation condition 1 below, the circuit diffusion rate is 0.001-8 volume percentage. Evaluation Criterion 1: Circuit diffusion rate (volume percentage) = (diffusion width (μm) / circuit width (μm)) × 100.

18. The method for manufacturing a semiconductor packaging substrate according to claim 17, characterized in that, When the palladium plating composition of the method for manufacturing the semiconductor packaging substrate is used on the semiconductor packaging substrate and measured under the solder ball welding strength evaluation conditions of evaluation condition 2 below, the solder ball welding strength is 660 to 850 gf. Evaluation condition 2: Measurement method: Solder ball pull-out test. Solder balls: Arpmetal 0.45ΦSAC305, Sn-3.0Ag-0.5Cu, Reflow soldering: BTU's VIP-70 multi-function reflow soldering machine. Reflow soldering conditions: Maximum 260℃.

19. The method for manufacturing a semiconductor packaging substrate according to claim 17, characterized in that, When the palladium plating composition of the semiconductor packaging substrate manufacturing method is used on the semiconductor packaging substrate and evaluated under the solder diffusion evaluation conditions of evaluation condition 3 below, the solder ball diffusion is (width + length) / 2 of the diffused solder ball, and the solder ball diffusion length is 700 to 950 μm. Evaluation condition 3: The solder balls were reflow soldered for evaluation. Solder ball diameter: 300μm Solder ball type: SAC 305, a solder ball containing 96.5% by weight of tin, 3% by weight of silver, and 0.5% by weight of copper. Reflow soldering conditions: Preheat at 130–200°C for 80–120 seconds, then bond at 240–260°C for 20–60 seconds, i.e., soldering.

20. The method for manufacturing a semiconductor packaging substrate according to claim 17, characterized in that, When the palladium plating composition of the method for manufacturing the semiconductor packaging substrate is used on the semiconductor packaging substrate and measured under the lead bond strength evaluation conditions of evaluation condition 4 below, the average lead bond strength is 9 to 15 gf. Evaluation Criterion 4: Wire bonding machine: HB-16, W-4626 from 3H Corporation; Leads: 1mil-Au. Stage temperature: 165℃ The bond strength was determined by taking the average strength value after performing tensile tests on 30 specimens. The bond strength was evaluated by identifying the break point of the lead wire to distinguish between good and bad modes where the bond interface was damaged.

21. The method for manufacturing a semiconductor packaging substrate according to claim 17, characterized in that, When the palladium plating composition of the method for manufacturing the semiconductor packaging substrate is used on the semiconductor packaging substrate to measure the interlayer blank area before heat treatment, the interlayer blank area before heat treatment is 0 to 5% by volume.

22. The method for manufacturing a semiconductor packaging substrate according to claim 17, characterized in that, When the palladium plating composition of the method for manufacturing the semiconductor packaging substrate is used on the semiconductor packaging substrate to measure the interlayer blank area after heat treatment, the interlayer blank area after heat treatment is 0 to 5% by volume.

23. The method for manufacturing a semiconductor packaging substrate according to claim 17, characterized in that, When the palladium plating composition of the semiconductor packaging substrate manufacturing method is used on the semiconductor packaging substrate to perform a peel test on the adhesive tape to determine the adhesion of the plating to confirm whether the base metal and the plating are separated and adhered to the adhesive tape, the base metal and the plating do not separate.

24. The method for manufacturing a semiconductor packaging substrate according to claim 17, characterized in that, When the gold plating composition of the method for manufacturing the semiconductor packaging substrate is used on the semiconductor packaging substrate, the gold plating thickness is 0.03 to 0.50 μm.

25. The method for manufacturing a semiconductor packaging substrate according to claim 17, characterized in that, When the palladium plating composition of the method for manufacturing the semiconductor packaging substrate is used in the semiconductor packaging substrate, the palladium plating thickness is 0.03 to 0.50 μm.

26. The method for manufacturing a semiconductor packaging substrate according to any one of claims 17 to 25, characterized in that, The thickness of the impact gold plating layer is 2–30 nm.

27. The method for manufacturing a semiconductor packaging substrate according to any one of claims 17 to 25, characterized in that, Prior to step (a-1) of degreasing the copper substrate using a degreasing solution, a pretreatment step is also included, using a pretreatment solution for removing the pre-washed material from the copper substrate.

28. A method for manufacturing a semiconductor packaging substrate according to any one of claims 17 to 25, characterized in that, The step (a-2) of etching the degreased copper substrate using an etching solution also includes an acid treatment step using an acid treatment solution to remove etching residues.

29. A method for manufacturing a semiconductor packaging substrate according to any one of claims 17 to 25, characterized in that, In step (a-3) of forming an impact gold plating layer on an etched copper substrate using an impact gold plating composition, a post-treatment step is also included, which uses a post-treatment solution to prevent the diffusion of fine-pitch particles.

30. A substrate for semiconductor packaging, characterized in that, Manufactured by the method for manufacturing a semiconductor packaging substrate according to any one of claims 17 to 25.

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