Optical proximity correction method and system, equipment and storage medium
By selecting interconnect end patterns for end compensation processing in the optical proximity correction method, the problem of large dimensional deviations in the design pattern during optical proximity correction is solved, thereby improving the accuracy of the interconnect structure and the performance of semiconductor devices.
Patent Information
- Application Number
- CN202410573342.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-09
- Publication Date
- 2025-11-11
AI Technical Summary
Existing optical proximity correction methods suffer from significant dimensional deviations during semiconductor manufacturing, particularly at the interconnect ends of the designed patterns. This results in insufficient precision in the interconnect structure and affects the performance of semiconductor devices.
In the design drawing, select the drawing with interconnected ends as the target drawing, extend it through end compensation processing, and perform optical proximity correction to form an optimized drawing to reduce dimensional deviations.
This improves the effectiveness of optical proximity correction processing, reduces dimensional deviations at interconnect ends, and enhances the accuracy of interconnect structures and the performance of semiconductor devices.
Smart Images
Figure CN120928642A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing, and more particularly to an optical proximity correction method and system, apparatus and storage medium. Background Technology
[0002] When the feature size of an integrated circuit approaches the system limit of a photolithography machine—that is, when the feature size is close to or smaller than the photolithography light source—significant distortion occurs in the pattern fabricated on the silicon wafer. This phenomenon is called the optical proximity effect. To address the optical proximity effect, resolution enhancement techniques have been proposed. Optical Proximity Correction (OPC) is a widely used resolution enhancement technique in advanced semiconductor manufacturing. OPC works by finding the relationship between pattern distortion and the inherent characteristics of the pattern, then using a model combining physics and mathematics to fit this relationship. Subsequently, based on this model, all patterns involved in the layout are comprehensively modified to ensure that a pattern conforming to design requirements is formed on the semiconductor substrate after exposure.
[0003] However, the effectiveness of the optical proximity correction method used in the existing technology still needs to be improved. Summary of the Invention
[0004] The problem addressed by the embodiments of the present invention is to provide an optical proximity correction method, system, device, and storage medium to improve the effect of optical proximity correction processing.
[0005] To address the aforementioned problems, embodiments of the present invention provide an optical proximity correction method, comprising: providing a design layout including multiple design patterns; selecting a design pattern with interconnect ends as a target pattern from the multiple design patterns, wherein the interconnect ends are used to realize the interconnection of corresponding structures of the design patterns on a wafer; performing end compensation processing on the interconnect ends of the target pattern to extend the interconnect ends of the target pattern to form an optimized pattern; and performing optical proximity correction processing on the optimized pattern.
[0006] Optionally, the design layout is provided, which includes a first layout layer and a second layout layer located above the first layout layer. The first layout layer includes a plurality of design graphics. The second layout layer includes interconnect via graphics, the projection of which onto the first layout layer is located within the design graphics. Among the plurality of design graphics, a design graphic with an interconnect end is selected as the target graphic, and the end of the design graphic with the projection of the interconnect via graphics is defined as the interconnect end.
[0007] Optionally, in the design layout, a plurality of design graphics extend along a first direction and are arranged in parallel along a second direction, wherein the first direction is perpendicular to the second direction; among the plurality of design graphics, a design graphic with interconnected ends is selected as the target graphic, wherein the design graphic whose interconnected ends are recessed along the first direction relative to the ends of adjacent design graphics is selected as the target graphic.
[0008] Optionally, the design layout may include metal line graphics.
[0009] Optionally, after selecting a design pattern with interconnected ends as the target pattern from among the multiple design patterns, the method further includes: setting a mark on the interconnected ends of the target pattern; performing end compensation processing on the interconnected ends of the target pattern to extend the interconnected ends of the target pattern to form an optimized pattern, wherein the end compensation processing is performed on the interconnected ends at the marked locations.
[0010] Optionally, end compensation processing is performed on the interconnect ends of the target graphic to extend the interconnect ends of the target graphic to form an optimized graphic, including: extending the target graphic along the first direction at the interconnect ends to obtain a compensation graphic of a preset length in the first direction; and combining the compensation graphic with the target graphic to form the optimized graphic.
[0011] Optionally, before selecting the design graphic with interconnected ends as the target graphic from among the multiple design graphics, the correction method further includes: performing global optical proximity correction processing on the design graphic of the design layout, wherein the global optical proximity correction processing includes: dividing the edges of the design graphic into multiple sequentially connected line segments; performing the global optical proximity correction processing on the design graphic using the multiple line segments; extending the target graphic along the first direction at the interconnected ends to obtain a compensation graphic of a preset length in the first direction, wherein the preset length is 2 to 3 times the length of the line segment.
[0012] Optionally, before selecting the design pattern with interconnected ends as the target pattern from among the multiple design patterns, the correction method further includes: performing global optical proximity correction processing on the design pattern of the design layout; and in performing optical proximity correction processing on the optimized pattern, performing local optical proximity correction processing on the portion of the design layout containing the optimized pattern.
[0013] Optionally, a local optical proximity correction process is performed on a portion of the design layout containing the optimized graphic, including: performing one or more correction iterations until the number of correction iterations reaches a preset number, wherein the correction iteration process includes: obtaining a portion of the design layout containing the optimized graphic as a reference area; performing local optical proximity correction on the reference area; wherein the reference area of the later correction iteration is expanded based on the reference area of the previous correction iteration.
[0014] Accordingly, embodiments of the present invention also provide an optical proximity correction system, comprising: a design layout providing module for providing a design layout including a plurality of design patterns; a target pattern acquisition module for selecting a design pattern with interconnect ends as a target pattern from the plurality of design patterns, wherein the interconnect ends are used to realize the interconnection of corresponding structures of the design patterns on a wafer; an optimized pattern generation module for performing end compensation processing on the interconnect ends of the target pattern to extend the interconnect ends of the target pattern to form an optimized pattern; and an optical proximity correction processing module for performing optical proximity correction processing on the optimized pattern.
[0015] Accordingly, embodiments of the present invention also provide an apparatus including at least one memory and at least one processor, wherein the memory stores one or more computer instructions, and the one or more computer instructions are executed by the processor to implement the optical proximity correction method provided in the embodiments of the present invention.
[0016] Accordingly, embodiments of the present invention also provide a storage medium storing one or more computer instructions, which are used to implement the optical proximity correction method provided in the embodiments of the present invention.
[0017] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:
[0018] In the optical proximity correction method provided in this embodiment of the invention, a design pattern with interconnect ends is selected as the target pattern from multiple design patterns. The interconnect ends are used to realize the interconnection of the corresponding structure of the design pattern on the wafer. The interconnect ends of the target pattern are subjected to end compensation processing to extend the interconnect ends of the target pattern to form an optimized pattern. The optimized pattern is then subjected to optical proximity correction processing. After optical proximity correction processing, the ends of the design pattern are prone to large dimensional deviations. In this embodiment of the invention, the target pattern has interconnect ends that need to be interconnected. The interconnect ends are subjected to end compensation processing to extend the interconnect ends of the target pattern, and the extended target pattern is the optimized pattern. This helps to reduce the probability that the position where the target pattern needs to be interconnected is far away from the end of the optimized pattern after optical proximity correction processing of the optimized pattern. This helps to reduce the probability that the position where the target pattern needs to be interconnected will have a large dimensional deviation, thereby improving the correction accuracy at the interconnect ends of the target pattern and thus improving the effect of optical proximity correction processing. Attached Figure Description
[0019] Figure 1 This is a flowchart of an optical proximity correction method;
[0020] Figures 2 to 3 This is a schematic diagram showing the steps in one embodiment of an optical proximity correction method.
[0021] Figure 4 This is a flowchart of an embodiment of the optical proximity correction method of the present invention;
[0022] Figures 5 to 7 This is a schematic diagram of each step in one embodiment of the optical proximity correction method of the present invention;
[0023] Figure 8 This is a functional block diagram of an embodiment of the optical proximity correction system of the present invention;
[0024] Figure 9 This is a hardware structure diagram of an embodiment of the device provided by the present invention. Detailed Implementation
[0025] The effectiveness of optical proximity correction processing needs improvement. This paper analyzes the reasons why the effectiveness of optical proximity correction processing needs further improvement, using one such method as an example.
[0026] Figure 1 This is a flowchart of an optical proximity correction method. Figures 2 to 3 This is a schematic diagram of each step in an embodiment of an optical proximity correction method.
[0027] Reference Figures 1 to 3 Optical proximity correction methods include:
[0028] Step s1: Provide a design layout 10a, including multiple design graphics 10, each design graphic 10 having interconnecting ends 11.
[0029] An interconnect via pattern 20 is typically formed above the interconnect end 11. The design pattern 10 corresponds to the structure on the wafer, and the interconnect end 11 and the interconnect via pattern 20 are electrically connected through contact.
[0030] Step s2: Perform optical proximity correction processing on the design graphic 10.
[0031] The optical proximity correction process obtains the simulated exposure pattern 30 corresponding to the design pattern 10. However, the ends of the design pattern 10 are prone to large dimensional deviations after optical proximity correction. In particular, the interconnect ends 11 of the design pattern 10 are recessed relative to the adjacent design patterns 10. The recessed interconnect ends 11 cannot be well taken care of by the light source during the exposure and development process, resulting in severe loss of high-frequency information. This leads to more severe dimensional deviations at the position of the simulated exposure pattern 30 corresponding to the interconnect ends 11. Consequently, the structure corresponding to the interconnect via pattern 20 at the position of the interconnect ends 11 is prone to deviate from the structure corresponding to the design pattern 10 and cannot make good contact with the structure corresponding to the design pattern 10, thus leading to the risk of open circuit. Therefore, the optical proximity correction process in the prior art is not effective and easily affects the accuracy of the structure corresponding to the design pattern 10 on the wafer.
[0032] To address the technical problem, embodiments of the present invention provide an optical proximity correction method. (Reference) Figure 4 The flowchart of an embodiment of the optical proximity correction method of the present invention is shown.
[0033] In this embodiment, the optical proximity correction method includes the following basic steps:
[0034] Step S1: Provide the design layout, including multiple design graphics;
[0035] Step S2: Select a design pattern with interconnect ends from the plurality of design patterns as the target pattern, wherein the interconnect ends are used to realize the interconnection of the corresponding structure of the design pattern on the wafer;
[0036] Step S3: Perform end compensation processing on the interconnect ends of the target graphic to extend the interconnect ends of the target graphic and form an optimized graphic;
[0037] Step S4: Perform optical proximity correction processing on the optimized pattern.
[0038] After optical proximity correction processing, the ends of the designed pattern are prone to large dimensional deviations. In this embodiment of the invention, the target pattern has interconnection ends that need to be interconnected. End compensation processing is performed on the interconnection ends to extend the interconnection ends of the target pattern. The extended target pattern is the optimized pattern. This helps to reduce the distance between the interconnection positions of the target pattern and the ends of the optimized pattern after optical proximity correction processing. This helps to reduce the probability of large dimensional deviations at the interconnection positions of the target pattern, thereby improving the correction accuracy at the interconnection ends of the target pattern and thus improving the effect of optical proximity correction processing.
[0039] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0040] Figures 5 to 6 This is a schematic diagram of each step in one embodiment of the optical proximity correction method of the present invention.
[0041] refer to Figure 5 Step S1: Provide a design layout 100a, which includes multiple design graphics 100.
[0042] Design pattern 100 is a pattern transferred onto the wafer.
[0043] Specifically, after optical proximity correction processing is performed on the design pattern 100, the obtained pattern is used to make a mask, and then the mask is used for photolithography to form the corresponding pattern structure on the wafer.
[0044] In this embodiment, the design layout 100a includes a metal line graphic.
[0045] The metal wire pattern is the same as forming a metal wire structure on the wafer.
[0046] In this embodiment, the design layout 100a includes a first layout layer and a second layout layer located above the first layout layer. The first layout layer includes multiple design graphics 100. The second layout layer includes interconnect via graphics 200, and the projection of the interconnect via graphics 200 on the first layout layer is located in the design graphics 100.
[0047] The first layer is used to obtain the mask corresponding to the design pattern 100, and the second layer is used to obtain the mask corresponding to the interconnect via pattern 200, wherein the interconnect via pattern 200 is used to form interconnect via structures on the wafer.
[0048] In this embodiment, the projection of the interconnect via pattern 200 on the first layer is located in the design pattern 100. When the design pattern 100 and the interconnect via pattern 200 are transferred to the wafer, the interconnect via structure is located on the metal line structure and is in contact with the metal line structure. The metal line structure is electrically connected to other structures through electrical connection with the interconnect via structure.
[0049] In this embodiment, in the provided design layout 100a, multiple design graphics 100 are arranged along a first direction (e.g., Figure 5 Extending along the Y direction (as shown in the middle) and along the second direction (as shown in the middle Y direction) Figure 5 (As shown in the X direction) arranged in parallel, with the first direction perpendicular to the second direction.
[0050] In the design layout 100a, multiple design graphics 100 extend along a first direction and are arranged in parallel along a second direction, that is, multiple design graphics 100 are strip graphics. The ends of the design graphics 100 are prone to dimensional deviations during optical proximity correction processing. Therefore, for strip graphic design graphics 100, the optical proximity correction method of this embodiment is particularly suitable for targeted processing of their ends.
[0051] It should be noted that in this embodiment, the metal wire patterns are mostly arranged in a way that extends along the first direction and is parallel to the second direction.
[0052] Step S2: Select the design pattern 100 with interconnect end 110a from the multiple design patterns 100 as the target pattern 110, wherein the interconnect end 110a is used to realize the interconnection of the corresponding structure of the design pattern 100 on the wafer.
[0053] When the design pattern 100 is transferred onto the wafer, it is electrically connected to other structures through the position corresponding to the interconnect end 110a. Therefore, the design pattern 100 with the interconnect end 110a needs to be used as the target pattern 110, and the target pattern 110 is subjected to targeted correction processing using the optical proximity correction method of this embodiment.
[0054] Specifically, the dimensional accuracy of the interconnect ends 110a of the design pattern 100 has a critical impact on the working performance of the corresponding pattern structure on the wafer. Therefore, for the design pattern 100 with interconnect ends 110a, the optical proximity correction method of this embodiment is particularly suitable for targeted processing of its ends.
[0055] In this embodiment, among multiple design patterns 100, the design pattern 100 with interconnect end 110a is selected as the target pattern 110, and the end of the design pattern 100 with the projection of the interconnect via pattern 200 is the interconnect end 110a.
[0056] When the design pattern 100 has the projection of the interconnect via pattern 200 onto the wafer, at the location where the interconnect via structure is formed on the corresponding pattern structure of the design pattern 100, the end of the design pattern 100 with the projection of the interconnect via pattern 200 is used as the interconnect end 110a for targeted optical proximity correction processing.
[0057] In this embodiment, among the multiple design patterns 100, the design pattern 100 with interconnect end 110a is selected as the target pattern 110, and the design pattern 100 whose interconnect end 110a is recessed in a first direction relative to the end of the adjacent design pattern 100 is selected as the target pattern 110.
[0058] If the interconnect end 110a of the design pattern 100 is recessed in the first direction compared to the end of the adjacent design pattern 100, then during exposure and development after the photomask is formed, the recessed end is more likely to cause dimensional deviations (especially dimensional deviations in the second direction) because it is difficult for the light source to take good care of it. Therefore, the recessed interconnect end 110a needs to be subjected to targeted optical proximity correction processing. In this embodiment, the design pattern 100 in which the interconnect end 110a of the design pattern 100 is recessed in the first direction compared to the end of the adjacent design pattern 100 is taken as the target pattern 110.
[0059] In this embodiment, before selecting the design pattern 100 with interconnection end 110a as the target pattern 110 from multiple design patterns 100, the correction method further includes: performing global optical proximity correction processing on the design pattern 100 of the design layout 100a.
[0060] Before performing targeted optical proximity correction on the target graphic 110, global optical proximity correction is first performed on the design graphic 100 of the design layout 100a. This allows for the initial correction effect of the design layout 100a, providing a reference for subsequent targeted corrections. The target graphic 110 can be selected based on the initial correction effect, making the selection of the target graphic 110 more accurate. This, in turn, makes the targeted correction of the target graphic 110 more precise. Furthermore, by performing global optical proximity correction first, subsequent targeted corrections of the target graphic 110 can be performed locally, which helps save computing power, improves the correction effect, and increases the efficiency of optical proximity correction.
[0061] Specifically, in this embodiment, the global optical proximity correction process includes: dividing the edges of the design graphic 100 into multiple sequentially connected line segments; and using the multiple line segments to perform global optical proximity correction processing on the design graphic 100.
[0062] In this embodiment, global optical proximity correction is performed by adjusting the position of the line segment.
[0063] Specifically, in the process of optical proximity correction of the design graphic 110, in order to reduce the arbitrariness of edge movement, the edge of the design graphic 100 is divided into multiple sequentially connected line segments, and the position of the line segments is adjusted (e.g., the line segments are translated) to reduce edge placement error.
[0064] In this embodiment, after selecting the design pattern 100 with interconnect end 110a as the target pattern 110 from multiple design patterns 100, the method further includes setting a marker on the interconnect end 110a of the target pattern 110.
[0065] Markings are provided at the interconnection end 110a of the target pattern 110 so that when the target pattern 110 is subsequently subjected to targeted optical proximity correction processing, the marks can be used to accurately locate the position that needs targeted correction, which helps to improve the efficiency of the correction processing.
[0066] refer to Figure 6 Step S3: Perform end compensation processing on the interconnect ends 110a of the target pattern 110 to extend the interconnect ends 110a of the target pattern 110 to form an optimized pattern 130.
[0067] The optimized graphic 130 includes the target graphic. Subsequently, optical proximity correction processing is performed on the optimized graphic 130 to perform targeted optical proximity correction processing on the target graphic 110.
[0068] After optical proximity correction processing, the ends of the design pattern 100 are prone to large dimensional deviations. In this embodiment, the target pattern 110 has interconnection ends 110a that need to be interconnected. End compensation processing is performed on the interconnection ends 110a to extend the interconnection ends 110a of the target pattern 110. The extended target pattern 110 is the optimized pattern 130. This helps to reduce the distance between the interconnection positions of the target pattern 110 and the ends of the optimized pattern 130 after optical proximity correction processing. This helps to reduce the probability of large dimensional deviations at the interconnection positions of the target pattern 110, thereby improving the correction accuracy at the interconnection ends 110a of the target pattern 110 and improving the effect of optical proximity correction processing.
[0069] Accordingly, in this embodiment, the interconnect ends 110a of the target pattern 110 are subjected to end compensation processing to extend the interconnect ends 110a of the target pattern 110 to form the optimized pattern 130, and the interconnect ends 110a are subjected to end compensation processing at the marked locations.
[0070] In this embodiment, the interconnect end 110a of the target pattern 110 is subjected to end compensation processing to extend the interconnect end 110a of the target pattern 110 to form an optimized pattern 130. This includes extending the target pattern 110 at the interconnect end 110a along a first direction to obtain a compensated pattern 120 with a preset length L in the first direction.
[0071] The compensation pattern 120 is used to compensate for the interconnect ends 110a of the target pattern 110 by extending the target pattern 110, so that the interconnect ends 110a are far away from the actual ends of the formed optimized pattern 130.
[0072] It should be noted that in this embodiment, when the target pattern 110 is extended along the first direction at the interconnect end 110a to obtain the compensation pattern 120 with a preset length L in the first direction, the preset length L should not be too large or too small. If the preset length L is too large, it is easy to cause unnecessary pattern waste and subsequent process waste in transferring the pattern to the wafer, and it is also easy to affect other patterns at the compensation pattern 120. If the preset length L is too small, the distance between the interconnect end 110a and the actual end of the optimized pattern 130 is too small, and the distance between the position where the target pattern 110 needs to be interconnected and the actual end of the optimized pattern 130 is too small, which is easy to reduce the probability of a large dimensional deviation at the position where the target pattern 110 needs to be interconnected, thus resulting in poor effect on improving the correction accuracy at the interconnect end 110a of the target pattern 110. Therefore, in this embodiment, when the target pattern 110 is extended along the first direction at the interconnect end 110a to obtain the compensation pattern 120 with a preset length L in the first direction, the preset length L is 2 to 3 times the length of the line segment.
[0073] It should also be noted that when optical proximity correction is performed by adjusting the position of line segments, the dimensional deviation at the first three line segments of the end of the design pattern 100 is usually quite severe. Therefore, in this embodiment, the target pattern 110 is extended along the first direction at the interconnect end 110a to obtain a compensation pattern 120 with a preset length L in the first direction. The preset length L is 2 to 3 times the line segment length. This allows the interconnection position of the target pattern 110 to better avoid the first three line segments at the end with severe dimensional deviation. At the same time, it makes the size of the optimized pattern 130 moderate in the first direction, avoiding unnecessary pattern waste and subsequent process waste when transferring the pattern to the wafer due to excessive pattern size, and avoiding affecting other patterns at the compensation pattern 120.
[0074] Accordingly, in this embodiment, the compensation graphic 120 and the target graphic 110 are combined to form the optimized graphic 130.
[0075] The compensation pattern 120 and the target pattern 110 are combined to form an optimized pattern 130. Subsequently, optical proximity correction processing is performed on the entire optimized pattern 130 so that the position of the target pattern 110 used to achieve interconnection is far away from the end of the pattern when optical proximity correction processing is performed.
[0076] refer to Figure 7 Step S4: Perform optical proximity correction processing on the optimized graphic 130.
[0077] Optical proximity correction is applied to the optimized pattern 130 to address the optical proximity effect, ensuring that the pattern transferred to the wafer is accurate.
[0078] In this embodiment, during the optical proximity correction process for the optimized graphic 130, a local optical proximity correction process is performed on the portion of the design layout 100a containing the optimized graphic 130.
[0079] Performing local optical proximity correction processing on the part of the design layout 100a that includes the optimized graphics 130 is beneficial for saving computing power and improving the efficiency of correction processing.
[0080] In this embodiment, before performing optical proximity correction on the optimized graphic 130, global optical proximity correction is performed on the design graphic 100 of the design layout 100a, and then targeted local correction is performed on the optimized graphic 130. This helps to save computing power, improve the correction effect, and improve the efficiency of optical proximity correction.
[0081] In other embodiments, global optical proximity correction (OPC) may not be performed before selecting the design pattern with interconnected ends as the target pattern from among multiple design patterns, but OPC may be performed on the overall design layout during the OPC process for optimizing the pattern.
[0082] In this embodiment, a local optical proximity correction process is performed on a portion of the design layout 100a containing the optimized graphic 130, including: performing one or more correction iterations until the number of correction iterations reaches a preset number.
[0083] The number of iterations for correction is reached to indicate that the result of the local optical proximity correction process meets the standard.
[0084] In this embodiment, the correction iteration process includes: obtaining a portion of the design layout 100a containing the optimized graphic 130 as a reference area; performing local optical proximity correction processing on the reference area; wherein the reference area of the subsequent correction iteration process is expanded based on the reference area of the previous correction iteration process.
[0085] The reference area of the subsequent correction iteration is expanded based on the reference area of the previous correction iteration, which enables multiple iterations to continuously expand the reference area to improve the results of local optical proximity correction processing on the part of the design layout 100a containing the optimized graphic 130.
[0086] Specifically, in this embodiment, optical proximity correction processing is performed on the optimized pattern 130 to obtain the corresponding simulated exposure pattern 300.
[0087] The simulated exposure pattern 300 is used to form a photomask, which is used as a mask to obtain the actual exposure pattern in the subsequent actual exposure step.
[0088] Accordingly, the present invention also provides an optical proximity correction system. Figure 8 This is a functional block diagram of an embodiment of the optical proximity correction system of the present invention.
[0089] In this embodiment, the optical proximity correction system 50 includes: a design layout providing module 501, used to provide a design layout including multiple design patterns; a target pattern acquisition module 502, used to select a design pattern with interconnect ends as a target pattern from the multiple design patterns, wherein the interconnect ends are used to realize the interconnection of the corresponding structure of the design pattern on the wafer; an optimized pattern generation module 503, used to perform end compensation processing on the interconnect ends of the target pattern to extend the interconnect ends of the target pattern to form an optimized pattern; and an optical proximity correction processing module 504, used to perform optical proximity correction processing on the optimized pattern.
[0090] Design layout provider module 501 is used to provide design layouts, including multiple design graphics.
[0091] The design pattern is the pattern transferred onto the wafer.
[0092] Specifically, after optical proximity correction processing is performed on the design pattern, the obtained pattern is used to make a mask, and then the mask is used for photolithography to form the corresponding pattern structure on the wafer.
[0093] In this embodiment, the design layout includes metal line graphics.
[0094] The metal wire pattern is the same as forming a metal wire structure on the wafer.
[0095] In this embodiment, a design layout is provided, which includes a first layout layer and a second layout layer located above the first layout layer. The first layout layer includes multiple design graphics, and the second layout layer includes interconnect via graphics. The projection of the interconnect via graphics on the first layout layer is located in the design graphics.
[0096] The first layer is used to obtain the mask corresponding to the design pattern, and the second layer is used to obtain the mask corresponding to the interconnect via pattern. The interconnect via pattern is used to form interconnect via structures on the wafer.
[0097] In this embodiment, the projection of the interconnect via pattern on the first layer is located in the design pattern. When the design pattern and the interconnect via pattern are transferred to the wafer, the interconnect via structure is located on the metal line structure and is in contact with the metal line structure. The metal line structure is electrically connected to other structures through electrical connection with the interconnect via structure.
[0098] In this embodiment, a design layout is provided in which multiple design graphics extend along a first direction and are arranged in parallel along a second direction, with the first direction being perpendicular to the second direction.
[0099] In the design layout, multiple design graphics extend along a first direction and are arranged in parallel along a second direction, that is, multiple design graphics are strip graphics. The ends of the design graphics are prone to dimensional deviations during optical proximity correction processing. Therefore, for strip graphics, the optical proximity correction method of this embodiment is particularly suitable for targeted processing of their ends.
[0100] It should be noted that in this embodiment, the metal wire patterns are mostly arranged in a way that extends along the first direction and is parallel to the second direction.
[0101] The target pattern acquisition module 502 is used to select a design pattern with interconnect ends as the target pattern from multiple design patterns, wherein the interconnect ends are used to realize the interconnection of the corresponding structure of the design pattern on the wafer.
[0102] When transferring the design pattern onto the wafer, electrical connections are made with other structures through the corresponding positions of the interconnect ends. Therefore, the design pattern with interconnect ends needs to be used as the target pattern, and the optical proximity correction method of this embodiment is used to perform targeted correction processing on the target pattern.
[0103] Specifically, the dimensional accuracy of the interconnect ends of the design pattern has a critical impact on the working performance of the corresponding pattern structure on the wafer. Therefore, for design patterns with interconnect ends, the optical proximity correction method of this embodiment is particularly suitable for targeted processing of their ends.
[0104] In this embodiment, among multiple design patterns, a design pattern with interconnect ends is selected as the target pattern, and the end of the design pattern with the projection of the interconnect via pattern is taken as the interconnect end.
[0105] When the design pattern with interconnect via patterns is transferred to the wafer, the location where the interconnect via structure is formed on the corresponding pattern structure of the design pattern is then used as the interconnect end for targeted optical proximity correction processing.
[0106] In this embodiment, among multiple design patterns, a design pattern with interconnected ends is selected as the target pattern, and a design pattern whose interconnected ends are recessed in a first direction relative to the ends of adjacent design patterns is selected as the target pattern.
[0107] If the interconnect ends of the design pattern are recessed in the first direction compared to the ends of the adjacent design patterns, then during exposure and development after the photomask is formed, the recessed ends are more likely to cause dimensional deviations (especially dimensional deviations in the second direction) because they are difficult to be well taken care of by the light source. Therefore, the recessed interconnect ends need to be subject to targeted optical proximity correction processing. In this embodiment, the design pattern in which the interconnect ends of the design pattern are recessed in the first direction compared to the ends of the adjacent design patterns is used as the target pattern.
[0108] In this embodiment, before selecting the design pattern with interconnected ends as the target pattern from multiple design patterns, the correction method further includes: performing global optical proximity correction processing on the design pattern of the design layout.
[0109] Before performing targeted optical proximity correction on the target graphic, global optical proximity correction is first performed on the design layout. This allows for an initial correction effect on the design layout, providing a reference for subsequent targeted corrections. The target graphic can be selected based on the initial correction effect, making the selection more accurate and thus enabling more precise targeted corrections. Furthermore, by performing global optical proximity correction first, subsequent targeted corrections of the target graphic can be performed locally, which helps save computing power, improves the correction effect, and increases the efficiency of optical proximity correction.
[0110] Specifically, in this embodiment, the global optical proximity correction process includes: dividing the edges of the design graphic into multiple sequentially connected line segments; and using the multiple line segments to perform global optical proximity correction processing on the design graphic.
[0111] In this embodiment, global optical proximity correction is performed by adjusting the position of the line segment.
[0112] Specifically, in the process of optical proximity correction of the design graphic, in order to reduce the arbitrariness of edge movement, the edge of the design graphic is divided into multiple sequentially connected line segments, and then the position of the line segments is adjusted (e.g., the line segments are translated) to reduce edge placement error.
[0113] In this embodiment, after selecting the design pattern with interconnected ends as the target pattern from multiple design patterns, the method further includes setting a marker on the interconnected ends of the target pattern.
[0114] Markings are set at the interconnecting ends of the target graphic so that when performing targeted optical proximity correction on the target graphic in the future, the location that needs to be targeted for correction can be accurately located by the marks, which helps to improve the efficiency of the correction process.
[0115] The optimized graphic generation module 503 is used to perform end compensation processing on the interconnect ends of the target graphic to extend the interconnect ends of the target graphic and form an optimized graphic.
[0116] The optimized image includes the target image. Subsequently, optical proximity correction processing is performed on the optimized image to perform targeted optical proximity correction processing on the target image.
[0117] After optical proximity correction processing, the ends of the designed pattern are prone to large dimensional deviations. In this embodiment, the target pattern has interconnection ends that need to be interconnected. End compensation processing is performed on the interconnection ends to extend the interconnection ends of the target pattern. The extended target pattern is the optimized pattern. This helps to reduce the distance between the interconnection positions of the target pattern and the ends of the optimized pattern after optical proximity correction processing. This helps to reduce the probability of large dimensional deviations at the interconnection positions of the target pattern, thereby improving the correction accuracy at the interconnection ends of the target pattern and thus improving the effect of optical proximity correction processing.
[0118] Accordingly, in this embodiment, the interconnect ends of the target pattern are subjected to end compensation processing to extend the interconnect ends of the target pattern and form an optimized pattern. The interconnect ends are subjected to end compensation processing at the marked locations.
[0119] In this embodiment, the interconnect ends of the target graphic are subjected to end compensation processing to extend the interconnect ends of the target graphic to form an optimized graphic, including: extending the target graphic along a first direction at the interconnect ends to obtain a compensated graphic of a preset length in the first direction.
[0120] The compensation pattern is used to compensate for the interconnect ends of the target pattern by extending the target pattern, so that the interconnect ends are far away from the actual ends of the formed optimized pattern.
[0121] It should be noted that in this embodiment, when the target pattern is extended along the first direction at the interconnect end to obtain a compensation pattern of a preset length in the first direction, the preset length should not be too large or too small. If the preset length is too large, it is easy to cause unnecessary pattern waste and subsequent process waste in transferring the pattern to the wafer, and it is also easy to affect other patterns at the compensation pattern location; if the preset length is too small, the distance between the interconnect end and the actual end of the optimized pattern is too small, and the distance between the corresponding target pattern location where interconnection is required and the actual end of the optimized pattern is too small, which is easy to lead to poor effect in reducing the probability of large dimensional deviations at the target pattern location where interconnection is required, thereby resulting in poor effect in improving the correction accuracy at the interconnect end of the target pattern. Therefore, in this embodiment, when the target pattern is extended along the first direction at the interconnect end to obtain a compensation pattern of a preset length in the first direction, the preset length is 2 to 3 times the line segment length.
[0122] It should also be noted that when using optical proximity correction (OPC) by adjusting the position of line segments, the dimensional deviation at the first three line segments of the design pattern is usually quite severe during the OPC process. Therefore, in this embodiment, the target pattern is extended along the first direction at the interconnect end to obtain a compensation pattern of a preset length in the first direction. The preset length is 2 to 3 times the line segment length. This allows the interconnect position of the target pattern to better avoid the first three line segments at the end where the dimensional deviation is severe. At the same time, it makes the size of the optimized pattern moderate in the first direction, avoiding unnecessary pattern waste and subsequent process waste when transferring the pattern to the wafer due to excessive pattern size, and avoiding affecting other patterns at the compensation pattern location.
[0123] Accordingly, in this embodiment, the compensation graphic and the target graphic are combined to form an optimized graphic.
[0124] The compensation graphic and the target graphic are combined to form an optimized graphic. Subsequently, optical proximity correction is performed on the entire optimized graphic so that the position of the target graphic used to realize the interconnection is far away from the end of the graphic when optical proximity correction is performed.
[0125] The optical proximity correction processing module 504 is used to perform optical proximity correction processing on the optimized graphic.
[0126] Optical proximity correction is applied to the optimized pattern to address the optical proximity effect, ensuring the accuracy of the pattern transferred to the wafer.
[0127] In this embodiment, during the optical proximity correction process for the optimized graphic, local optical proximity correction is performed on the portion of the design layout containing the optimized graphic.
[0128] Performing local optical proximity correction on the portion of the design layout containing optimized graphics helps save computing power and improve correction efficiency.
[0129] In this embodiment, before performing targeted optical proximity correction on the optimized graphic, global optical proximity correction is performed on the design graphic of the design layout first, and then targeted local correction is performed on the optimized graphic. This helps to save computing power, improve the correction effect, and improve the efficiency of optical proximity correction.
[0130] In other embodiments, global optical proximity correction (OPC) may not be performed before selecting the design pattern with interconnected ends as the target pattern from among multiple design patterns, but OPC may be performed on the overall design layout during the OPC process for optimizing the pattern.
[0131] In this embodiment, local optical proximity correction processing is performed on the part of the design layout containing the optimized graphics, including: performing one or more correction iterations until the number of correction iterations reaches a preset number.
[0132] The number of iterations for correction is reached to indicate that the result of the local optical proximity correction process meets the standard.
[0133] In this embodiment, the correction iteration process includes: obtaining a portion of the design layout area containing the optimized graphic as a reference area; performing local optical proximity correction processing on the reference area; wherein, the reference area of the subsequent correction iteration process is expanded based on the reference area of the previous correction iteration process.
[0134] The reference area for each subsequent correction iteration is expanded based on the reference area for the previous correction iteration. This allows multiple iterations to continuously expand the reference area to improve the results of local optical proximity correction processing on the part of the design layout containing the optimized graphics.
[0135] Specifically, in this embodiment, optical proximity correction processing is performed on the optimized pattern to obtain a corresponding simulated exposure pattern.
[0136] The simulated exposure pattern is used to form a photomask, which is then used as a mask to obtain the actual exposure pattern in the subsequent actual exposure step.
[0137] This invention also provides a device that can implement the optical proximity correction method provided in this invention by loading a program, as described above. An optional hardware structure of the terminal device provided in this invention can be as follows: Figure 9 As shown, it includes: at least one processor 01, at least one communication interface 02, at least one memory 03, and at least one communication bus 04.
[0138] In this embodiment, the number of processor 01, communication interface 02, memory 03, and communication bus 04 is at least one, and the processor 01, communication interface 02, and memory 03 communicate with each other through communication bus 04. Communication interface 02 can be an interface of a communication module for network communication, such as the interface of a GSM module. Processor 01 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention. Memory 03 may include high-speed RAM and may also include non-volatile memory (NVM), such as at least one disk storage device. Memory 03 stores one or more computer instructions, which are executed by processor 01 to implement the optical proximity correction method provided in this embodiment of the present invention.
[0139] It should be noted that the aforementioned terminal device may also include other devices (not shown) that may not be essential to understanding the content disclosed in the embodiments of the present invention; given that these other devices may not be essential for understanding the content disclosed in the embodiments of the present invention, the embodiments of the present invention will not describe them one by one.
[0140] This invention also provides a storage medium storing one or more computer instructions for implementing the optical proximity correction method provided in this invention.
[0141] After optical proximity correction processing, the ends of the designed pattern are prone to large dimensional deviations. In this embodiment of the invention, the target pattern has interconnection ends that need to be interconnected. End compensation processing is performed on the interconnection ends to extend the interconnection ends of the target pattern. The extended target pattern is the optimized pattern. This helps to reduce the distance between the interconnection positions of the target pattern and the ends of the optimized pattern after optical proximity correction processing. This helps to reduce the probability of large dimensional deviations at the interconnection positions of the target pattern, thereby improving the correction accuracy at the interconnection ends of the target pattern and thus improving the effect of optical proximity correction processing.
[0142] The embodiments of the present invention described above are combinations of elements and features of the present invention. Unless otherwise stated, elements or features may be considered optional. Individual elements or features may be practiced without combination with other elements or features. Furthermore, embodiments of the present invention may be constructed by combining some elements and / or features. The order of operations described in the embodiments of the present invention may be rearranged. Some constructions of any embodiment may be included in another embodiment and may be replaced by corresponding constructions of another embodiment. It will be apparent to those skilled in the art that claims in the appended claims that are not expressly referenced in each other may be combined to form embodiments of the present invention, or may be included as new claims in amendments made after the filing of this application.
[0143] Embodiments of the present invention can be implemented by various means, such as hardware, firmware, software, or combinations thereof. In a hardware configuration, the method according to an exemplary embodiment of the present invention can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, etc. In a firmware or software configuration, embodiments of the present invention can be implemented in the form of modules, processes, functions, etc. Software code can be stored in memory units and executed by a processor. The memory units are located inside or outside the processor and can send data to and receive data from the processor via various known means.
[0144] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is accorded the widest scope consistent with the principles and novel features disclosed herein.
[0145] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. An optical proximity correction method, characterized in that, include: Provides a design layout, including multiple design graphics; Among the multiple design patterns, a design pattern with interconnect ends is selected as the target pattern, wherein the interconnect ends are used to realize the interconnection of the corresponding structure of the design pattern on the wafer; End compensation processing is performed on the interconnect ends of the target pattern to extend the interconnect ends of the target pattern and form an optimized pattern; The optimized pattern is then subjected to optical proximity correction processing.
2. The optical proximity correction method as described in claim 1, characterized in that, The design layout includes a first layout layer and a second layout layer located above the first layout layer. The first layout layer includes a plurality of design graphics. The second layout layer includes interconnect via graphics, and the projection of the interconnect via graphics onto the first layout layer is located within the design graphics. Among the multiple design patterns, the design pattern with interconnect ends is selected as the target pattern, and the end of the design pattern with the projection of the interconnect via pattern is the interconnect end.
3. The optical proximity correction method as described in claim 1, characterized in that, In the provided design layout, a plurality of design graphics extend along a first direction and are arranged in parallel along a second direction, wherein the first direction is perpendicular to the second direction; Among the multiple design patterns, a design pattern with interconnected ends is selected as the target pattern, and the design pattern whose interconnected ends are indented relative to the ends of adjacent design patterns along the first direction is selected as the target pattern.
4. The optical proximity correction method according to any one of claims 1 to 3, characterized in that, The design layout provided includes metal line graphics.
5. The optical proximity correction method as described in claim 1, characterized in that, After selecting a design pattern with interconnected ends as the target pattern from among the multiple design patterns, the method further includes: setting a mark at the interconnected ends of the target pattern; End compensation processing is performed on the interconnect ends of the target pattern to extend the interconnect ends of the target pattern and form an optimized pattern. In the optimized pattern, end compensation processing is performed on the interconnect ends at the marked locations.
6. The optical proximity correction method as described in claim 3, characterized in that, The interconnection ends of the target graphic are subjected to end compensation processing to extend the interconnection ends of the target graphic to form an optimized graphic, including: extending the target graphic at the interconnection ends along the first direction to obtain a compensated graphic with a preset length in the first direction; The compensation graphic and the target graphic are combined to form the optimized graphic.
7. The optical proximity correction method as described in claim 6, characterized in that, Before selecting a design graphic with interconnected ends as the target graphic from among the multiple design graphics, the correction method further includes: performing global optical proximity correction processing on the design graphic of the design layout, wherein the global optical proximity correction processing includes: dividing the edges of the design graphic into multiple sequentially connected line segments; and performing the global optical proximity correction processing on the design graphic using the multiple line segments. The target pattern is extended along the first direction at the interconnect end to obtain a compensation pattern of a preset length in the first direction, wherein the preset length is 2 to 3 times the length of the line segment.
8. The optical proximity correction method as described in claim 1, characterized in that, Before selecting the design pattern with interconnected ends as the target pattern from among the multiple design patterns, the correction method further includes: performing global optical proximity correction processing on the design pattern of the design layout; In the optical proximity correction process for the optimized graphic, local optical proximity correction is performed on the portion of the design layout containing the optimized graphic.
9. The optical proximity correction method as described in claim 8, characterized in that, Perform local optical proximity correction processing on a portion of the design layout containing the optimized graphic, including: performing one or more correction iterations until the number of correction iterations reaches a preset number, wherein the correction iterations include: Obtain a portion of the design layout area containing the optimized graphics as a reference area; The reference region is subjected to local optical proximity correction processing; In this process, the reference area of the subsequent correction iteration is expanded based on the reference area of the previous correction iteration.
10. An optical proximity correction system, characterized in that, include: The design layout module provides a design layout, which includes multiple design graphics. The target pattern acquisition module is used to select a design pattern with interconnect ends as the target pattern from a plurality of design patterns, wherein the interconnect ends are used to realize the interconnection of the corresponding structure of the design pattern on the wafer; An optimized graphic generation module is used to perform end compensation processing on the interconnect ends of the target graphic to extend the interconnect ends of the target graphic and form an optimized graphic. An optical proximity correction processing module is used to perform optical proximity correction processing on the optimized pattern.
11. A device, characterized in that, It includes at least one memory and at least one processor, the memory storing one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the optical proximity correction method as described in any one of claims 1-8.
12. A storage medium, characterized in that, The storage medium stores one or more computer instructions for implementing the optical proximity correction method as described in any one of claims 1-8.