A step-by-step decoding method, device, storage medium and electronic equipment

Abstract

Embodiments of the present application provide a step-by-step decoding method and device, a storage medium and an electronic device, relating to the technical field of computers, which comprises: obtaining a code word and a target check matrix; determining a first SW value according to the code word and the target check matrix; comparing the first SW value with a target threshold value, and performing a corresponding decoding operation according to the comparison result. In this way, the decoding operation is dynamically selected according to the SW value, unnecessary iterations are avoided, the relationship between the number of iterations and the throughput is balanced, the decoding delay and power consumption are reduced, and the decoding efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computers, and in particular to a step-by-step decoding method and device, a storage medium, and an electronic device. BACKGROUND

[0002] The rapid development of the Internet of Things, 5G, and artificial intelligence and other fields has put forward higher requirements for computing power. The rapid development of computing power has also put forward new standards for storage power. The parameter scale of current artificial intelligence large models has broken through the trillion level, bringing exponential growth of data. Enterprise-level SSD based on NAND flash memory is the foundation of computing infrastructure and the guarantee of the intelligentization of AI end-side devices. However, the physical characteristics of NAND flash memory particles make their threshold voltage distribution susceptible to programming interference and the cumulative effect of erase cycles. As the storage units undergo repeated write / erase operations, the charge trapping effect of the floating gate layer and the inter-cell coupling effect will cause threshold voltage drift. This drift phenomenon not only exacerbates the risk of overlapping voltage distribution curves of adjacent storage units, but also causes the probability of level misjudgment in read operations to rise, ultimately resulting in deterioration of the raw bit error rate (RBER) and degradation of data persistence, which becomes a core bottleneck restricting the long-term reliability of high-density flash memory.

[0003] Low Density Parity Check (LDPC) code has become the mainstream error correction scheme in NAND flash memory media due to its theoretical performance close to the Shannon limit. Its iterative decoding strategy based on belief propagation can effectively guarantee the data reliability in current 3D NAND flash memory media. For the application of LDPC code in NAND flash memory media, it is usually more dependent on its hard-decision performance. The difference between hard decision and soft decision is that hard decision uses 0 / 1 threshold judgment, while soft decision uses statistical information of voltage distribution to provide more reliable information and has stronger decoding ability but requires more computational complexity. In addition, the contradiction between the number of decoding iterations and high throughput in the decoding iteration process not only leads to the squeezing of storage resources, but also increases the latency and power consumption.

[0004] Currently, the general process adopted when decoding NAND flash media includes: the code word after encoding and channel scrambling is preferentially entered into hard decoding when decoding, when the hard decoding fails, the host chip may try to read the data again at different voltage axes, because the incorrect voltage setting may cause the inaccurate data read. After multiple adjustments of the voltage axis, if it still fails, it will turn to soft decoding, which recovers the data using a more complex method. This is because the delay and power consumption of adjusting the voltage axis are relatively low, while soft decoding requires more computing resources, which may affect the overall performance. Therefore, before entering a soft decoding, the LDPC has already performed a maximum number of hard decoding iterations at multiple voltage axes. This increases the data latency during the LDPC decoding process, and also increases the iterations of decoding. At the same time, for a part of the code word with high RBER (Raw Bit Error Rate), it is impossible to be corrected even after the LDPC soft decoding. The latency caused by this part of the code word not only increases the power consumption in the iteration calculation process, but also affects the final data throughput. SUMMARY

[0005] The present application provides a step-by-step decoding method, device, storage medium and electronic equipment to at least solve the above technical problems in the prior art.

[0006] The technical scheme of the embodiments of the present application is as follows:

[0007] In a first aspect, the embodiments of the present application provide a step-by-step decoding method, the method comprising:

[0008] obtaining a code word and a target check matrix;

[0009] determining a first SW value according to the code word and the target check matrix;

[0010] comparing the first SW value with a target threshold value, and performing a corresponding decoding operation according to the comparison result.

[0011] In a second aspect, the embodiments of the present application provide a step-by-step decoding device, the device comprising:

[0012] an acquisition module configured to obtain a code word and a target check matrix;

[0013] a first processing module configured to determine a first SW value according to the code word and the target check matrix;

[0014] a second processing module configured to compare the first SW value with a target threshold value, and perform a corresponding decoding operation according to the comparison result.

[0015] In a third aspect, an electronic device is provided, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform any of the step-by-step decoding methods.

[0016] In a fourth aspect, a non-transitory computer-readable storage medium storing computer instructions is provided, and the computer instructions are used to enable a computer to perform any of the step-by-step decoding methods.

[0017] The embodiments of the present application have the following beneficial effects:

[0018] By applying the step-by-step decoding method, the apparatus, the storage medium and the electronic device provided by the embodiments of the present application, the method includes: obtaining a code word and a target check matrix; determining a first SW value according to the code word and the target check matrix; comparing the first SW value with a target threshold value, and performing a corresponding decoding operation according to the comparison result. In this way, the decoding operation is dynamically selected according to the SW value, unnecessary iterations are avoided, the relationship between the number of iterations and the throughput is balanced, the decoding delay and power consumption are reduced, and the decoding efficiency is improved.

[0019] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent through the following description. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 A flowchart of a step-by-step decoding method provided by the embodiments of the present application;

[0021] Figure 2 A schematic diagram of a check matrix provided by the embodiments of the present application;

[0022] Figure 3 A schematic diagram of the relationship between error bits and SW values of a check matrix of a code rate provided by the embodiments of the present application;

[0023] Figure 4 A schematic diagram of the relationship between error bits and SW values of a check matrix of another code rate provided by the embodiments of the present application;

[0024] Figure 5 A schematic diagram of the error correction capability of soft and hard solutions corresponding to matrix1 provided by the embodiments of the present application;

[0025] Figure 6 A schematic diagram of the error correction capability of soft and hard solutions corresponding to matrix2 provided by the embodiments of the present application;

[0026] Figure 7 A schematic diagram of bit flipping decoding performance of matrix1 and matrix2 provided for an embodiment of the present application;

[0027] Figure 8 A structural schematic diagram of a step-by-step decoding device provided for an embodiment of the present application;

[0028] Figure 9 A structural schematic diagram of another step-by-step decoding device provided for an embodiment of the present application;

[0029] Figure 10 A structural schematic diagram of an electronic device provided for an embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to make the objectives, characteristics and advantages of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0031] In the following description, "some embodiments" are described, which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0032] If similar descriptions of "first / second" appear in the application file, the following description is added. In the following description, the terms "first\second\third" are only to distinguish similar objects, and do not represent a specific order of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application, and are not intended to limit the present application.

[0034] Figure 1 A flowchart of a step-by-step decoding method provided for an embodiment of the present application; as shown in Figure 1 The method comprises:

[0035] Step 101, obtaining a code word and a target check matrix;

[0036] Step 102, determining a first SW (Syndrome Weight) value according to the codeword and the target check matrix;

[0037] Step 103, comparing the first SW value with a target threshold value, and performing a corresponding decoding operation according to a comparison result.

[0038] Here, in coding theory, a codeword refers to a bit sequence obtained after a coding process. In error correction coding (e.g., LDPC (Low-Density Parity-Check Code) code), a codeword is a fixed-length bit sequence formed by encoding information by applying a specific coding rule (e.g., parity check matrix). That is, a codeword is a result of encoding information, and is a vector composed of 0 and 1.

[0039] For example, in the decoding operation of an LDPC code, assume that a codeword c after coding by a check matrix H is c = [c(1) c(2) c(3) … c(m)], where c is a vector composed of bits, and each c(i) is a bit in the codeword, which can be 0 or 1. For c, it is indicated that the codeword is a correct codeword only if the vector satisfies the result of multiplying the codeword c and the transpose of the check matrix H is 0 (i.e., satisfies the check equation c·H T =0, where T represents transpose). The decoding process is to continuously adjust the element values in different positions of c by different means so that the check equation is satisfied. When the codeword is affected by a channel and an error bit occurs, the check equation is no longer established, and the SW value represents the number of check equations that are no longer established.

[0040] In an LDPC code, a check matrix is a tool for describing how to check whether the transmitted coding has an error. As described above, H is a check matrix, which is used to verify whether a codeword is correct. If the received codeword c has an error, the check equation will no longer be established. The check matrix is multiplied by the received codeword, and the result is called a syndrome value or syndrome vector, denoted as S.

[0041] The SW value refers to a vector obtained by operating the received codeword c by the check matrix H in an LDPC code. If the received codeword is completely correct (without error), the SW value is 0; if the received codeword contains an error bit, the SW value is the number of non-zero elements. That is, the SW value is the number of check equations that are no longer established. That is, the larger the SW value, the more errors in the codeword, and the more serious the check failure. If an error occurs, the decoder needs to make more adjustments to repair the error. After correction, the SW value will gradually decrease. If the SW value does not significantly decrease after continuous iteration correction for multiple times, it is considered that the correction ability has reached the limit and cannot be further corrected.

[0042] The check matrix H is a sparse matrix, and the number of 0s is significantly more than 1. For each check matrix of a code rate, the number of error bits in the current code word can be inferred according to the size of the corresponding SW value. When the number of error bits is in a certain range, the extra energy consumption and decoding delay generated in the decoding process can be avoided by selecting a suitable decoding operation (or decoder).

[0043] In the embodiments of the present application, the number of error bits in the current code word is inferred according to the size of the SW value. When the number of error bits is in a certain range, the storage space of intermediate information can be saved, the extra energy consumption and decoding delay generated in the decoding process can be avoided, and intelligent optimization is achieved, which can effectively reduce power consumption, reduce time delay, and improve throughput.

[0044] In some embodiments, the target check matrix is obtained, including:

[0045] The second SW value is calculated according to the code word and a preset initial check matrix;

[0046] If the second SW value is less than a first SW threshold, a first check matrix is selected as the target check matrix;

[0047] If the second SW value is greater than or equal to the first SW threshold and less than a second SW value, a second check matrix is selected as the target check matrix;

[0048] If the second SW value is greater than or equal to the second SW threshold, a third check matrix is selected as the target check matrix;

[0049] The code rate of the first check matrix is greater than the code rate of the second check matrix, and the code rate of the second check matrix is greater than the code rate of the third check matrix.

[0050] Here, the size of the SW value can be used to estimate the errors in the code word, and then the target check matrix used is dynamically selected. From the pre-configured multiple check matrices for different error ranges or the most matching target check matrix for subsequent decoding operations.

[0051] Specifically, if the calculated second SW value is less than the first SW threshold, a check matrix with a higher code rate and a simpler structure (i.e., the first check matrix) can be selected, sacrificing part of the error correction capability to obtain more information transmission bits, and gaining speed and power consumption advantages.

[0052] If the second SW value is greater than or equal to the first SW threshold and less than the second SW value, a standard matrix (i.e., the second check matrix) is selected;

[0053] If the second SW value is greater than or equal to a second SW threshold value, a check matrix with a lower code rate and more check bits (i.e., a third check matrix) is selected, and the number of transmitted information bits is reduced to exchange for the accuracy of decoding.

[0054] In this way, dynamic selection is performed based on the SW value, the check matrix can be dynamically switched to match the environment, and the limitations of the static matrix are avoided. Thus, the system can more flexibly and intelligently select a suitable error correction scheme when facing different communication conditions, and a balance between ensuring data accuracy and effective transmission speed is achieved.

[0055] In some embodiments, before the first SW value is compared with the target threshold value, the method further includes:

[0056] According to the target check matrix, a preset threshold table is queried to determine a target threshold value corresponding to the target check matrix.

[0057] The preset threshold table includes at least one check matrix and a target threshold value corresponding to each check matrix, and the target threshold value includes multiple threshold values for comparison with the SW value.

[0058] Here, different check matrices of different code rates can correspond to different target threshold values, and the target threshold value includes multiple threshold values for comparison with the SW value, such as a first threshold value, a second threshold value, a third threshold value, and the like.

[0059] Here, for a check matrix H, the dimension is determined by the information bits and the check bits, and the format of the check matrix is as shown in Figure 2 where n-m represents the information bit length, m represents the check bit length and the number of rows, and n represents the complete codeword length and the number of columns. The code rate is (n-m) / n. When the code rate is higher, the check bits are smaller, and the effective information that can be transmitted is longer. When the matrix dimension is large, although the decoding capability can be improved, a larger matrix dimension often leads to more storage resource consumption. In addition, in the decoding process, more check bits also lengthen the one-round complete iterative decoding delay, thereby further affecting the power consumption of the decoder. Therefore, the SW value can be used to balance the relationship between the error correction capability and the matrix dimension. Further from Figure 3 and Figure 4 It can be seen that within a certain error range, selecting a matrix with a higher code rate can also bring good error correction capability.

[0060] For check matrices of different code rates, there is a certain relationship between the size of the calculated SW value and the initial number of error bits. Based on this relationship in the embodiments of the present application, the target threshold values corresponding to the check matrices of different code rates are determined in advance, the target threshold value is compared with the SW value, and different decoding operations are selected according to the comparison result.

[0061] Thus, by determining the target threshold corresponding to the check matrix of different code rates in advance, the actual SW value can be effectively compared with the target threshold, and different operations can be dynamically selected, thereby reducing unnecessary calculations, improving the overall performance of the system, reducing power consumption and time delay, and selecting the most suitable decoding strategy according to specific conditions to ensure that the best decoding effect can be achieved under different conditions, improve the decoding efficiency and accuracy.

[0062] Specifically, for check matrices of different code rates, there is a certain relationship between the size of the calculated SW value and the initial error bit number, and the relationship includes:

[0063] When the error number is within a certain range, the SW value and the initial error bit number are basically in a linear relationship; that is, the more the error bits, the faster the SW value increases;

[0064] When the error number exceeds this range, the SW value will continue to grow with the increase of the initial error, but the growth rate will slow down significantly; that is, as the number of error bits increases, the effect of the check matrix becomes less significant, resulting in a gradual increase in the SW value;

[0065] When the initial error number continues to grow beyond a certain range, the growth trend of the SW value will further slow down, and the SW value will remain basically unchanged as the number of errors increases; that is, after too many errors, the correction ability of the check matrix is close to saturation, and it cannot effectively increase the correction ability of the error bits.

[0066] For check matrices of different code rates, in addition to the initial error bit interval of the SW value trend change varying with the code rate of the check matrix, the overall change trend of the SW value with the increase of the error number is the same.

[0067] It should be noted that the above only illustrates that the decoder can be dynamically selected according to the SW value. In actual application, different target thresholds can be set for check matrices of different code rates. Here, the values of the first threshold, the second threshold, the third threshold, and the fourth threshold corresponding to each check matrix are not limited.

[0068] The target threshold corresponding to the check matrix of different code rates can be obtained in advance by simulation test, experimental data analysis, and data fitting, etc. For example, the target threshold of the check matrix of different code rates can be detected by experiment or simulation, different check matrices can be selected, and the n and m values thereof are adjusted to obtain different code rates; the number of error bits and the SW value of the check matrix in the simulation transmission process are simulated, and the results in each case are recorded; for each code rate, the bit error rate under different channel conditions is tested, and the corresponding SW value is measured. Through a large number of simulations and experimental data, the relationship between the SW value and the number of error bits under each code rate can be obtained, and then the target threshold of each code rate is calculated.

[0069] The SW value and the number of error bits under different code rates are collected, and a statistical analysis method (such as regression analysis or curve fitting) is used to model the relationship between the SW value and the number of error bits. According to the fitting results of these data, the corresponding target threshold of the check matrix for each code rate can be determined.

[0070] In some embodiments, the performing a corresponding decoding operation according to the comparison result comprises:

[0071] If the first SW value is less than a first threshold, correcting the error bits in the code word by using a bit flipping decoder;

[0072] If the first SW value is greater than or equal to the first threshold and less than a second threshold, performing a hard-decision operation on the code word by using a belief propagation decoder;

[0073] If the first SW value is greater than or equal to the second threshold and less than a third threshold, adjusting a voltage axis, re-reading the code word under the adjusted voltage axis and calculating a third SW value, and selecting to perform a hard-decision operation or a soft-decision operation according to the third SW value;

[0074] If the first SW value is greater than or equal to the third threshold and less than a fourth threshold, performing a soft-decision operation on the code word by using a belief propagation decoder;

[0075] Wherein, the second threshold is greater than the first threshold, the third threshold is greater than the second threshold, and the fourth threshold is greater than the third threshold.

[0076] Here, a method of dynamically selecting a corresponding decoding operation by using the size of the SW value is provided, which involves a bit flipping decoder, a belief propagation decoder, a hard-decision operation, a soft-decision operation, an adjustment of a voltage axis, etc. In this way, the decision is made based on the SW value, realizing error estimation, resource adaptation (selecting a target check matrix, selecting a suitable decoder, adjusting a voltage axis, etc.), and through the above intelligent selection, the power consumption can be effectively reduced, the time delay can be reduced, and the throughput can be improved.

[0077] In some embodiments, the correcting the error bits in the codeword by the bit flipping decoder comprises:

[0078] performing at least one round of first iteration operation by the bit flipping decoder until the codeword after the iteration operation meets a decoding decision and / or reaches a set maximum number of iterations; if the decoding fails until the maximum number of iterations, determining a SW value corresponding to the last N first iteration operations; N is greater than or equal to 2;

[0079] determining a first SW average value according to the N SW values;

[0080] if the first SW average value is less than a first SW value, performing a hard-decision operation on the codeword after the decoding failure by a belief propagation decoder;

[0081] if the first SW average value is greater than or equal to the first SW value and less than a second threshold value, performing a hard-decision operation on the initial codeword by the belief propagation decoder;

[0082] if the first SW average value is greater than or equal to the second threshold value, performing a soft-decision operation on the initial codeword by the belief propagation decoder.

[0083] Here, the main operation logic of the bit flipping decoder is the AND and XOR of 1 bit (i.e. c·H T ). The calculation steps of the bit flipping decoder are simple, and the hardware resources and power consumption are small.

[0084] The meeting the decoding decision includes the following cases:

[0085] the decoding is successful;

[0086] or,

[0087] the decoding enters a platform period, i.e. there is no obvious decrease in continuous multiple iterations, then the current decoding can be terminated in advance, and it is considered that the decoding fails.

[0088] In an example, the first iteration operation includes:

[0089] calculating the check equations according to the check matrix, and counting the positions of the check equations that are not established in the check matrix;

[0090] determining and flipping the bit positions involved in the most check equations that are not established;

[0091] continuing to calculate the check equations after the flipping, and making a decoding decision according to the calculation result; if the calculation result is 0, it is determined that the decoding is successful; if the calculation result is not 0, the next round of iteration operation is performed.

[0092] Here, each row of the check matrix represents a constraint condition, i.e., a relationship between information bits and check bits in the encoding. For example, in error correction encoding, each check equation usually involves some information bits and redundant bits, requiring that a linear combination of these bits satisfies a certain condition (e.g., sum to 0).

[0093] The positions where the check equation is not established refer to positions where, in the decoding process, when the check equation is calculated according to the current codeword, it is found that the check equation is not established (i.e., the constraint condition is not met). These positions indicate that there may be errors in the bit positions of the codeword. For the check matrix, if the calculation result of a certain check equation is not 0 (i.e., the check is not established), the variable node (bit position of the codeword) involved is the position of the error.

[0094] That is, in the decoding process, by calculating the check equation and obtaining a result of 0, it is indicated that the current codeword has been successfully corrected and has no error or has been successfully repaired. If the calculation result is not 0, it means that the decoding fails, and error correction needs to be continued until the decoding decision is met or the maximum number of iterations is reached.

[0095] If the decoding fails until the maximum number of iterations, the SW value of the codeword after the last N iteration operations of flipping is determined, the target SW value is determined according to the last N SW values, and if the target SW value exceeds a set threshold, a hard decoding operation is performed.

[0096] Specifically, the first operation is to perform the following operations using a bit flipping decoder:

[0097] Step 11, according to the check matrix and the codeword, find the positions where the check equation is not established, and sequentially count the number of check equations of all variable nodes in the check equation (if the maximum column weight is 5, then the check equation of each variable node is at most 5);

[0098] Step 12, flip the point with the most errors in the check equation;

[0099] Step 13, continue to calculate c·H T for the flipped codeword, and make a decoding decision according to the calculation result; if the calculation result is 0, output the flipped codeword, and if the calculation result is not 0, record the positions where the check equation is not established, repeat steps 11 and 12 above, until the decoding decision is met or the maximum number of iterations is reached.

[0100] The method further comprises:

[0101] Step 14, when the decoding fails, determine according to the SW value after the last N iteration operations of flipping.

[0102] Specifically, a first SW average value is calculated according to the SW values after the last N iterations of the SW operation;

[0103] If the first SW average value is less than the first SW value (i.e., the initial SW value, which is considered to be reduced compared to the initial codeword), the codeword after decoding failure is sent to the belief propagation decoder, and a hard-decision operation is performed on the codeword after decoding failure by using the belief propagation decoder;

[0104] If the first SW average value is greater than or equal to the first SW value and less than a second threshold value, the initial codeword is sent to the belief propagation decoder, and a hard-decision operation is performed on the initial codeword by using the belief propagation decoder;

[0105] If the first SW average value is greater than or equal to the second threshold value, indicating that the error correction effect is poor or the error is stubborn, a hard-decision operation is skipped, and a soft-decision operation is directly performed on the initial codeword by using the belief propagation decoder or it is evaluated whether to give up.

[0106] In some embodiments, the hard-decision operation performed on the codeword by using the belief propagation decoder comprises:

[0107] At least one round of second iteration operation is performed by using the belief propagation decoder until the codeword after the iteration operation satisfies a decoding decision and / or a maximum number of iterations is reached; if the decoding failure still occurs until the maximum number of iterations, a SW value corresponding to the last M iterations of the operation is determined; M is greater than or equal to 2;

[0108] A second SW average value is determined according to the M SW values;

[0109] If the second SW average value is less than the fourth threshold value, a soft-decision operation is performed on the initial codeword by using the belief propagation decoder;

[0110] If the second SW average value is greater than or equal to the fourth threshold value, the decoding operation is given up.

[0111] Here, each round of the second iteration operation comprises: performing a hard-decision operation according to the codeword, the check matrix and a selected voltage axis.

[0112] The main operation logic in the belief propagation decoder is a multiplication and addition operation according to LLR (Log-Likelihood Ratio) information. Since the LLR information also has a requirement for bit quantization, compared with the operation of the bit flipping decoder, more SRAM storage resources are consumed in the calculation process, and the reading and writing of the SRAM also causes power consumption.

[0113] The decoding decision being satisfied includes the following cases:

[0114] Decoding success;

[0115] Or,

[0116] If the decoding enters a plateau, i.e. there is no significant decrease in successive iterations, the current decoding can be terminated early and the decoding is considered to have failed.

[0117] In an example, a hard decoding operation is performed according to a codeword, a check matrix and a voltage axis using a belief propagation decoder, comprising:

[0118] Step 21, initializing the LLR information of each check node in the check matrix, the Lr information of the check node to the variable node, and the Lq information of the variable node to the check node;

[0119] The codeword is generated by the information of the variable node and the check node. Each variable node updates its state according to the received feedback, and finally forms a codeword that meets the check matrix rule.

[0120] In the check matrix, the variable node is the column node in the check matrix, and each variable node represents a data bit in the codeword. In the LDPC code, each column in the check matrix corresponds to a variable node, indicating the participation of the data bit in certain check equations.

[0121] The check node is the row node in the check matrix, and each check node corresponds to a check equation, which is used to verify whether the variable nodes (data bits) connected to it meet certain check rules.

[0122] The LLR (Log-Likelihood Ratio) information of each check node: indicates the confidence of the check node to the received bits.

[0123] The Lr information of the check node to the variable node: indicates the message passed by the check node to the variable node through the iteration process. Specifically, it is the information passed by the check node to the variable node after a certain calculation according to the information of the adjacent variable nodes around it. The goal of the check node is to help the variable node adjust its bit estimate through the Lr information. For example, if the check node detects that the bits of certain variable nodes have a certain relationship with other bits (for example, satisfying a certain parity check equation), it will pass the information Lr to the variable node to remind the variable node to adjust its current estimate.

[0124] Lq information from variable node to check node: indicates the information passed to check node by variable node after updating its estimation of the bit during the decoding process by using the received signal LLR and the information received from other check nodes. Lq represents the latest judgment of variable node for a certain bit, which combines the LLR of the signal received and the information of other nodes. Variable node will use this information to adjust its own decision and provide updated information for subsequent decoding process.

[0125] Variable node and check node update and correct their respective judgments by exchanging Lq and Lr information, until the final result of decoding is reached.

[0126] Step 22, quantize the LLR information corresponding to each variable node according to the voltage axis selected at the moment, and record the quantized LLR information as LQ;

[0127] Here, bit quantization refers to converting the LLR (Log-Likelihood Ratio) value into a form more suitable for hardware processing (such as integer or discrete value) according to the currently selected voltage axis. The quantized LLR value is denoted as LQ.

[0128] Step 23, calculate the updated Lr information, which specifically includes:

[0129] Lq update: calculate Lq = LQ - Lr at the corresponding position of the first layer;

[0130] Compare the absolute value of Lq: calculate and compare the minimum value, the second minimum value and the column index of the minimum value of the absolute value of Lq; at the same time, get the Lq total symbol of the row;

[0131] Lr update: calculate the Lr information corresponding to each variable node of the row, Lr = total symbol × current position symbol × (minimum value / second minimum value) × α, α is a normalization factor, whose size is between 0.5 and 1.

[0132] Step 24, update LQ, specifically: calculate LQ = Lr + Lq;

[0133] Step 25, execute decoding decision, specifically, make a decision according to the updated LQ value, when LQ is greater than 0, record the position as 1, when LQ is less than 0, record the position as 0.

[0134] Step 26, decoding check, specifically, calculate H·c T If the calculation result is 0, the check is passed and the decoding is successful. If H·c T≠ 0, the check fails, at which time the iteration of the next layer of data is performed, and the process of steps 23 to 26 is re-read (i.e., a new second iteration operation is performed), until the decoding decision is finally satisfied or the maximum number of iterations is reached.

[0135] The method further comprises:

[0136] Step 27, when the decoding fails, judging according to the SW value after the last M flag iteration operation.

[0137] Specifically, the average value is calculated according to the SW value after the last M flag iteration operation, to obtain a second SW average value.

[0138] If the second SW average value is lower than a fourth threshold value, the initial codeword is sent to a belief propagation decoder, and a soft decoding operation is performed on the initial codeword by using the belief propagation decoder.

[0139] If the second SW average value is greater than or equal to the fourth threshold value, it indicates that the hard decoding is almost invalid, and the current codeword is directly abandoned, and the operation is ended.

[0140] In some embodiments, if the first SW value is greater than or equal to the second threshold value and less than a third threshold value, the voltage axis is adjusted, the codeword is re-read under the adjusted voltage axis, and a third SW value is calculated, and the hard decoding operation or the soft decoding operation is selected according to the third SW value.

[0141] The number of the adjusted voltage axis is at least one.

[0142] The selection of the hard decoding operation or the soft decoding operation according to the third SW value comprises:

[0143] If the third SW value corresponding to a plurality of voltage axes in the at least one voltage axis is greater than or equal to a first threshold value and less than a second threshold value, the voltage axis with the minimum third SW value is selected as the selected voltage axis, and the hard decoding operation is performed on the selected voltage axis by using the belief propagation decoder.

[0144] Specifically, a certain range of voltage axes can be set in advance as selectable voltage axes, and there is a certain offset between each voltage axis. When stored, the voltage axes can be sequentially sorted from small to large, and the offset relationship is clear.

[0145] If the voltage axis is reselected, the re-reading of the codeword and the recalculation of the SW value are further performed under the selected voltage axis, and the calculated SW value is recorded as a third SW value.

[0146] Whether to enter the hard decoding under the current voltage axis is determined according to the third SW value recalculated.

[0147] In some embodiments, the method further comprises:

[0148] If the third SW value corresponding to each of the at least one voltage axis is greater than the second threshold value and less than the fourth threshold value, performing a soft decoding operation using the belief propagation decoder.

[0149] In some embodiments, re-reading the codeword under the adjusted voltage axis and calculating the third SW value comprises:

[0150] If the first SW value is less than the third threshold value and the difference between the first SW value and the third threshold value is less than a first difference threshold value, re-reading the codeword and calculating the third SW value using all preset voltage axes respectively;

[0151] If the difference between the first SW value and a fifth threshold value is less than a second difference threshold value, re-reading the codeword and calculating the third SW value using voltage axes having a shift from the default voltage axis within a first range; the fifth threshold value is an intermediate value between the second threshold value and the third threshold value;

[0152] If the first SW value is greater than the second threshold value and the difference between the first SW value and the second threshold value is less than a third difference threshold value, re-reading the codeword and calculating the third SW value using a voltage axis having a minimum shift from the default voltage axis.

[0153] Here, the first difference threshold value is configured according to the code rate of the check matrix and the setting of each threshold value, for example, can be 3, 4, 5, etc. Similarly, the second threshold value difference and the third difference threshold value can also be: 3, 4, 5, etc.

[0154] The voltage axis having a shift within the first range refers to a voltage axis having a small shift from the default voltage axis, for example, the three voltage axes before and after the default voltage axis.

[0155] Specifically, under the default voltage axis (i.e., the voltage axis in an initial reading), the calculated SW value is the first SW value described above.

[0156] If the first SW value is greater than or equal to the second threshold value and less than the third threshold value, fast re-reading of the voltage axis and re-calculation of the SW value are required.

[0157] When the first SW value is large (close to the third threshold value, i.e., less than the third threshold value and the difference between the first SW value and the third threshold value is less than the first difference threshold value), all the voltage axes set are attempted, i.e., the codeword is re-read and the third SW value is calculated using all preset voltage axes respectively;

[0158] When the first SW value is medium (close to the middle value of the second threshold value and the third threshold value, i.e. the difference between the first SW value and the fifth threshold value is less than the second difference threshold value), a voltage axis with a smaller offset from the default voltage axis (i.e. the offset from the default voltage axis is in the first range of voltage axes) is attempted;

[0159] When the first SW value is low (close to the second threshold value, i.e. greater than the second threshold value and the difference between the first SW value and the second threshold value is less than the third difference threshold value), a voltage axis with the smallest offset from the default voltage axis is attempted.

[0160] During the reading and selection of the voltage axis, the SW value calculated after each voltage axis and each voltage axis read codeword is recorded. When the SW values corresponding to multiple voltage axes meet the set hard solution range (i.e. greater than or equal to the first threshold value and less than the second threshold value), the candidate voltage axis with the smallest SW value is selected to enter the confidence propagation decoder of the hard solution mode.

[0161] If each SW value in the range of the selected voltage axis is greater than the second threshold value and less than the fourth threshold value, the codeword will not enter the hard solution mode, but will directly enter the soft solution stage.

[0162] Need to be explained, the soft solution operation and the soft solution operation are basically the same, except that the initial value of each LLR in the first iteration is changed from the "hard information" determined by a voltage axis to the "soft information" obtained by multiple voltage axis readings. It can be seen that the acquisition of each soft information requires multiple voltage axis readings, and the time delay and power consumption will be more.

[0163] In some embodiments, the performing a corresponding decoding operation according to the comparison result comprises:

[0164] If the first SW value is greater than or equal to the fourth threshold value, the decoding operation for the codeword is abandoned.

[0165] Here, when the calculated first SW value exceeds the fourth threshold value, it indicates that the codeword will not be successful even after multiple iterations of soft solution decoding, and the decoding operation of the codeword is abandoned.

[0166] The method provided by the embodiments of the present application can enter a bit flip decoder with smaller power consumption and area when the first SW value is less than the first threshold value, thereby avoiding the excessive use of power consumption and storage space caused by multiplication and addition operations in the interaction process between the LLR information in the check node and the variable node when the BP (Belief-Propagation, belief propagation) algorithm scheme is used in the early life of NAND with a small number of errors.

[0167] When the first SW value is greater than or equal to the first threshold value and less than a second threshold value, a hard-decision mode in a belief propagation decoder can be entered, which makes a single voltage axis read to determine a final data value.

[0168] When the first SW value is greater than or equal to the second threshold value and less than a third threshold value, a voltage axis re-read and SW value re-acquisition are performed, and whether to enter a hard-decision under the current voltage axis is determined according to the SW value corresponding to the codeword under different voltage axes.

[0169] When the SW value still exceeds the second threshold value but is less than a fourth threshold value after a set number of voltage axis re-adjustments, the codeword will not enter a hard-decision mode, but directly enters a soft-decision operation in the belief propagation decoder, and the soft information obtained through multiple read voltage axes is used for soft-decision operation. When the SW value exceeds the fourth threshold value, it indicates that the codeword will not be successfully decoded even after multiple iterations of soft-decision, and the decoding operation of the codeword is abandoned.

[0170] In addition, the above also provides a hierarchical progressive decoding, in which the SW value is monitored in real time in the iteration operation of any level, and if it is detected that the SW value does not decrease significantly in continuous multiple iterations, it indicates that the decoding enters a plateau period, and the decoding of the current level can be terminated in advance, and it is determined whether to progress to the next level decoder or directly abandon according to the current SW value level, and when the SW value exceeds a preset fourth threshold value (regardless of which level decoding or re-read stage), it is directly determined that the codeword is not correctable under the current condition, and all decoding attempts are immediately terminated, and resources are released to start processing the next codeword.

[0171] In this way, the number of unnecessary iterations is reduced, power consumption is reduced, and data throughput is improved. At the same time, the hierarchical progressive decoding reduces the number of iterations while ensuring the accuracy of codeword decoding.

[0172] The principle of evaluating the number of errors in the initial codeword by the size of the SW value in the embodiments of the present application, and further selecting the corresponding decoding operation according to the estimated value to perform decoding, is described below.

[0173] As shown in Figure 3 and Figure 4 , the relationship between the error bits and the average SW value of the check matrix under two different code rates is given. Among them, the code rates of the two check matrices are 0.8716 and 0.8989, specifically, the code rate of matrix 1 is: 0.8716, and the code rate of matrix 2 is: 0.8989. The SW value is the average value calculated by performing 100000 times of statistics under each error bit (Error Bits).

[0174] In combination withFigure 3 and Figure 4 It can be seen that for different code rate check matrix, the size of the calculated SW value and the initial error bit number have a certain relationship, that is, when the error number is within a certain range, the SW value and its initial error bit are basically linearly related; when the error number exceeds this range, the SW value will continue to grow with the increase of the initial error, but the growth rate will slow down significantly; when the initial error number continues to grow beyond a certain range, the growth trend of the SW value will further slow down, and with the increase of the error number, the SW value is basically unchanged. For different code rate matrix, in addition to the initial error bit interval of the SW value trend change, which will change according to the code rate of the matrix, the overall change trend of the SW value with the increase of the error number is the same.

[0175] For a specific check matrix H, its dimension is determined by the information bits and the check bits, and the format of the check matrix is as shown in Figure 2 , wherein n-m represents the information bit length, m represents the check bit length, and n represents the complete code word length, wherein the code rate is (n-m) / n, and when the code rate is higher, the check bit is smaller, and the effective information that can be transmitted is longer. When the matrix dimension is large, although the decoding ability can be improved, a larger matrix dimension often brings more storage resource consumption. In addition, in the decoding process, more check bits will also make the one-round complete iterative decoding delay longer, thereby further affecting the power consumption of the decoder. Therefore, the SW value can be used to balance the relationship between the error correction ability and the matrix dimension. Further from Figure 3 and Figure 4 It can be seen that within a certain error range, selecting a matrix with a higher code rate can also bring good error correction ability.

[0176] Figure 5 The error correction performance of a code rate check matrix (mantrix1) in soft decision and hard decision mode is given; it can be seen that for the same code rate check matrix (such as matrix 1 in Figure 5 , the threshold performance of soft decision (Soft Decision) and hard decision (Hard Decision) is also different, if the order of 1E-4 is taken as the lowest decoding requirement, that is, a maximum of one error is allowed in 10000 decoding operations, the applicable range of hard decision is less than 367 bits of initial error, and the applicable range of soft decision is less than 820 bits of initial error.

[0177] When the initial error is greater than 900 bits, even if the soft decoding is entered, the decoding will have a great probability of failure at this time, and such meaningless decoding not only increases the iteration time, wastes power consumption, but also affects the final data throughput. Since the decoding process of LDPC is similar to the decoding process of soft decoding and hard decoding, but the initial information used by the two is different, specifically, the initial LLR value of soft decoding and hard decoding is different. The LLR value is a measurement method for evaluating the bit information in the received signal, which measures the relative possibility of a bit being "0" or "1".

[0178] When the error bits are less (for example, less than 300 bits), although the performance can be greatly improved by starting soft decoding to read multiple voltage axes, the process of multiple reading also causes the increase of time delay and the waste of power consumption.

[0179] Figure 6 The error correction performance of another code rate check matrix (matrix2) in soft decoding and hard decoding modes is given, and the comparison Figure 5 and Figure 6 It can be seen that, for different code rate check matrices (such as matrix 1 in Figure 5 and matrix 2 in Figure 6 ), the initial error interval of the soft and hard decoding trials is different.

[0180] Based on this, the embodiment of the present application proposes that the relationship between the above-mentioned SW value and the initial error bits can be used to determine the target threshold value corresponding to the SW value when each check matrix starts soft decoding and hard decoding, and the value is configured in the decoder in advance during the decoding start process, and different decoding modes are selected according to the actual initial SW value of each code word.

[0181] In addition, since the number of error bits existing in the early life of the NAND flash particle is often small, especially within the linear interval of the SW value and the initial error bits shown in Figure 4 , at this time, the errors are basically distributed on different check equations. If hard decoding is used for error correction, since the initial code word needs to be converted into the corresponding prior probability, multiplication and addition operations of confidence are performed, and the storage of intermediate information is also involved in the operation process. These steps not only cause the use of storage space, but also cause power consumption and the increase of time delay in the information reading and writing process. Therefore, in this stage, a fast bit flipping decoding method is proposed, which uses whether the size of the SW value corresponding to each bit on each error check equation meets the set threshold value to determine whether the bit is flipped, without additional information operation and storage, which can significantly reduce power consumption and improve decoding efficiency. The bit flipping decoding performance of the above-mentioned matrix (matrix) 1 and matrix (matrix) 2 is as follows Figure 7It can be seen that the bit flipping also has good decoding performance when the number of errors is small, i.e. the corresponding SW value is in the linear region of the matrix.

[0182] In addition, it should be noted that for some codewords, although the initial SW value satisfies the corresponding decoder, there is still a certain probability of decoding failure under the set maximum number of iterations. Some of the failed codewords can be successfully decoded by further iteration in the next level decoder, and some cannot be decoded successfully even after the next level decoder. At this time, the SW value of the last iteration or the average SW value of the last few iterations is evaluated. If the value meets the preset condition, the initial codeword or the codeword after decoding failure is sent to the next level decoder for decoding. If the preset condition is not met, the decoding attempt is terminated directly, and the decoding of the next segment of codewords is started. For the codewords in the iteration process, the SW value in each iteration process can also be used to judge the errors in the iteration process. If the SW value does not decrease significantly in continuous multiple iterations or is in a fluctuating state, it is considered that the codeword has entered the "trap set", i.e. it cannot be correctly decoded no matter how many iterations are performed. At this time, the decoding of the current level is terminated in advance, and the next level decoder is selected according to the corresponding SW value or given up.

[0183] Figure 8 A structure diagram of a step-by-step decoder provided by an embodiment of the present application is shown in FIG. 1. Figure 7 As shown in FIG. 1, the step-by-step decoder includes a decoding control module and a decoding operation module.

[0184] The decoding control module is configured to set a maximum number of iterations, calculate an SW value, configure a target threshold, and select a decoder in the decoding operation module.

[0185] Here, the selected decoder can include a bit flipping decoder and a belief propagation decoder, wherein the belief propagation decoder can perform a soft operation or a hard operation.

[0186] The operations of the bit flipping decoder and the belief propagation decoder have been described in detail in the method shown in FIG. 2, and will not be described here. Figure 1

[0187] It should be noted that Figure 8 The SW value calculation in the decoding control module is equivalent to calculating the first SW value described above, and the SW value calculation in the decoding operation module includes calculating the SW value after each round of iteration operation of the bit flipping decoder and calculating the average value of the SW values.

[0188] Figure 9 A structure diagram of another step-by-step decoding device provided by an embodiment of the present application is shown in FIG. 3. Figure 9 As shown in FIG. 3, the device includes​

[0189] an obtaining module, configured to obtain a codeword and a target check matrix;

[0190] a first processing module, configured to determine a first SW value according to the codeword and the target check matrix;

[0191] a second processing module, configured to compare the first SW value with a target threshold value, and perform a corresponding decoding operation according to a comparison result.

[0192] In some embodiments, the obtaining module is configured to determine a second SW value according to the codeword and a preset initial check matrix;

[0193] If the second SW value is less than a first SW threshold value, a first check matrix is selected as the target check matrix;

[0194] If the second SW value is greater than or equal to the first SW threshold value and less than a second SW threshold value, a second check matrix is selected as the target check matrix;

[0195] If the second SW value is greater than or equal to the second SW threshold value, a third check matrix is selected as the target check matrix; wherein a code rate of the first check matrix is greater than a code rate of the second check matrix, and the code rate of the second check matrix is greater than a code rate of the third check matrix.

[0196] In some embodiments, the second processing module is configured to, if the first SW value is less than a first threshold value, correct error bits in the codeword by using a bit flipping decoder;

[0197] If the first SW value is greater than or equal to the first threshold value and less than a second threshold value, a hard decision operation is performed on the codeword by using a belief propagation decoder;

[0198] If the first SW value is greater than or equal to the second threshold value and less than a third threshold value, a voltage axis is adjusted, the codeword is re-read under the adjusted voltage axis, a third SW value is calculated, and a hard decision operation or a soft decision operation is selected to be performed according to the third SW value;

[0199] wherein the second threshold value is greater than the first threshold value, and the third threshold value is greater than the second threshold value.

[0200] In some embodiments, the second processing module is configured to perform at least one round of first iteration operation by using the bit flipping decoder until the codeword after the iteration operation meets a decoding decision and / or a maximum iteration number set is reached; if the decoding fails until the maximum iteration number, a SW value corresponding to the last N rounds of first iteration operation is determined; N is greater than or equal to 2.

[0201] The first average SW value is determined based on the N SW values;

[0202] If the average value of the first SW is less than the first SW value, the confidence propagation decoder is used to perform a hard decoding operation on the codeword after the decoding failure.

[0203] If the average value of the first SW is greater than or equal to the first SW value and less than the second threshold, the initial codeword is hard-decoded using a confidence propagation decoder.

[0204] If the average value of the first SW is greater than or equal to the second threshold, a soft decoding operation is performed on the initial codeword using a confidence propagation decoder.

[0205] If the first SW value is greater than or equal to the third threshold and less than the fourth threshold, a soft decoding operation is performed on the codeword using a confidence propagation decoder.

[0206] Wherein, the second threshold is greater than the first threshold, the third threshold is greater than the second threshold, and the fourth threshold is greater than the third threshold.

[0207] In some embodiments, the second processing module is configured to perform at least one round of second iteration operation using the confidence propagation decoder until the codeword after the iteration operation satisfies the decoding decision and / or reaches the set maximum number of iterations; if decoding still fails until the maximum number of iterations, the SW value corresponding to the last M iteration operations is determined; M is greater than or equal to 2.

[0208] The second average SW value is determined based on the SW values ​​of the M times;

[0209] If the average value of the second SW is less than the fourth threshold, the initial codeword is soft-decoded using the confidence propagation decoder.

[0210] If the average value of the second SW is greater than or equal to the fourth threshold, then the decoding operation is abandoned.

[0211] In some embodiments, the number of adjusted voltage axes is at least one;

[0212] The second processing module is configured to, if there are multiple voltage axes in at least one voltage axis whose corresponding third SW values ​​are greater than or equal to a first threshold and less than a second threshold, select the voltage axis with the smallest third SW value as the selected voltage axis, and use the confidence propagation decoder to perform a hard decoding operation based on the selected voltage axis.

[0213] In some embodiments, the second processing module is configured to perform a soft decoding operation on the codeword using the confidence propagation decoder if the third SW value corresponding to each voltage axis in the at least one voltage axis is greater than the second threshold and less than the fourth threshold.

[0214] In some embodiments, the second processing module is configured to reread the codewords and calculate the third SW value using all preset voltage axes if the first SW value is less than a third threshold and the difference between the first SW value and the third threshold is less than a first difference threshold.

[0215] If the difference between the first SW value and the fifth threshold is less than the second difference threshold, the codeword is reread using the voltage axis in the first range with the offset from the default voltage axis, and the third SW value is calculated respectively; the fifth threshold is the intermediate value between the second threshold and the third threshold;

[0216] If the first SW value is greater than the second threshold and the difference between the first SW value and the second threshold is less than the third difference threshold, the codeword is reread using the voltage axis with the smallest offset from the default voltage axis and the third SW value is calculated.

[0217] In some embodiments, the second processing module is configured to abandon the decoding operation for the codeword if the first SW value is greater than or equal to a fourth threshold.

[0218] In some embodiments, before comparing the first SW value with the target threshold, the method further includes:

[0219] The target threshold corresponding to the target verification matrix is ​​determined by querying a preset threshold table based on the target verification matrix.

[0220] The preset threshold table includes at least one check matrix and a target threshold corresponding to each check matrix. The target threshold includes multiple thresholds used for comparison with the SW value.

[0221] It is understood that the step-by-step decoding apparatus provided in the above embodiments can, as needed, distribute the above processing to different program modules to complete all or part of the processing described above when implementing the corresponding step-by-step decoding method. Furthermore, the apparatus and the corresponding method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiments, which will not be repeated here.

[0222] This application provides a computer program product or computer program that includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform a step-by-step decoding method.

[0223] This application provides a computer-readable storage medium storing executable instructions. When the executable instructions are executed by a processor, the processor will execute the step-by-step decoding method provided in this application.

[0224] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or it may be a variety of devices including one or any combination of the above-mentioned memories.

[0225] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0226] As an example, executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple collaborating files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0227] As an example, executable instructions can be deployed to execute on a single computing device, or on multiple computing devices located in one location, or on multiple computing devices distributed across multiple locations and interconnected via a communication network.

[0228] Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application; as shown below. Figure 10 As shown, the electronic device 100 includes a processor 1001 and a memory 1002 communicatively connected to the processor 1001; the memory 1002 stores instructions executable by the processor 1001. The instructions are executed by the processor 1001 to enable the processor 1001 to perform the aforementioned step-by-step decoding method.

[0229] The electronic devices provided in the above embodiments and the corresponding step-by-step decoding method embodiments belong to the same concept. For details of their specific implementation process, please refer to the method embodiments, which will not be repeated here.

[0230] In practical applications, the electronic device 100 may further include at least one network interface 1003. The various components in the electronic device 100 are coupled together via a bus system 1004. It is understood that the bus system 1004 is used to implement communication between these components. In addition to a data bus, the bus system 1004 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 10 All buses are labeled as bus system 1004. The number of processors 1001 can be at least one, and the number of memories 1002 can be at least one. Network interface 1003 is used for wired or wireless communication between electronic device 100 and other devices.

[0231] The memory 1002 in this embodiment is used to store various types of data to support the operation of the electronic device 100.

[0232] The methods disclosed in the embodiments of this application can be applied to or implemented by the processor 1001. The processor 1001 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in the processor 1001 or by instructions in the form of software. The processor 1001 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 1001 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium, which is located in the memory 1002. The processor 1001 reads the information in the memory 1002 and, in conjunction with its hardware, completes the steps of the aforementioned step-by-step decoding method.

[0233] In some embodiments, the electronic device 100 may be implemented by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors, or other electronic components to perform the aforementioned methods.

[0234] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0235] In the above description, the term "some embodiments" refers to a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0236] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used in this application is for the purpose of describing embodiments of this application only and is not intended to be limiting of this application.

[0237] It should be understood that in the various embodiments of this application, the sequence number of each implementation process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0238] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0239] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A step-by-step decoding method, characterized in that, The method includes: Obtain the codeword and target verification matrix; The first comprehensive weight SW value is determined based on the codeword and the target verification matrix; Compare the first SW value with the target threshold, and perform the corresponding decoding operation based on the comparison result; Obtaining the target verification matrix includes: The second SW value is determined based on the codeword and the preset initial parity check matrix; If the second SW value is less than the first SW threshold, then the first verification matrix is ​​selected as the target verification matrix; If the second SW value is greater than or equal to the first SW threshold and less than the second SW threshold, then the second verification matrix is ​​selected as the target verification matrix. If the second SW value is greater than or equal to the second SW threshold, then the third parity check matrix is ​​selected as the target parity check matrix; wherein, the bitrate of the first parity check matrix is ​​greater than the bitrate of the second parity check matrix, and the bitrate of the second parity check matrix is ​​greater than the bitrate of the third parity check matrix. The step of performing the corresponding decoding operation based on the comparison result includes: If the first SW value is less than the first threshold, the erroneous bits in the codeword are corrected using a bit-flipping decoder. If the first SW value is greater than or equal to the first threshold and less than the second threshold, a hard decoding operation is performed on the codeword using a belief propagation decoder. If the first SW value is greater than or equal to the second threshold and less than the third threshold, the voltage axis is adjusted, the codeword is reread under the adjusted voltage axis and the third SW value is calculated, and either hard decoding or soft decoding is performed based on the third SW value. If the first SW value is greater than or equal to the third threshold and less than the fourth threshold, a soft decoding operation is performed on the codeword using a confidence propagation decoder. Wherein, the second threshold is greater than the first threshold, the third threshold is greater than the second threshold, and the fourth threshold is greater than the third threshold.

2. The method according to claim 1, characterized in that, The step of using a bit-flipping decoder to correct erroneous bits in the codeword includes: The bit-flipping decoder is used to perform at least one round of first iteration operation until the codeword after the iteration operation satisfies the decoding decision and / or reaches the set maximum number of iterations; if decoding still fails after the maximum number of iterations, the SW value corresponding to the last N first iteration operations is determined; N is greater than or equal to 2. The first average SW value is determined based on the N SW values; If the average value of the first SW is less than the first SW value, the confidence propagation decoder is used to perform a hard decoding operation on the codeword after the decoding failure. If the average value of the first SW is greater than or equal to the first SW value and less than the second threshold, the initial codeword is hard-decoded using a confidence propagation decoder. If the average value of the first SW is greater than or equal to the second threshold, a soft decoding operation is performed on the initial codeword using a confidence propagation decoder.

3. The method according to claim 1, characterized in that, The step of performing hard decoding on the codeword using a belief propagation decoder includes: The confidence propagation decoder is used to perform at least one round of second iteration operation until the codeword after the iteration operation satisfies the decoding decision and / or reaches the set maximum number of iterations; if decoding still fails until the maximum number of iterations, the SW value corresponding to the last M iteration operations is determined; M is greater than or equal to 2. The second average SW value is determined based on the SW values ​​of the M times; If the average value of the second SW is less than the fourth threshold, the initial codeword is soft-decoded using the confidence propagation decoder. If the average value of the second SW is greater than or equal to the fourth threshold, then the decoding operation is abandoned.

4. The method according to claim 1, characterized in that, The adjusted number of voltage axes is at least one; The step of selecting to perform a hard decoding operation or a soft decoding operation based on the third SW value includes: If there are multiple voltage axes in at least one voltage axis whose corresponding third SW values ​​are greater than or equal to the first threshold and less than the second threshold, then the voltage axis with the smallest third SW value is selected as the selected voltage axis, and the confidence propagation decoder performs a hard decoding operation based on the selected voltage axis.

5. The method according to claim 4, characterized in that, The method further includes: If the third SW value corresponding to each voltage axis in at least one voltage axis is greater than the second threshold and less than the fourth threshold, the confidence propagation decoder is used to perform a soft decoding operation on the codeword.

6. The method according to claim 4, characterized in that, Reread the codeword and calculate the third SW value under the adjusted voltage axis, including: If the first SW value is less than the third threshold and the difference between the first SW value and the third threshold is less than the first difference threshold, the codeword is reread using all preset voltage axes and the third SW value is calculated respectively. If the difference between the first SW value and the fifth threshold is less than the second difference threshold, the codeword is reread using the voltage axis in the first range with the offset from the default voltage axis, and the third SW value is calculated respectively; the fifth threshold is the intermediate value between the second threshold and the third threshold; If the first SW value is greater than the second threshold and the difference between the first SW value and the second threshold is less than the third difference threshold, the codeword is reread using the voltage axis with the smallest offset from the default voltage axis and the third SW value is calculated.

7. The method according to claim 1, characterized in that, The step of performing the corresponding decoding operation based on the comparison result includes: If the first SW value is greater than or equal to the fourth threshold, the decoding operation for the codeword is abandoned.

8. The method according to claim 1, characterized in that, Before comparing the first SW value with the target threshold, the method further includes: The target threshold corresponding to the target verification matrix is ​​determined by querying a preset threshold table based on the target verification matrix. The preset threshold table includes at least one check matrix and a target threshold corresponding to each check matrix. The target threshold includes multiple thresholds used for comparison with the SW value.

9. A step-by-step decoding device, characterized in that, The device includes: The acquisition module is used to acquire codewords and the target verification matrix; The first processing module is used to determine the first SW value based on the codeword and the target parity check matrix; The second processing module is used to compare the first SW value with the target threshold and perform the corresponding decoding operation according to the comparison result; The acquisition module is used to determine the second SW value based on the codeword and the preset initial check matrix; If the second SW value is less than the first SW threshold, then the first verification matrix is ​​selected as the target verification matrix; If the second SW value is greater than or equal to the first SW threshold and less than the second SW threshold, then the second verification matrix is ​​selected as the target verification matrix. If the second SW value is greater than or equal to the second SW threshold, then the third parity check matrix is ​​selected as the target parity check matrix; wherein, the bitrate of the first parity check matrix is ​​greater than the bitrate of the second parity check matrix, and the bitrate of the second parity check matrix is ​​greater than the bitrate of the third parity check matrix. The second processing module is used to correct erroneous bits in the codeword using a bit-flipping decoder if the first SW value is less than the first threshold. If the first SW value is greater than or equal to the first threshold and less than the second threshold, a hard decoding operation is performed on the codeword using a belief propagation decoder. If the first SW value is greater than or equal to the second threshold and less than the third threshold, the voltage axis is adjusted, the codeword is reread under the adjusted voltage axis and the third SW value is calculated, and either hard decoding or soft decoding is performed based on the third SW value. If the first SW value is greater than or equal to the third threshold and less than the fourth threshold, a soft decoding operation is performed on the codeword using a confidence propagation decoder. Wherein, the second threshold is greater than the first threshold, the third threshold is greater than the second threshold, and the fourth threshold is greater than the third threshold.

10. An electronic device, characterized in that, include: At least one processor; And a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the step-by-step decoding method according to any one of claims 1 to 8.

11. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to execute the step-by-step decoding method according to any one of claims 1 to 8.

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