Vector mask calculation method and device

Abstract

The invention relates to a vector mask calculation method and device. Comprising the following steps: marking mask cache labels hit by mask registers corresponding to a plurality of mask calculation instructions which are ready to register, and selecting at least one mask calculation instruction as a target mask calculation instruction; determining a mask cache item corresponding to a mask cache tag of the target mask calculation instruction, and reading a mask recorded in the mask cache item; and calculating the target mask calculation instruction according to the read mask. According to the embodiment of the invention, under the condition that the system performance is not influenced, the number of reading ports of the vector register file is reduced by a quarter, so that the area and the power consumption of the vector register file of the corresponding item number are reduced, and more vector execution units can be supported under the same manufacturing process.

Description

Technical Field

[0001] The embodiments in this specification relate to the field of computer technology, and in particular to a vector mask calculation method and apparatus. Background Technology

[0002] Vector computing refers to a single vector computing instruction performing multiple identical operations simultaneously, processing different fields, and producing different target data. Most RISC-V vector instructions currently support masked computing, meaning the instruction only writes to the masked (i.e., fields with a mask bit set to 1) fields in the target register, while the values ​​of unmasked (i.e., fields with a mask bit set to 0) remain unchanged. For these instructions, the vm bit in the opcode indicates whether masked computing is performed.

[0003] vm=1: Maskless computation, all field calculation results will be written to registers;

[0004] vm = 0: Mask calculation, the mask value comes from mask register v0. At this time, each bit in mask register v0, starting from the least significant bit, identifies a field. When v0[i] is 1, the calculation result can be written to the corresponding field; otherwise, it is not written.

[0005] Most CPU cores implement register renaming, which maps an architectural register to a physical register within the core. This avoids false register dependencies such as write-after-read and write-after-write, thereby improving instruction-level parallelism (ILP) and performance. For CPU cores implementing register renaming, the masked instruction needs to copy the unmasked fields from the old target physical register A to the new target physical register B mapped from the same architectural register, ensuring that the values ​​of these fields remain unchanged. In this case, a single masked instruction needs to read four different physical register values: the first source register storing the main data operands, the second source register storing the minor data operands, the mask register storing the mask, and the target physical register storing the original values ​​of the target architectural register. This significantly increases the number of read ports required for the vector register file, increasing its area and power consumption. Furthermore, due to the maximum number of read ports limited by the manufacturing process, this approach cannot support more vector execution units, severely restricting the vector computing capabilities of processors using this solution. Summary of the Invention

[0006] To address the problems existing in the prior art, embodiments of this specification provide a vector mask calculation method and apparatus that eliminates the mask register and adds a mask cache (MC), a mask cache tag (MCT), and a mask cache allocation buffer (MCAB). The MC stores the most recently calculated mask register value and provides an optimized mask calculation architecture from the MC to provide the mask required for a dispatched instruction. Compared to traditional solutions, the method of this specification reduces the number of vector register file read ports by one-quarter without affecting system performance, thereby reducing the area and power consumption of the corresponding number of vector register files and enabling the support of more vector execution units under the same manufacturing process.

[0007] The specific technical solutions of the embodiments in this specification are as follows:

[0008] On the one hand, embodiments of this specification provide a vector mask calculation method, the method comprising:

[0009] The mask cache tag corresponding to the mask register of each of the multiple mask calculation instructions that are ready for registration is marked, and at least one mask calculation instruction is selected as the target mask calculation instruction.

[0010] Determine the mask cache entry corresponding to the mask cache tag of the target mask calculation instruction, and read the mask recorded in the mask cache entry;

[0011] The target mask calculation instruction is calculated based on the read mask.

[0012] Furthermore, selecting at least one mask calculation instruction as the target mask calculation instruction includes:

[0013] Based on the mask cache label, two computation instructions that meet predetermined conditions are selected from the rearranged buffer header, and at least one of the two computation instructions includes the target mask computation instruction.

[0014] Furthermore, the two computation instructions that satisfy predetermined conditions for selecting the rearranged buffer header based on the mask buffer label include:

[0015] The first registered ready computation instruction at the head of the rearranged buffer is taken as the first candidate computation instruction, and the second registered ready computation instruction at the head of the rearranged buffer is taken as the second candidate computation instruction.

[0016] Based on the calculation type and / or mask cache label of the first candidate calculation instruction and the second candidate calculation instruction, determine the number of physical register file read ports for the first candidate calculation instruction and the second candidate calculation instruction, and calculate the total number of physical register file read ports.

[0017] If the total number of physical register file read ports does not exceed the threshold, then the first candidate calculation instruction and the second candidate calculation instruction satisfy the predetermined conditions.

[0018] Further, based on the computation type and / or mask cache label of the first and second candidate computation instructions, the number of physical register file read ports for the first and second candidate computation instructions is determined, including:

[0019] The first candidate calculation instruction and the second candidate calculation instruction are respectively designated as candidate calculation instructions;

[0020] If the computation type of the candidate computation instruction is non-mask computation, then the number of physical register file read ports of the candidate computation instruction is the first number;

[0021] If the computation type of the candidate computation instruction is mask computation, and the candidate computation instruction is marked with the mask cache tag, then the number of physical register file read ports of the candidate computation instruction is the second number;

[0022] If the computation type of the candidate computation instruction is mask computation, and the candidate computation instruction is not marked with the mask cache label, then the number of physical register file read ports of the candidate computation instruction is the third number;

[0023] Among them, the first quantity < the second quantity < the third quantity.

[0024] Furthermore, if the total number of physical register file read ports exceeds a threshold, the method further includes:

[0025] The number of physical register file read ports for the candidate computation instructions following the second candidate computation instruction at the head of the rearranged buffer is determined, and the total number of physical register file read ports for the first candidate computation instruction and the candidate computation instruction is calculated. If the total number of physical register file read ports does not exceed the threshold, then the first candidate computation instruction and the candidate computation instruction satisfy the predetermined condition.

[0026] Furthermore, the method also includes:

[0027] If the number of registered ready computation instructions between the first candidate computation instruction and the candidate computation instruction following the second candidate computation instruction exceeds a predetermined value, then the first candidate computation instruction is processed separately in the I1 pipeline stage and the I2 pipeline stage.

[0028] Furthermore, the threshold is 6.

[0029] Furthermore, the first quantity is 2, the second quantity is 3, and the third quantity is 4.

[0030] Furthermore, the mask cache tags corresponding to the mask register hits of the multiple mask calculation instructions that are marked as ready for registration include:

[0031] By matching the identifier of the mask register corresponding to each mask calculation instruction with the mask register identifier recorded in each mask cache tag in the mask cache tag list, the mask cache tag matched by each mask calculation instruction is obtained.

[0032] Furthermore, the method also includes:

[0033] Extract the calculation results as the calculation instructions for the mask, and use them as the target calculation instructions;

[0034] Assign mask cache labels to the calculation results of the target calculation instruction, and initialize the assigned mask cache labels;

[0035] Write the identifier of the mask cache entry corresponding to the allocated mask cache label and the identifier of the target physical register corresponding to the target calculation instruction into the target mask allocation buffer entry. The target mask allocation buffer entry is an empty mask allocation buffer entry in the mask allocation buffer.

[0036] When the I2 pipeline of the target computation instruction forwards, the corresponding target mask allocation buffer entry is searched from the target mask allocation buffer according to the identifier of the target physical register corresponding to the target computation instruction. The mask cache entry corresponding to the identifier of the mask cache entry recorded in the found target mask classification allocation buffer entry is determined, and the mask recorded in the determined mask cache entry is updated to the computation result of the target computation instruction.

[0037] Furthermore, assigning mask cache labels to the calculation results of the target calculation instruction further includes:

[0038] Find reassignable mask cache tags;

[0039] Update the mask register identifier recorded in the reassignable mask cache tag to the identifier of the target physical register corresponding to the target computation instruction.

[0040] Furthermore, finding reassignable mask cache tags includes:

[0041] Find invalid mask cache tags and use them as reassignable mask cache tags.

[0042] Furthermore, finding reassignable mask cache tags includes:

[0043] If no invalid mask cache tag is found, then look for mask cache tags that have not been used by computation instructions in the pipeline and use them as reassignable mask cache tags.

[0044] On the other hand, embodiments of this specification also provide a vector mask calculation device, the device comprising:

[0045] The mask cache tag marking unit is used to mark the mask cache tags that the mask registers of the multiple registered and ready mask calculation instructions hit, and to select at least one mask calculation instruction as the target mask calculation instruction.

[0046] A mask cache reading unit is used to determine the mask cache entry corresponding to the mask cache label of the target mask calculation instruction, and read the mask recorded in the mask cache entry;

[0047] An execution unit is used to calculate the target mask calculation instructions based on the read mask.

[0048] On the other hand, embodiments of this specification also provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0049] The embodiments described in this specification eliminate the mask register and add MC, MCT, and MCAB. MC stores the most recently calculated mask register value and provides an optimized mask calculation architecture for the mask required by a distributed instruction. Multiple registered ready mask calculation instructions are marked with their corresponding MCT entries in the mask register. At least one mask calculation instruction is selected as the target mask calculation instruction. The MC entry corresponding to the MCT entry of the target mask calculation instruction is determined. The mask recorded in the MC entry is read, and the target mask calculation instruction is calculated based on the read mask. Compared to traditional solutions, the method in these embodiments reduces the number of vector register file read ports by one-quarter without affecting system performance, thereby reducing the area and power consumption of the corresponding number of vector register files and enabling support for more vector execution units under the same manufacturing process. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 The diagram shows a CPU architecture in the prior art that includes multiple pipeline stages.

[0052] Figure 2 The diagram shown is an example architecture of the distribution and execution pipeline stages in a processor in the prior art;

[0053] Figure 3 The diagram shown is a schematic flowchart of the vector mask calculation method in the embodiments of this specification;

[0054] Figure 4 The diagram shown is an example architecture diagram of the improved distribution / execution unit according to an embodiment of this specification;

[0055] Figure 5 The diagram shown is a flowchart illustrating how the I0 pipeline stage determines whether each uop is ready and whether its mask value is obtained from the MC in an embodiment of this specification.

[0056] Figure 6 The diagram shown is a flowchart illustrating how, in an embodiment of this specification, two computation instructions that satisfy predetermined conditions are selected from the head of the rearrange buffer based on the mask buffer label.

[0057] Figure 7 The diagram shown is a flowchart illustrating the updating and replacement process of MCT / MC in the embodiments of this specification.

[0058] Figure 8 The diagram shown is a flowchart illustrating the process of assigning mask cache tags to the calculation results of the target calculation instruction in an embodiment of this specification.

[0059] Figure 9 The diagram shown is a schematic representation of a vector mask calculation device according to an embodiment of this specification.

[0060] Figure 10 The diagram shown is a structural schematic of the computer device in an embodiment of this specification.

[0061] [Explanation of Figure Markers]:

[0062] 901. Mask Buffer Tag Marking Unit;

[0063] 902. Mask buffer read unit;

[0064] 903. Execution Unit;

[0065] 1002. Computer equipment;

[0066] 1004. Processing equipment;

[0067] 1006. Storage resources;

[0068] 1008. Drive mechanism;

[0069] 1010. Input / Output Module;

[0070] 1012. Input devices;

[0071] 1014. Output devices;

[0072] 1016. Presentation device;

[0073] 1018. Graphical User Interface;

[0074] 1020. Network interface;

[0075] 1022. Communication link;

[0076] 1024. Communication bus. Detailed Implementation

[0077] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the embodiments of this specification, and not all embodiments. Based on the embodiments of this specification, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the embodiments of this specification.

[0078] It should be noted that the terms "first," "second," etc., in the description, claims, and accompanying drawings of the embodiments herein are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, apparatus, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0079] It should be noted that the acquisition, storage, use, and processing of data in the technical solutions of the embodiments of this specification all comply with the relevant provisions of national laws and regulations.

[0080] It should be noted that in the embodiments of this specification, certain software, components, models and other existing solutions in the industry may be mentioned. These should be regarded as exemplary and are only intended to illustrate the feasibility of implementing the technical solution of this application. However, they do not mean that the applicant has used or necessarily used the solution.

[0081] To improve performance, modern CPU architectures typically include multiple pipeline stages, such as... Figure 1 As shown. Most CPU cores implement register renaming, which maps an architecture register to a physical register within the kernel. This avoids false register dependencies such as write-after-read and write-after-write, thereby improving instruction-level parallelism (ILP) and performance. For CPU cores that implement register renaming, the masked instruction needs to copy the unmasked fields from the old target physical register A to the new target physical register B mapped from the same architecture register, ensuring that the values ​​of these fields remain unchanged. In this case, a single masked instruction needs to read the values ​​of four different physical registers: the first source register storing the main data operands, the second source register storing the secondary data operands, the mask register storing the mask, and the target physical register storing the original value of the target architecture register.

[0082] Register renaming is typically accomplished using the following hardware buffers:

[0083] (1) Speculative rename table (SRT): Stores the latest (but may be erroneous or flushed) mapping between architectural registers and physical registers.

[0084] (2) Architectural rename table (ART): Stores the mapping relationship between architectural registers and physical registers in the architectural state.

[0085] (3) Free register list (FRL): It is generally implemented as a bit list, with each physical register corresponding to one bit. A bit value of 1 indicates that the physical register is not currently in use.

[0086] (4) Reorder buffer (ROB): ROB is a first-in-first-out circular buffer used to maintain the order of instructions in a CPU core that is executing out of order.

[0087] When an instruction renames a register, the renaming unit performs the following operations.

[0088] Step 1: Query the SR to find the physical register currently mapped to each source architecture register. When this instruction is subsequently inserted into the ROB in the Dispatch pipeline, the renaming information of its destination register is also stored in the corresponding ROB entry.

[0089] Step 2: For each target architecture register, select a physical register with the corresponding FRL bit set to 1, write the mapping into the SRT entry corresponding to the target architecture register, and set the FRL bit to 0.

[0090] In subsequent execution, the instruction (or its corresponding one or more microinstructions) reads and writes these physical registers.

[0091] In the Retire pipeline, if the oldest instruction (i.e., at the ROB header) has completed execution without exception, it can be retireed, which means releasing the hardware resources used by these instructions, including their mapped physical registers. At this time, the mapping relationship between the target architecture register and the physical register is written into the Architecture Rename Table (ART). The physical register that is replaced in the ART will have its FRL bit set to 1, and it can be reused in a new register mapping in the next clock cycle.

[0092] Another function of ART is to restore the SRT (System Time Limit) when a pipeline flush occurs due to a branch prediction error. When a pipeline flush occurs due to a branch prediction error, the branch prediction instruction that triggered the flush is not necessarily the oldest instruction in the pipeline. In this case, the following operations are required to restore the SRT content up to that instruction:

[0093] 1. Clear and temporarily halt the CPU pipeline.

[0094] 2. Clear all instruction entries in ROB that are younger than the instruction in this branch.

[0095] 3. Write each item of ART into the corresponding item of SRT.

[0096] 4. Starting with the first item of ROB, write its target register mapping content into SRT.

[0097] 5. The CPU pipeline resumes operation, fetching and executing instructions from the correct instruction address after the corrected branch instruction.

[0098] Both scalar and vector instructions can encounter exceptions. Exception handling is performed when the instruction is the oldest instruction in the pipeline. In RISC-V, when handling exceptions for vector instructions, the location of the field where the exception occurred is first saved in the vstart CSR register in the destination register (group). Then, all fields with indices less than the exception index are written to the destination register, and exception handling is performed. After exception handling, the vector instruction is re-executed. This re-execution reads the vstart value, and the mask of all fields with indices less than vstart is set to 0, meaning their results are not written to the corresponding locations in the destination register.

[0099] Figure 2 This is an example architecture diagram of the dispatch and execution pipeline stages in a processor in the prior art. In this example, the issue queue is a unified architecture (i.e., one issue queue connects all execution units), dispatching three pipeline stages (I0 / I1 / I2) with two execution units. Therefore, two micro-operations (Uops) (or compute instructions) are selected each clock cycle. Different types of instructions may have different numbers of execution pipeline stages.

[0100] Pipeline 0: For each source register of each uop, the register ready bits (RRB) are checked to determine if the source register is ready. Ready is defined as the register value already existing in the register file, or the execution unit being able to provide the corresponding value in the I2 pipeline (called forward). Among all uops with ready sources, the two oldest uops are selected to proceed to the next pipeline stage.

[0101] I1 Pipeline: Reads all source register values ​​of the two uops in this pipeline. A single RISC-V vector instruction needs to read up to four source register values: the first source register sources1 which stores the main data operands, the second source register sources2 which stores the secondary data operands, the mask register mask which stores the mask, and the current value of the destination physical register destination which stores the original value of the destination architecture register.

[0102] I2 Pipeline: The execution unit forwards the remaining source register values ​​required by uop in this pipeline, so that all source register values ​​of uop are obtained at the end of this pipeline.

[0103] Execution Unit: Different instructions require different pipeline stages. After Uop is executed, the result is written to the register file and forwarded to the I2 pipeline stage.

[0104] Register Ready Bits assign one bit to each entry in the physical register to indicate whether it is available (ready). There are two states for Ready:

[0105] 1. The Uop that writes to this register has been completed, or the next clock cycle has been completed. Therefore, the value of this register will be obtained from the PRF physical register file.

[0106] 2. The Uop that writes to this register has already been dispatched or executed. It will complete when this Uop enters the last dispatch pipeline stage (i.e., I2 in the example). Therefore, the register value can be passed to this Uop via the forward bus. a) CountDown mechanism: In order to set the ready bit of the corresponding register in the correct clock cycle in this case, each Uop selected in I0 sets a counter, the value of which is the number of clock cycles required for the micro-operation of this Uop to be executed (for example, a simple ALU Uop only requires 1 stage, while multiplication, division, and load Uops require 2 or more stages). Then, each clock cycle, the counter is decremented by 1. If the counter value is 0 after decrementing by 1, the countdown stops, and the ready bit of the corresponding target register is set to 1.

[0107] b) A distributed and executed UOP may fail to complete execution due to certain circumstances and be cancelled. In this case, all UOPs that have been issued and have data dependencies on that UOP will also be cancelled. Meanwhile,

[0108] The ready bits corresponding to the destination registers of these canceled uops will also be cleared to zero.

[0109] To handle cases where tail elements remain unchanged during a single calculation, each UOP also needs to read the corresponding VL value. Since this solution does not require changes to the VL reading and usage logic, therefore... Figure 2 The vl signal is not identified in the code.

[0110] RISC-V vector instruction mask calculations require the value of the mask register, while RISC-V uses normal vector registers to store the mask. Therefore, in existing technologies, a vector instruction with vm=0 requires reading four source registers: two source registers, one mask register, and one physical register storing the original value of the target architecture register. This significantly increases the number of read ports required for the vector register file (for example, an architecture with four vector execution units requires 4*4=16 vector register file read ports), which increases the area of ​​the vector register file and the corresponding power consumption of the implementation.

[0111] In response to the aforementioned requirement for the number of vector register file read ports in RISC-V vector instruction mask computation, this specification proposes an optimized solution to reduce the number of vector register file read ports required for RISC-V vector instruction mask computation to 3 without affecting performance. This reduces the area and power consumption of the corresponding number of vector register files and enables the support of more vector execution units under the same manufacturing process.

[0112] Specifically, the embodiments of this specification provide a vector mask calculation method that eliminates the mask register and adds a mask cache (MC), a mask cache tag (MCT), and a mask cache allocation buffer (MCAB). The MC is used to store the most recently calculated mask register value, and the MC provides an optimized mask calculation architecture for the mask required by a distributed instruction. Figure 3 The diagram shown is a flowchart illustrating a vector mask calculation method according to an embodiment of this specification. This diagram depicts the process of mask calculation instructions being distributed and executed in the processor pipeline. The order of steps listed in the embodiment is merely one possible execution order among many and does not represent the only possible execution order. In actual system or device products, the method can be executed sequentially or in parallel according to the embodiment or the accompanying drawings. Specifically, as shown... Figure 3 As shown, the method may include:

[0113] Step 301: Mark the mask cache tag that the mask register of each of the multiple mask calculation instructions that are ready for registration hits, and select at least one mask calculation instruction as the target mask calculation instruction;

[0114] Step 302: Determine the mask cache entry corresponding to the mask cache tag of the target mask calculation instruction, and read the mask recorded in the mask cache entry;

[0115] Step 303: Calculate the target mask calculation instruction based on the read mask.

[0116] The embodiments described in this specification eliminate the mask register and add MC, MCT, and MCAB. MC stores the most recently calculated mask register value and provides an optimized mask calculation architecture for the mask required by a distributed instruction. Multiple registered ready mask calculation instructions are marked with their corresponding MCT entries in the mask register. At least one mask calculation instruction is selected as the target mask calculation instruction. The MC entry corresponding to the MCT entry of the target mask calculation instruction is determined. The mask recorded in the MC entry is read, and the target mask calculation instruction is calculated based on the read mask. Compared to traditional solutions, the method in these embodiments reduces the number of vector register file read ports by one-quarter without affecting system performance, thereby reducing the area and power consumption of the corresponding number of vector register files and enabling support for more vector execution units under the same manufacturing process.

[0117] like Figure 4 This is an example architecture diagram of the improved distribution / execution unit in the embodiments of this specification, compared to... Figure 2 The diagram shown is an example architecture diagram of the CPU distribution and execution pipeline stage in the prior art. Figure 3 The yellow boxes in the middle indicate components newly added to the embodiments of this specification, including:

[0118] Mask Cache (MC): Stores only recently computed mask values ​​from the vector execution unit. Each entry has the same width as a physical register entry. MC and register file are accessed in the same clock cycle (I1) and data is provided for arbitration in the next clock cycle (I2). MC entries contain the same information as register file entries, but there are far fewer MC entries. It supports one lookup port for each issued UOP within the same clock cycle, and the same number of lookup results are output in the same clock cycle (as shown in the figure, both lookup and result ports are 2).

[0119] Mask Cache Tag (MCT): Stores the physical register (mask register) index corresponding to each MC entry, and has the same number of entries and organizational structure (fully / set associativity) as the MC. It is accessed at the I / O pipeline level. Each MCT contains the following fields:

[0120] 1. Valid: 1 bit, a value of 1 indicates that the MCT item has valid data, otherwise the item is invalid.

[0121] 2. PRF_ID: N bits. If the Valid field of the same item is 1, this field stores the index of the physical register (mask register) corresponding to the mask. The size of N can cover all PRF indices. For example, if there are 256 PRF items, then N is at least 8 bits (2^8 = 256).

[0122] 3. Use counter: Its maximum value can represent (X-1)*Y. It is used to represent the number of uops that use this MC item in the I0 / I1 stage. Where X: issue pipeline number. Figure 2 or Figure 4 The scheme shown has X=3, Y: the number of UOPs that can be issued per clock cycle. Figure 2 or Figure 4 The proposed scheme has Y = 2.

[0123] Mask Cache Allocation Buffer (MCAB): (X-1)*Y entries, used to temporarily store and synchronize the update results of MCT / MC. An MCAB entry is allocated during MCT updates. When writing to MC, the target physical register index is used to search the MCAB, find the corresponding MC entry for that physical register, and write the calculation result (mask value) into that MC entry. MCAB contains the following fields:

[0124] 1. Valid: 1 bit, a value of 1 indicates that the MCAB item has valid data, otherwise the item is invalid.

[0125] 2. PRF_ID: N bits, consistent with the PRF_ID content of MCT.

[0126] 3. MC_ID: M bits, representing the MC entry allocated to PRF_ID. The size of MC_ID is large enough to cover all MC indices.

[0127] In addition to adding MC and MCT, the embodiments in this specification also make the following adjustments to hardware resources:

[0128] The number of PRF read ports has been reduced from 8 to 6. The first source register (sources1), the second source register (sources2), and the destination physical register (destination) for each uop remain unchanged; only the read port for the mask register has been removed.

[0129] Each uop's mask mux has changed from a 3-choose-1 to a 4-choose-1 system: an additional data source from the MC has been added. Simultaneously, to effectively utilize the PRF's six read ports, the mask of one uop shares the same PRF data source as the target physical register of another uop.

[0130] Each uop adds a 1-bit field MASK_DST, which is 1 when the uop generates a mask (possibly). This field is set during the decoding phase if any of the following conditions are met:

[0131] 1. This instruction is a RISC-V vector instruction for generating a mask, namely one of the following instructions: vm{and,nand,andn,xor,or}.mm, vmsbf.m, vmsif.m, vmsof.m.

[0132] 2. The target register for this instruction is v0, and LMUL <= 1. Since RISC-V mask calculations use v0 as the mask register by default, an instruction to write to v0 may be generating a mask value.

[0133] Depending on the implemented process and the number of MC items, MC and MCT can be organized in a fully associative or set associative manner, and the replacement strategy will be detailed later. Since there will not be many MC / MCT items, as a preferred embodiment, the embodiments in this specification assume a fully associative MC / MCT.

[0134] The method described in this specification's embodiments modifies the flow stage as follows:

[0135] In the I0 pipeline stage, the mask cache tags corresponding to the mask registers of the multiple mask computation instructions that are ready for registration are marked, and at least one mask computation instruction is selected as the target mask computation instruction.

[0136] Specifically, for each source register of each uop, the register ready bits are queried to determine whether the source register is ready. For the mask register of a uop where all source registers are ready and vm=0 (indicating that the computation instruction is a mask computation instruction), it is checked whether it hits the MCT. As follows: Figure 5 As shown. If an MCT is hit, then mark the MCT hit by the mask calculation instruction (uop with vm=0).

[0137] Among them, the mask cache tags that the mask registers of the multiple mask calculation instructions that are marked as ready for registration include:

[0138] By matching the identifier of the mask register corresponding to each mask calculation instruction (i.e., the ID of the mask register that the mask calculation instruction originally obtained) with the mask register identifier (PRF_ID) recorded in each mask cache tag in the mask cache tag list, the mask cache tag matched by each mask calculation instruction is obtained.

[0139] Then, at least one mask calculation instruction is selected as the target mask calculation instruction. It should be noted that in actual implementation, the selected calculation instruction may also be a non-mask calculation instruction (i.e., uop with vm=1). In this case, the non-mask calculation instruction is processed using the existing technology (the non-mask calculation instruction only needs to read the data in the first source register sources1 and the second source register sources2, and does not need to read the mask).

[0140] In the embodiments of this specification, selecting at least one mask calculation instruction as the target mask calculation instruction includes:

[0141] Based on the mask cache label, select two computation instructions (uop) in the rearrange buffer (ROB) header that meet predetermined conditions, wherein at least one of the two computation instructions includes the target mask computation instruction.

[0142] According to one embodiment of this specification, such as Figure 6 As shown, the two computation instructions that select the rearranged buffer header based on the mask buffer label and satisfy the predetermined conditions include:

[0143] Step 601: The first registered ready calculation instruction at the head of the rearranged buffer is taken as the first candidate calculation instruction, and the second registered ready calculation instruction at the head of the rearranged buffer is taken as the second candidate calculation instruction.

[0144] Step 602: Determine the number of physical register file read ports for the first and second candidate calculation instructions based on their respective calculation types and / or mask cache tags, and calculate the total number of physical register file read ports.

[0145] Step 603: If the total number of physical register file read ports does not exceed the threshold, then the first candidate calculation instruction and the second candidate calculation instruction satisfy the predetermined conditions.

[0146] In the embodiments of this specification, the threshold can be set to 6. If the total number of physical register file read ports of the first candidate calculation instruction and the second candidate calculation instruction does not exceed 6, then the first candidate calculation instruction and the second candidate calculation instruction meet the predetermined conditions.

[0147] In the embodiments of this specification, determining the number of physical register file read ports for the first and second candidate computation instructions based on their respective computation types and / or mask cache tags includes:

[0148] The first candidate calculation instruction and the second candidate calculation instruction are respectively designated as candidate calculation instructions;

[0149] If the computation type of the candidate computation instruction is non-mask computation (vm=1), then the number of physical register file read ports of the candidate computation instruction is the first number, where the first number is 2, that is, the uop of non-mask computation only needs to read source1 and source2;

[0150] If the computation type of the candidate computation instruction is mask computation (vm=0), and the candidate computation instruction is marked with the Mask Cache Tag (MCT), it means that the mask of the candidate computation instruction can be obtained from MC instead of from the mask register v0. Then the number of physical register file read ports of the candidate computation instruction is the second number, where the second number is 3. That is, the uop of mask computation marked with MCT only needs to read source1, source2 and destination, and does not need to read mask register v0.

[0151] If the computation type of the candidate computation instruction is mask computation, and the candidate computation instruction is not marked with the mask cache tag, then the number of physical register file read ports of the candidate computation instruction is the third number, where the third number is 4. That is, for mask computation and uop not marked with MCT, only the existing technology can be used to read the four source registers: source1, source2, v0 and destination.

[0152] For example, if the first UOP is the oldest ready UOP (i.e., the first candidate computation instruction), then the selection of the second UOP (i.e., the second candidate computation instruction) must satisfy the condition that the oldest UOP among the two UOPs with a total PRF read slots does not exceed 6:

[0153] (1) If the first uop's vm=1 (only 2 PRF read ports are needed): the second uop can be selected according to age.

[0154] (2) If the first uop has vm=0 but hits the MCT (requires 3 PRF read ports): the second uop can have vm=1, or vm=0 but must hit the MCT.

[0155] (3) If the first uop has vm=0, the MCT is not hit (4 PRF read ports are required): the second uop must have vm=1.

[0156] In practical implementation, the first oldest and ready UOP in the ROB header and the second oldest and ready UOP in the ROB header may not meet the aforementioned predetermined conditions. Therefore, the first oldest and ready UOP in the ROB header can be selected first, and then it can be determined whether the UOPs after the second oldest and ready UOP in the ROB header meet the aforementioned predetermined conditions with the first oldest and ready UOP. Specifically, if the total number of physical register file read ports exceeds a threshold, the method further includes:

[0157] The number of physical register file read ports for the candidate computation instructions following the second candidate computation instruction at the head of the rearranged buffer is determined, and the total number of physical register file read ports for the first candidate computation instruction and the candidate computation instruction is calculated. If the total number of physical register file read ports does not exceed the threshold, then the first candidate computation instruction and the candidate computation instruction meet the predetermined conditions, and then the first candidate computation instruction and the candidate computation instruction enter the next stage pipeline.

[0158] It should be noted that because ROBs need to follow the first-in-first-out principle, the interval between the first candidate computation instruction and the second candidate computation instruction cannot be too large. Therefore, if the number of registered ready computation instructions between the first candidate computation instruction and the candidate computation instruction after the second candidate computation instruction exceeds a predetermined value, it is considered that two uops that meet the predetermined conditions cannot be selected, and only the first candidate computation instruction will enter the next stage pipeline.

[0159] In the embodiments of this specification, the predetermined value can be 1, 2, or other integers. Developers can set the predetermined value according to actual needs, and this embodiment of the specification does not impose any restrictions. If the predetermined value is 1, it means that if the first candidate calculation instruction and the second candidate calculation instruction do not meet the above predetermined requirements, the first candidate calculation instruction will be directly entered into the next stage of the pipeline, and the second candidate calculation instruction will become the first candidate calculation instruction in the next calculation cycle, and the above steps will be repeated.

[0160] In the embodiments of this specification, if the I0 pipeline selects one or two uops, and one or two uops are used for mask calculation and hit the MCT, then the Use counter for the hit MCT item is added.

[0161] In the I1 pipeline stage, the mask cache entry corresponding to the mask cache tag of the target mask calculation instruction is determined, and the mask recorded in the mask cache entry is read. If the calculation instruction selected by the I0 pipeline stage is a non-mask calculation instruction or is not tagged with MCT, the corresponding source register value is read from the PRF using existing methods.

[0162] In the I2 pipeline stage, the target mask calculation instruction is calculated based on the read mask. In the embodiments described in this specification, the selection algorithm for the two UOPs in the I0 pipeline stage ensures that no port conflicts occur and that each UOP obtains all the required source data. This clock cycle also decrements the Use counter by one for each UOP that hits an MCT term.

[0163] Execution Unit: Different instructions require different pipeline stages. After Uop is executed, the result is written to the register file and forwarded to the I2 pipeline stage.

[0164] According to one embodiment of this specification, if the count-down counter of an already issued uop is 0, its destination register RRB bit will be set to 1. If the MASK_DST bit of the uop is 1 (i.e., the uop is a calculation instruction for calculating the mask) and an MC item is allocated (indicating that the mask calculated by the calculation instruction can be cached in the MC), then the result is written to the MC at the same time.

[0165] This specification's embodiments are based on the RRB / PRF update mechanism to implement the update and replacement of MCT / MC. While PRF and RRB are updated in different clock cycles, MCT and RRB are updated / replaced in the same clock cycle, and PRF and MC are updated in the same clock cycle, with an interval of (X-1) clock cycles between them.

[0166] Specifically, such as Figure 7 As shown, the method further includes:

[0167] Step 701: Extract the calculation result as the calculation instruction of the mask, and use it as the target calculation instruction;

[0168] Step 702: Assign mask cache labels to the calculation results of the target calculation instruction, and initialize the assigned mask cache labels;

[0169] Step 703: Write the identifier of the mask cache entry corresponding to the allocated mask cache tag and the identifier of the target physical register corresponding to the target calculation instruction into the target mask allocation buffer entry, wherein the target mask allocation buffer entry is an empty mask allocation buffer entry in the mask allocation buffer;

[0170] Step 704: When the I2 pipeline of the target computation instruction forwards, the corresponding target mask allocation buffer entry is searched from the target mask allocation buffer according to the identifier of the target physical register corresponding to the target computation instruction. The mask cache entry corresponding to the identifier of the mask cache entry recorded in the found target mask classification allocation buffer entry is determined, and the mask recorded in the determined mask cache entry is updated to the computation result of the target computation instruction.

[0171] Because the method in this embodiment adds a MASK_DST bit to uop, the MASK_DST bit is used to identify whether uop is a uop for calculating the mask. If the MASK_DST bit is 1, it means that uop is a uop for calculating the mask, and the calculation result of the uop (the calculated mask) can be cached in MC.

[0172] In the embodiments of this specification, because the number of MC items cannot be too large, therefore, as Figure 8 As shown in the embodiments of this specification, allocating mask cache labels to the calculation results of the target calculation instruction further includes:

[0173] Step 801: Locate relocatable mask cache tags;

[0174] Step 802: Update the mask register identifier recorded in the reassignable mask cache tag to the identifier of the target physical register corresponding to the target calculation instruction.

[0175] Specifically, finding reassignable mask cache tags can be based on the following principles:

[0176] 1. If there is an invalid item in the MCT (invalid mask cache tag), then that item will be allocated first.

[0177] 2. Otherwise, starting from the first item in the MCT, search for items with a use counter of zero. The first item found is selected to replace it. A use counter of zero indicates that the item is not currently being used by a UOP in the distribution pipeline, and therefore can be replaced.

[0178] 3. If no MCT item with a use counter of zero is found, no MC / MCT item will be assigned to this uop.

[0179] The newly allocated MCT entry will set its valid value to 1, its use counter to 0, and its PRF_ID to the new physical register ID (this ID is the ID of the target physical register corresponding to the uop, such as the ID of the target physical register to which the uop's computational structure is input). This result will then be written to an MCAB entry with valid = 0 (indicating it's idle). Since MCAB has (X-1)*Y entries, it can be guaranteed that an MCAB entry with valid = 0 will always be available when MCT needs it.

[0180] After a uop with a MASK_DST field of 1 is executed, the following operations will be performed while writing the result to the PRF and forwarding:

[0181] 1. Use the target physical register index of the uop to query the MCAB;

[0182] 2. If a valid=1 MCAB item is found (i.e., the target mask allocation buffer item is found), read the MC_ID value recorded in the target mask allocation buffer item (i.e., the identifier of the mask cache item corresponding to the allocated mask cache label).

[0183] 1) Write the result of uop execution into the MC item pointed to by MC_ID;

[0184] 2) Set the validity of the MCAB item to 0 so that the item can be reused.

[0185] 3. If MCAB is not hit, it will not be written to MC.

[0186] It should be noted that the above embodiments are based on Figure 2 The example architecture (with three distribution pipeline stages I0 / I1 / I2 and two vector execution units) is used to illustrate the details of the vector mask calculation method in the embodiments of this specification. However, the vector mask calculation method in the embodiments of this specification does not depend on these microarchitectural parameters and a specific number of pipeline stages, and is equally applicable to other architectures using different numbers of distribution / execution pipeline stages and execution units.

[0187] In the embodiments described in this specification, MC / MCT only caches the mask and physical register values ​​that may be masks. In some other embodiments described in this specification, it is also possible to cache the mask and other non-mask physical register values. Both methods have their advantages and disadvantages:

[0188] Mask-only caching scheme: Since the mask is updated less frequently than other vector instructions, MC only needs a few items; since each uop has at most one mask source, MC only needs to provide Y ports.

[0189] Non-Mask-only caching scheme: Since this cache can provide all source registers such as src1 / src / mask / dest, the number of read ports for the PRF can be further reduced. However, due to the need for more frequent updates and storage of more data, the number of cache entries needs to be increased significantly to ensure effective use of the cache entries, and the number of read ports needs to be increased to ensure that multiple data entries can be provided per clock cycle. The forward logic of this method is also more complex.

[0190] In the embodiments described in this specification, the MCAB has (X-1)*Y entries to ensure that all uops updating the MC can be allocated an MCAB entry. In some other embodiments of this specification, fewer MCAB entries can be selected. In this case, if a uop with MASK_DST of 1 fails to obtain an MCAB entry when there are very few MCAB entries with valid=0, it will not update the MC / MCT.

[0191] The embodiments in this specification assume that the vector issue queue is a unified architecture, meaning that all vector execution units are provided with UOPs by the same issue queue. In some other embodiments of this specification, a non-unified issue queue can also be chosen, i.e., an architecture with multiple issue queues, each connecting one or more execution units. The latter can also implement a mask cache, but because multiple issue queues cannot select matching UOPs based on resource requirements at the I0 pipeline stage, resource conflicts may occur at the I2 stage (i.e., some UOPs cannot obtain all source register values). In this case, these UOPs need to be canceled at the I2 stage, allowing them to re-run the issue phase.

[0192] Based on the same inventive concept, embodiments of this specification also provide a vector mask calculation device, such as... Figure 9 As shown, it includes:

[0193] The mask cache tag marking unit 901 is used to mark the mask cache tags that the mask registers of the multiple registered and ready mask calculation instructions hit, and to select at least one mask calculation instruction as the target mask calculation instruction.

[0194] The mask cache reading unit 902 is used to determine the mask cache item corresponding to the mask cache tag of the target mask calculation instruction, and read the mask recorded in the mask cache item;

[0195] The execution unit 903 is used to calculate the target mask calculation instruction based on the read mask.

[0196] The beneficial effects obtained by the above-described device are the same as those obtained by the above-described method, and will not be described in detail in the embodiments of this specification.

[0197] like Figure 10The diagram illustrates the structure of a computer device according to an embodiment of this specification. The apparatus in this embodiment can be the computer device described above, executing the methods described in the embodiments of this specification. The computer device 1002 may include one or more processing devices 1004, such as one or more central processing units (CPUs), each of which can implement one or more hardware threads. The computer device 1002 may also include any storage resource 1006 for storing information of any kind, such as code, settings, data, etc. Without limitation, for example, the storage resource 1006 may include any one or more combinations of the following: any type of RAM, any type of ROM, flash memory, hard disk, optical disk, etc. More generally, any storage resource can use any technology to store information. Furthermore, any storage resource can provide volatile or non-volatile retention of information. Furthermore, any storage resource can represent a fixed or removable component of the computer device 1002. In one case, when the processing device 1004 executes associated instructions stored in any storage resource or combination of storage resources, the computer device 1002 can perform any operation of the associated instructions. The computer device 1002 also includes one or more drive mechanisms 1008 for interacting with any storage resource, such as hard disk drive mechanism, optical disk drive mechanism, etc.

[0198] Computer device 1002 may also include an input / output module 1010 (I / O) for receiving various inputs (via input device 1012) and providing various outputs (via output device 1014). A specific output mechanism may include a presentation device 1016 and an associated graphical user interface (GUI) 1018. In other embodiments, the input / output module 1010 (I / O), input device 1012, and output device 1014 may be omitted, and the device may function solely as a computer device within a network. Computer device 1002 may also include one or more network interfaces 1020 for exchanging data with other devices via one or more communication links 1022. One or more communication buses 1024 couple the components described above together.

[0199] The communication link 1022 can be implemented in any way, such as via a local area network, a wide area network (e.g., the Internet), a point-to-point connection, or any combination thereof. The communication link 1022 may include any combination of hardwired links, wireless links, routers, gateway functions, name servers, etc., governed by any protocol or combination of protocols.

[0200] This specification also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0201] This specification also provides computer-readable instructions, wherein when a processor executes the instructions, the program therein causes the processor to perform the above-described method.

[0202] It should be understood that in the various embodiments of this specification, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this specification.

[0203] It should also be understood that, in the embodiments of this specification, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, in the embodiments of this specification, the character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0204] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this specification can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of the embodiments in this specification.

[0205] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0206] In the embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections through some interfaces, devices, or units, or they may be electrical, mechanical, or other forms of connection.

[0207] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments described in this specification, depending on actual needs.

[0208] Furthermore, the functional units in the various embodiments of this specification can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0209] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this specification, in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this specification. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0210] This specification describes the principles and implementation methods of the embodiments using specific examples. The above descriptions of the embodiments are only for the purpose of helping to understand the methods and core ideas of the embodiments in this specification. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the embodiments in this specification. Therefore, the content of this specification should not be construed as a limitation on the embodiments in this specification.

Claims

1. A vector mask calculation method, characterized in that, The method includes: The mask cache tag corresponding to the mask register of each of the multiple mask calculation instructions that are ready for registration is marked, and at least one mask calculation instruction is selected as the target mask calculation instruction. Determine the mask cache entry corresponding to the mask cache tag of the target mask calculation instruction, and read the mask recorded in the mask cache entry; The target mask calculation instruction is calculated based on the read mask.

2. The method according to claim 1, characterized in that, Selecting at least one mask calculation instruction as the target mask calculation instruction includes: Based on the mask cache label, two computation instructions that meet predetermined conditions are selected from the rearranged buffer header, and at least one of the two computation instructions includes the target mask computation instruction.

3. The method according to claim 2, characterized in that, The two computation instructions that satisfy predetermined conditions for selecting the rearrange buffer header based on the mask buffer label include: The first registered ready computation instruction at the head of the rearranged buffer is taken as the first candidate computation instruction, and the second registered ready computation instruction at the head of the rearranged buffer is taken as the second candidate computation instruction. Based on the calculation type and / or mask cache label of the first candidate calculation instruction and the second candidate calculation instruction, determine the number of physical register file read ports for the first candidate calculation instruction and the second candidate calculation instruction, and calculate the total number of physical register file read ports. If the total number of physical register file read ports does not exceed the threshold, then the first candidate calculation instruction and the second candidate calculation instruction satisfy the predetermined conditions.

4. The method according to claim 3, characterized in that, Based on the computation type and / or mask cache label of the first and second candidate computation instructions, the number of physical register file read ports for the first and second candidate computation instructions is determined, including: The first candidate calculation instruction and the second candidate calculation instruction are respectively designated as candidate calculation instructions; If the computation type of the candidate computation instruction is non-mask computation, then the number of physical register file read ports of the candidate computation instruction is the first number; If the computation type of the candidate computation instruction is mask computation, and the candidate computation instruction is marked with the mask cache tag, then the number of physical register file read ports of the candidate computation instruction is the second number; If the computation type of the candidate computation instruction is mask computation, and the candidate computation instruction is not marked with the mask cache label, then the number of physical register file read ports of the candidate computation instruction is the third number; Among them, the first quantity < the second quantity < the third quantity.

5. The method according to claim 3, characterized in that, If the total number of physical register file read ports exceeds the threshold, the method further includes: The number of physical register file read ports for the candidate computation instructions following the second candidate computation instruction at the head of the rearranged buffer is determined, and the total number of physical register file read ports for the first candidate computation instruction and the candidate computation instruction is calculated. If the total number of physical register file read ports does not exceed the threshold, then the first candidate computation instruction and the candidate computation instruction satisfy the predetermined condition.

6. The method according to claim 5, characterized in that, The method further includes: If the number of registered ready computation instructions between the first candidate computation instruction and the candidate computation instruction following the second candidate computation instruction exceeds a predetermined value, then the first candidate computation instruction is processed separately in the I1 pipeline stage and the I2 pipeline stage.

7. The method according to claim 3, characterized in that, The threshold is 6.

8. The method according to claim 4, characterized in that, The first quantity is 2, the second quantity is 3, and the third quantity is 4.

9. The method according to claim 1, characterized in that, The mask cache tags that the mask registers of the multiple mask calculation instructions that are marked as ready for registration include: By matching the identifier of the mask register corresponding to each mask calculation instruction with the mask register identifier recorded in each mask cache tag in the mask cache tag list, the mask cache tag matched by each mask calculation instruction is obtained.

10. The method according to claim 1, characterized in that, The method further includes: Extract the calculation results as the calculation instructions for the mask, and use them as the target calculation instructions; Assign mask cache labels to the calculation results of the target calculation instruction, and initialize the assigned mask cache labels; Write the identifier of the mask cache entry corresponding to the allocated mask cache label and the identifier of the target physical register corresponding to the target calculation instruction into the target mask allocation buffer entry. The target mask allocation buffer entry is an empty mask allocation buffer entry in the mask allocation buffer. When the I2 pipeline of the target computation instruction forwards, the corresponding target mask allocation buffer entry is searched from the target mask allocation buffer according to the identifier of the target physical register corresponding to the target computation instruction. The mask cache entry corresponding to the identifier of the mask cache entry recorded in the found target mask classification allocation buffer entry is determined, and the mask recorded in the determined mask cache entry is updated to the computation result of the target computation instruction.

11. The method according to claim 10, characterized in that, Assigning mask cache labels to the calculation results of the target calculation instruction further includes: Find reassignable mask cache tags; Update the mask register identifier recorded in the reassignable mask cache tag to the identifier of the target physical register corresponding to the target computation instruction.

12. The method according to claim 11, characterized in that, Finding reassignable mask cache tags includes: Find invalid mask cache tags and use them as reassignable mask cache tags.

13. The method according to claim 11, characterized in that, Finding reassignable mask cache tags includes: If no invalid mask cache tag is found, then look for mask cache tags that have not been used by computation instructions in the pipeline and use them as reassignable mask cache tags.

14. A vector mask calculation device, characterized in that, The device includes: The mask cache tag marking unit is used to mark the mask cache tags that the mask registers of the multiple registered and ready mask calculation instructions hit, and to select at least one mask calculation instruction as the target mask calculation instruction. A mask cache reading unit is used to determine the mask cache entry corresponding to the mask cache label of the target mask calculation instruction, and read the mask recorded in the mask cache entry; An execution unit is used to calculate the target mask calculation instructions based on the read mask.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method of any one of claims 1 to 13.

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