Method and apparatus for determining the optimal offset voltage of flash memory storage media

Abstract

This application relates to the field of solid-state drive technology, and particularly to a method and apparatus for determining the optimal offset voltage of a flash memory storage medium. The method includes: determining a data retention trigger threshold based on the current bit error rate of the target storage block, and determining a read interference trigger threshold based on the current read operation frequency; performing an offset voltage scan on the target storage block based on the current erase / write count, erase / write count trigger threshold, current data retention duration, data retention trigger threshold, current read count, and read interference trigger threshold, when the target storage block meets preset offset voltage determination conditions, and determining the current optimal offset voltage based on the offset voltage scan results. This solves the problem in related technologies where rigid triggering mechanisms and low search efficiency prevent real-time adaptation to temperature, error rate, and load changes, leading to insufficient read voltage matching accuracy and increased error rate. It significantly improves the search efficiency and real-time performance of the optimal offset voltage and effectively reduces the read error rate.

Description

Technical Field

[0001] This application relates to the field of solid-state drive technology, and in particular to a method and apparatus for determining the optimal offset voltage of a flash memory storage medium. Background Technology

[0002] NAND flash memory, as the mainstream non-volatile storage medium, is widely used in storage devices such as solid-state drives (SSDs). It records data by presenting different voltage thresholds based on the varying amounts of charge in the storage cells. However, with the increase in program / erase counts (PE), retention time (RT), read disturbances (RD), and changes in ambient temperature, the charge characteristics of the storage cells drift. This causes a mismatch between the reference voltage during reading and the actual storage state, leading to an increase in the bit error rate (BER). If the error rate exceeds the error correction capability of the error correction code, data read failures will occur, severely impacting the reliability and lifespan of the storage device.

[0003] In related technologies, the Fixed Read Tables (FRT) method is commonly used to address the aforementioned problems. This method selects corresponding reference voltage combinations at different stages based on preset PE, RT, and RD thresholds to optimize read performance. However, this method has significant shortcomings: First, the triggering mechanism is rigid, failing to consider the accelerated impact of dynamic environmental factors such as temperature on storage cell characteristics and lacking real-time feedback adjustment; second, the search efficiency is low, typically requiring traversal of all in-use blocks and a full-range voltage scan, with time increasing significantly with capacity; third, the voltage matching accuracy is insufficient, failing to dynamically adjust the search strategy based on real-time BER data; fourth, the ability to handle multi-factor coupling is weak, as the effects of PE, RT, RD, and temperature on voltage offset are not independent, making it difficult for existing solutions to adapt to the dynamic adjustment requirements under complex operating conditions, which urgently need to be addressed. Summary of the Invention

[0004] This application provides a method and apparatus for determining the optimal offset voltage of a flash memory storage medium, which solves the problem that the fixed lookup table method in related technologies cannot adapt to changes in temperature, error rate and load in real time due to rigid triggering mechanism and low search efficiency, resulting in insufficient read voltage matching accuracy and increased error rate. Through dynamic adaptive triggering and error rate feedback mechanism, the search efficiency and real-time performance of the optimal offset voltage are significantly improved, and the read error rate is effectively reduced.

[0005] To achieve the above objectives, a first aspect of this application proposes a method for determining the optimal offset voltage of a flash memory storage medium, the method comprising the following steps:

[0006] Obtain the current erase / write count, current data retention time, current read count, current operating temperature, current bit error rate, and current read operation frequency of the target storage block;

[0007] The erase / write cycle trigger threshold is determined based on the current operating temperature, the data retention trigger threshold is determined based on the current bit error rate, and the read interference trigger threshold is determined based on the current read operation frequency.

[0008] Based on the current erase / write count, the erase / write count trigger threshold, the current data retention time, the data retention trigger threshold, the current read count, and the read interference trigger threshold, determine whether the target memory block meets the preset offset voltage determination condition according to the current bit error rate;

[0009] If the target memory block meets the preset offset voltage determination condition, then an offset voltage scan is performed on the target memory block to obtain the offset voltage scan result, and the current optimal offset voltage is determined based on the offset voltage scan result.

[0010] The optimal offset voltage determination method for flash memory storage media proposed in this application determines a data retention trigger threshold based on the current bit error rate of the target storage block and a read interference trigger threshold based on the current read operation frequency. Based on the current erase / write count, erase / write count trigger threshold, current data retention duration, data retention trigger threshold, current read count, and read interference trigger threshold, when the target storage block meets the preset offset voltage determination conditions, an offset voltage scan is performed on the target storage block, and the current optimal offset voltage is determined based on the offset voltage scan results. This solves the problem in related technologies where the fixed lookup table method, due to its rigid trigger mechanism and low search efficiency, cannot adapt to changes in temperature, error rate, and load in real time, leading to insufficient read voltage matching accuracy and increased error rate. Through a dynamic adaptive triggering and error rate feedback mechanism, the search efficiency and real-time performance of the optimal offset voltage are significantly improved, effectively reducing the read error rate.

[0011] To achieve the above objectives, a second aspect of this application provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the optimal offset voltage determination method for a flash memory storage medium as described in the above embodiments.

[0012] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0013] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a flowchart of a method for determining the optimal offset voltage of a flash memory storage medium according to an embodiment of this application;

[0015] Figure 2 This is a flowchart of a method for determining the optimal offset voltage of a flash memory storage medium according to an embodiment of this application;

[0016] Figure 3 This is a block diagram of an apparatus for determining the optimal offset voltage of a flash memory storage medium according to an embodiment of this application;

[0017] Figure 4 This is a schematic diagram of the structure of an electronic device provided according to an embodiment of this application.

[0018] Reference numerals: 10-Optimal offset voltage determination device for flash memory storage medium; 100-Acquisition module; 200-Threshold determination module; 300-Judgment module; 400-Optimal offset voltage determination module; 401-Memory; 402-Processor; 403-Communication interface. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0020] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0021] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] As those skilled in the art will understand, NAND Flash, as a widely used storage medium, records data by presenting different voltage values ​​through different amounts of charge in the storage cells. However, due to the electrical characteristics of NAND chips, during their lifespan, the charge storage characteristics of the storage cells change with variations in factors such as PE (Program / Erase Cycle), RT (Retention Time), RD (Read Disturbance), and temperature. If the reference voltage axis does not change accordingly, it will lead to an excessively high BER (Bit Error Rate), exceeding the decoding capability and causing read failures.

[0023] In this field, related technologies generally use the Fixed Reference Table (FRT) method to solve the above problems. That is, the optimal combination of three reference voltages (FRT1, FRT2, FRT3) is selected in different stages of the Nand Flash life cycle (PE, RT, RD) to generate the FRT table. During the read operation, the reference voltage of the corresponding stage is selected to read the data to improve the success rate.

[0024] However, the relevant technologies have significant shortcomings in the following aspects: (1) Rigid triggering mechanism: The existing scheme is based on fixed interval PE, RT, RD threshold triggering search, which does not fully consider the accelerated impact of dynamic environmental factors such as temperature on the characteristics of storage units. For example, high temperature will significantly shorten the data retention time and lack real-time temperature feedback adjustment. (2) Low search efficiency: The relevant technologies traverse all used blocks (block storage units in the storage medium) and perform full-range voltage scanning on pages 0, 1, and 2 of fixed Wl. When the NandFlash capacity increases or the number of blocks increases, the search time increases linearly, and high error risk areas are not prioritized for search, resulting in a high proportion of invalid scans. (3) Insufficient voltage matching accuracy: The existing scheme does not combine real-time BER data to dynamically adjust the search scheme. The same search offset voltage strategy is used for both low and high BER blocks. (4) Insufficient multi-factor coupling processing: The effects of factors such as PE, RT, RD and temperature on voltage offset are not independent and linear. The existing triggering conditions are only combined by logic AND / or simple combination, without establishing a multi-factor coupling model, which is difficult to adapt to the voltage dynamic adjustment requirements under complex working conditions.

[0025] Based on the technical problems existing in the prior art, this application proposes a method for dynamically obtaining the optimal offset voltage during NAND Flash reads. By introducing real-time temperature monitoring and error rate hierarchical feedback, the trigger conditions are dynamically adjusted and the search strategy is optimized, thereby improving the real-time performance and efficiency of NAND Flash read offset voltage updates.

[0026] The method and apparatus for determining the optimal offset voltage of a flash memory storage medium according to embodiments of this application are described below with reference to the accompanying drawings.

[0027] Figure 1 This is a flowchart of a method for determining the optimal offset voltage of a flash memory storage medium according to an embodiment of this application.

[0028] For example, such as Figure 1 As shown, the method for determining the optimal offset voltage of the flash memory storage medium includes the following steps:

[0029] In step S101, the current number of erase / write operations, current data retention time, current number of read operations, current operating temperature, current bit error rate, and current read operation frequency of the target storage block are obtained.

[0030] The current write / erase count refers to the total number of programming (writing) and erasing operations that the target memory block has undergone since it was put into use. The oxide layer of NAND Flash memory cells is subjected to electrical stress damage during each write / erase process. As the number of write / erase cycles increases, the charge retention capability of the memory cells gradually degrades, leading to increased threshold voltage drift. Therefore, the write / erase count is one of the core indicators for measuring the aging degree of a memory block. This data is typically continuously recorded by a counter inside the flash memory controller and can be read in real time through the firmware interface.

[0031] Furthermore, the current data retention time refers to the length of time that data in the target memory block remains after the last write or refresh. Floating-gate transistors in NAND Flash memory experience charge leakage over time, especially at high temperatures, significantly reducing data retention and leading to increased read error rates. Therefore, data retention time reflects the natural aging effect of memory cells over time. The current data retention time can be calculated using the system real-time clock and the last write timestamp of each block.

[0032] The current read count refers to the cumulative number of read operations performed on the target memory block during the current lifecycle phase. Frequent read operations can cause unexpected electric field interference (i.e., read interference) to adjacent unselected memory cells, leading to a slow change in their charge state and subsequently causing voltage shift. Therefore, the read count is directly related to the dynamic aging caused by usage patterns. In this embodiment, the read count can be statistically analyzed by the read operation monitoring module in the controller and recorded independently by block.

[0033] The current operating temperature refers to the real-time temperature of the NAND Flash chip or its surrounding environment, typically obtained through a temperature sensor integrated into the controller or flash memory package. Temperature is a critical external factor affecting the reliability of NAND Flash: high temperatures accelerate charge leakage, exacerbate oxide layer degradation, and significantly shorten data retention time and erase / write endurance; low temperatures may affect the stability of the read signal. Therefore, real-time temperature is used to dynamically adjust other trigger thresholds, making the system response more closely reflect actual physical changes.

[0034] The current bit error rate (BER) refers to the proportion of erroneous bits detected after decoding with error correction codes, such as LDPC (Low-Density Parity-Check), during data reading from a target storage block, out of the total number of bits read. It is typically expressed as bits per page (Bit / Page). The BER is a direct indicator of the severity of voltage offset in storage cells; a higher BER indicates a worse match between the reference voltage and the current actual threshold voltage, resulting in lower data reliability. The BER value is decoded and reported in real-time by the ECC (Error-Correcting Code) engine during each read operation, exhibiting high dynamism and sensitivity.

[0035] The current read operation frequency refers to the number of read requests for a target memory block per unit of time (e.g., per hour), used to measure the access frequency of that block. A high read frequency means that the block faces more severe read interference effects, resulting in a faster voltage offset rate. This frequency is obtained by periodically counting the number of read operations over a period of time and can be used to identify "hot" blocks, thereby allowing for early adjustment of their voltage calibration strategies.

[0036] In step S102, the erase / write count trigger threshold is determined based on the current operating temperature, the data retention trigger threshold is determined based on the current bit error rate, and the read interference trigger threshold is determined based on the current read operation frequency.

[0037] Specifically, the core logic of this application's embodiment in determining the erase / write cycle trigger threshold based on the current operating temperature lies in compensating for the accelerated aging effect of temperature on NAND Flash. It is understood that high-temperature environments significantly exacerbate damage to the oxide layer of storage cells and charge leakage, resulting in a much higher degree of aging for high-temperature blocks compared to normal-temperature blocks under the same erase / write cycles. Therefore, this application's embodiment introduces a temperature-adaptive PE triggering mechanism. Utilizing a preset temperature influence coefficient, when an increase in the current operating temperature is detected, the PE trigger threshold is actively lowered and the subsequent trigger interval is shortened. For example, at a high temperature of 50°C, the first voltage scan is triggered at PE=500, while at normal temperature (e.g., 25°C), it is triggered only at PE=1000. This strategy of triggering earlier at higher temperatures ensures early intervention under high-stress environments, preventing read failures due to excessively rapid voltage offset accumulation.

[0038] In detail, the core logic of the temperature adaptive PE triggering mechanism in this application embodiment is: high temperature environment will accelerate the aging of Nand Flash (such as faster charge leakage and more significant drift of memory cell characteristics). Therefore, voltage scanning needs to be started at a lower PE value (erasure and write cycles) to avoid read errors caused by excessive voltage deviation.

[0039] In some embodiments, the erase / write cycle trigger threshold is:

[0040] ;

[0041] in, To account for the effect of temperature on the erase / write cycle trigger threshold, As the trigger point, The current operating temperature. The initial erase / write cycles trigger threshold is set at a preset temperature. This is the reduction factor of the current operating temperature on the initial erase / write trigger threshold at the preset temperature. The trigger interval at the preset temperature. This is the reduction factor of the trigger interval at the current operating temperature relative to the preset temperature.

[0042] Therefore, the above formula dynamically adjusts the PE trigger threshold through the temperature coefficient, lowers the trigger threshold in high-temperature environments, and initiates voltage search earlier.

[0043] Optionally, the specific parameter settings in practical applications can be... =1000 (initial trigger PE threshold at room temperature); =500 (trigger interval at room temperature); =-0.02 (temperature reduction factor for the initial threshold); =-0.01 (temperature reduction factor for interval).

[0044] For example, the following provides a comparison of the trigger thresholds when the current temperature is 25°C and 50°C.

[0045] At room temperature (25℃), temp - 25 = 0, and the formula simplifies to: Trigger points (n=0,1,2,...): 1000, 1500, 2000, 2500..., that is, the first trigger occurs when the PE value of the Block reaches 1000, and then it is triggered once every 500 PE values ​​thereafter.

[0046] At a high temperature (50℃): temp - 25 = 25, substituting into the formula: Trigger points (n=0,1,2,...): 500, 875, 1250, 1625..., that is, the first trigger occurs when the PE value of the Block reaches 500, and then it is triggered once every 375 PE values ​​thereafter.

[0047] Comparing the trigger points of 25℃ and 50℃:

[0048] First trigger: PE=1000 is required at 25℃, and only PE=500 is required at 50℃ (threshold reduced by 50%).

[0049] Second trigger: PE=1500 is required at 25℃, and only PE=875 is required at 50℃ (threshold reduced by 42%).

[0050] Subsequent trigger intervals: 500 intervals at 25℃, 375 intervals at 50℃ (intervals shortened by 25%).

[0051] Therefore, the temperature-adaptive PE triggering formula in this application introduces negative temperature coefficients (α, β) to lower the triggering PE threshold and shorten the interval under high temperature conditions, thereby starting voltage scanning when the Block aging degree is lower, achieving "early triggering". This is completely consistent with the physical law that high temperature accelerates the degradation of NAND characteristics, and solves the problem that fixed threshold cannot adapt to temperature changes.

[0052] Furthermore, in this embodiment, the purpose of determining the data retention trigger threshold based on the current bit error rate is to proactively warn of the risk of voltage drift in the storage cell. Data retention time is itself a time-dimensional indicator, but its impact on voltage deviation is directly related to the current bit error rate (BER). When a significant increase in BER is detected in real-time, it indicates that the charge state of the storage cell has become unstable, and data reliability drops sharply. At this point, if the trigger is still waited for at a fixed interval of 10 or 20 days, the optimal calibration opportunity will be missed. Therefore, this embodiment employs an error rate-driven mechanism, using BER as a dynamic adjustment factor. The higher the BER, the shorter the calculated RT trigger threshold (i.e., the maximum allowable retention time). For example, when the BER approaches the error correction limit, the trigger interval can be shortened by 37.5%, enabling scanning to start 50% earlier, thereby completing voltage correction before an error occurs.

[0053] In detail, the core logic of shortening the trigger interval and triggering earlier in the error rate-driven RT triggering mechanism is as follows: when the real-time error rate (BER) of Nand Flash increases, it indicates that the voltage deviation of the storage cell is deteriorating at an accelerated rate. It is necessary to shorten the trigger interval of RT (data retention time) and update the optimal voltage more frequently to avoid the accumulation of errors that lead to unreadable data.

[0054] Furthermore, in some embodiments, the data retention trigger threshold is:

[0055] ;

[0056] in, To retain trigger thresholds for data, As an acceleration factor, The fixed trigger interval (e.g., 10 days) is set at a preset temperature (e.g., room temperature 25℃). The error rate sensitivity coefficient (empirical value 0.5~0.8, 0.5 can be used in this application). This represents the number of real-time error bits in the target storage block (i.e., the number of Block Bit errors monitored in real time). The maximum error correction capability for low-density parity-check code decoding (e.g., 200 Bit / Page).

[0057] Taking specific numerical values ​​as an example (assuming) =10 days =0.5, =200Bit), the data retention adjustment trigger interval based on real-time BER in this application embodiment is shown in Table 1.

[0058] Table 1

[0059]

[0060] As shown in Table 1, for every 50 bits increase in the error rate (accounting for 25%), the trigger interval is shortened by 12.5% ​​to 25%; when the BER is close to the error correction limit (such as 150 bits), the trigger interval is shortened by 37.5% compared to when there are no errors, thus enabling scanning to start 50% earlier.

[0061] For example, in the actual algorithm determination of this application embodiment, the acceleration factor K=2, and the triggering process is as follows:

[0062] (1) The host read process collects the BER value of the block in real time;

[0063] (2) Periodically calculate based on the current BER value ;

[0064] (3) Compare the difference ΔT between the current time and the last scan time. If ΔT If ΔT Then continue monitoring (recalculated every 15 minutes). (Dynamically update the threshold).

[0065] For example: Day 0: BER = 50 Bits =17.5 days (interval allowed 17.5 days);

[0066] Day 10: BER = 150 Bits =12.5 days (remaining allowable interval = 12.5 - 10 = 2.5 days);

[0067] Day 12: ΔT = 12 days < =12.5, continue to wait;

[0068] Day 12.5: ΔT = 12.5 days ≥ =12.5, trigger scan (started 7.5 days (20-12.5) in advance).

[0069] Therefore, through the formula The system implements linear compression intervals, dynamic threshold updates, and proactive fault prevention. For every 1% increase in the error rate, the trigger interval is shortened proportionally (not a fixed threshold); the trigger interval is recalculated every 15 minutes to respond to error fluctuations in real time; and before the BER approaches the error correction limit (e.g., the 80% threshold), scanning is initiated 50% earlier, nipping problems in the bud. This closed-loop mechanism of "the higher the error rate, the more frequent the scanning" better matches the trigger timing with the actual aging state of the NandFlash compared to a fixed interval scheme, achieving precise optimization of "scanning where the risk is high first."

[0070] Furthermore, in this embodiment, the read interference trigger threshold is determined based on the current read operation frequency to address the premature failure of hotspot blocks. Frequent reading of the same block generates continuous read interference to its adjacent cells, accelerating their voltage shift. However, the globally average read load cannot reflect individual differences. This embodiment identifies high-load "hotspot" blocks by comparing the current read operation frequency of the target block with the globally average frequency, and dynamically compresses their RD trigger threshold based on the load sensitivity coefficient. For example, when the read frequency of a block reaches twice the peak load of the globally average, its trigger interval can be shortened by 30% compared to normal load, enabling scanning to start 30% earlier. This "scan where the load is high first" strategy avoids ineffective scanning of low-load blocks, precisely allocating limited system resources to the highest-risk areas.

[0071] In detail, in the load-balanced driven RD (read interference) triggering mechanism, the core logic of shortening the trigger interval and triggering earlier is: when the read operation frequency (load) of a certain block of NandFlash is significantly higher than the global average, it indicates that the charge disturbance of the block is aggravated due to frequent reading, and the voltage offset rate is accelerated. It is necessary to dynamically shorten the RD trigger interval and calibrate the voltage more intensively to prevent read error outbreaks.

[0072] Furthermore, in some embodiments, the read interference trigger threshold is:

[0073] ;

[0074] in, The threshold for triggering read interference. The initial read interference trigger interval (e.g., 5000 reads). For load sensitivity coefficient, This represents the current read operation frequency of the Block (times / hour). This represents the global average read operation frequency. Set the maximum load threshold preset for the system (e.g., twice the global average).

[0075] Taking specific numerical values ​​as an example (assuming) =5000 times, =100 times / hour =200 times / hour =0.6), the read interference adjustment trigger interval for Block read load is shown in Table 2.

[0076] Table 2

[0077]

[0078] As shown in Table 2, for every 50 reads (25%) that the global average is exceeded, the trigger interval is shortened by 15%; under peak load, the trigger interval is shortened by 30% compared to normal load, enabling scanning to start 30% earlier.

[0079] For example, the actual load balancing RD triggering process in this application embodiment is as follows:

[0080] (1) Real-time statistics: Count the number of reads of each block every hour (through the read counter of the Nand controller).

[0081] (2) Formula calculation: Calculated based on the current load. ;

[0082] (3) Number Comparison: Compare the difference (ΔRD) between the current total number of reads (RD_total) and the number of reads since the last scan (RD_last); if ΔRD ≥ If ΔRD < Continue monitoring (recalculated every 1000 reads) ).

[0083] For example: Scan 0: RD_last=0, load=100 scans / hour =5000;

[0084] 3000th read: load = 180 reads / hour =3800, ΔRD=3000<3800, no trigger;

[0085] 3800th read: ΔRD=3800≥3800, trigger scan (started 1200 times (5000-3800) in advance).

[0086] Through formula The system implements dynamic threshold compression, precise hotspot detection, and proactive fault prevention. The higher the load, the shorter the trigger interval (not a fixed threshold); accelerated scanning is only applied to blocks with read frequencies exceeding the average, avoiding indiscriminate global scanning; and calibration is initiated 30% in advance before read interference causes voltage deviation to run away (e.g., when the number of reads reaches the 80% threshold). This "scan where the load is high first" strategy, compared to a fixed interval scheme, better matches the trigger timing with the actual aging state of the NandFlash, truly achieving the optimal goals of on-demand scanning and high energy efficiency.

[0087] In step S103, based on the current number of erase / write operations, the erase / write operation trigger threshold, the current data retention time, the data retention trigger threshold, the current number of read operations, and the read interference trigger threshold, it is determined whether the target memory block meets the preset offset voltage determination condition according to the current bit error rate.

[0088] Further, in some embodiments, based on the current erase / write count, erase / write count trigger threshold, current data retention time, data retention trigger threshold, current read count, and read interference trigger threshold, the target storage block is determined to meet the preset offset voltage determination condition according to the current bit error rate. This includes: determining whether the current erase / write count is greater than or equal to the erase / write count trigger threshold, or whether the current data retention time is greater than or equal to the data retention trigger threshold, or whether the current read count is greater than or equal to the read interference trigger threshold; if the current erase / write count is greater than or equal to the erase / write count trigger threshold, or the current data retention time is greater than or equal to the data retention trigger threshold, or the current read count is greater than or equal to the read interference trigger threshold, determining whether the current bit error rate is greater than or equal to the preset bit error rate threshold; if the current bit error rate is greater than or equal to the preset bit error rate threshold, then the target storage block is determined to meet the preset offset voltage determination condition.

[0089] The preset bit error rate threshold can be 100, and no specific limit is specified here.

[0090] Specifically, this application embodiment evaluates the current number of erase / write operations, the current data retention time, and the current number of read operations of the target storage block in real time, and compares them with the erase / write trigger threshold, data retention trigger threshold, and read interference trigger threshold dynamically calculated based on real-time temperature, error rate, and read load, respectively. When any one of these indicators reaches or exceeds its corresponding dynamic threshold, i.e., the current number of erase / write operations is greater than or equal to the erase / write trigger threshold, or the current data retention time is greater than or equal to the data retention trigger threshold, or the current number of read operations is greater than or equal to the read interference trigger threshold, it indicates that the storage block has entered a potential risk area in a certain dimension, and further checks whether the current bit error rate of the storage block is greater than or equal to a preset bit error rate threshold.

[0091] In other words, even if a storage block reaches the trigger point in terms of erase, write, retain, or read cycles, if its actual read error rate remains low, it indicates that its voltage offset is still within a controllable range, and there is no need to immediately perform a full-range voltage scan, thus avoiding a large number of invalid and inefficient operations. Only when a storage block not only reaches the trigger condition of a certain aging dimension, but its BER also reaches a high-risk level (BER ≥ preset threshold), is the target storage block ultimately determined to meet the preset offset voltage determination condition, and the subsequent offset voltage scan process needs to be initiated.

[0092] Therefore, by linking the trigger thresholds of three aging dimensions—write / erase cycles, data retention time, and read interference—with the real-time bit error rate, accurate identification of voltage offset risks is achieved. This effectively avoids unnecessary voltage search operations under low-risk conditions, significantly reduces system overhead, and greatly improves the overall operating efficiency and resource utilization of storage devices while ensuring data read reliability.

[0093] Furthermore, in some embodiments, after determining whether the current erase / write count is greater than or equal to the erase / write count trigger threshold, or whether the current data retention time is greater than or equal to the data retention trigger threshold, or whether the current read count is greater than or equal to the read interference trigger threshold, the method further includes: if the current erase / write count is less than the erase / write count trigger threshold, the current data retention time is less than the data retention trigger threshold, and the current read count is less than the read interference trigger threshold, then re-execute the step of obtaining the current erase / write count, current data retention time, current read count, current operating temperature, current bit error rate, and current read operation frequency of the target storage block.

[0094] Specifically, when the current state of the target storage block (i.e., the current number of erase / write operations, the current data retention time, and the current number of read operations) is below its respective dynamic trigger threshold (erase / write trigger threshold, data retention trigger threshold, and read interference trigger threshold), it indicates that the storage block has not yet reached the warning level requiring voltage scanning in the three main aging dimensions of PE, RT, and RD. Therefore, there is no need to proceed with the subsequent BER risk confirmation and voltage scanning process. Instead, the initial data acquisition steps are immediately re-executed, i.e., all real-time parameters of the target storage block, such as the current number of erase / write operations, the current data retention time, the current number of read operations, the current operating temperature, the current bit error rate, and the current read operation frequency, are re-acquired. This re-execution constitutes a continuously running monitoring loop. The execution frequency of this loop is not fixed but can be optimized according to system load and design requirements. For example, it can be recalculated every 1000 reads or every 15 minutes, automatically refreshing the perception of the storage block's state.

[0095] This avoids misjudgments caused by single sampling errors when the system state changes rapidly, ensuring the accuracy and timeliness of voltage calibration trigger decisions. At the same time, the time-consuming voltage search process is only initiated when truly needed, effectively reducing invalid operations, improving system resource utilization and overall operating efficiency, and achieving refined and adaptive management of NAND Flash aging risks.

[0096] Furthermore, in some embodiments, after determining whether the current bit error rate is greater than or equal to a preset bit error rate threshold, the method further includes: if the current bit error rate is less than the preset bit error rate threshold, then determining that the target memory block does not meet the preset offset voltage determination condition, and re-executing the steps of obtaining the current erase / write count, current data retention time, current read count, current operating temperature, current bit error rate, and current read operation frequency of the target memory block.

[0097] Specifically, if the current bit error rate is detected to be less than the preset bit error rate threshold at this stage, it means that although the storage block has met the triggering conditions in a certain aging dimension, its actual data reading performance is still stable and the error level is within an acceptable low-risk range.

[0098] At this point, the system determines that the target storage block does not meet the preset offset voltage determination conditions, thereby avoiding the immediate execution of a time-consuming and bandwidth-intensive full-range offset voltage scan. This prevents the system from performing unnecessary voltage searches on storage blocks that meet the parameters but have good actual performance, thus significantly reducing invalid operations, lowering the computing load and overall power consumption of the main control chip, and improving the overall performance and response speed of the SSD.

[0099] After determining that the current bit error rate is less than the preset bit error rate threshold, the data acquisition step is repeated to obtain all key parameters, including the current bit error rate, ensuring the continuity of the monitoring loop. Since the state of the storage block evolves dynamically, continuous and high-frequency data refresh allows for real-time tracking of BER trends.

[0100] In step S104, if the target memory block meets the preset offset voltage determination conditions, an offset voltage scan is performed on the target memory block to obtain the offset voltage scan result, and the current optimal offset voltage is determined based on the offset voltage scan result.

[0101] Further, in some embodiments, an offset voltage scan is performed on the target memory block to obtain the offset voltage scan result, and the current optimal offset voltage is determined based on the offset voltage scan result, including: reading the target page data in the target memory block under multiple candidate reference voltages to obtain the target page data corresponding to a portion of the candidate reference voltages; determining the total number of error bits corresponding to the portion of the candidate reference voltages based on the target page data corresponding to the portion of the candidate reference voltages; and taking the candidate reference voltage with the smallest total number of error bits in the total number of error bits set corresponding to the portion of the candidate reference voltages as the current optimal offset voltage of the target memory block.

[0102] Specifically, firstly, under a set of preset candidate reference voltages, specific target pages in the target memory block are read. These candidate reference voltages are typically derived from a reference voltage candidate table pre-loaded into DDR memory, covering multiple offset points within a certain range above and below the standard reference voltage. To balance search accuracy and execution efficiency, the system does not scan all data pages of the entire block, but instead selects specific pages (such as pages 0, 1, and 2) on a representative fixed word line (Wl) as target pages. By reading these target pages under different candidate voltages, the target page data corresponding to some of the candidate reference voltages can be obtained.

[0103] Furthermore, the target page data read at each candidate reference voltage is analyzed. Specifically, error correction code engines such as LDPC are used to decode the read data, and the total number of error bits generated at that voltage is counted. Through this process, a set of total error bits corresponding to the candidate reference voltages participating in the test can be established, that is, the number of read errors caused by each test voltage point.

[0104] Finally, the total number of error bits is analyzed to select the candidate reference voltage with the smallest total number of error bits. This voltage point with the fewest errors is the reference voltage that most accurately matches the actual threshold voltage of the memory cell under the current physical conditions. Therefore, it is determined as the current optimal offset voltage for the target memory block.

[0105] Therefore, this decision logic directly optimizes the reading error rate, ensuring the scientific validity and effectiveness of the selected voltage, effectively suppressing voltage deviations caused by factors such as PE, RT, RD and temperature, and guaranteeing high reliability of data reading.

[0106] Furthermore, in some embodiments, after taking the candidate reference voltage with the smallest total number of error bits in the set of error bits corresponding to a subset of candidate reference voltages as the current optimal offset voltage of the target memory block, the method further includes: storing the current optimal offset voltage in the voltage configuration information table of the target memory block.

[0107] Specifically, after testing multiple candidate reference voltages and selecting the optimal offset voltage with the minimum number of error bits, this voltage is written to a specially maintained Block voltage information table stored in DDR memory. This table maintains one record for each memory block or its representative area (such as a Word Line) to store its current optimal offset voltage configuration. By updating the corresponding target memory block entry in this table with the newly determined optimal voltage, subsequent read operations on that memory block can directly use the latest data in the voltage configuration information table to quickly select the most suitable reference voltage for reading. This avoids the overhead of performing a complex voltage search for each read, greatly improving read performance.

[0108] Therefore, the optimal offset voltage determination method for flash memory storage media according to the embodiments of this application proposes a dynamic adjustment formula for triggering conditions that integrates temperature, error rate, and load, thereby achieving real-time optimization of the triggering threshold, solving the problem of existing fixed-interval triggering being out of sync with actual operating conditions, and establishing a Block error rate mapping table, i.e., an error rate hierarchical pre-screening mechanism, to divide Blocks into high and low risk levels, and only perform voltage search on high-risk BER blocks, thereby achieving accurate allocation of search resources and improving voltage search update efficiency.

[0109] To enable those skilled in the art to understand more clearly and intuitively the method for determining the optimal offset voltage of the flash memory storage medium proposed in this application, a detailed description is provided below in conjunction with specific embodiments.

[0110] The method for obtaining the optimal offset voltage of Nand Flash based on dynamic parameter adaptation and error rate feedback includes the following steps:

[0111] Step 1, in the initialization phase: Load the reference voltage candidate table into DDR, establish the Block error rate mapping table, and preset the PE / RT / RD basic thresholds, temperature / error rate / load impact coefficients, and BER risk classification standards (high risk ≥100, low risk <100).

[0112] Step 2, Real-time monitoring: Continuously acquire the Block's PE (erasure / write count), RT (data retention time), RD (read count), temperature, BER (error rate), and read frequency.

[0113] Step 3, Dynamic Threshold Calculation: The trigger threshold is calculated based on three optimization formulas: the PE trigger value is adaptively adjusted according to temperature, the RT trigger interval is compressed according to BER, and the RD trigger interval is shortened according to read load.

[0114] Step 4, Trigger Condition Determination: Calculate the temperature adaptive PE trigger value and determine whether the current Block PE has been reached. ; Calculate the RT trigger interval based on the current BER, and determine whether the RT has been reached. ;Calculate the RD trigger interval based on Block load and determine whether the RD has been reached. If any triggering condition is met and the Block is considered high-risk, then a voltage search is initiated.

[0115] Step 5, Voltage Search: Record the reading information of specific Wlpage0, 1, and 2, and select the voltage with the smallest number of errors as the optimal value based on the BER.

[0116] Step 6, Result Storage: Update the optimal voltage offset value of each block to the DDR block voltage information table, and repeat Step 2.

[0117] The following is combined with Figure 2 The method for determining the optimal offset voltage of the flash memory storage medium in this application is described in detail.

[0118] like Figure 2 As shown, the optimal offset voltage determination method for the flash memory storage medium in this embodiment includes initialization parameters, real-time data acquisition, calculation of trigger threshold, determination of trigger conditions, determination of risk level, voltage scanning and optimal value selection, and updating and looping.

[0119] The parameter initialization step aims to set basic parameters, including the PE start threshold (PE_start=1000), PE interval (PE_brp=500), temperature influence coefficient (α=-0.02, β=-0.01); RT base interval (t_brp_ret=10d), error rate influence factor (γ=0.5), error correction limit (ber_limit=200); RD base interval (RD_brp_rd=5000), load adjustment coefficient (δ=0.6), average read frequency (load_avg=100); and BER risk threshold (high risk ≥100, low risk <100), etc.

[0120] The real-time data acquisition steps aim to continuously collect key parameters of the block, including erase / write count (PE value), data retention time (RT duration), read count (RD count), current temperature (temp), real-time error rate (BER), and read operation frequency (load).

[0121] The steps for calculating the trigger threshold are based on three optimized formulas to calculate the trigger conditions:

[0122] Temperature-adaptive PE trigger value: The PE trigger threshold is dynamically adjusted based on the current temperature (the higher the temperature, the lower the threshold, and the earlier the trigger).

[0123] Error rate-driven RT trigger value: Adjust the RT interval based on the real-time BER (the higher the BER, the shorter the interval, and the faster the triggering).

[0124] Load balancing RD trigger value: The RD interval is adjusted based on the difference between the reading frequency and the average load (the higher the load, the shorter the interval, and the higher the priority of triggering).

[0125] The steps for determining the trigger conditions include: if the PE value of the Block is greater than or equal to the PE trigger value, or the RT duration is greater than or equal to the RT trigger value, or the RD count is greater than or equal to the RD trigger value, proceed to risk assessment; otherwise, return to continue collecting data.

[0126] The steps for determining the risk level include: if BER ≥ 100 (high risk), proceed to the voltage scanning process; if BER < 100 (low risk), return to continue collecting data.

[0127] The voltage scanning and optimal value selection steps include: traversing the sample voltages, reading page 0 / 1 / 2 of the fixed Wl interval in each block, recording the number of error bits corresponding to each voltage, and selecting the voltage with the fewest errors as the optimal offset voltage.

[0128] The update and loop steps include: writing the optimal voltage into the DDR's Block information table, returning to the real-time acquisition stage, continuously monitoring and dynamically updating, forming a closed loop.

[0129] Therefore, this application achieves deep coupling between triggering conditions and real-time operating conditions through temperature-adaptive PE triggering, error rate-driven RT triggering, and load-balanced RD triggering. This improves the timeliness of voltage updates by 30%-50% under high-temperature, high-error-rate, and high-load scenarios, enhances the dynamic adaptability of the triggering mechanism, and effectively reduces the read failure rate caused by voltage deviation. Combined with error rate-based pre-screening, the effective search rate for high-risk blocks is increased to over 80%, and the overall search time is reduced by 40%-60%, significantly improving search efficiency, especially in high-capacity NAND Flash scenarios. Through mathematical models, the coupling effects of multiple factors such as PE, RT, RD, and temperature on voltage deviation are effectively handled, significantly improving the ability to adapt to complex operating conditions and further enhancing the universality of NAND flash memory from different manufacturers and models, thereby strengthening the ability to handle multi-factor coupling.

[0130] The optimal offset voltage determination method for flash memory storage media proposed in this application determines a data retention trigger threshold based on the current bit error rate of the target storage block and a read interference trigger threshold based on the current read operation frequency. Based on the current erase / write count, erase / write count trigger threshold, current data retention duration, data retention trigger threshold, current read count, and read interference trigger threshold, when the target storage block meets the preset offset voltage determination conditions, an offset voltage scan is performed on the target storage block, and the current optimal offset voltage is determined based on the offset voltage scan results. This solves the problem in related technologies where the fixed lookup table method, due to its rigid trigger mechanism and low search efficiency, cannot adapt to changes in temperature, error rate, and load in real time, leading to insufficient read voltage matching accuracy and increased error rate. Through a dynamic adaptive triggering and error rate feedback mechanism, the search efficiency and real-time performance of the optimal offset voltage are significantly improved, effectively reducing the read error rate.

[0131] Next, with reference to the accompanying drawings, an optimal offset voltage determination device for a flash memory storage medium according to an embodiment of this application is described.

[0132] Figure 3 This is a block diagram of an optimal offset voltage determination device for a flash memory storage medium according to an embodiment of this application.

[0133] like Figure 3 As shown, the optimal offset voltage determination device 10 for the flash memory storage medium includes: an acquisition module 100, a threshold determination module 200, a judgment module 300, and an optimal offset voltage determination module 400.

[0134] The module includes: an acquisition module 100, used to acquire the current number of erase / write operations, current data retention time, current number of read operations, current operating temperature, current bit error rate, and current read operation frequency of the target storage block; a threshold determination module 200, used to determine the erase / write trigger threshold based on the current operating temperature, the data retention trigger threshold based on the current bit error rate, and the read interference trigger threshold based on the current read operation frequency; a judgment module 300, used to determine whether the target storage block meets the preset offset voltage determination conditions based on the current number of erase / write operations, the erase / write trigger threshold, the current data retention time, the data retention trigger threshold, the current number of read operations, and the read interference trigger threshold, and the current bit error rate; and an optimal offset voltage determination module 400, used to perform an offset voltage scan on the target storage block if it meets the preset offset voltage determination conditions, obtain the offset voltage scan result, and determine the current optimal offset voltage based on the offset voltage scan result.

[0135] Furthermore, in some embodiments, the erase / write cycle trigger threshold is:

[0136] ;

[0137] in, The threshold is triggered by the number of erase / write cycles. As the trigger point, The current operating temperature. The initial erase / write cycles trigger threshold is set at a preset temperature. This is the reduction factor of the current operating temperature on the initial erase / write trigger threshold at the preset temperature. The trigger interval at the preset temperature. This is the reduction factor of the trigger interval at the current operating temperature relative to the preset temperature.

[0138] Furthermore, in some embodiments, the data retention trigger threshold is:

[0139] ;

[0140] in, To retain trigger thresholds for data, As an acceleration factor, A fixed trigger interval at a preset temperature. The error rate sensitivity coefficient. The number of real-time error bits in the target memory block. This represents the maximum error correction capability for low-density parity-check code decoding.

[0141] Furthermore, in some embodiments, the read interference trigger threshold is:

[0142] ;

[0143] in, The threshold for triggering read interference. This is the initial read interference trigger interval. For load sensitivity coefficient, This represents the current read operation frequency. This represents the global average read operation frequency. The maximum load threshold preset for the system.

[0144] Furthermore, in some embodiments, the optimal offset voltage determination module 400 is configured to: read target page data in the target memory block under multiple candidate reference voltages to obtain target page data corresponding to a portion of the candidate reference voltages; determine the total number of error bits corresponding to the portion of the candidate reference voltages based on the target page data corresponding to the portion of the candidate reference voltages; and take the candidate reference voltage with the smallest total number of error bits in the total number of error bits set corresponding to the portion of the candidate reference voltages as the current optimal offset voltage of the target memory block.

[0145] Furthermore, in some embodiments, after taking the candidate reference voltage with the smallest total number of error bits in the set of error bits corresponding to some candidate reference voltages as the current optimal offset voltage of the target memory block, the optimal offset voltage determination module 400 is further configured to: store the current optimal offset voltage in the voltage configuration information table of the target memory block.

[0146] Further, in some embodiments, the determination module 300 is used to: determine whether the current erase / write count is greater than or equal to the erase / write count trigger threshold, or whether the current data retention time is greater than or equal to the data retention trigger threshold, or whether the current read count is greater than or equal to the read interference trigger threshold; if the current erase / write count is greater than or equal to the erase / write count trigger threshold, or the current data retention time is greater than or equal to the data retention trigger threshold, or the current read count is greater than or equal to the read interference trigger threshold, determine whether the current bit error rate is greater than or equal to a preset bit error rate threshold; if the current bit error rate is greater than or equal to the preset bit error rate threshold, then determine that the target memory block meets the preset offset voltage determination condition.

[0147] Furthermore, in some embodiments, after determining whether the current erase / write count is greater than or equal to the erase / write count trigger threshold, or whether the current data retention time is greater than or equal to the data retention trigger threshold, or whether the current read count is greater than or equal to the read interference trigger threshold, the determination module 300 is further configured to: re-execute the steps of obtaining the current erase / write count, current data retention time, current read count, current operating temperature, current bit error rate, and current read operation frequency of the target storage block when the current erase / write count is less than the erase / write count trigger threshold, the current data retention time is less than the data retention trigger threshold, and the current read count is less than the read interference trigger threshold.

[0148] Furthermore, in some embodiments, after determining whether the current bit error rate is greater than or equal to a preset bit error rate threshold, the determination module 300 is further configured to: if the current bit error rate is less than the preset bit error rate threshold, determine that the target storage block does not meet the preset offset voltage determination condition, and re-execute the steps of obtaining the current erase / write count, current data retention time, current read count, current operating temperature, current bit error rate, and current read operation frequency of the target storage block.

[0149] It should be noted that the explanation of the above-described embodiment of the optimal offset voltage determination method for flash memory storage media also applies to the optimal offset voltage determination device for flash memory storage media in this embodiment, and will not be repeated here.

[0150] The optimal offset voltage determination device for flash memory storage media proposed in this application determines a data retention trigger threshold based on the current bit error rate of the target storage block and a read interference trigger threshold based on the current read operation frequency. Based on the current erase / write count, erase / write count trigger threshold, current data retention duration, data retention trigger threshold, current read count, and read interference trigger threshold, when the target storage block meets the preset offset voltage determination conditions, an offset voltage scan is performed on the target storage block, and the current optimal offset voltage is determined based on the offset voltage scan results. This solves the problem in related technologies where the fixed lookup table method, due to its rigid trigger mechanism and low search efficiency, cannot adapt to changes in temperature, error rate, and load in real time, leading to insufficient read voltage matching accuracy and increased error rate. Through a dynamic adaptive triggering and error rate feedback mechanism, the search efficiency and real-time performance of the optimal offset voltage are significantly improved, effectively reducing the read error rate.

[0151] Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device may include:

[0152] The memory 401, the processor 402, and the computer program stored on the memory 401 and capable of running on the processor 402.

[0153] When the processor 402 executes the program, it implements the optimal offset voltage determination method for the flash memory storage medium provided in the above embodiments.

[0154] Furthermore, electronic devices also include:

[0155] Communication interface 403 is used for communication between memory 401 and processor 402.

[0156] The memory 401 is used to store computer programs that can run on the processor 402.

[0157] The memory 401 may include high-speed RAM (Random Access Memory) memory, and may also include non-volatile memory, such as at least one disk storage.

[0158] If the memory 401, processor 402, and communication interface 403 are implemented independently, then the communication interface 403, memory 401, and processor 402 can be interconnected via a bus to complete communication between them. The bus can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 4 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0159] Optionally, in a specific implementation, if the memory 401, processor 402, and communication interface 403 are integrated on a single chip, then the memory 401, processor 402, and communication interface 403 can communicate with each other through an internal interface.

[0160] Processor 402 may be a CPU (Central Processing Unit), an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of this application.

[0161] This application also provides a non-volatile computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the above-described method for determining the optimal offset voltage of a flash memory storage medium.

[0162] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method for determining the optimal offset voltage of a flash memory storage medium.

[0163] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0164] The above provides a detailed description of a method for determining the optimal offset voltage of a flash memory storage medium. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for determining the optimal offset voltage of a flash memory storage medium, characterized in that, Includes the following steps: Obtain the current erase / write count, current data retention time, current read count, current operating temperature, current bit error rate, and current read operation frequency of the target storage block; The erase / write cycle trigger threshold is determined based on the current operating temperature, the data retention trigger threshold is determined based on the current bit error rate, and the read interference trigger threshold is determined based on the current read operation frequency. Based on the current number of erase / write operations, the erase / write operation trigger threshold, the current data retention time, the data retention trigger threshold, the current number of read operations, and the read interference trigger threshold, the target storage block is determined to meet the preset offset voltage determination condition according to the current bit error rate. If the current bit error rate is less than the preset bit error rate threshold, the target storage block is determined not to meet the preset offset voltage determination condition. If the target memory block meets the preset offset voltage determination condition, then an offset voltage scan is performed on the target memory block to obtain the offset voltage scan result, and the current optimal offset voltage is determined based on the offset voltage scan result; The erase / write trigger threshold is as follows: ； in, The erase / write count trigger threshold, As the trigger point, The current operating temperature. The initial erase / write cycles trigger threshold is set at a preset temperature. This is the reduction factor of the current operating temperature on the initial erase / write trigger threshold at the preset temperature. The trigger interval at the preset temperature. This is the reduction factor of the trigger interval at the current operating temperature relative to the preset temperature; The data retention trigger threshold is: ； in, Reserve a trigger threshold for the data. As an acceleration factor, A fixed trigger interval at a preset temperature. The error rate sensitivity coefficient. The number of real-time error bits in the target storage block. This represents the maximum error correction capability for low-density parity-check code decoding. The read interference trigger threshold is: ； in, The read interference trigger threshold is... This is the initial read interference trigger interval. For load sensitivity coefficient, This represents the current read operation frequency. This represents the global average read operation frequency. The maximum load threshold preset for the system; The step of determining whether the target storage block meets the preset offset voltage determination condition based on the current erase / write count, the erase / write count trigger threshold, the current data retention time, the data retention trigger threshold, the current read count, and the read interference trigger threshold, according to the current bit error rate, includes: determining whether the current erase / write count is greater than or equal to the erase / write count trigger threshold, or whether the current data retention time is greater than or equal to the data retention trigger threshold, or whether the current read count is greater than or equal to the read interference trigger threshold; if the current erase / write count is greater than or equal to the erase / write count trigger threshold, or the current data retention time is greater than or equal to the data retention trigger threshold, or the current read count is greater than or equal to the read interference trigger threshold, determining whether the current bit error rate is greater than or equal to a preset bit error rate threshold; if the current bit error rate is greater than or equal to the preset bit error rate threshold, then determining that the target storage block meets the preset offset voltage determination condition.

2. The method according to claim 1, characterized in that, The step of performing an offset voltage scan on the target memory block, obtaining the offset voltage scan result, and determining the current optimal offset voltage based on the offset voltage scan result includes: The target page data corresponding to a portion of the candidate reference voltages is obtained by reading the target page data in the target memory block under multiple candidate reference voltages respectively. Determine the total number of error bits corresponding to the partial candidate reference voltages based on the target page data corresponding to the partial candidate reference voltages; The candidate reference voltage with the smallest total number of error bits in the set of candidate reference voltages is taken as the current optimal offset voltage of the target memory block.

3. The method according to claim 2, characterized in that, After selecting the candidate reference voltage with the smallest total number of error bits from the set of candidate reference voltages as the current optimal offset voltage for the target memory block, the method further includes: The current optimal offset voltage is stored in the voltage configuration information table of the target storage block.

4. The method according to claim 1, characterized in that, After determining whether the current erase / write count is greater than or equal to the erase / write count trigger threshold, or whether the current data retention time is greater than or equal to the data retention trigger threshold, or whether the current read count is greater than or equal to the read interference trigger threshold, the method further includes: If the current number of erase / write operations is less than the erase / write trigger threshold, the current data retention time is less than the data retention trigger threshold, and the current number of read operations is less than the read interference trigger threshold, then the steps of obtaining the current number of erase / write operations, current data retention time, current number of read operations, current operating temperature, current bit error rate, and current read operation frequency of the target storage block are re-executed.

5. The method according to claim 1, characterized in that, After determining whether the current bit error rate is greater than or equal to a preset bit error rate threshold, the method further includes: If the current bit error rate is less than the preset bit error rate threshold, the target memory block is determined not to meet the preset offset voltage determination condition, and the steps of obtaining the current erase / write count, current data retention time, current read count, current operating temperature, current bit error rate, and current read operation frequency of the target memory block are re-executed.

6. An electronic device, characterized in that, include: A memory, a processor, and a computer program stored on the memory and executable on the processor, the processor executing the computer program to implement the optimal offset voltage determination method for a flash memory storage medium as described in any one of claims 1-5.

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