Memory management method and storage device

Abstract

The application provides a memory management method and a memory device. The method comprises: detecting a target operation event, wherein the target operation event indicates that a target operation is performed on a target word line; in response to the target operation event, determining that the target word line is located in a target management area in a plurality of management areas, wherein the plurality of management areas are vertically distributed in a memory module according to respective electrical characteristics; from a plurality of management tables, determining a target management table corresponding to the target management area; adjusting a reference electrical parameter according to the target management table; and performing the target operation on the target word line according to the adjusted reference electrical parameter. Thus, the operation performance and / or operation stability of the memory device can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory, in particular to a memory management method and a storage device. BACKGROUND

[0002] As the current mainstream non-volatile storage medium, NAND Flash is widely used in solid state drives (SSD), embedded multimedia controllers (eMMC), universal flash storage (UFS), U disks and various portable multimedia devices due to its high read / write speed, good shock resistance and low power consumption.

[0003] In recent years, with the continuous evolution of semiconductor manufacturing processes, especially the rapid development of 3D NAND technology, the storage density of NAND Flash has been continuously improved, and the number of layers has rapidly expanded from the early 32 layers and 64 layers to the current mainstream 128 layers and above.

[0004] In the 3D NAND architecture with high stack layer number, due to the complexity of the device structure and process limitations, the coupling effect between word lines (WL) is significantly enhanced, especially in the physical edge area of the array (i.e. the topmost and bottommost word lines), the word line disturbance presents a non-linear growth trend. This interference effect directly affects the charge stability of the storage unit, and thus causes the raw bit error rate (RBER) to increase significantly. SUMMARY

[0005] The present application provides a memory management method and a storage device, which can improve the above-mentioned problems and improve the operation performance and / or operation stability of the storage device.

[0006] Embodiments of the present application provide a memory management method for a storage device, the storage device comprising a memory module, the memory module comprising a plurality of word lines, and the memory management method comprising: detecting a target operation event, wherein the target operation event indicates that a target operation is performed on a target word line in the plurality of word lines; in response to the target operation event, determining that the target word line is located in a target management area in a plurality of management areas, wherein the plurality of management areas are vertically distributed in the memory module according to respective electrical characteristics; from a plurality of management tables, determining a target management table corresponding to the target management area; adjusting a reference electrical parameter according to the target management table; and performing the target operation on the target word line according to the adjusted reference electrical parameter.

[0007] Embodiments of the present disclosure provide a memory device. The memory device includes a connection interface, a memory module, and a memory controller. The connection interface is configured to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory module includes a plurality of word lines. The memory controller is configured to: detect a target operation event, wherein the target operation event indicates a target operation performed on a target word line of the plurality of word lines; in response to the target operation event, determine that the target word line is located in a target management zone of a plurality of management zones, wherein the plurality of management zones are vertically distributed in the memory module according to respective electrical characteristics; determine, from a plurality of management tables, a target management table corresponding to the target management zone; adjust a baseline electrical parameter according to the target management table; and perform the target operation on the target word line according to the adjusted baseline electrical parameter.

[0008] Based on the above, after detecting a target operation event indicating a target operation performed on a target word line, in response to the target operation event, it is determined that the target word line is located in a target management zone of a plurality of management zones, and a target management table corresponding to the target management zone is determined. In particular, the plurality of management zones are vertically distributed in the memory module according to respective electrical characteristics. Then, according to the target management table, a baseline electrical parameter is adjusted, and the adjusted baseline electrical parameter is used to perform the target operation on the target word line. In this way, the operation performance and / or operation stability of the memory device can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a schematic diagram of a data storage system according to embodiments of the present disclosure;

[0010] Figure 2 is a schematic diagram of a memory controller according to embodiments of the present disclosure;

[0011] Figure 3 is a schematic diagram of a management memory module according to embodiments of the present disclosure;

[0012] Figure 4 is a schematic diagram of a management memory module according to embodiments of the present disclosure;

[0013] Figures 5 to 8 is a schematic diagram of a management zone division according to embodiments of the present disclosure;

[0014] Figure 9 is a schematic diagram of a sub-management zone cut from a management zone according to embodiments of the present disclosure;

[0015] Figure 10 is a flowchart of a memory management method according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0016] Reference will now be made to the exemplary embodiments of the present application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0017] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present application. Please refer to Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 is connectable to the host system 11 and is operable to store data from the host system 11. For example, the host system 11 can be a smartphone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a computer system installed in a specific carrier (e.g., a vehicle, an aircraft, or a ship), and the type of the host system 11 is not limited thereto. In addition, the storage device 12 can include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0018] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 can support an embedded Multi-Media Card (eMMC), a Universal Flash Storage (UFS), a Peripheral Component Interconnect Express (PCI Express), a Non-Volatile Memory Express (NVM express), a Serial Advanced Technology Attachment (SATA), a Universal Serial Bus (USB), or other types of connection interface standards. Thus, the storage device 12 can communicate (e.g., exchange signals, instructions, and / or data) with the host system 11 via the connection interface 121.

[0019] The memory module 122 is used to store data. For example, the memory module 122 can include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module can include one or more arrays of memory cells. A memory cell in an array of memory cells stores data in the form of a voltage, also referred to as a threshold voltage. For example, the memory module 122 can include a Single Level Cell (SLC) NAND-type flash memory module, a Multi Level Cell (MLC) NAND-type flash memory module, a Triple Level Cell (TLC) NAND-type flash memory module, a Quad Level Cell (QLC) NAND-type flash memory module, and / or other memory modules having the same or similar characteristics.

[0020] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be considered as a control core of the storage device 12 and is used to control the storage device 12. For example, the memory controller 123 can be used to control or manage the overall or partial operation of the storage device 12. For example, the memory controller 123 can include a Central Processing Unit (CPU), or other programmable general purpose or special purpose microprocessors, Digital Signal Processors (DSPs), programmable controllers, Application Specific Integrated Circuits (ASICs), Programmable Logic Devices (PLDs), or other similar devices, or a combination of such devices. In an embodiment, the memory controller 123 can include a flash memory controller.

[0021] The memory controller 123 can send a sequence of instructions to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a sequence of write instructions to the memory module 122 to instruct the memory module 122 to store data into specific memory cells. For example, the memory controller 123 can send a sequence of read instructions to the memory module 122 to instruct the memory module 122 to read data from specific memory cells. For example, the memory controller 123 can send a sequence of erase instructions to the memory module 122 to instruct the memory module 122 to erase data stored in specific memory cells. In addition, the memory controller 123 can send other types of sequences of instructions to the memory module 122 to instruct the memory module 122 to perform other types of operations, without limitation. The memory module 122 can receive the sequences of instructions from the memory controller 123 and access the memory cells within the memory module 122 according to the sequences of instructions.

[0022] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present application. Please refer to Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0023] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 can be used to control or manage the overall or partial operation of the memory controller 123. For example, the memory control circuit 23 can communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 can include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0024] In an embodiment, the memory controller 123 can further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and used to buffer data. For example, the buffer memory 24 can be used to buffer instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0025] In one embodiment, the memory controller 123 can further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to perform encoding and decoding on data to ensure the correctness of the data. For example, the decoding circuit 25 can support various encoding / decoding algorithms such as Low Density Parity Check (LDPC) code, BCH code, Reed-solomon code (RS code), Exclusive OR (XOR) code, etc. In one embodiment, the memory controller 123 can further include other types of various circuit modules (such as power management circuit, etc.), which are not limited by the present application.

[0026] Figure 3 is a schematic diagram of managing a memory module according to an embodiment of the present application. Please refer to Figures 1 to 3 The memory module 122 includes a plurality of physical units 301(1)~301(B). Each physical unit includes a plurality of memory cells and is used to store data non-volatilily.

[0027] In one embodiment, one physical unit can include one physical programming unit. In one embodiment, the physical programming unit is also referred to as a physical programming unit. In one embodiment, one physical programming unit can be regarded as one physical page.

[0028] In one embodiment, one physical programming unit can include a plurality of physical sectors. For example, the data capacity of one physical sector can be 512 Bytes (B), and one physical programming unit can include 32 physical sectors. However, the data capacity of one physical sector and / or the total number of physical sectors included in one physical programming unit can be adjusted according to practical needs, which are not limited by the present application. For example, the storage capacity of one physical programming unit can be 16 kilobytes, and the present application is not limited thereto.

[0029] In one embodiment, one physical programming unit is the minimum unit of synchronously writing data in the memory module 122. For example, when performing a programming operation (also referred to as a write operation) on one physical programming unit to write data to the physical programming unit, a plurality of memory cells in the physical programming unit can be programmed synchronously to store corresponding data. For example, when programming one physical programming unit, a write voltage can be applied to the physical programming unit to change the threshold voltage of at least part of the memory cells in the physical programming unit. For example, the threshold voltage of one memory cell can reflect the bit data stored in the memory cell.

[0030] In one embodiment, one physical erase unit can include a plurality of physical programming units. In one embodiment, one physical erase unit can be considered as one physical block.

[0031] In one embodiment, the plurality of physical programming units in one physical erase unit can be erased synchronously. For example, when an erase operation is performed on one physical erase unit, an erase voltage can be applied to the plurality of physical programming units in the physical erase unit to change the threshold voltage of at least some of the storage cells in the physical programming units. By performing an erase operation on one physical erase unit, the data stored in the physical erase unit can be cleared.

[0032] In one embodiment, the memory control circuit 23 can logically associate the physical units 301(1)-301(A) and 301(A+1)-301(B) to the data area 31 and the free area 32, respectively. The physical units 301(1)-301(A) in the data area 31 all store data (also referred to as user data) from the host system 11. For example, any of the physical units in the data area 31 can store valid data and / or invalid data. In addition, the physical units 301(A+1)-301(B) in the free area 32 all do not store data (e.g., valid data).

[0033] In one embodiment, if a physical unit does not store valid data, the physical unit can be associated to the free area 32. In addition, the physical unit in the free area 32 can be erased to clear the data in the physical unit. In one embodiment, the physical unit in the free area 32 is also referred to as a free physical unit. In one embodiment, the free area 32 is also referred to as a free pool.

[0034] In one embodiment, when data is to be stored, the memory control circuit 23 can select one or more physical units from the free area 32 and instruct the memory module 122 to store the data in the selected physical units. After the data is stored in the physical units, the physical units can be associated to the data area 31. In other words, one or more physical units can be alternately used between the data area 31 and the free area 32.

[0035] In one embodiment, the memory control circuit 23 can configure a plurality of logical units 302(1)-302(C) to map the physical units (i.e., the physical units 301(1)-301(A)) in the data area 31. For example, one logical unit can correspond to one logical block address (LBA) or other logical management unit. One logical unit can be mapped to one or more physical units.

[0036] In one embodiment, if a certain physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in the physical unit includes valid data. Conversely, if a certain physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that the physical unit currently does not store any valid data.

[0037] In one embodiment, the memory control circuit 23 can record the mapping relationship between the logical units and the physical units in at least one management table (also referred to as a logical-to-physical mapping table). In one embodiment, the memory control circuit 23 can instruct the memory module 122 to perform data read, write, or erase operations, etc. according to the information in the management table (i.e., the logical-to-physical mapping table).

[0038] In one embodiment, the memory module 122 includes a three-dimensional (3D) stacked memory module. The 3D stacked memory module can include 128 layers, 256 layers, 512 layers, or other number of word line layers stacked in a vertical direction. Each word line layer includes a plurality of word lines. Each word line can include a plurality of memory cells. In addition, the plurality of memory cells on each word line can form one or more physical program units.

[0039] In one embodiment, the plurality of word line layers in the memory module 122 are stacked in a vertical direction by a bonding process. For example, the bonding process refers to a process in semiconductor manufacturing in which two or more memory chips are stacked in a vertical direction to form a 3D stacked memory module. Thus, by the bonding process, the number of stacked layers of word line layers can be increased, thereby increasing the amount of stored data per unit area (i.e., data storage density) of the memory module 122.

[0040] It should be noted that as the number of stacked layers increases, the bonding process, while increasing the data storage density, also causes serious side effects. One of the obvious side effects is the increase in interlayer interference, i.e., the discontinuity of the electrical properties between layers at the bonding interface and the appearance of new interface trap states. If these defects are not specifically improved, the operation performance of the entire 3D stacked memory module will be lower than expected in the long run.

[0041] The 'electrical properties' of the present application refer to parameters and phenomena that affect the electrical performance of memory cells during operation, which mainly include but are not limited to: threshold voltage (Vt) and its distribution width of memory cells, strength of random telegraph noise (RTN), size of punch-through leakage current, and decay rate of data retention, etc. The differences in these properties are mainly caused by the non-uniformity of the manufacturing process in three-dimensional space.

[0042] Therefore, the memory management method and the storage device provided by the embodiments of the present application can perform grouping management on the word lines in the memory module in the vertical direction based on the specially configured management table, so as to satisfy the electrical defect compensation for the word lines with different electrical characteristics (for example, different process defects). In this way, the overall operation performance and / or operation stability of the storage device can be effectively improved. Each management table includes, but is not limited to, the following fields: management area identifier, voltage compensation value, voltage step precision, temperature compensation coefficient, wear adjustment parameter, and the like.

[0043] Figure 4 is a schematic diagram of managing a memory module according to an embodiment of the present application. Please refer to Figure 4 In an embodiment, it is assumed that the memory module 122 includes a three-dimensional stacked structure 40. In the three-dimensional stacked structure 40, there are multiple word line layers stacked in the vertical direction (i.e., the Z-axis direction) and each word line layer includes multiple word lines. For example, the total number of these word line layers stacked in the vertical direction (i.e., the Z-axis direction) can be 128, 256, 512, or other numbers, depending on practical requirements.

[0044] In an embodiment, the memory control circuit 23 can divide multiple management areas 41(1)~41(D) in the three-dimensional stacked structure 40. Each of the management areas 41(1)~41(D) covers a part of the word lines in the three-dimensional stacked structure 40. In particular, the management areas 41(1)~41(D) can be vertically distributed in the memory module 122 in the vertical direction (i.e., the Z-axis direction) according to their respective electrical characteristics. For example, in the vertical direction (i.e., the Z-axis direction), a word line in the three-dimensional stacked structure 40 can be located in the management area 41(i) (also referred to as the first management area), and another word line in the three-dimensional stacked structure 40 can be located in the management area 41(j) (also referred to as the second management area). i and j are integers between 1 and D, and i is different from j.

[0045] In a three-dimensional stacked memory, due to the non-uniformity of the bonding process and the etching process, there are significant differences in electrical characteristics of the word lines in different regions. If a unified management strategy is adopted, it will cause the operation voltage to be mismatched, thereby causing problems such as an increase in read / write error rate, a decrease in data retention capability, and the like. To solve this problem, the present application divides the memory module into a bonding interface region, a bonding transition region, an etching variation region, and a center stable region, each of which corresponds to different process defect characteristics. Through this division method, differentiated voltage management and compensation strategies can be implemented for the electrical characteristic defects of different regions, thereby significantly improving the operation stability and data reliability of the memory.

[0046] In one embodiment, after dividing the management areas 41(1)~41(D) in the vertical direction (i.e. Z-axis direction), the memory control circuit 23 can configure a plurality of management tables 401(1)~401(D) according to the electrical characteristics of the management areas 41(1)~41(D) respectively. Meanwhile, the memory control circuit 23 can associate the management tables 401(1)~401(D) to the management areas 41(1)~41(D) respectively. For example, the memory control circuit 23 can associate the management tables 401(1)~401(D) to the management areas 41(1)~41(D) one-to-one respectively. The management table 401(i) (also referred to as the first management table) can match the electrical characteristics (also referred to as the first electrical characteristics) of the management area 41(i). The management table 401(j) (also referred to as the second management table) can match the electrical characteristics (also referred to as the second electrical characteristics) of the management area 41(j).

[0047] After configuring the management tables 401(1)~401(D), the memory control circuit 23 can manage the management areas 41(1)~41(D) according to the management tables 401(1)~401(D) respectively. For example, the memory control circuit 23 can manage (including operating) the word lines in the management area 41(i) according to the management table 401(i). Alternatively, the memory control circuit 23 can manage (including operating) the word lines in the management area 41(j) according to the management table 401(j).

[0048] In one embodiment, the management table (e.g. 401(i)) can be a data structure, and the fields recorded therein can include but are not limited to: management area identifier, reference read voltage, voltage offset, voltage step precision adjustment coefficient, temperature compensation coefficient, wear level compensation mapping table, etc.

[0049] After the memory control circuit 23 finds the corresponding management table according to the target management area, the memory control circuit 23 can calculate the final applied operating voltage according to the following formula (or logic):

[0050] Final operating voltage = reference operating voltage + voltage offset + temperature compensation value + wear compensation value

[0051] Wherein, the reference operating voltage is a standard value for the entire memory module; the voltage offset is a fixed compensation value preset by the management table for the characteristics of the core management area; the temperature compensation value and the wear compensation value are dynamic compensation values obtained from the management table mapping according to the real-time detected temperature information and wear level information.

[0052] In this way, the management table not only provides static compensation parameters, but also provides dynamic compensation rules, making the voltage adjustment strategy more precise and adaptive.

[0053] In one embodiment, by analyzing the electrical characteristics of each word line layer in the 3D stack structure 40 and referring to the process techniques such as the bonding process and the plasma etching process applied to the memory module 122, the memory control circuit 23 can divide the management regions 41(1)~41(D) in the 3D stack structure 40. For example, the management regions 41(1)~41(D) can include a Bonding Interface Region (BIR), a Deck Bonding Transition Region (DBTR), a Physical Deck Edge Region (PDER), and a Deck Center Region (DCR). That is, each of the management regions 41(1)~41(D) can be one of the Bonding Interface Region (BIR), the Deck Bonding Transition Region (DBTR), the Physical Deck Edge Region (PDER), and the Deck Center Region (DCR). It should be noted that the type of at least one of the management regions 41(1)~41(D) can also be adjusted according to practical needs as the process techniques used vary, without being limited to these types.

[0054] In one embodiment, in the 3D stack structure 40, the management regions 41(1)~41(D) can have the following characteristics:

[0055] (1) The word lines in the Bonding Interface Region (BIR) have more significant interface bonding process defects than other word lines.

[0056] (2) The word lines in the Physical Deck Edge Region (PDER) have more significant plasma etching process defects than other word lines.

[0057] (3) The word lines in the Deck Center Region (DCR) have the most stable electrical characteristics than other word lines.

[0058] (4) The electrical characteristics of the word lines in the Deck Bonding Transition Region (DBTR) gradually change according to the word line position.

[0059] For the above characteristic (1), due to physical discontinuity and interface traps generated during the manufacturing process, the electrical characteristics of the word lines in the Bonding Interface Region (BIR) are extremely unstable, which is the largest disturbance source in the entire 3D stack structure 40. The programming and reading behaviors of the word lines in this region are very susceptible to the influence of surrounding word lines, resulting in a significant increase in the raw bit error rate (RBER). Therefore, during operation, the word lines in the Bonding Interface Region (BIR) require the most aggressive voltage compensation and / or optimization strategies.

[0060] For the above characteristic (2), the word lines in the etch variation region (PDER) are usually located at the top and bottom of each stack. Due to the non-uniformity of plasma etching at the physical edges, the physical structures of these word lines usually have slight variations. Compared to the bond interface region (BIR), although the word lines in the etch variation region (PDER) have relatively slight interference, their unstable electrical characteristics also affect the charge retention capability and data integrity of the word lines. Therefore, during operation, the word lines in the etch variation region (PDER) still need to be compensated for the deviation of the electrical characteristics by adjusting the read or program voltage, etc.

[0061] For the above characteristic (3), the word lines in the center stable region (DCR) are relatively far away from the chip edge and the bond interface, and are usually located at or near the center of the three-dimensional stack structure 40. Therefore, the word lines in the center stable region (DCR) have the most uniform and stable physical and electrical characteristics, and are subject to the least interference. In an embodiment, the overall management strategy for the three-dimensional stack structure 40 is mainly a management strategy (e.g., a standard voltage value) for the center stable region (DCR) that is biased or designed differently.

[0062] For the above characteristic (4), the word lines in the bond transition region (DBTR) are generally located between the bond interface region (BIR) and the center stable region (DCR). Therefore, the electrical characteristics of the word lines in the bond transition region (DBTR) generally show a gradual change according to their word line positions. For example, in the bond transition region (DBTR), the closer the word line is to the bond interface region (BIR), the worse the electrical characteristics are, and the greater the voltage compensation required. Conversely, the closer the word line is to the center stable region (DCR) (i.e., the farther away from the bond interface region (BIR)), the more stable the electrical characteristics are, and the smaller the voltage compensation required. However, the above characteristics are only an overview, and one or more of the above characteristics can change in different applications.

[0063] In the following embodiments of Figures 5 to 8 , different types, different models, and / or memory modules 122 manufactured using different semiconductor processes are shown in various possible management region division manners.

[0064] Figure 5 is a schematic diagram of the management region division according to an embodiment of the present application. Please refer to Figure 5In an embodiment, the memory module 122 is assumed to include a three-dimensional stacked structure 50. In the vertical direction (i.e. Z-axis direction) of the three-dimensional stacked structure 50, a bonding interface region (BIR) 501 is located at the center of the stack of the three-dimensional stacked structure 50, and configuration combinations 51 and 52 are located above and below the bonding interface region (BIR) 501, respectively.

[0065] The configuration combination 51 includes a bonding transition region (DBTR) 511, a center stable region (DCR) 512, and a etching variation region (PDER) 513. The configuration combination 52 includes a bonding transition region (DBTR) 521, a center stable region (DCR) 522, and a etching variation region (PDER) 523. In addition, the etching variation region (PDER) 513 can be located at or connected to the top of the three-dimensional stacked structure 50, and the etching variation region (PDER) 523 can be located at or connected to the bottom of the three-dimensional stacked structure 50.

[0066] Taking a 138-layer vertical stack structure as an example, in the vertical direction (i.e. Z-axis direction) of the three-dimensional stacked structure 50, the etching variation region (PDER) 523 can include the 3rd-7th word line layers; the center stable region (DCR) 522 can include the 20th-59th word line layers; the bonding transition region (DBTR) 521 can include the 60th-63rd word line layers; the bonding interface region (BIR) 501 can include the 64th-67th word line layers and the 70th-73rd word line layers; the bonding transition region (DBTR) 511 can include the 74th-77th word line layers; the center stable region (DCR) 512 can include the 80th-133rd word line layers; and the etching variation region (PDER) 513 can include the 134th-137th word line layers. It should be noted that the actual configuration and / or the word line layers covered by each management region in the three-dimensional stacked structure 50 can also be adjusted according to actual needs.

[0067] In a multi-layer stack structure, the distribution positions of different process defect regions vary due to manufacturing processes, and if the stack configurations cannot be flexibly adapted to multiple stack configurations, the application range of the management method will be limited. Therefore, the present application supports multiple vertical distribution configurations of management regions, such as combining the bonding transition region, the center stable region, and the etching variation region above, below, or other relative positions of the bonding interface region. Through this flexible configuration, the present application can be applied to three-dimensional stacked memories of different numbers of layers and different process nodes, enhancing the versatility and practicality of the method.

[0068] Figure 6 is a schematic diagram of the division of management regions according to an embodiment of the present application. Please refer to Figure 6In an embodiment, assume that the memory module 122 comprises a three-dimensional stacked structure 60. In the vertical direction (i.e., the Z-axis direction) of the three-dimensional stacked structure 60, a bonding interface region (BIR) 601 is located at or connected to the top of the three-dimensional stacked structure 60, and a configuration combination 61 is located below the bonding interface region (BIR) 601.

[0069] The configuration combination 61 comprises a bonding transition region (DBTR) 611, a center stable region (DCR) 612, and a etching variation region (PDER) 613. In addition, the etching variation region (PDER) 613 can be located at or connected to the bottom of the three-dimensional stacked structure 60.

[0070] For example, in a 147-layer vertical stacked structure, in the vertical direction (i.e., the Z-axis direction) of the three-dimensional stacked structure 60, the etching variation region (PDER) 613 can comprise the 0th-2nd word line layers; the center stable region (DCR) 612 can comprise the 3rd-129th word line layers; the bonding transition region (DBTR) 611 can comprise the 130th-139th word line layers; and the bonding interface region (BIR) 601 can comprise the 140th-146th word line layers. It should be noted that the actual configuration manner and / or the covered word line layers of each management region in the three-dimensional stacked structure 60 can also be adjusted according to actual needs.

[0071] Figure 7 is a schematic diagram of the management region division according to an embodiment of the present application. Please refer to Figure 7 In an embodiment, assume that the memory module 122 comprises a three-dimensional stacked structure 70. In the vertical direction (i.e., the Z-axis direction) of the three-dimensional stacked structure 70, a center stable region (DCR) 701 is located at the stacking center of the three-dimensional stacked structure 70, and configuration combinations 71 and 72 are located above and below the center stable region (DCR) 701, respectively.

[0072] The configuration combination 71 comprises an etching variation region (PDER) 711, a bonding transition region (DBTR) 712, and a bonding interface region (BIR) 713. The configuration combination 72 comprises an etching variation region (PDER) 721, a bonding transition region (DBTR) 722, and a bonding interface region (BIR) 723. In addition, the bonding interface region (BIR) 713 can be located at or connected to the top of the three-dimensional stacked structure 70, and the bonding interface region (BIR) 723 can be located at or connected to the bottom of the three-dimensional stacked structure 70.

[0073] As an example, for a 184-tier vertically stacked structure, in the vertical direction (i.e., Z-axis direction) of the three-dimensional stacked structure 70, the bonding interface region (BIR) 723 can include the 0th-3rd tiers of word lines; the bonding transition region (DBTR) 722 can include the 4th-10th tiers of word lines; the etch variation region (PDER) 721 can include the 11th-15th tiers of word lines; the center stable region (DCR) 701 can include the 16th-167th tiers of word lines; the etch variation region (PDER) 711 can include the 168th-172nd tiers of word lines; the bonding transition region (DBTR) 712 can include the 173rd-179th tiers of word lines; and the bonding interface region (BIR) 713 can include the 180th-183rd tiers of word lines. It is noted that the actual configuration and / or the tiers of word lines covered by each management region in the three-dimensional stacked structure 70 can be adjusted according to practical needs.

[0074] Figure 8 is a schematic diagram of management region division according to an embodiment of the present application. Please refer to Figure 8 In an embodiment, it is assumed that the memory module 122 includes a three-dimensional stacked structure 80. In the vertical direction (i.e., Z-axis direction) of the three-dimensional stacked structure 80, between any two bonding interface regions (BIRs), there is a configuration combination including a center stable region (DCR), an etch variation region (PDER), and a bonding transition region (DBTR).

[0075] Specifically, in the vertical direction (i.e., Z-axis direction) of the three-dimensional stacked structure 80 (or the memory module 122), from top (top) to bottom (bottom), there are, in sequence, a bonding interface region (BIR) 801, a configuration combination 81, a bonding interface region (BIR) 802, a configuration combination 82, a bonding interface region (BIR) 803, a configuration combination 83, and a bonding interface region (BIR) 804.

[0076] The configuration combination 81 includes a center stable region (DCR) 811, an etch variation region (PDER) 812, and a bonding transition region (DBTR) 813. The configuration combination 82 includes a center stable region (DCR) 821, an etch variation region (PDER) 822, and a bonding transition region (DBTR) 823. The configuration combination 83 includes a center stable region (DCR) 831, an etch variation region (PDER) 832, and a bonding transition region (DBTR) 833. In addition, the bonding interface region (BIR) 801 can be located at or connected to the top of the three-dimensional stacked structure 80, and the bonding interface region (BIR) 804 can be located at or connected to the bottom of the three-dimensional stacked structure 80. It is noted that the actual configuration and / or the tiers of word lines covered by each management region in the three-dimensional stacked structure 80 can be adjusted according to practical needs.

[0077] Please refer back to Figure 4In one embodiment, the memory control circuit 23 can perform noise detection across word line layers for at least some of the word lines in the three-dimensional stack structure 40 to determine and / or adjust the partitioning range of at least one of the management zones 41(1)~41(D). For example, such noise detection can include telegraph noise detection or other types of noise detection to meet the electrical defect characterization of one or more types of management zones.

[0078] In one embodiment, the electrical defects at the bonding interface region (BIR) are mainly affected by random telegraph noise. Random telegraph noise is a phenomenon caused by a single or a few interface traps, characterized by random jumps in voltage between two or more discrete energy levels.

[0079] In one embodiment, the partitioning of the plurality of management zones is based on electrical characterization results of a plurality of word lines. The electrical characterization includes random telegraph noise detection and / or threshold voltage distribution detection.

[0080] In one embodiment, the memory control circuit 23 can detect random telegraph noise in the three-dimensional stack structure 40 and accurately find the word line layer range affected by the bonding process based on the detection results. Then, the memory control circuit 23 can label the word lines located in this word line layer range as belonging to the bonding interface region (BIR). In one embodiment, after initially determining some word lines (or word line layers) to be located in the bonding interface region (BIR), the memory control circuit 23 can further determine or fine-tune the boundary of this bonding interface region (BIR) through the aforementioned random telegraph noise detection method.

[0081] In one embodiment, the memory control circuit 23 can obtain the threshold voltage distributions of at least some of the word lines in the three-dimensional stack structure 40. The memory control circuit 23 can estimate, based on the threshold voltage distributions, whether the threshold voltage distributions of the some of the word lines have the electrical defect characteristics of a particular type of management zone. For example, if the threshold voltage distributions of certain word lines are concentrated and narrow (i.e., the threshold voltage distributions of these word lines satisfy a first distribution condition), the memory control circuit 23 can designate these word lines (or a word line layer containing these word lines) as belonging to a DCR. For example, the first distribution condition can include that the standard deviation of the threshold voltage distribution of a word line is less than a preset value (also referred to as a first threshold value, such as 15% or another ratio). Alternatively, if the threshold voltage distributions of certain word lines are abnormally wide due to etching variation (i.e., the threshold voltage distributions of these word lines satisfy a second distribution condition), the memory control circuit 23 can designate these word lines (or a word line layer containing these word lines) as belonging to a PDER or a BIR. For example, the second distribution condition can include that the standard deviation of the threshold voltage distribution of a word line is greater than a preset value (also referred to as a second threshold value, such as 15% or another ratio). In addition, the foregoing distribution conditions for the threshold voltage can be increased or adjusted according to actual needs to satisfy the grouping needs of the management zones 41(1) to 41(D).

[0082] In one embodiment, after the preliminary grouping designation of the management zones 41(1) to 41(D), the memory control circuit 23 can also determine whether the grouping of the word lines located at the boundary positions of at least some of the management zones is correct or can be adjusted based on whether the threshold voltage distributions of these word lines satisfy a particular distribution condition. For example, after the preliminary grouping designation of the management zones 41(1) to 41(D), if a word line located at the boundary position of a PDER is initially determined to belong to the PDER, but the threshold voltage distribution of this word line satisfies the foregoing first distribution condition (e.g., the threshold voltage distribution of this word line is concentrated and narrow), the memory control circuit 23 can re-designate this word line as belonging to a DCR. Alternatively, after the preliminary grouping designation of the management zones 41(1) to 41(D), if a word line located at the boundary position of a DCR is initially determined to belong to the DCR, but the threshold voltage distribution of this word line satisfies the foregoing second distribution condition (e.g., the threshold voltage distribution of this word line is abnormally wide), the memory control circuit 23 can re-designate this word line as belonging to a PDER. In one embodiment, the memory control circuit 23 can also detect and / or fine-tune the word line designation and / or grouping of the management zones 41(1) to 41(D) in other manners, which are not described herein.

[0083] In one embodiment, the management regions 41(1)~41(D) can also include a dummy word line region. The word lines in the dummy word line region are not used for storing user data. The main function of the dummy word line region and the word lines therein is to assist the operation of the surrounding or neighboring word lines. For example, by specially controlling the voltage of the word lines in the dummy word line region, the operation stability can be improved when operating (e.g. reading, writing or erasing data) the surrounding or neighboring word lines. In one embodiment, the dummy word line region can also be used to isolate word lines in the stack structure that are too close to each other and are likely to interfere with each other.

[0084] In one embodiment, when a read operation is needed for a word line in the bonding interface region (BIR) adjacent to the dummy word line region, the memory control circuit 23 first determines the required read voltage (e.g. 4.5V) according to the management table of the bonding interface region. Subsequently, the controller applies a voltage (e.g. a fixed ratio value, 4.5V) associated with the read voltage to the word lines in the dummy word line region, instead of a fixed Vpass voltage. In this way, the adjacent interference can be more effectively shielded, and the accuracy of the read operation can be improved.

[0085] In high speed or high precision operations, the capacitive coupling and interference between adjacent word lines can cause the operation voltage to fluctuate, affecting the accuracy of data reading and writing. To suppress the interference, the present application introduces a dummy word line region, which does not store user data, but by applying a fixed voltage or a voltage associated with the adjacent region, it plays a role in shielding or stabilizing the voltage. In this way, the interference between word lines can be effectively reduced, and the operation stability of the adjacent storage region can be improved.

[0086] In one embodiment, the dummy word line region can be located at the outermost side (e.g. at the top and / or bottom) or relatively outer side of the management regions 41(1)~41(D). In one embodiment, the dummy word line region can also be interleaved between or adjacent to any two specific types of management regions according to practical needs, which is not limited by the present application.

[0087] In one embodiment, the voltage applied to the dummy word line region can always be a fixed voltage. In one embodiment, the voltage applied to the dummy word line region can also change in association with the voltage applied to any adjacent management region. For example, when the voltage applied to a certain management region adjacent to a certain dummy word line region changes, this change can be reflected in the dummy word line region, so that the subsequent voltage applied to the dummy word line region also changes correspondingly. In this way, the operation assistance capability of the dummy word line region to the adjacent management region can be optimized.

[0088] ​If the voltage of the dummy word line region is fixed, it can not effectively cope with the interference caused by the voltage change of the adjacent region. To solve this problem, the present application supports the voltage of the dummy word line region to change in conjunction with the voltage of the adjacent management region. In this way, the operating state change of the adjacent region can be responded to in real time, providing more accurate voltage shielding effect, and further improving the operating stability.

[0089] In an embodiment, the memory control circuit 23 can further divide one management region into a plurality of management regions (also referred to as sub-management regions). For example, when the originally divided single management region causes the single management table to be insufficient to completely reflect the plurality of electrical characteristics within the management region due to special reasons, the memory control circuit 23 can further divide the management region into a plurality of sub-management regions. Then, the memory control circuit 23 can configure a plurality of management tables (also referred to as sub-management tables) to manage the sub-management regions. For example, the sub-management tables can correspond to the sub-management regions, respectively.

[0090] In an embodiment, the memory control circuit 23 can determine whether a plurality of electrical characteristics exist in the originally divided single management region. In response to a plurality of electrical characteristics existing in the originally divided single management region, the memory control circuit 23 can divide the management region into a plurality of sub-management regions. However, if the originally divided single management region remains to have only a single electrical characteristic, the memory control circuit 23 can not perform the division operation of the sub-management regions on the management region.

[0091] Figure 9 is a schematic diagram showing the division of a sub-management region from a management region according to an embodiment of the present application. Please refer to Figure 9 , the management region 91 can be any one of the management regions 41(1)~41(D) in Figure 4 In an embodiment, in response to a plurality of electrical characteristics existing in the management region 91, the memory control circuit 23 can divide the management region 91 into a plurality of sub-management regions 92(1)~92(E). The sub-management regions 92(1)~92(E) can have a plurality of electrical characteristics, respectively. Then, the memory control circuit 23 can configure sub-management tables 901(1)~901(E) to manage the sub-management regions 92(1)~92(E), respectively.

[0092] In an embodiment, assuming that a plurality of electrical characteristics F(1)~F(E) exist in the management region 91, the sub-management regions 92(1)~92(E) can correspond to the electrical characteristics F(1)~F(E), respectively. Among them, the sub-management region 92(k) can correspond to the electrical characteristic F(k), and k is an integer between 1 and E. Then, the memory control circuit 23 can manage the sub-management region 92(k) according to the sub-management region 92(k). In this way, even if the electrical characteristics of part of the management regions change during the operation of the storage device 12, the configuration of each management region can be dynamically adjusted according to the current demand.

[0093] In one embodiment, the memory control circuit 23 can detect at least one of wear level information, temperature information, and model information of the memory module 122. The wear level information can reflect a wear level of the memory module 122. For example, the wear level information can include a wear level value. The wear level value can reflect a wear level (or an average wear level) of at least a portion of the management area in the memory module 122. For example, as the usage time, the usage number, and / or the usage frequency of the memory module 122 increases, the wear level of the memory module 122 can correspondingly increase. The temperature information can reflect a temperature of the memory module 122. For example, the temperature information can be obtained by a temperature sensor disposed inside the storage device 12. The model information can reflect a brand, a model, and / or a version of the memory module 122.

[0094] In one embodiment, the memory control circuit 23 can adjust the word line coverage of at least one of the management areas 41(1)~41(D) according to at least one of the wear level information, the temperature information, and the model information of the memory module 122. For example, in response to a change in at least one of the wear level information, the temperature information, and the model information of the memory module 122, the memory control circuit 23 can expand the word line coverage of the management area 41(i) (e.g., include a portion of the word lines originally not belonging to the management area 41(i) into the management area 41(i)) or reduce the word line coverage of the management area 41(i) (e.g., exclude a portion of the word lines adjacent to other management areas from the management area 41(i)).

[0095] As the usage time of the memory increases or the ambient temperature changes, the electrical characteristics of the word lines can drift, and the original management area division can no longer be applicable. To solve this problem, the present application supports dynamically adjusting the word line coverage of the management area according to the wear level, the temperature, the model, and the like. In this way, the actual state of the memory can be adapted in real time, and the effectiveness and accuracy of the management strategy can be maintained.

[0096] In detail, regarding the above-mentioned "dynamic adjustment", examples of the triggering condition of the adjustment and the adjustment range, for example, the memory control circuit 23 can periodically detect the program / erase (P / E) cycles of the memory module 122. When the average P / E cycles of a certain management area (e.g., the bonding interface region BIR) exceed a preset threshold (e.g., 1000 times), it is determined that the wear level of the management area increases. At this time, the memory control circuit 23 can adjust the read voltage offset recorded in the management table corresponding to the management area from +50mV to +70mV according to a preset algorithm to compensate for the decrease in charge retention ability due to wear.

[0097] For another example, when the temperature sensor detects that the temperature of the memory module 122 increases from 25°C to 70°C, the memory control circuit 23 can query the temperature compensation mapping table in the management table, and apply a compensation value of -20mV to all the program verification voltages of the management zones to offset the influence of high temperature on the threshold voltage of the transistor.

[0098] The above-mentioned embodiment of numerical or logical is used to illustrate the above-mentioned "dynamic adjustment", and the specific implementation means of the trigger condition and the adjustment range of the adjustment support.

[0099] In an embodiment, in response to at least one of the wear level information, the temperature information, and the model information of the memory module 122 changing, the memory control circuit 23 can also change the total number of the divided management zones 41(1)~41(D). For example, changing the total number of the divided management zones 41(1)~41(D) can include adding a new management zone to the management zones 41(1)~41(D), removing a certain management zone from the management zones 41(1)~41(D), or merging any two adjacent management zones in the management zones 41(1)~41(D) into a single management zone, and the like.

[0100] In an embodiment, the memory control circuit 23 can also adjust the recorded content of at least one of the management tables 401(1)~401(D) according to at least one of the wear level information, the temperature information, and the model information of the memory module 122. For example, in response to at least one of the wear level information, the temperature information, and the model information of the memory module 122 changing, the memory control circuit 23 can correspondingly update or adjust the recorded content of at least one of the management tables 401(1)~401(D). The recorded content of the adjusted management table can be closer to the electrical characteristics of the current management zones. For example, the above-mentioned operation of updating or adjusting the recorded content of at least one of the management tables 401(1)~401(D) can include changing the adjustment parameters recorded in at least one of the management tables 401(1)~401(D).

[0101] The electrical characteristics of the memory can change with the use process and environmental factors, and if the management table content is fixed and unchanged, it will not be able to adapt to the actual operation requirements. Therefore, the present application can dynamically adjust the voltage parameters or other compensation values in the management table according to the wear, temperature, model, and other information. In this way, it can be ensured that the management table always reflects the current memory state, and the accuracy of voltage compensation and the operation reliability are improved.

[0102] Based on the above, even if the state of the storage device 12 itself or the environmental state changes, the management efficiency of the memory module 122 and / or the operation stability of the memory module 122 can be maintained or even improved through dynamic updating of the management zones and / or the management tables.

[0103] In one embodiment, the memory control circuit 23 can manage at least one of the read voltage, the read through (bypass) voltage, the program voltage, the program verify voltage, the erase voltage, the erase verify voltage, and the pre-program voltage (also referred to as first electrical parameters) applied to the management area 41(i) according to the management table 401(i). In addition, the memory control circuit 23 can manage at least one of the read voltage, the read through voltage, the program voltage, the program verify voltage, the erase voltage, the erase verify voltage, and the pre-program voltage (also referred to as second electrical parameters) applied to the management area 41(j) according to the management table 401(j). It is noted that the first electrical parameters and / or the second electrical parameters can also include other types of electrical parameters, which are not limited by the present application. Thus, the performance and / or stability of using these electrical parameters to operate each of the management areas 41(1)~41(D) can be improved.

[0104] Different management areas have different electrical characteristics, and thus require different optimal operating voltages (e.g., read voltage, program voltage, erase voltage, etc.). If uniform voltage parameters are used, it will result in low operating efficiency or high error rate for some areas. Therefore, the present application configures an independent management table for each management area to record the required voltage parameters, thereby achieving targeted voltage compensation. This approach can optimize the operating voltages of each area and improve the overall read / write performance and data retention capability.

[0105] In one embodiment, after dividing the management areas 41(1)~41(D), the memory control circuit 23 can detect an operation event (also referred to as a target operation event) for at least one word line (also referred to as a target word line) in the memory module 122. For example, the target operation event can be a read event, a write event, or an erase event for the target word line. The read event indicates reading data from the target word line (i.e., reading the data stored in the target word line). The write event indicates writing data to the target word line. The erase event indicates erasing the data stored in the target word line.

[0106] In one embodiment, in response to the target operation event, the memory control circuit 23 can determine that the target word line is located in a particular management area (also referred to as a target management area) among the management areas 41(1)~41(D). For example, the target management area can be the management area 41(i) or the management area 41(j). The management areas 41(i) and 41(j) can be any two management areas among the management areas 41(1)~41(D).

[0107] In one embodiment, if the target word line is located in the management zone 41(i) (i.e., the target management zone is the management zone 41(i)), the memory control circuit 23 can perform an operation (also referred to as a target operation) corresponding to a target operation event on the target word line based on a certain electrical parameter (i.e., a first electrical parameter). In particular, the first electrical parameter can match an electrical characteristic (i.e., a first electrical characteristic) of the management zone 41(i). For example, the target operation can be a read operation, a write operation, or an erase operation on the target word line. The read operation is used to read data from the target word line (i.e., read data stored in the target word line). The write operation is used to write data to the target word line. The erase operation is used to erase data stored in the target word line.

[0108] On the other hand, if the target word line is located in the management zone 41(j) (i.e., the target management zone is the management zone 41(j)), the memory control circuit 23 can perform the aforementioned target operation on the target word line based on a certain electrical parameter (i.e., a second electrical parameter). In particular, the second electrical parameter can match an electrical characteristic (also referred to as a second electrical characteristic) of the management zone 41(j). It is noted that the management zones 41(i) and 41(j) are located at different positions in the vertical direction of the memory module 122, and thus the electrical characteristic of the management zone 41(i) can be different from the electrical characteristic of the management zone 41(j).

[0109] In one embodiment, the difference between the first electrical parameter and the second electrical parameter is used to compensate for the difference between the first electrical characteristic and the second electrical characteristic. For example, the read voltage (i.e., the first electrical parameter) used in the read operation (i.e., the target operation) performed on a certain word line (also referred to as a first word line) in the management zone 41(i) can be different from the read voltage (i.e., the second electrical parameter) used in the read operation (i.e., the target operation) performed on a certain word line (also referred to as a second word line) in the management zone 41(j). Alternatively, the program voltage (i.e., the first electrical parameter) used in the write operation (i.e., the target operation) performed on the first word line in the management zone 41(i) can be different from the program voltage (i.e., the second electrical parameter) used in the write operation (i.e., the target operation) performed on the second word line in the management zone 41(j), and so on.

[0110] In one embodiment, the difference (e.g., the voltage difference) between the first electrical parameter and the second electrical parameter can be positively correlated to the difference between the first electrical characteristic and the second electrical characteristic. That is, the greater the difference between the first electrical characteristic and the second electrical characteristic, the greater the difference (e.g., the voltage difference) between the first electrical parameter and the second electrical parameter can be.

[0111] In one embodiment, the memory control circuit 23 can determine a reference electrical parameter corresponding to the target operation to be performed, according to the target operation to be performed. For example, the reference electrical parameter can be at least one of a read voltage, a read pass voltage, a program voltage, a program verify voltage, an erase voltage, an erase verify voltage, and a pre-program voltage, and the type of the reference electrical parameter is not limited thereto. For example, in one embodiment, the reference electrical parameter can further include a voltage step precision, etc., without limitation.

[0112] In one embodiment, in response to the target operation to be performed being a read operation, the determined reference electrical parameter can include a read voltage and / or a read pass voltage. For example, in a read operation, a read voltage is applied to a target word line, and a read pass voltage is applied to a neighboring word line (non-target word line) of the target word line. In particular, the read voltage is applied to the target word line for sensing the voltage state (or on state) of each memory cell in the target word line to read data from the target word line. However, the read pass voltage is applied to the neighboring word line for causing each memory cell in the neighboring word line to be in an on state to assist in reading data from the target word line.

[0113] In one embodiment, when the target operation is a read operation, performing the target operation on the target word line according to the adjusted reference electrical parameter further includes identifying a management zone to which a neighboring word line of the target word line belongs, and determining a read pass voltage to be applied to the neighboring word line according to a management table corresponding to the management zone to which the neighboring word line belongs.

[0114] In one embodiment, in response to the target operation to be performed being a write operation, the determined reference electrical parameter can include a program voltage, a program verify voltage, and / or a voltage step precision. For example, in a write operation, a plurality of program-verify cycles can be performed. In each program-verify cycle, a program voltage is applied to a target word line to store data to the target word line, and a program verify voltage is subsequently applied to the target word line to verify whether the voltage state of each memory cell in the target word line is as expected. In addition, in a write operation, the voltage step precision is used to adjust the adjustment magnitude of the program voltage and / or the program verify voltage in the plurality of program-verify cycles.

[0115] In one embodiment, in response to the target operation to be performed is an erase operation, the determined reference electrical parameter can include an erase voltage, an erase verify voltage, a program voltage, and / or a voltage step precision. For example, in an erase operation, a plurality of erase-verify cycles can be performed. In each erase-verify cycle, a program voltage can be applied to the target word line to perform a program operation on the target word line, and then an erase voltage can be applied to the target word line to actually erase the data stored in the target word line, and finally, an erase verify voltage can be applied to the target word line to verify whether the voltage state of each memory cell in the target word line is as expected. In addition, in an erase operation, the voltage step precision is used to adjust the adjustment range of the erase voltage, the erase verify voltage, and / or the program voltage used in multiple erase-verify cycles.

[0116] It should be noted that the above-mentioned different types of target operations use reference electrical parameters as examples. In one embodiment, the type and / or number of corresponding reference electrical parameters for different types of target operations can also be adjusted according to practical needs.

[0117] In one embodiment, after determining the target management area, the memory control circuit 23 can determine a management table corresponding to the target management area (also referred to as a target management table) from the management tables 401(1)~401(D). For example, if the target management area is the management area 41(i), the memory control circuit 23 can determine the management table 401(i) as the target management table. Alternatively, if the target management area is the management area 41(j), the memory control circuit 23 can determine the management table 401(j) as the target management table.

[0118] In one embodiment, after determining the reference electrical parameter and the target management table, the memory control circuit 23 can adjust the reference electrical parameter according to the target management table to obtain the first electrical parameter or the second electrical parameter. Then, the memory control circuit 23 can perform the target operation on the target word line according to the adjusted reference electrical parameter (i.e., the first electrical parameter or the second electrical parameter). For example, if the target management area is the management area 41(i), the memory control circuit 23 can adjust the reference electrical parameter according to the management table 401(j) to obtain the first electrical parameter. Then, the memory control circuit 23 can perform the target operation on the target word line according to the first electrical parameter. Alternatively, if the target management area is the management area 41(j), the memory control circuit 23 can adjust the reference electrical parameter according to the management table 401(j) to obtain the second electrical parameter. Then, the memory control circuit 23 can perform the target operation on the target word line according to the second electrical parameter. In this way, by adaptively adjusting the reference electrical parameter for the target word line (or the target management area), the efficiency and / or stability of the subsequent target operation on the target word line can be improved.

[0119] In one embodiment, the selected target management table can have the following characteristics according to the type of the target management area (e.g., belonging to a bonding interface region (BIR), a plasma etching variation region (PDER), a center stable region (DCR), or a bonding transition region (DBTR)):

[0120] (1) If the target management area belongs to a bonding interface region (BIR), the selected target management table (or the information recorded in the target management table) can be dedicated or mainly used for compensating for the interface bonding process defects of the target word line during the execution of the target operation on the target word line. For example, if the target management area belongs to a bonding interface region (BIR), the memory control circuit 23 can adjust the read voltage for the target word line, for example, increase the read voltage by an offset value (also referred to as a first offset value). For example, the first offset value can be -0.1V, and the present application is not limited thereto. In addition, if the target management area belongs to a bonding interface region (BIR), the memory control circuit 23 can also reduce the voltage stepping precision.

[0121] (2) If the target management area belongs to a plasma etching variation region (PDER), the selected target management table (or the information recorded in the target management table) can be dedicated or mainly used for compensating for the plasma etching process defects of the target word line during the execution of the target operation on the target word line. For example, if the target management area belongs to a plasma etching variation region (PDER), the memory control circuit 23 can adjust the voltage stepping precision for the target word line (for example, reduce the voltage stepping precision), for example, reduce the voltage stepping precision by a preset amplitude (also referred to as a first preset amplitude) (for example, reduce by 20%) to improve the verification accuracy, and the present application is not limited thereto.

[0122] (3) If the target management area belongs to a center stable region (DCR), the selected target management table (or the information recorded in the target management table) can be dedicated or mainly used for compensating for the most stable electrical characteristics of the target word line during the execution of the target operation on the target word line. For example, if the target management area belongs to a center stable region (DCR), the memory control circuit 23 can adjust the voltage stepping precision for the target word line (for example, increase the voltage stepping precision), for example, increase the voltage stepping precision by a preset amplitude (also referred to as a second preset amplitude) (for example, increase by 10%) to speed up the verification speed, and the present application is not limited thereto.

[0123] (4) If the target management area belongs to the DBTR, the target management table (or the information recorded in the target management table) used can be dedicated or mainly used for performing corresponding electrical compensation for the word line position where the target word line is located during the target operation performed on the target word line. For example, if the target management area belongs to the DBTR, the memory control circuit 23 can perform gradient compensation on the read voltage used for the target word line. For example, in the DBTR, the memory control circuit 23 can increase (or decrease) the read voltage used by an offset value (also referred to as a second offset value) every time a preset number of word line positions are crossed. For example, the second offset value can be 0.05V, and the present application is not limited thereto.

[0124] It should be noted that in the above embodiments, the division of the management area, the setting of the word line coverage range of the management area, the initial content setting of the management table, the content updating mechanism of the management table, and the parameter adjustment mechanism corresponding to various types of management areas, etc. can all be automatically performed by the memory control circuit 23 based on a preset operation logic. For example, through a firmware code downloaded and installed in advance, after the storage device 12 is powered on, the memory control circuit 23 can automatically complete the above operations based on the firmware code.

[0125] Figure 10 is a flowchart of a memory management method according to an embodiment of the present application. Please refer to Figure 10 In step S1001, a target operation event is detected, where the target operation event indicates that a target operation is performed on a target word line. In step S1002, in response to the target operation event, a target management area in which the target word line is located is determined from a plurality of management areas. In step S1003, a target management table corresponding to the target management area is determined from a plurality of management tables. In step S1004, a reference electrical parameter is adjusted according to the target management table. In step S1005, the target operation is performed on the target word line according to the adjusted reference electrical parameter.

[0126] However, Figure 10 The steps in the above have been described in detail, and will not be repeated here. It should be noted that Figure 10 The steps in the above can be implemented as a plurality of program codes or circuits, and the present application is not limited thereto. In addition, Figure 10 The method of the above can be used in combination with the above example embodiments, or can be used alone, and the present application is not limited thereto.

[0127] In summary, the memory management method and the storage device provided by the embodiments of the present application can group the word lines in the memory module in the vertical direction based on the specially configured management table, so as to satisfy the electrical defect compensation of the word lines with different electrical characteristics (for example, different process defects). Therefore, the overall operation performance and / or operation stability of the storage device can be effectively improved.

[0128] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory management method, characterized in that, Applied to a storage device, the storage device including a memory module, the memory module including multiple word lines, the memory management method includes: Detect a target operation event, wherein the target operation event indicates that a target operation is performed on a target word line among the plurality of word lines; In response to the target operation event, it is determined that the target word line is located in a target management area among multiple management areas, wherein the multiple management areas are vertically distributed in the memory module according to their respective electrical characteristics; From multiple management tables, determine the target management table corresponding to the target management area; Adjust the baseline electrical parameters according to the target management table; and The target operation is performed on the target word line based on the adjusted reference electrical parameters. The plurality of management areas include virtual word line areas, which are interspersed between two specific types of management areas. Word lines within the virtual word line areas are not used to store user data, and the voltage applied to the word lines within the virtual word line areas changes in conjunction with the operating voltage applied to adjacent management areas, including: When the voltage applied to the adjacent management area changes, the change can be reflected in the virtual word line area, so that the voltage subsequently applied to the virtual word line area also changes accordingly.

2. The memory management method according to claim 1, wherein the step of performing the target operation on the target word line according to the adjusted reference electrical parameters includes: If the target management area is the first management area among the plurality of management areas, then the target operation is performed on the target word line based on the first electrical parameters; as well as If the target management area is the second management area among the plurality of management areas, the target operation is performed on the target word line based on the second electrical parameters; The first electrical parameter matches the first electrical characteristic of the first management area, the second electrical parameter matches the second electrical characteristic of the second management area, and the first electrical characteristic is different from the second electrical characteristic.

3. The memory management method according to claim 2, wherein the difference between the first electrical parameter and the second electrical parameter is used to compensate for the difference between the first electrical characteristic and the second electrical characteristic.

4. The memory management method according to claim 2, wherein the step of performing the target operation on the target word line according to the adjusted reference electrical parameters includes: If the target management area is the first management area among the plurality of management areas, the first management table corresponding to the first management area in the plurality of management tables shall be determined as the target management table; The reference electrical parameters are adjusted according to the first management table to obtain the first electrical parameters, wherein the first management table is also matched with the first electrical characteristics; as well as If the target management area is the second management area among the plurality of management areas, the second management table corresponding to the second management area in the plurality of management tables is determined as the target management table, and the reference electrical parameters are adjusted according to the second management table to obtain the second electrical parameters, wherein the second management table also matches the second electrical characteristics.

5. The memory management method according to claim 1, further comprising: The reference electrical parameters are determined based on the target operation to be performed; The reference electrical parameters include at least one of the following: read voltage, read pass voltage, programming voltage, programming verification voltage, erase voltage, erase verification voltage, pre-programming voltage, and voltage step accuracy.

6. The memory management method of claim 5, wherein in response to the target operation to be performed being a read operation, the reference electrical parameters include at least one of the read voltage and the read pass voltage; In response to the target operation to be performed being a write operation, the reference electrical parameters include at least one of the programming voltage, the programming verification voltage, and the voltage step accuracy; In response to the target operation to be performed being an erase operation, the reference electrical parameters include at least one of the erase voltage, the erase verification voltage, the pre-programmed voltage, and the voltage step accuracy.

7. The memory management method according to claim 1, wherein the plurality of management regions include a bonding interface region, a bonding transition region, an etching variation region, and a central stabilization region. Word lines located in the bonding interface area have more significant interface bonding process defects compared to other word lines; Word lines located in the etching variation zone exhibit more significant plasma etching process defects compared to other word lines; Word lines located in the central stability region have the most stable electrical characteristics compared to other word lines, and The electrical characteristics of word lines located in the bonding transition region change gradually according to the word line position.

8. The memory management method according to claim 7, wherein if the target management area belongs to the bonding interface area, the target management table is used to compensate for interface bonding process defects of the target word line during the execution of the target operation on the target word line. If the target management area belongs to the etching variation area, the target management table is used to compensate for the plasma etching process defects of the target word line during the target operation performed on the target word line. If the target management area belongs to the central stable area, the target management table is used to compensate for the most stable electrical characteristics of the target word line during the execution of the target operation on the target word line, and If the target management area belongs to the bonding transition area, the target management table is used to perform corresponding electrical compensation for the word line position where the target word line is located during the target operation performed on the target word line.

9. The memory management method according to claim 1, further comprising: Based on at least one of the wear level information, temperature information, and model information of the memory module, adjust the word line coverage of at least one of the plurality of management areas.

10. The memory management method according to claim 1, further comprising: Based on at least one of the wear level information, temperature information, and model information of the memory module, adjust the recorded content of at least one of the plurality of management tables.

11. The memory management method according to claim 1, wherein adjusting the reference electrical parameters according to the target management table includes: The reference electrical parameters are adjusted according to at least one of the voltage offset, temperature compensation coefficient, and loss adjustment parameters recorded in the target management table.

12. The memory management method of claim 11, wherein the reference electrical parameters are adjusted according to at least one of the voltage offset, temperature compensation coefficient, and loss adjustment parameters recorded in the target management table, based on the following formula: Final operating voltage = Reference operating voltage + Voltage offset + Temperature compensation value + Wear compensation value.

13. The memory management method according to claim 1, wherein the virtual word line region is used to apply voltage during operation to assist in the operation of adjacent word lines or to isolate interference.

14. The memory management method according to claim 1, further comprising: In response to the detection of multiple electrical characteristics within a certain management area, the management area is divided into multiple sub-management areas; Configure corresponding sub-management tables for the multiple sub-management areas; as well as Based on the sub-management area where the target word line is located and its corresponding sub-management table, adjust the reference electrical parameters and execute the target operation.

15. The memory management method according to claim 1, wherein the division of the plurality of management areas is based on the electrical characteristic detection results of the plurality of word lines, the electrical characteristic detection including random telegraph noise detection and / or critical voltage distribution detection.

16. The memory management method according to claim 15, wherein dividing the plurality of management regions based on the critical voltage distribution detection result includes: If the standard deviation of the critical voltage distribution of the word line is less than the first threshold, then the word line is classified into the central stable region. If the standard deviation of the critical voltage distribution of the word line is greater than the second threshold, the word line is classified into the etching variation region or the bonding interface region.

17. The memory management method according to claim 1, wherein the target operation includes a read operation, a write operation, or an erase operation; When the target operation is the read operation, performing the target operation on the target word line according to the adjusted reference electrical parameters further includes: Identify the management area to which the word line adjacent to the target word line belongs; The read pass voltage applied to the adjacent word line is determined based on the management table corresponding to the management area to which the adjacent word line belongs.

18. The memory management method according to claim 5, wherein adjusting the voltage step accuracy according to the target management table comprises: If the target management area is a bonding interface area or an etch variation area, then the voltage step accuracy is reduced; If the target management area is a central stable area, then the voltage step accuracy is increased.

19. A storage device, characterized in that, include: Connection interface, used to connect to the host system; Memory module; as well as The memory controller is connected to the connection interface and the memory module. The memory module includes multiple word lines, and the memory controller is configured to perform the memory management method according to any one of claims 1 to 18.

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