Semiconductor wafer and preparation method thereof

Abstract

The invention provides a semiconductor wafer and a preparation method thereof, and the preparation method comprises the steps: providing a wafer, measuring the warping data of the wafer, and depositing a bow-shaped stress film on the back surface of the wafer according to the warping data, and the bow-shaped stress film meets the following rules: if the front surface of the wafer is warped in the x direction, the bow-shaped stress film distributed in the y direction of the back surface is used for correction; if the front surface of the wafer is warped in the y direction, correcting by the arched stress film distributed in the x direction of the back surface; if the front surface of the wafer warps upwards, depositing a tensile stress film on the back surface of the wafer; and if the front surface of the wafer warps downwards, depositing a pressure stress film on the back surface of the wafer. According to the invention, various types of initial deformation can be counteracted, so that warping generated in specific steps in the production process can be reduced to the greatest extent, and the product quality and reliability requirements can be fully ensured.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit design and manufacturing, and in particular relates to a semiconductor wafer and its preparation method. Background Technology

[0002] Since the invention of the transistor, the semiconductor industry has far from reached saturation; on the contrary, it is showing an even more prosperous scene. Many studies show that the minimum physical gate length of a transistor is the physical limit of silicon, because this limit is the size of atoms and molecules. Therefore, under the constraints of Moore's Law, the industry has been discussing the future of "More Moore," "More than Moore," and "Beyond CMOS." Recently, the development of artificial intelligence technology has opened up a richer application space, and big data analysis has become a new and powerful driving force for the semiconductor business, making the direction of semiconductor market demand clearer. As a future technology trend, nanosheets and 3D-ICs are being researched, and the semiconductor industry, including R&D, is full of vitality. Power devices have their own unique evolutionary trajectory. Power semiconductors are the core components of power electronic products, mainly used for frequency conversion, voltage transformation, rectification, power conversion, and management in power electronic equipment, while also possessing energy-saving effects. The future deployment of autonomous driving in automobiles and renewable energy systems to achieve carbon neutrality has become a new driving force for the power device business. Research shows that the power device business is facing a new turning point. For power semiconductors, emerging applications place greater emphasis on energy efficiency, power density, and reliability. Authoritative institutions predict that power devices will grow at a rate of no less than 6% annually in the coming years. Similar to the development of integrated circuits, the manufacturing of power devices has also transitioned to 300mm wafers. As product performance improves, the manufacturing process becomes more complex; the more compact structure coupled with a high aspect ratio brings new challenges, the biggest of which is wafer warping caused by stress mismatch.

[0003] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor wafer and its preparation method, which solves the problem of wafer warping of various shapes that is difficult to solve in actual production in the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a method for fabricating a semiconductor wafer, the method comprising: providing a wafer, measuring warpage data of the wafer, and depositing an arc-shaped stress film on the back side of the wafer based on the warpage data, wherein the arc-shaped stress film satisfies the following rules: if the warpage is in the x-direction of the front side of the wafer, it is corrected by an arc-shaped stress film distributed in the y-direction of the back side; if the warpage is in the y-direction of the front side of the wafer, it is corrected by an arc-shaped stress film distributed in the x-direction of the back side; if the front side of the wafer warps upward, a tensile stress film is deposited on the back side of the wafer; if the front side of the wafer warps downward, a compressive stress film is deposited on the back side of the wafer.

[0006] Optionally, adjacent arcuate stress membranes are separated from each other, or when adjacent arcuate stress membranes are in contact with each other, the boundary line between adjacent arcuate stress membranes is a 45° and 135° oblique line passing through the center of the wafer.

[0007] Optionally, the configuration of the bow-shaped stress film is selected from one of the following combinations based on the initial warpage type of the wafer: Type 1: If the x-axis region on the front side of the wafer is warped upwards and the y-axis region on the front side is not warped, then an arch-shaped tensile stress film is deposited at both ends of the y-axis on the back side of the wafer. The second type: If the x-axis region on the front side of the wafer warps downward and the y-axis region on the front side does not warp, then an arch-shaped compressive stress film is deposited at both ends of the y-axis on the back side of the wafer. The third type: If the front x-axis region of the wafer is not warped and the front y-axis region is warped upward, then an arc-shaped tensile stress film is deposited at both ends of the back x-axis of the wafer. Category 4: If the front x-axis region of the wafer is not warped, but the front y-axis region warps downward, then an arched compressive stress film is deposited at both ends of the back x-axis of the wafer. Fifth type: If the front x-axis region of the wafer warps downward and the front y-axis region warps upward, then an arc-shaped tensile stress film is deposited at both ends of the back x-axis of the wafer, and an arc-shaped compressive stress film is deposited at both ends of the back y-axis. Category 6: If the x-axis region on the front side of the wafer warps upward and the y-axis region on the front side warps downward, then an arc-shaped compressive stress film is deposited at both ends of the x-axis on the back side of the wafer, and an arc-shaped tensile stress film is deposited at both ends of the y-axis on the back side.

[0008] Optionally, the preparation of the fifth or sixth type of arc-shaped stress membrane includes the following steps: 1) Deposit a tensile stress film on the back side of the wafer, then use photolithography to define the area where the excess film is located, and then remove the excess tensile stress film by etching to form the desired bow-shaped tensile stress film; 2) Deposit a compressive stress film on the back side of the wafer, then use photolithography to define the area where the excess film is located, and then remove the excess compressive stress film by etching to form the desired bow-shaped compressive stress film.

[0009] Optionally, the preparation of the fifth or sixth type of bow-shaped stress film includes the following steps: depositing a fan-shaped tensile stress film and a fan-shaped compressive stress film on the back side of the wafer simultaneously in the corresponding regions by a regional deposition process; removing the tensile stress film and compressive stress film in the middle rectangular region by a photolithography process and an etching process; and forming the desired bow-shaped tensile stress film and bow-shaped compressive stress film on the back side of the wafer.

[0010] Optionally, the preparation of the fifth or sixth type of bow-shaped stress film includes the steps of simultaneously depositing a bow-shaped tensile stress film and a bow-shaped compressive stress film on the corresponding area on the back side of the wafer using a regional deposition process.

[0011] Optionally, after preparing the bow-shaped tensile stress film and the bow-shaped compressive stress film, the method further includes the steps of: depositing a zero-stress film on the back side of the wafer, wherein the thickness of the zero-stress film is greater than the thickness of the bow-shaped tensile stress film and the bow-shaped compressive stress film; and planarizing the zero-stress film by a chemical mechanical polishing process.

[0012] Optionally, within the capabilities of thin film deposition, the width of the bow-shaped stress film can be reduced by increasing the stress and / or thickness of the bow-shaped stress film.

[0013] The present invention also provides a semiconductor wafer, the semiconductor wafer comprising: a wafer, wherein an arc-shaped stress film is deposited on the back side of the wafer, wherein the arc-shaped stress film satisfies the following rules: if the front side of the wafer warps in the x direction, it is corrected by an arc-shaped stress film distributed in the y direction on the back side; if the front side of the wafer warps upward, a tensile stress film is deposited on the back side of the wafer; if the front side of the wafer warps downward, a compressive stress film is deposited on the back side of the wafer.

[0014] Optionally, the maximum warpage value of the wafer is between 150 micrometers and 300 micrometers.

[0015] As described above, the semiconductor wafer and its fabrication method of the present invention have the following beneficial effects: This invention provides a systematic solution to various wafer warpage problems. By depositing stress films with a set geometry in different areas on the back of the wafer, the film generates a deformation that is opposite in direction and equal in magnitude to the initial deformation of the wafer, thereby offsetting the initial deformation. This minimizes warpage at specific steps in the production process and fully ensures product quality and reliability requirements.

[0016] This invention corrects wafer warpage by depositing a stress film on the back side, which has no impact on the front-side devices and will not adversely affect device performance.

[0017] Based on the capabilities of chemical vapor deposition equipment, combined with photolithography and etching processes, this invention proposes a variety of methods for fabricating back-side stress films. In particular, it can simultaneously deposit bow-shaped tensile stress films and bow-shaped compressive stress films in corresponding areas on the back side of the wafer through a regional deposition process. The process is simple, efficient, and has high application value.

[0018] This invention reduces wafer warpage by more than 50%, meeting the requirements of conveying equipment and other devices for wafer warpage.

[0019] The method of this invention can significantly reduce local spherical warping and is very compatible with photolithography and chemical mechanical polishing processes. Attached Figure Description

[0020] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.

[0021] Figure 1 The diagram shows a split-gate transistor structure.

[0022] Figure 2 The diagram shows a saddle-shaped warping effect.

[0023] Figure 3 The diagram shows a step flow diagram of a method for improving wafer warpage of various shapes according to an embodiment of the present invention.

[0024] Figure 4 The diagram shows the distribution of wafer deformation measurement points according to an embodiment of the present invention.

[0025] Figure 5 The diagram shown is a schematic representation of the initial warping morphology measurement according to an embodiment of the present invention.

[0026] Figures 6-9 The diagram shown is a schematic representation of a finite element model for simulating the stress film on the back side of a wafer, according to an embodiment of the present invention. Figure 6 The diagram shows a structural schematic of the stress simulation model. Figure 7 This is a schematic diagram of the geometric partitioning of the wafer surface. Figure 8 This is a schematic diagram showing the assignment of stress membrane (xy compression-tension) nodes. Figure 9 The image displayed is a schematic diagram of the deformed or warped shape of the wafer in the simulation output.

[0027] Figures 10-13 The diagrams shown illustrate various warping morphologies and their representation methods according to embodiments of the present invention. Figure 10 The diagram is shown as an umbrella shape and its symbol. Figure 11 The symbol for the bowl shape is shown in the diagram. Figure 12The diagram is shown in the shape of a potato chip and its symbol. Figure 13 The diagram is shown as a saddle shape and its symbol.

[0028] Figures 14-15 The diagram shown illustrates the arc-shaped stress membrane and its parameters according to an embodiment of the present invention. Figure 14 The diagram shows a structure where adjacent stress membranes do not contact each other. Figure 15 The diagram shows a structural schematic of adjacent stress membranes in contact.

[0029] Figure 16 This diagram illustrates a localized spherical deformation caused by a large-area stress film on the back side of a wafer, as shown in an embodiment of the present invention.

[0030] Figures 17-22 The diagram shows a schematic representation of a structure in an embodiment of the present invention that uses a combination of bow-shaped stress films on the back side of a wafer to reduce various types of warpage.

[0031] Figure 23 The diagram shows a first manufacturing process flow of the stress film on the back side of a wafer according to an embodiment of the present invention.

[0032] Figure 24 The diagram shows a first manufacturing process flow of the stress film on the back side of a wafer according to an embodiment of the present invention.

[0033] Figure 25 The diagram shows a first manufacturing process flow of the stress film on the back side of a wafer according to an embodiment of the present invention.

[0034] Figure 26 The diagram shows a simulation model correction process according to an embodiment of the present invention.

[0035] Figures 27-29 The diagram shows experimental results from an embodiment of the present invention. Figure 27 The image shown is a schematic diagram of the initial warpage of a measured wafer. Figure 28 The diagram shown is a schematic representation of wafer warpage with a fan-shaped stress film deposited on the back side of the wafer, as described in an embodiment of the present invention. Figure 29 This diagram illustrates wafer warping with an arched stress film retained on the back side of the wafer.

[0036] Figures 30-31 The diagram shown is a schematic representation of the stress film design on the back side of the wafer during an experiment according to an embodiment of the present invention. Figure 30 The diagram shows a fan-shaped stress film assembly on the back side of a wafer. Figure 31 The diagram shows a bow-shaped stress film assembly on the back side of a wafer.

[0037] Figure 32 The diagram shows the wafer warpage improvement effect according to an embodiment of the present invention.

[0038] Component labeling description: wafer substrate 10, stress film 11, bow-shaped tensile stress film 111, bow-shaped compressive stress film 112, fan-shaped tensile stress film 201, fan-shaped compressive stress film 202, steps S11~S16. Detailed Implementation

[0039] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0041] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0042] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0043] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0044] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0045] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0046] In the fabrication of power devices, with the continuous development and iteration of process technology, split-gate transistors (SGT) and insulated-gate bipolar transistors (IGBTs) employ narrower and deeper trench processes to effectively improve power density and reduce losses, while simultaneously enhancing product reliability. During the fabrication process, films of different compositions and / or thicknesses need to be repeatedly formed or deposited on the device. The films and silicon substrates, due to their different chemical compositions, possess different mechanical properties, which is the cause of interfacial stress mismatch. The following is an example of a step in the SGT process: Figure 1 This is a cross-sectional schematic of an SGT (Semiconductor Gravity Transmission) structure. This process involves etching deep trenches on an epitaxial substrate and depositing a high-temperature thermal oxide film within these trenches to form two polysilicon gates. The main purpose is to reduce gate-drain capacitance by isolating the gate and drain, thus converting the gate-drain capacitance into gate-source capacitance. This increases the device's input capacitance, and the higher input capacitance to Miller capacitance ratio provides greater resistance to the effects of drain voltage oscillations on the gate. When an oxide film is formed on one surface of silicon, stress mismatch occurs at the interface due to the difference in thermal expansion coefficients (CTE) between silicon dioxide and monocrystalline silicon during the cooling process. For the SGT structure, the oxide film formed at high temperature causes stress mismatch on the trench bottom, sidewalls, and back surface of the wafer during the cooling process. The sum of stress mismatches in the trench extension direction (y-direction) and trench alignment direction (x-direction), combined with the stress mismatch on the back side of the wafer, causes severe warping of the wafer after oxide layer formation. Furthermore, the degree of warping differs significantly between the x- and y-directions. This difference causes the wafer to warp into a saddle-shaped structure with the x-direction pointing upwards and the y-direction downwards. Figure 2 The stress-deformation relationship (Equation 2) shows that with constant substrate and film thickness, the mechanical properties of the material remain constant. However, as the substrate geometry increases, the strain at the substrate edges increases. This characteristic is reflected in the semiconductor industry's transition from 6-inch and 8-inch wafers to 12-inch wafers. With larger wafer sizes and more complex structures, the warpage of power devices on the production line becomes increasingly pronounced. This deformation directly disrupts the product manufacturing process, leading to reduced yield, impacting product quality, and even scrapping.

[0047] When the warpage (maximum y-axis deformation – maximum x-axis deformation) exceeds 250 micrometers, the following problems can easily occur: 1) During robotic arm handling, wafer slippage can easily occur, leading to wafer breakage; 2) Vacuum adsorption platforms cannot achieve good wafer adsorption, hindering subsequent processing operations, especially in photolithography, which severely affects photolithography and alignment accuracy, resulting in pattern contour deformation and directly impacting device performance; 3) In mass production cleaning equipment, excessive warpage, combined with the surface tension of the cleaning solution, can cause adjacent wafers to overlap, making cleaning impossible. Therefore, improving wafer warpage, especially addressing the excessive difference in warpage between the x and y directions, is a major challenge in the current production of power devices.

[0048] The warpage is typically related to trench depth, trench width, number of trenches, and oxide film thickness. Table 1 below shows the measured data for a certain SGT product. After the wafer completes high-temperature thermal oxide layer growth in the trench, the warpage in the y-direction is -357 micrometers, and the warpage in the x-direction is 199 micrometers, a difference of up to 556 micrometers. This warpage exceeds the mechanical transfer, vacuum adsorption, and process cavity handling capabilities of most equipment, making the product unmanufacturing.

[0049] Therefore, a new manufacturing process is needed to solve the saddle-shaped warpage problem of wafers in order to achieve mass production, improve production efficiency, and ensure device performance.

[0050]

[0051] The following are known methods for addressing wafer warpage: 1) Adjustment is achieved by vertically arranging chips with different trench orientations on a mask. The limitation of this approach is that chips with different orientations must have square dies of the same size, otherwise the packaging and testing process cannot achieve dicing.

[0052] 2) Stress can be managed through photolithography. Specifically, a stress film is deposited on the wafer surface, a specific area is protected with photoresist, and ion implantation is performed on other areas to release stress in a specific direction. The limitation of this method is that ion implantation has a significant impact on semiconductor devices (especially in the front-end process), and the growth and removal of the stress film are relatively complex.

[0053] 3) For saddle-shaped warpage, a fan-shaped stress film is deposited on the back side, with different film types in different directions, to correct the warpage in the X and Y directions in different directions. This method additionally forms local spherical warpage, limiting the warpage adjustment range. Furthermore, spherical warpage is not friendly to photolithography and chemical mechanical polishing processes, easily leading to alignment failure and wafer breakage.

[0054] 4) A method is proposed in the authorized Chinese patent application number 202310384155.9: forming a trench structure on the back side of a wafer, with the trench's position and extension direction consistent with the front side trench; then forming a silicon oxide thin film at the bottom, top, and sidewalls of the back side trench. The compressive stress of the oxide film in the trench structure produces warping directions in the X and Y directions differently, and exactly opposite to the warping direction produced by the front side trench, thereby reducing saddle-shaped warping. This method is effective, but it requires first depositing an oxide film on the front side to protect the front structure from mechanical damage and contamination. After the back side processing is completed, the front oxide film needs to be removed. The process involves front side chemical vapor deposition, back side photolithography, back side etching, cleaning, formation of the back side protective film, and removal of the front side protective film, resulting in numerous steps and room for optimization.

[0055] For the reasons mentioned above, such as Figure 3 As shown, this embodiment provides a method for improving wafer warpage of various shapes, the method comprising the following steps: Step S11: Measure the initial warpage morphology of the wafer and obtain the measured deformation distribution data of the wafer; Step S12: Calculate the three-dimensional deformation of the wafer warpage using a finite element simulation model. Based on this, optimize the parameters of the back stress film of the wafer using the linear superposition method based on the measured deformation distribution data. The parameters include the type, geometry, stress value, and thickness of the stress film, so that the back stress film produces a deformation distribution opposite to the initial warpage morphology. Step S13: Based on the optimized parameters of the stress film in step S12, a stress film is prepared on the back side of the wafer. The stress film is distributed in an arc shape in the four quadrants near the circumference on the back side of the wafer. Step S14: Measure the deformation distribution data of the optimized wafer; Step S15: Determine whether the warpage value of the optimized wafer meets the requirements. If the warpage value of the wafer is less than or equal to the maximum allowable warpage specification of the wafer, then wafer fabrication is performed according to the parameters of the stress film in step S13. If the warpage value of the wafer is greater than the maximum allowable warpage specification of the wafer, then proceed to step S16. Step S16: Based on the measurement results of step S14, the parameters of the stress membrane are corrected by reverse calculation, and the parameters of the stress membrane are corrected in the finite element simulation model. Then, steps S12 to S15 are repeated until the warpage value of the wafer is less than or equal to the maximum allowable warpage specification of the wafer.

[0056] In some embodiments, the method further includes the step: 7) Based on the above steps, a matrix table of stress films on the back side of the wafer is formulated. Based on the initial warpage values ​​in the X and Y directions on the front side, the parameters for depositing stress films in four regions in the X and Y directions on the back side of the wafer can be obtained by looking up the table.

[0057] In some embodiments, when measuring the initial warpage morphology of a wafer, the measurement points are uniformly distributed across the entire wafer, and the height value of each point is measured to obtain the wafer's deformation distribution data. The deformation distribution data satisfies the following function:

[0058] Where z0 represents the initial displacement of a point on the wafer surface in a direction perpendicular to the wafer surface, and is a bivariate function of the point (x,y) on the wafer surface.

[0059] In some embodiments, based on the measured deformation distribution data from step 1), the deformation distribution z1 corresponding to the back stress membrane satisfies:

[0060] For a warpage symmetrical about the z-axis passing through the center of the wafer, the finite element simulation model calculates the stress and thickness of the stress membrane using the following formulas:

[0061] B is the wafer warpage. For axisymmetric warpage, B is the height difference between the edge and center of the wafer's front side, satisfying the following:

[0062] Where σ is the stress of the back stress membrane, h f denoted as the thickness of the stress film, T is the product of the stress and the thickness of the stress film, is the torque per unit area, i.e., the torque density, which is the decisive factor causing wafer deformation, E is the Young's modulus of the substrate, h is the substrate thickness, v is the Poisson's ratio of the substrate material, and R is the wafer radius. After determining T, the stress and thickness of the stress film are determined based on the principle of optimal economy, provided that the feasibility of the film formation process, such as chemical vapor deposition, is satisfied.

[0063] In some embodiments, for non-centrosymmetric warping, the finite element simulation model is constructed based on the equations of elasticity, satisfying:

[0064] Where D is the bending stiffness:

[0065] Δ is the Laplace operator for Cartesian coordinates:

[0066] z is the displacement of each point on the wafer in the z direction under stress, Δz refers to the second partial differential with respect to z, i.e. the Laplace operator operation, U(x,y) is the displacement field that satisfies the Laplace equation ΔU(x,y)=0, h is the substrate thickness, v is the Poisson's ratio of the substrate material, T is the product of the stress and the thickness of the stress film, and E is the Young's modulus of the substrate.

[0067] In some embodiments, equation (5) satisfies the following boundary conditions:

[0068] Based on the above equations (5) to (9), the equivalent stress distribution of the front microstructure is obtained based on the finite element simulation model, T=T(z) or z=z(T), and the wafer deformation under this stress distribution is output as z(x,y)=z(T(x,y)), where R represents the wafer radius, θ is the angle in the cylindrical coordinate system, and U(R, θ) represents the boundary condition at the edge of the wafer.

[0069] In some embodiments, the optimal torque density distribution T is obtained by the following method: opt (x,y) such that:

[0070] Based on equations (5) to (9), z(T(x,y)) is a linear system that satisfies the following formula:

[0071] Wafer warpage is described by a cos(2θ) curve, and wafer deformation is described by a polynomial curve. A polar coordinate expression for equation (12) is constructed to describe wafer deformation, resulting in the following formula:

[0072] The first term Ar in equation (13) 2 That is, it is a centrally symmetric warping, and the corresponding moment density T can be obtained from equation (3); observe the second term Br 2 cos(2θ), which is the product of r squared and the cosine of 2θ; A and B are the coefficients of these two terms, with units of m. -1 Since z(r,θ) and T(r,θ) are linear systems, the input T(r,θ) is decomposed into the product of an even-power polynomial P(r) of r and an even-multiple cosine C(θ), resulting in the following formula:

[0073] Where T(r,θ) represents the three-dimensional distribution of torque density a i and b j a is a coefficient i The unit is N / m2i+1 b j As a dimensionless constant, T(x,y) is decomposed into (n+1)(m+1) terms; For the following equation (17), the corresponding three-dimensional deformation is calculated using finite element software:

[0074] Where i = 0, 1, 2, ..., n; j = 0, 1, 2, ..., m; For the target deformable surface -z0(x,y), a linear superposition fitting is performed using the basic deformation array:

[0075] Among them, the dimensionless coefficient sequence p ij The moment density and deformation in equations (17) and (18) can be determined by the least squares method. The physical dimension coefficients of equation (5) are normalized into iterable deformation elements z during the finite element calculation. ij dimensionless coefficient p ij ; According to the principle of linear superposition in equation (11), p ij It satisfies both deformation superposition and moment density superposition, producing a stress distribution T with deformation -z0(r,θ). opt (r,θ) satisfies the following formula:

[0076] In some embodiments, front-side warpage is eliminated by forming an arc-shaped stress film on the back side of the wafer, through the arc width (d) x1 , d x2 ), (d y1 , d y2 The geometry is uniquely determined by (T) x1 , T x2 ), (T y1 , T y2 The optimal moment density distribution T is obtained by describing the product of stress and film thickness. opt (x,y) is transformed into a single-objective multivariable optimization problem under constraints, satisfying: Optimization goal:

[0077] Constraints:

[0078] Where, σ lim and h f_lim These represent the stress and thickness limits achievable by thin film deposition processes.

[0079] In some embodiments, the above problem is solved by one or more of the following algorithms: genetic algorithm, particle swarm optimization algorithm, gradient descent algorithm, and simulated annealing algorithm. The optimized T value and the bow width d are determined by the initial warping morphology.

[0080] In some embodiments, adjacent arcuate stress membranes are separated from each other, or, when the width of the arcuate stress membrane is large, adjacent arcuate stress membranes are in contact with each other, and the boundary line between adjacent arcuate stress membranes is a 45° and 135° oblique line passing through the center of the wafer.

[0081] In some embodiments, the arcuate stress film is configured to satisfy the following rules: if the wafer front side warps in the x direction, it is corrected by an arcuate stress film distributed in the y direction on the back side; if the wafer front side warps in the y direction, it is corrected by an arcuate stress film distributed in the x direction on the back side; if the wafer front side warps upward, a tensile stress film is deposited on the back side of the wafer; if the wafer front side warps downward, a compressive stress film is deposited on the back side of the wafer.

[0082] In some embodiments, within the capabilities of thin film deposition processes, the width of the bow-shaped stress film is reduced by increasing the stress and / or thickness of the bow-shaped stress film.

[0083] In some embodiments, the configuration of the bow-shaped stress film is selected from one of the following combinations based on the initial warpage type of the wafer: First type: If the front x-axis region of the wafer warps upwards and the front y-axis region has no warpage, then a bow-shaped tensile stress film 111 is deposited at both ends of the y-axis on the back side of the wafer; Second type: If the front x-axis region of the wafer warps downwards and the front y-axis region has no warpage, then a bow-shaped compressive stress film 112 is deposited at both ends of the y-axis on the back side of the wafer; Third type: If the front x-axis region of the wafer has no warpage and the front y-axis region warps upwards, then a bow-shaped tensile stress film 111 is deposited at both ends of the x-axis on the back side of the wafer; Fourth type... Type 5: If the front x-axis region of the wafer is not warped and the front y-axis region warps downward, then an arc-shaped compressive stress film 112 is deposited at both ends of the back x-axis of the wafer; Type 6: If the front x-axis region of the wafer warps downward and the front y-axis region warps upward, then an arc-shaped tensile stress film 111 is deposited at both ends of the back x-axis of the wafer, and an arc-shaped compressive stress film 112 is deposited at both ends of the back y-axis of the wafer; Type 7: If the front x-axis region of the wafer warps upward and the front y-axis region warps downward, then an arc-shaped compressive stress film 112 is deposited at both ends of the back x-axis of the wafer, and an arc-shaped tensile stress film 111 is deposited at both ends of the back y-axis of the wafer.

[0084] In some embodiments, the preparation of the fifth or sixth type of arc-shaped stress film includes the steps of: 1) depositing a tensile stress film on the back side of a wafer, then using a photolithography process to precisely define the area where the excess film is located, and then removing the excess film by etching to form the desired arc-shaped tensile stress film 111; 2) depositing a compressive stress film on the back side of a wafer, then using a photolithography process to precisely define the area where the excess film is located, and then removing the excess film by etching to form the desired arc-shaped compressive stress film 112.

[0085] In some embodiments, the preparation of the fifth or sixth type of bow-shaped stress film includes the steps of: depositing a fan-shaped tensile stress film and a fan-shaped compressive stress film on the back side of the wafer simultaneously in the corresponding regions by a regional deposition process; removing the tensile stress film and compressive stress film in the middle rectangular region by a photolithography process and an etching process; and forming the desired bow-shaped tensile stress film 111 and bow-shaped compressive stress film 112 on the back side of the wafer.

[0086] In some embodiments, the preparation of the fifth or sixth type of bow-shaped stress film includes the step of simultaneously depositing a bow-shaped tensile stress film 111 and a bow-shaped compressive stress film 112 on the corresponding area of ​​the back side of the wafer by a regional deposition process.

[0087] In some embodiments, when iteratively correcting the simulation model, the parameters are adjusted according to the following steps: keeping the geometry of the arc-shaped stress membrane unchanged, adjusting the product of the stress and the membrane thickness (T) of the stress membrane. x1 , T x2 ), (T y1 , T y2 The values ​​of the four parameters are then calculated by the model to output a simulated deformed surface. The difference between the maximum and minimum values ​​of this surface is set as B. sim The difference between the simulation results and the measured results yields a surface, and the difference between the maximum and minimum values ​​of this surface is denoted as B. error If B error <10% B sim If the condition is met, the finite element simulation model is deemed acceptable; otherwise, repeat the above steps until condition B is satisfied. error <10% B sim .

[0088] This embodiment also provides a method for fabricating a power device, the power device including a trench structure formed on the front side of a wafer, the fabrication method including the method for improving wafer warpage as described in any of the above embodiments.

[0089] In some embodiments, the power device includes a split-gate transistor and an insulated-gate bipolar transistor.

[0090] This embodiment also provides a power device, which is prepared using the power device preparation method described in any of the above schemes.

[0091] This embodiment also provides a wafer multi-morphology warpage correction system for implementing the method for improving wafer multi-morphology warpage as described in any of the above schemes, comprising: a deformation measurement module for measuring the initial warpage morphology of the wafer and obtaining measured deformation distribution data of the wafer; a simulation optimization module for calculating the three-dimensional deformation of the wafer warpage through a finite element simulation model and, based on the measured deformation distribution data, optimizing the parameters of the stress film on the back side of the wafer using a linear superposition method, wherein the parameters include the type, geometry, stress value, and thickness of the stress film, so that the stress film on the back side produces a deformation distribution opposite to the initial warpage morphology; a deposition and etching module for preparing a stress film on the back side of the wafer according to the parameters of the stress film optimized by the simulation optimization module, wherein the stress film is distributed in an arc shape in the four quadrants near the circumference on the back side of the wafer; and a feedback control module for correcting the parameters of the stress film in the finite element simulation model until the wafer warpage value is less than or equal to the maximum allowable warpage specification of the wafer.

[0092] In some embodiments, a stress film matrix table is also included, which is used to look up the parameters for depositing stress films in the four regions X and Y on the back side of the wafer based on the initial warpage values ​​in the X and Y directions on the front side.

[0093] This embodiment also provides a computer-readable storage medium storing program instructions that, when executed, implement the method for improving wafer multimorphic warpage as described in any of the above schemes.

[0094] This embodiment also provides a method for fabricating a semiconductor wafer, the method comprising: providing a wafer, measuring warpage data of the wafer, and depositing an arc-shaped stress film on the back side of the wafer based on the warpage data, wherein the arc-shaped stress film satisfies the following rules: if the warpage is in the x-direction of the front side of the wafer, it is corrected by an arc-shaped stress film distributed in the y-direction of the back side; if the warpage is in the y-direction of the front side of the wafer, it is corrected by an arc-shaped stress film distributed in the x-direction of the back side; if the front side of the wafer warps upward, a tensile stress film is deposited on the back side of the wafer; if the front side of the wafer warps downward, a compressive stress film is deposited on the back side of the wafer.

[0095] In some embodiments, adjacent arcuate stress membranes are separated from each other, or when adjacent arcuate stress membranes are in contact with each other, the boundary line between adjacent arcuate stress membranes is a 45° and 135° oblique line passing through the center of the wafer.

[0096] In some embodiments, the configuration of the bow-shaped stress film is selected from one of the following combinations based on the initial warpage type of the wafer: Type 1: If the x-axis region on the front side of the wafer is warped upwards and the y-axis region on the front side is not warped, then an arch-shaped tensile stress film is deposited at both ends of the y-axis on the back side of the wafer. The second type: If the x-axis region on the front side of the wafer warps downward and the y-axis region on the front side does not warp, then an arch-shaped compressive stress film is deposited at both ends of the y-axis on the back side of the wafer. The third type: If the front x-axis region of the wafer is not warped and the front y-axis region is warped upward, then an arc-shaped tensile stress film is deposited at both ends of the back x-axis of the wafer. Category 4: If the front x-axis region of the wafer is not warped, but the front y-axis region warps downward, then an arched compressive stress film is deposited at both ends of the back x-axis of the wafer. Fifth type: If the front x-axis region of the wafer warps downward and the front y-axis region warps upward, then an arc-shaped tensile stress film is deposited at both ends of the back x-axis of the wafer, and an arc-shaped compressive stress film is deposited at both ends of the back y-axis. Category 6: If the x-axis region on the front side of the wafer warps upward and the y-axis region on the front side warps downward, then an arc-shaped compressive stress film is deposited at both ends of the x-axis on the back side of the wafer, and an arc-shaped tensile stress film is deposited at both ends of the y-axis on the back side.

[0097] In some embodiments, the preparation of the fifth or sixth type of arc-shaped stress membrane includes the steps of: 1) Deposit a tensile stress film on the back side of the wafer, then use photolithography to define the area where the excess film is located, and then remove the excess tensile stress film by etching to form the desired bow-shaped tensile stress film; 2) Deposit a compressive stress film on the back side of the wafer, then use photolithography to define the area where the excess film is located, and then remove the excess compressive stress film by etching to form the desired bow-shaped compressive stress film.

[0098] In some embodiments, the preparation of the fifth or sixth type of bow-shaped stress film includes the steps of: depositing a fan-shaped tensile stress film and a fan-shaped compressive stress film on the back side of the wafer simultaneously in the corresponding regions by a regional deposition process; removing the tensile stress film and compressive stress film in the middle rectangular region by a photolithography process and an etching process; and forming the desired bow-shaped tensile stress film and bow-shaped compressive stress film on the back side of the wafer.

[0099] In some embodiments, the preparation of the fifth or sixth type of bow-shaped stress film includes the step of simultaneously depositing a bow-shaped tensile stress film and a bow-shaped compressive stress film in the corresponding area on the back side of the wafer by a regional deposition process.

[0100] In some embodiments, after preparing the bow-shaped tensile stress film and the bow-shaped compressive stress film, the method further includes the steps of: depositing a zero-stress film on the back side of the wafer, wherein the thickness of the zero-stress film is greater than the thickness of the bow-shaped tensile stress film and the bow-shaped compressive stress film; and planarizing the zero-stress film by a chemical mechanical polishing process.

[0101] In some embodiments, within the capabilities of thin film deposition processes, the width of the bow-shaped stress film is reduced by increasing the stress and / or thickness of the bow-shaped stress film.

[0102] This embodiment also provides a semiconductor wafer, the semiconductor wafer comprising: a wafer, wherein an arc-shaped stress film is deposited on the back side of the wafer, wherein the arc-shaped stress film satisfies the following rules: if the front side of the wafer warps in the x direction, it is corrected by an arc-shaped stress film distributed in the y direction on the back side; if the front side of the wafer warps in the y direction, it is corrected by an arc-shaped stress film distributed in the x direction on the back side; if the front side of the wafer warps upward, a tensile stress film is deposited on the back side of the wafer; if the front side of the wafer warps downward, a compressive stress film is deposited on the back side of the wafer.

[0103] In some embodiments, the maximum warpage value of the wafer is between 150 micrometers and 300 micrometers.

[0104] This embodiment establishes a methodology and process flow for solving multi-morphological warpage. This method involves depositing stress films with predetermined geometric shapes in different regions on the back side, causing deformations that are opposite in direction and equal in magnitude to the initial deformation of the wafer. This counteracts the initial deformation, minimizing warpage at specific steps in the production process and fully ensuring product quality and reliability requirements. The process flow of this embodiment is as follows: Figure 3 As shown, the process mainly consists of four steps: Step S11, firstly, for a given wafer warped due to previous processes, the deformation at multiple points on the entire wafer is measured to ensure that the deformation distribution can be graphically represented in three-dimensional space; Step S12, through a stress finite element simulation model, the type, geometry, stress, and film thickness of the stress film deposited on the back of the wafer required to reduce warping are derived; Step S13, the required stress film is formed on the back of the wafer using processes such as chemical vapor deposition, photolithography, and etching; Step S14, for each different type of warping, an optimization process may be required, namely steps S15-S16, and steps S12-S14 are repeated; after meeting the requirements, the process parameters are solidified.

[0105] The following is a detailed explanation of each step: Step S11: Measure the initial warpage morphology of the wafer and obtain the measured deformation distribution data of the wafer.

[0106] Traditional wafer warpage measurement methods only measure several points along a straight line passing through the wafer's center on the X or Y axis. The height of each point on the wafer surface is measured, and the height difference between the highest and lowest points is the warpage marker. This method is suitable for centrally symmetric warpage patterns but not for asymmetric warpage patterns such as saddle-shaped warpage patterns. In this invention, the distribution of measurement points is as follows: Figure 4 As shown, the measurement points are evenly distributed across the entire wafer, and the height value of each point is measured to obtain the deformation distribution of the wafer.

[0107] Here it is described using the surface form (1):

[0108] Where z0 represents the initial displacement of a point on the wafer surface in a direction perpendicular to the wafer surface, i.e. the initial warping morphology, which is a binary function of the point (x,y) on the wafer surface.

[0109] like Figure 5 As shown, this method can reveal details of wafer warpage, providing initial deformation data for subsequent simulation optimization.

[0110] Step S12: Based on the deformation distribution data, optimize the parameters of the stress film on the back side of the wafer using a finite element simulation model. The parameters include the type, geometry, stress value, and thickness of the stress film, so that the stress film on the back side produces a deformation distribution opposite to the initial warping morphology.

[0111] Based on the warping morphology measured in step S11, the shape, type, stress magnitude and thickness of the back stress membrane need to be optimized to produce a distribution opposite to the initial stress and a corresponding deformation distribution z1.

[0112] Ideally, z1 and z0 cancel each other out, and the initial warp is completely eliminated. For warp that is z-axis symmetric through the wafer center, the stress and thickness of the front / back stress film can be quickly determined using the Stoney formula (3).

[0113]

[0114] B is the wafer warpage. For axisymmetric warpage, B is the height difference between the edge and center of the wafer's front side, satisfying the following:

[0115] Where σ is the stress of the back stress membrane, h f denoted as the thickness of the stress film, T is the product of the stress and thickness of the stress film, E is the Young's modulus of the substrate, h is the substrate thickness, v is the Poisson's ratio of the substrate material, and R is the wafer radius.

[0116] However, for non-centrosymmetric warping, the finite element simulation model can be constructed based on the equations of elasticity, where the relationship between deformation z and T is:

[0117] Where D is the bending stiffness:

[0118] Δ is the Laplace operator for Cartesian coordinates:

[0119] z represents the displacement field, which is the displacement of each point on the wafer in the z-direction under stress.

[0120] U(x,y) is the displacement field that satisfies the Laplace equation ΔU(x,y) = 0.

[0121] Equation (5) is a second-order partial differential equation. To determine a unique solution, the following boundary conditions (cylindrical coordinates) must also be satisfied:

[0122] It should be noted that T is the product of stress and film thickness, which is the fundamental cause of wafer deformation. Its physical meaning is the torque generated per unit area, referred to here as torque density. Knowing z0 or z1, equations (5) to (9) can be solved using a finite element numerical algorithm to obtain the equivalent stress distribution of the front microstructure, T=T(z) or z=z(T). This embodiment uses a finite element modeling tool to solve this problem. First, a finite element simulation model based on structural mechanics is created, such as... Figures 6-9 As shown, Figure 6 The geometric structure diagram of the back stress membrane simulation model is divided into two parts: the upper part is the wafer substrate 10, and the lower part is the relatively thin stress membrane 11. Figure 7 The geometry is divided into dense nodes. For example... Figure 8 As shown, stress values ​​are first manually assigned to the stress membrane nodes (first, the stress properties of the region are determined macroscopically, and then stress values ​​are assigned to each point microscopically). Then, the calculation is started, and the stress-strain equation is numerically calculated using the finite element method. The resulting wafer deformation under this stress distribution is output, as shown below. Figure 9 As shown.

[0123] The parameters used in this simulation model are shown in Table 2. The simulation parameter settings are completely consistent with the actual parameters, which can effectively ensure the accuracy of the simulation model.

[0124]

[0125] Using the above methods, theoretically any warping can be eliminated. In practical engineering applications, such as... Figures 10-13 As shown, it is usually necessary to address four types of warping: umbrella-shaped, bowl-shaped, potato chip-shaped, and saddle-shaped.

[0126] After solving the problem of deformation calculation, as shown in equation (2), it is necessary to find the optimal torque density distribution T. opt (x,y) such that:

[0127] Although commercial finite element software can be used to optimize T opt(x,y), however, each iteration requires a round of three-dimensional finite element calculation to obtain z(x,y). When the number of subdivided nodes is large, this process requires a large amount of computing power and takes a long time. In practical applications, in order to obtain the results quickly, it is necessary to increase the computing server and software license, which greatly increases the cost of use. In response, this invention proposes a fast optimization method that makes full use of the linear characteristics of the stress-strain equation and obtains the result T of equation (10) quickly without increasing the cost of hardware and software. opt (x,y).

[0128] From equations (5) to (9), we can see that z(T(x,y)) is a linear system, that is:

[0129] Based on extensive measurement and simulation results from actual production lines, wafer warpage mainly manifests as follows: Figure 7 The figure shows four types of warpage: umbrella-shaped, bowl-shaped, potato chip-shaped, and saddle-shaped. As can be seen from the figure, from an angular perspective, the warpage is on both sides of the X direction and on both sides of the Y direction. The warpage direction and magnitude are symmetrical and suitable for description by cos(2θ) curves. From a radial perspective, the circumferential warpage is suitable for description by polynomial curves. Therefore, the polar coordinate expression shown in equation (12) describes the circumferential warpage:

[0130] Equation (13) consists of two terms, the first of which is Ar 2 That is, it is a centrally symmetric warping, and the corresponding moment density T can be obtained from equation (3); observe the second term Br 2 cos(2θ) is the product of r squared and the cosine of 2θ. A and B are the coefficients of these two terms, with units of m. -1 Since z(r,θ) and T(r,θ) are linear systems, the input T(r,θ) can be decomposed into the product of an even power polynomial of r and an even multiple of the cosine of θ, i.e.:

[0131] Here, T(r,θ) represents the three-dimensional distribution of torque density, a i and b j a is a coefficient i The unit is N / m 2i+1 b j is a dimensionless constant. Therefore, T(x,y) is decomposed into (n+1)(m+1) terms. It should be noted that n and m can be unequal. Furthermore, extensive simulation experience shows that when n and m are too large, the gradient becomes too large, making convergence during finite element analysis more likely. Therefore, their sizes should be limited according to the model.

[0132] when ai =1, b j When =1, the matrix shown in Table 3 is formed, and each element in the matrix represents an independent three-dimensional torque distribution.

[0133]

[0134] For each moment density distribution in Table 3, as shown in Equation (17), the corresponding three-dimensional deformation is calculated using finite element software:

[0135] Where i = 0, 1, 2, ..., n; j = 0, 1, 2, ..., m; The deformable surface matrix shown in Table 4 is obtained, where each element represents an independent three-dimensional deformable surface.

[0136]

[0137] For the target deformable surface -z0(x,y), a linear superposition fitting can be performed using the basic deformation array in Table 4:

[0138] dimensionless coefficient sequence p ij It can be determined by the least squares method. It should be noted that equation (5) determines the mechanical relationship between torque density and deformation, and the function is linear. The physical dimension coefficients in the equation ensure that the units on both sides of the equation are the same, so that they are not only equal in value, but also show the force equilibrium condition in the static state. Based on this principle, the torque density and deformation in equations (17) and (18) satisfy the physical dimension coefficients of equation (5), which are normalized into iterable deformation elements z in the finite element calculation process. ij dimensionless coefficient p ij .

[0139] According to the principle of linear superposition shown in equation (11), p ij It satisfies both the superposition of deformation and the superposition of moment density, thus producing the stress distribution T of deformation -z0(r,θ). opt (r,θ) can be determined as:

[0140] The proof is as follows: According to equation (11), we can obtain:

[0141] According to equation (12), we can obtain:

[0142] Therefore T optThe deformation produced by (r,θ) is equal to -z0(r,θ), which satisfies the optimization objective.

[0143] Simulation results show that the larger m and n are, the smaller the fitting error of equation (18) and the better the warp elimination effect, but the longer the calculation time. Based on experience, m=2 and n=2 can meet the accuracy requirements. Then, the deformation of the nine models is solved using the finite element method. Only one calculation is needed. For different initial warps, only the least squares method needs to be used to solve equation (17). The calculation speed of this algorithm is very fast. Compared with the iterative optimization of the finite element model, this method significantly reduces the computational power requirement and calculation time, and has strong engineering application value. It should be noted that T opt (r,θ) is a continuous three-dimensional surface. From the perspective of process feasibility, it needs to be discretized into a finite number of numerical distributions, usually two, one of which is 0.

[0144] To provide a more intuitive description of the 3D warpage diagram, this embodiment introduces a planar diagram and defines the warpage direction: "+" and "-" are used in the four directions along the X and Y axes of the wafer to represent upward and downward warpage, respectively. For example, Figure 10 It curves downwards in both the x and y directions, therefore it is represented by four "-" signs. Accordingly, Figure 13 The saddle-shaped warp curves upward in the x-direction and downward in the y-direction, so a "+" sign is used in the x-direction and a "-" sign is used in the y-direction.

[0145] for Figure 10 and Figure 11 The umbrella-shaped and bowl-shaped wafers shown are axially symmetric, so only a single uniform stress film needs to be deposited on the back side of the wafer. The film thickness h can be obtained using equation (3). f The product T of the film thickness and stress σ is used to select the optimal combination of film thickness and stress based on actual process considerations, economic efficiency, and cost-effectiveness.

[0146] for Figure 12 and Figure 13 The potato chip-shaped and saddle-shaped warpages shown are analyzed. Considering the feasibility of engineering implementation, this embodiment, after optimization using a simulation model, concludes that the optimal solution to eliminate front-side warpage is to form an arc-shaped stress film on the back side of the wafer. The parameters describing the arc-shaped stress film are as follows: Figure 14 As shown, the bow width (d) x1 , d x2 ), (d y1 , d y2 The geometry is uniquely determined by (T) x1 , T x2 ), (T y1 , T y2This describes the product of stress and membrane thickness. When the width of the arc-shaped stress membrane is large, adjacent arc-shaped stress membranes will contact each other, at which point their geometry changes. Figure 15 As shown, the boundaries between adjacent films are oblique lines at 45° and 135° passing through the center of the wafer. In actual processes, warping in the x and y directions is generally symmetrical; therefore, two stress films in the same direction are also symmetrical, i.e., d x1 =d x2 T x1 =T x2 d y1 = d y2 T y1 =T y2 However, asymmetric situations may arise under special processes, in which case all eight parameters in the four groups will be different. Therefore, the problem is transformed into a single-objective multivariable optimization problem under constraints: Optimization goal:

[0147] Constraints:

[0148] Where, σ lim and h f_lim These represent the stress and thickness limits achievable by thin film deposition processes.

[0149] The above problem can be solved using the fast algorithm proposed above, or using general algorithms such as genetic algorithm, particle swarm optimization, gradient descent, and simulated annealing. The optimized T value and the bow width d are determined by the initial warping morphology. After more than a large number of simulations (e.g., 100 times), the following clear conclusions are drawn: (1) The warping in the x direction of the front side is corrected by the arc-shaped stress membrane distributed in the y direction of the back side. The warping in the y direction of the front side is corrected by the arc-shaped stress membrane distributed in the x direction of the back side. (2) If the front side warps upwards, a tensile stress film is deposited on the back side; if the front side warps downwards, a compressive stress film is deposited on the back side. (3) The wider the arc-shaped film on the back, the greater the correction for warping on the front; however, new local spherical deformations are easily generated in the film-covered area, such as... Figure 16 As shown, this will cause a series of process problems such as failure of the machine to adsorb the wafer, wafer breakage, reduced or failed photolithography alignment accuracy, and poor consistency of critical dimensions; (4) Based on point (3) above, within the process capability of thin film deposition, and without affecting other subsequent processes, the total stress T value of the thin film should be increased as much as possible, that is, the film stress and thickness should be increased to reduce the width of the arc-shaped film and weaken the local spherical deformation effect. It should be noted that experiments show that, due to the limitations of chemical vapor deposition process capability, the T value is not directly proportional to the film thickness, that is, as the film thickness increases, the stress will decrease and the T value will tend to saturate.

[0150] Based on the above conclusions, such as Figures 17-22 As shown, for different warping patterns, corresponding combinations of arc-shaped stress membranes in both the x and y directions should be used. Types one through four are potato chip-shaped warping, while types five and six are saddle-shaped warping.

[0151] Type 1: The front x-axis region warps upwards, while the front y-axis region has no warping; to reduce front x-warping: deposit an arc-shaped tensile stress film 111 at both ends of the y-axis on the back side of the wafer; Category 2: The front x-axis region warps downwards, while the front y-axis region has no warping: Reduce front x-warping: Deposit an arc-shaped compressive stress film 112 at both ends of the y-axis on the back side of the wafer; Category 3: No warping in the front x-axis region, but upward warping in the front y-axis region; Reduce front y-warping: Deposit bow-shaped tensile stress film 111 at both ends of the back x-axis of the wafer; Category 4: No warping in the front x-axis region, downward warping in the front y-axis region, reducing front y-warping: depositing an arc-shaped compressive stress film 112 at both ends of the back x-axis of the wafer; Fifth type: The front x-axis region warps downward and the front y-axis region warps upward, reducing the front xy warping: Deposit bow-shaped tensile stress film 111 at both ends of the back x-axis of the wafer, and at the same time deposit bow-shaped compressive stress film 112 at both ends of the back y-axis. Category 6: The front x-axis region warps upward and the front y-axis region warps downward, reducing the front xy warping: an arc-shaped compressive stress film 112 is deposited at both ends of the back x-axis of the wafer, and an arc-shaped tensile stress film 111 is deposited at both ends of the back y-axis.

[0152] Step S13: Create an arc-shaped stress film on the back side of the wafer. The stress film is distributed in an arc shape in the four quadrants near the circumference on the back side of the wafer.

[0153] Based on the dimensions of the arc-shaped stress film on the back side of the wafer determined in step S12, it can be fabricated using chemical vapor deposition, photolithography, and etching processes. This embodiment provides the following three fabrication methods to manufacture... Figure 21 Taking the stress membrane shown as an example, the following preparation methods are included: like Figure 23 As shown, a tensile stress film is first deposited on the back side of the wafer using chemical vapor deposition (CVD). Then, photolithography is used to precisely define the areas containing excess film. Finally, etching removes the excess film, forming an arc-shaped tensile stress film 111. This process is repeated to further fabricate an arc-shaped compressive stress film 112 in the y-axis region on the back side of the wafer. This method can be implemented using a conventional CVD system.

[0154] like Figure 24As shown, a thin-film deposition system with back-side regional deposition capability is used to deposit two types of fan-shaped stress films on the back side of the wafer in a single pass: fan-shaped tensile stress films are deposited at both ends of the x-axis region on the back side, and fan-shaped compressive stress films are deposited at both ends of the y-axis region on the back side. Then, a single photolithography and etching process removes the film in the central rectangular region, forming an arc-shaped tensile stress film 111 and an arc-shaped compressive stress film 112 at the top of the x and y axes on the back side of the wafer. This process requires only one round of deposition, photolithography, and etching, which is relatively... Figure 23 The method simplifies the process steps, significantly reducing costs and running time.

[0155] like Figure 25 As shown, using a machine with back-side regional deposition capability, an arc-shaped tensile stress membrane 111 and an arc-shaped compressive stress membrane 112 are deposited on the back side in a single step. This method requires only one step in the process, relatively... Figure 24 The method further simplifies the process steps, reduces costs and running time, and eliminates the need for photolithography and etching, thus supporting the deposition of stress films with larger T values ​​and correcting larger initial warpage.

[0156] Step S14: Measure the deformation distribution data of the optimized wafer.

[0157] Similar to step S11, the warpage morphology of the wafer after back stress film correction is measured.

[0158] Step S15: Determine whether the warpage value of the optimized wafer meets the requirements. If the warpage value of the wafer is less than or equal to the maximum allowable warpage specification of the wafer, then wafer fabrication is performed according to the stress film parameters in step S13. If the warpage value of the wafer is greater than the maximum allowable warpage specification of the wafer, then proceed to step S16.

[0159] Extensive simulations show that, limited by the T-value of the back-side stress film, the corrected wafer may still have some residual warpage. From a practical application perspective, it is sufficient to reduce the warpage to an acceptable range, i.e., the maximum allowable wafer warpage specification. This specification is determined by the following three minimums: the maximum warpage that the robot arm of the subsequent process equipment can accept, the maximum warpage that the photolithography alignment operation can accept, and the maximum warpage that chemical mechanical polishing can accept without wafer breakage. Of course, within the feasible range of the back-side stress film deposition process, the larger the T-value, the better, as it can reduce warpage to a smaller level. However, another factor to consider is that if the arc-shaped stress film is thick, there will be a large step from the edge to the center, which will worsen the wafer flatness and may lead to other problems. To address this, a zero-stress thick film can be deposited again on the back side, followed by planarization using chemical mechanical polishing. In summary, based on extensive experiments, for power device manufacturing processes, the warpage specification is generally set between 150 micrometers and 300 micrometers. The specific value is determined by the process flow of each product platform.

[0160] If the corrected warpage is less than the specification, the warpage improvement method is effective. If the corrected warpage is still greater than the specification, the optimization result of the arc-shaped stress membrane has a large error, the simulation model accuracy is low, and the stress membrane needs to be re-optimized after model correction.

[0161] Step S16: Based on the measurement results of step S14, the parameters of the stress membrane are corrected by reverse calculation, and the parameters of the stress membrane are corrected in the finite element simulation model. Then, steps S12 to S15 are repeated until the warpage value of the wafer is less than or equal to the maximum allowable warpage specification of the wafer.

[0162] Among the parameters of the simulation model, the stress σ in equations (11) and (12) cannot be directly measured in actual engineering. Therefore, the actual parameters are most prone to deviation from the simulation settings, requiring correction of the stress value. The correction method is to deduce the stress σ of the actual deposited stress film based on the measurement results in step S14, and then correct the setting of this parameter in the simulation model. The specific method is as follows: Figure 26 As shown: First, keeping the geometry of the arc-shaped stress membrane unchanged, and comparing it with the simulation results based on the actual measured surface curvature of the wafer in step S14, make targeted adjustments (T). x1 , T x2 ), (T y1 , T y2 The values ​​of the four parameters are then calculated by the model to output a simulated deformed surface. The difference between the maximum and minimum values ​​of this surface is set as B. sim The difference between the simulation results and the measured results yields a surface, and the difference between the maximum and minimum values ​​of this surface is denoted as B. error Used to represent model error, if B error <10% B sim If the model is deemed reasonable, then the above steps are repeated to ensure that condition B is met. error <10% B sim After multiple iterations, (T) x1 , T x2 ), (T y1 ,T y2 The four parameters have been corrected.

[0163] After the simulation model parameters are corrected, steps S12-S15 are executed again to finally complete the warpage correction. The above is a series of interconnected simulation, testing, and correction experiments for improving one type of warpage. Once the optimal solution is determined, the corresponding process parameters for the arc-shaped region of the back-side deposited film, film stress, and film thickness are solidified and inserted into the process following the warpage generation step. For other types of warpage improvement, the above steps are repeated to solidify the improvement process parameters and insert them into the corresponding steps.

[0164] To verify the effectiveness of this invention, a warp improvement experiment was conducted using a 12-inch wafer. Following... Figure 3 The process shown is as follows: 1) During the fabrication of the SGT power device, deep trenches need to be etched on the epitaxial substrate, and a high-temperature thermal oxide film needs to be deposited in the deep trenches. After this step, the wafer exhibits significant saddle-shaped warping. At this point, one wafer is separated from the production line for experimentation. First, the overall wafer morphology is measured, and the results are as follows: Figure 27 As shown, it warps upward in the x-direction with a warping amount of 180 micrometers and downward in the y-direction with a warping amount of -310 micrometers, with an overall warping amount as high as 490 micrometers, which seriously exceeds the specifications of subsequent equipment for wafer warping.

[0165] 2) According to Figures 17-22 This warping belongs to the sixth type; therefore, a compressive stress film is deposited in the x-direction and a tensile stress film in the y-direction. The parameters of the arc-shaped stress film are determined using a finite element model, as shown in Table 5. The T value is determined by the actual chemical vapor deposition process capability and, after being imported into the simulation model, the width d of the arc-shaped stress film is optimized.

[0166]

[0167] 3) Based on the existing machine capabilities, this experiment uses Figure 23 The method shown fabricates an arc-shaped stress film on the back side of a wafer. First, a film is deposited on the back side of the wafer as shown... Figure 30 The fan-shaped stress membrane shown includes a fan-shaped tensile stress membrane 201 and a fan-shaped compressive stress membrane 202. To observe the effect of the fan-shaped stress membrane on warpage, the wafer deformation at 625 points was measured after this step, and the results are as follows. Figure 28 As shown in the figure, the fan-shaped film reduced the initial warpage from 490 μm to 290 μm. Although the warpage was significantly improved, it still did not meet the warpage specification of 260 μm and additionally produced a large local spherical warpage. Then, photolithography was used to define the central rectangular region, and etching was used to remove the stress film in this region, successfully fabricating the arc-shaped stress film required in Table 3. Figure 31 As shown.

[0168] 4) Measure the amount of warpage after improvement, such as... Figure 29 As shown, the warpage is reduced to 158 μm, significantly less than the specification of 260 μm, leaving a warpage window of up to 102 μm for subsequent processes, which significantly improves the overall robustness of the process.

[0169] 5) Experimental results are as follows Figure 32As shown, the method proposed in this invention reduces warpage by 68%, meeting the requirements of subsequent processes. Furthermore, compared to the fan-shaped stress film solution, this method significantly reduces localized spherical warpage, making it more compatible with photolithography and chemical mechanical polishing processes. Therefore, the feasibility and practical performance of the method proposed in this embodiment are fully verified.

[0170] In summary, the semiconductor wafer and its fabrication method of the present invention have the following beneficial effects: This invention provides a systematic solution to various wafer warpage problems. By depositing stress films with a set geometry in different areas on the back of the wafer, the film generates a deformation that is opposite in direction and equal in magnitude to the initial deformation of the wafer, thereby offsetting the initial deformation. This minimizes warpage at specific steps in the production process and fully ensures product quality and reliability requirements.

[0171] This invention corrects wafer warpage by depositing a stress film on the back side, which has no impact on the front-side devices and will not adversely affect device performance.

[0172] Based on the capabilities of chemical vapor deposition equipment, combined with photolithography and etching processes, this invention proposes a variety of methods for fabricating back-side stress films. In particular, it can simultaneously deposit bow-shaped tensile stress films and bow-shaped compressive stress films in corresponding areas on the back side of the wafer through a regional deposition process. The process is simple, efficient, and has high application value.

[0173] This invention reduces wafer warpage by more than 50%, meeting the requirements of conveying equipment and other devices for wafer warpage.

[0174] The method of this invention can significantly reduce local spherical warping and is very compatible with photolithography and chemical mechanical polishing processes.

[0175] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0176] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a semiconductor wafer, characterized in that, The preparation method includes: A wafer is provided, warpage data of the wafer is measured, and an arcuate stress film is deposited on the back side of the wafer based on the warpage data, wherein the arcuate stress film satisfies the following rules: If there is warping in the x-direction on the front side of the wafer, it is corrected by the arc-shaped stress film distributed in the y-direction on the back side. If there is warping in the y-direction on the front side of the wafer, it is corrected by the bow-shaped stress film distributed in the x-direction on the back side. If the front side of the wafer is warped upwards, a tensile stress film is deposited on the back side of the wafer; If the front side of the wafer is warped downwards, a compressive stress film is deposited on the back side of the wafer.

2. The method for preparing a semiconductor wafer according to claim 1, characterized in that: Adjacent arch-shaped stress membranes are separated from each other, or when adjacent arch-shaped stress membranes are in contact with each other, the boundary line between adjacent arch-shaped stress membranes is a 45° and 135° oblique line passing through the center of the wafer.

3. The method for preparing a semiconductor wafer according to claim 1, characterized in that, The configuration of the bow-shaped stress film is selected from one of the following combinations based on the initial warpage type of the wafer: Type 1: If the x-axis region on the front side of the wafer is warped upwards and the y-axis region on the front side is not warped, then an arc-shaped tensile stress film is deposited at both ends of the y-axis on the back side of the wafer. The second type: If the x-axis region on the front side of the wafer warps downward and the y-axis region on the front side does not warp, then an arch-shaped compressive stress film is deposited at both ends of the y-axis on the back side of the wafer. The third type: If the front x-axis region of the wafer is not warped and the front y-axis region is warped upward, then an arc-shaped tensile stress film is deposited at both ends of the back x-axis of the wafer. Category 4: If the front x-axis region of the wafer is not warped, but the front y-axis region warps downward, then an arched compressive stress film is deposited at both ends of the back x-axis of the wafer. Fifth type: If the front x-axis region of the wafer warps downward and the front y-axis region warps upward, then an arc-shaped tensile stress film is deposited at both ends of the back x-axis of the wafer, and an arc-shaped compressive stress film is deposited at both ends of the back y-axis. Category 6: If the x-axis region on the front side of the wafer warps upward and the y-axis region on the front side warps downward, then an arc-shaped compressive stress film is deposited at both ends of the x-axis on the back side of the wafer, and an arc-shaped tensile stress film is deposited at both ends of the y-axis on the back side.

4. The method for preparing a semiconductor wafer according to claim 3, characterized in that, The preparation of the fifth or sixth type of arc-shaped stress membrane includes the following steps: 1) Deposit a tensile stress film on the back side of the wafer, then use photolithography to define the area where the excess film is located, and then remove the excess tensile stress film by etching to form the desired bow-shaped tensile stress film; 2) Deposit a compressive stress film on the back side of the wafer, then use photolithography to define the area where the excess film is located, and then remove the excess compressive stress film by etching to form the desired bow-shaped compressive stress film.

5. The method for preparing a semiconductor wafer according to claim 3, characterized in that, The preparation of the fifth or sixth type of arc-shaped stress membrane includes the following steps: By using a regional deposition process, fan-shaped tensile stress films and fan-shaped compressive stress films are deposited simultaneously on the back side of the wafer in the corresponding regions. The tensile stress films and compressive stress films in the central rectangular region are removed by photolithography and etching processes, forming the desired bow-shaped tensile stress films and bow-shaped compressive stress films on the back side of the wafer.

6. The method for preparing a semiconductor wafer according to claim 3, characterized in that, The preparation of the fifth or sixth type of bow-shaped stress film includes the following steps: simultaneously depositing a bow-shaped tensile stress film and a bow-shaped compressive stress film on the corresponding area on the back side of the wafer using a regional deposition process.

7. The method for preparing a semiconductor wafer according to any one of claims 4 to 6, characterized in that: After preparing the arc-shaped tensile stress membrane and the arc-shaped compressive stress membrane, the following steps are also included: A zero-stress film is deposited on the back side of the wafer, the thickness of which is greater than the thickness of the bow-shaped tensile stress film and the bow-shaped compressive stress film; The zero-stress membrane is planarized using a chemical mechanical polishing process.

8. The method for preparing a semiconductor wafer according to claim 1, characterized in that: Within the capabilities of thin film deposition processes, the width of the bow-shaped stress film can be reduced by increasing the stress and / or thickness of the bow-shaped stress film.

9. A semiconductor wafer prepared by the method for preparing a semiconductor wafer according to any one of claims 1 to 8, characterized in that, The semiconductor wafer includes: A wafer, wherein an arcuate stress film is deposited on the back side of the wafer, wherein the arcuate stress film satisfies the following rule: If there is warping in the x-direction on the front side of the wafer, it is corrected by the arc-shaped stress film distributed in the y-direction on the back side. If there is warping in the y-direction on the front side of the wafer, it is corrected by the bow-shaped stress film distributed in the x-direction on the back side. If the front side of the wafer is warped upwards, a tensile stress film is deposited on the back side of the wafer; If the front side of the wafer is warped downwards, a compressive stress film is deposited on the back side of the wafer.

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