Method for optimizing silicon through hole grinding

Abstract

The invention discloses a method for optimizing silicon through hole grinding. The method comprises the following steps: forming a silicon through hole in a silicon substrate; filling the bottom of the silicon through hole with a dielectric layer in advance; then filling a conductive material therein; and finally, thinning the back surface of the silicon substrate. In the thinning process, the dielectric layer serves as a grinding auxiliary layer and is used for adjusting the grinding rate difference between the conductive material and the silicon substrate, and finally the dielectric layer is removed to expose the conductive material. Through the method, the step difference generated after thinning due to material hardness difference is effectively reduced, the surface flatness after the back surface of the silicon through hole is exposed is remarkably improved, the subsequent process is facilitated, and the product yield and reliability are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for optimizing the polishing of through-silicon vias. Background Technology

[0002] Through-Silicon Vias (TSV) technology is one of the key technologies for achieving three-dimensional chip integration. This technology creates vertically penetrating conductive channels on a silicon wafer, enabling vertical electrical interconnections between multiple layers of chips. Compared to traditional two-dimensional packaging technologies such as wire bonding and flip-chip bonding, TSV technology significantly shortens the interconnect path length between chips, thereby reducing signal transmission delay, parasitic resistance and capacitance, reducing power consumption, and improving chip integration density and data transmission bandwidth. Especially in applications with extremely high signal integrity requirements, such as radio frequency (RF) devices, TSV technology can construct the shortest signal path, thus maximizing the optimization of device RF performance.

[0003] During the fabrication of TSVs, conductive materials, such as copper (Cu) or tungsten (W), are typically filled into the etched vias to form conductive pillars. Subsequently, the back side of the wafer needs to be thinned, for example by grinding or chemical mechanical polishing (CMP), until the conductive material at the bottom of the TSV is exposed for subsequent external interconnection.

[0004] However, existing thinning methods face a significant technical challenge when the hardness of the conductive material filling the TSV is significantly higher than that of the surrounding silicon substrate. Taking tungsten (W) as an example, its hardness is much higher than that of single-crystal silicon. During back-side thinning, due to the selectivity of the polishing process, the removal rate of the harder conductive material is typically lower than that of the less hard silicon. This results in exposed conductive pillars protruding significantly from the surrounding silicon surface at the polishing endpoint, forming a significant "step height." This uneven surface morphology negatively impacts subsequent process steps, such as photolithography, dielectric deposition, and metal wiring, and may even lead to device failure, thus affecting product yield and reliability.

[0005] Therefore, the industry urgently needs a new method to solve the step difference problem caused by the hardness difference between the conductive material and the silicon substrate during the thinning process, thereby improving the surface flatness after the back side of the TSV is exposed.

[0006] To address the aforementioned issues, a novel method for optimizing through-silicon via (TSV) polishing needs to be proposed. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide an optimized method for grinding through-silicon vias, which aims to overcome the defect in the prior art of significant step difference caused by the hardness difference between the conductive material and the silicon substrate when thinning the back side of through-silicon vias filled with high-hardness conductive material, thereby improving the flatness of the back side after thinning.

[0008] To achieve the above and other related objectives, the present invention provides a method for optimizing through-silicon via (TSV) polishing, comprising:

[0009] Step 1: Form through-silicon vias in the silicon substrate;

[0010] Step 2: Pre-fill the bottom of the through-silicon via with a dielectric layer;

[0011] Step 3: Fill the through-silicon vias containing the dielectric layer with conductive material; and

[0012] Step 4: Thin the side of the silicon substrate away from the opening of the through-silicon via (TSV) to remove the dielectric layer and expose the conductive material at the bottom of the TSV.

[0013] Preferably, the conductive material is tungsten.

[0014] Preferably, the dielectric layer comprises at least one of oxides or nitrides.

[0015] Preferably, the oxide is silicon oxide.

[0016] Preferably, in step two, the silicon oxide is a silicon oxide layer formed using a tetraethoxysilane source by plasma-enhanced chemical vapor deposition.

[0017] Preferably, the nitride is silicon nitride.

[0018] Preferably, in step four, the thinning process includes at least one of mechanical grinding and chemical mechanical polishing.

[0019] As described above, the optimized through-silicon via (TSV) polishing method of the present invention has the following beneficial effects:

[0020] This invention introduces a dielectric layer with specific polishing properties between the conductive material and the back side of the ultimately polished silicon substrate. This dielectric layer acts as a polishing aid or sacrificial layer during the thinning process, effectively buffering the mechanical and chemical interactions between the conductive material (such as tungsten) with its significantly different hardness and the silicon substrate, thus making the material removal rate more uniform across the entire surface. Therefore, this method can significantly reduce or even eliminate the step difference between the conductive material and the silicon substrate after thinning, resulting in a highly flat back side morphology. This excellent flatness provides an ideal substrate for subsequent processes such as back side passivation and redistribution layer (RDL) fabrication, thereby widening the process window and improving device manufacturing yield and final electrical performance and reliability. Attached Figure Description

[0021] Figure 1 The diagram shown is a schematic representation of the process flow of the present invention.

[0022] Figure 2 The diagram shown illustrates the filling of conductive material into a silicon via filled with a dielectric layer according to the present invention.

[0023] Figure 3 The diagram shows a thinning process performed on the side of the silicon substrate away from the opening of the through-silicon via (TSV) according to the present invention. Detailed Implementation

[0024] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0025] This invention provides an optimized method for polishing through-silicon vias (TSVs), aiming to solve the problem of step differences on the back side after thinning caused by the hardness difference between the conductive material and the silicon substrate in the prior art. By pre-setting a dielectric layer at the bottom of the TSV before filling with conductive material, and using this dielectric layer as a polishing aid layer in the final thinning step, the flatness of the back side after thinning can be significantly improved.

[0026] Please see Figure 1 The method may include the following steps:

[0027] Step 1: Form a silicon via in the silicon substrate 101. For example, via structures with a predetermined depth and width can be etched in the silicon substrate 101 using conventional semiconductor processes such as deep reactive ion etching (DRIE). These vias will serve as channels for subsequent vertical interconnects.

[0028] Step 2: A dielectric layer 102 is pre-filled at the bottom of the through-silicon via. This dielectric layer 102 acts as a buffer and transition in the subsequent thinning process. Its hardness or chemical reactivity in the chemical mechanical polishing solution is specially selected to harmonize the difference in polishing rate between the high-hardness conductive material 103 and the relatively soft silicon substrate 101 in the subsequent thinning steps, thereby laying the foundation for finally obtaining a flat surface.

[0029] In some embodiments, the dielectric layer 102 comprises at least one of oxides or nitrides, whose physical and chemical properties are suitable for use as a polishing aid layer or sacrificial layer in subsequent thinning steps.

[0030] In some embodiments, the oxide is silicon oxide. Silicon oxide, particularly silicon oxide formed by chemical vapor deposition, has good filling properties and uniformity, and its hardness is between that of common conductive materials such as tungsten and silicon, enabling it to achieve an ideal smooth transition during the polishing process.

[0031] In some embodiments, in step two, the silicon oxide is a silicon oxide layer formed using a tetraethoxysilane (TEOS) source via plasma-enhanced chemical vapor deposition (PECVD). Using TEOS as a precursor for PECVD deposition allows for the acquisition of dense and uniform silicon oxide films at relatively low temperatures. This low-temperature process has minimal impact on the thermal budget of the device structure already present on the silicon substrate 101, thus exhibiting good process compatibility.

[0032] In some embodiments, the nitride is silicon nitride. Silicon nitride is also a common dielectric material with high hardness and excellent chemical stability. It can be used as an effective polishing control layer in specific chemical mechanical polishing processes to obtain a flat surface by adjusting its polishing selectivity ratio with conductive material 103 and silicon.

[0033] Step 3: Fill the through-silicon via (TSV) filled with dielectric layer 102 with conductive material 103 to form a structure as shown in the figure. Figure 2 The structure shown is illustrated. The conductive material 103 will form the conductive core of the through-silicon via (TSV), enabling vertical electrical interconnections between different layers of the chip.

[0034] In some embodiments, the conductive material 103 is tungsten. Tungsten was chosen as the conductive material 103 because it has low resistivity, good step coverage, and excellent anti-electromigration properties, making it a commonly used through-silicon via (TSV) filling metal in high-performance devices. However, it is precisely because of tungsten's high hardness that a severe grinding step difference occurs between it and the silicon substrate 101 in the prior art. The method of the present invention can specifically address the challenges posed by this particular material combination.

[0035] Step 4: Thin the side of the silicon substrate 101 away from the opening of the through-silicon via (TSV) to remove the dielectric layer 102 and expose the conductive material 103 at the bottom of the TSV, forming a structure as shown in the figure. Figure 3 The structure is shown. During the thinning of the back side of the silicon substrate 101, the dielectric layer 102 at the bottom of the through-silicon via acts as a polishing aid or sacrificial layer, effectively buffering the differences in mechanical and chemical interactions between the high-hardness conductive material 103 and the low-hardness silicon substrate 101. This makes the overall surface removal rate tend to be uniform during the polishing process. When the polishing reaches its end, the dielectric layer 102 is completely removed, and the top surface of the finally exposed conductive material 103 can remain highly flat with the surrounding back side of the silicon substrate 101, significantly reducing or even eliminating the step differences that are common in conventional processes, which can be as high as tens or even hundreds of nanometers. Finally, a flat and smooth back side morphology is obtained, which greatly improves the process window for subsequent processes (such as back passivation layer deposition, photolithography and fabrication of redistribution layers (RDLs), etc.), thereby improving the manufacturing yield of the entire 3D integrated chip and the performance and reliability of the final product.

[0036] In some embodiments, step four includes at least one of mechanical polishing and chemical mechanical polishing (CMP). In practice, mechanical polishing is typically used first for rapid, large-scale thinning to bring the silicon substrate 101 to near-target thickness, followed by CMP for final, fine planarization to obtain a higher quality surface. The method proposed in this invention effectively improves the final surface flatness, whether in mechanical polishing or CMP processes alone, or in a combined thinning process.

[0037] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0038] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for optimizing through-silicon via (TSV) polishing, characterized in that, At least including: Step 1: Form through-silicon vias in the silicon substrate; Step 2: Pre-fill the bottom of the through-silicon via with a dielectric layer; Step 3: Fill the through-silicon vias containing the dielectric layer with conductive material; and Step 4: Thin the side of the silicon substrate away from the opening of the through-silicon via (TSV) to remove the dielectric layer and expose the conductive material at the bottom of the TSV.

2. The method for optimizing through-silicon via (TSV) grinding according to claim 1, characterized in that: The conductive material is tungsten.

3. The method for optimizing through-silicon via (TSV) grinding according to claim 1, characterized in that: The dielectric layer includes at least one of oxides or nitrides.

4. The method for optimizing through-silicon via (TSV) grinding according to claim 3, characterized in that: The oxide is silicon oxide.

5. The method for optimizing through-silicon via (TSV) grinding according to claim 4, characterized in that: In step two, the silicon oxide is a silicon oxide layer formed using a tetraethoxysilane source by plasma-enhanced chemical vapor deposition.

6. The method for optimizing through-silicon via (TSV) grinding according to claim 3, characterized in that: The nitride is silicon nitride.

7. The method for optimizing through-silicon via (TSV) grinding according to claim 1, characterized in that: In step four, the thinning process includes at least one of mechanical grinding and chemical mechanical polishing.

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