Semiconductor structure and manufacturing method thereof
By etching sharp-angled grooves on a beveled substrate and epitaxially growing a first epitaxial layer, the problem of high dislocation density in III-V compound semiconductor films was solved, improving crystal quality and device performance.
Patent Information
- Application Number
- CN202410585135.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-11
- Publication Date
- 2025-11-11
AI Technical Summary
In existing technologies, III-V compound semiconductor films have high dislocation densities, which leads to device performance degradation and failure.
A beveled substrate is used, and multiple grooves are etched on it. The bottom wall and sidewall of the groove form an acute angle. When the first epitaxial layer is grown, the sidewall is used to terminate the extension of dislocations, thereby reducing the dislocation density.
By etching sharp-angled grooves on a beveled substrate, the dislocation density of the semiconductor structure is effectively reduced, thereby improving crystal quality and device performance.
Smart Images
Figure CN120933243A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor structure and its fabrication method. Background Technology
[0002] With the development of science and technology, III-V compound semiconductors, with gallium nitride (GaN), gallium arsenide (GaAs), and indium phosphide (InP) as typical representatives, have gradually become a research hotspot. They are suitable for manufacturing high-speed, high-frequency, high-power, and light-emitting electronic devices, and therefore have broad application prospects.
[0003] There are still many problems to be solved in the epitaxial growth of III-V compounds on substrates, such as lattice mismatch between materials, polar / nonpolar effects, and large differences in thermal expansion coefficients, which can easily cause dislocations in heteroepitaxial growth. The dislocations are mainly line dislocations in the
[0001] crystal orientation. When the thickness of the III-V compound semiconductor film reaches the critical value, cracks are prone to occur, causing device performance degradation and failure. Summary of the Invention
[0004] In view of this, embodiments of this application provide a semiconductor structure and a method for fabricating the same, in order to solve the technical problem of a large number of dislocations in semiconductor film layers in the prior art.
[0005] According to one aspect of this application, a semiconductor structure is provided. The semiconductor structure includes: a beveled substrate, the beveled substrate including an upper surface and a lower surface located opposite each other, a plurality of grooves formed from the upper surface; a first epitaxial layer located within the grooves; wherein the groove includes a bottom wall end, and a first sidewall and a second sidewall located on both sides of the bottom wall end and opposite each other, the first included angle formed by the bottom wall end and the first sidewall is an acute angle.
[0006] According to another aspect of this application, a method for fabricating a semiconductor structure is provided. The method includes: providing a beveled substrate, the beveled substrate including opposing upper and lower surfaces; etching a plurality of grooves from the upper surface, each groove including a bottom wall end and opposing first and second sidewalls located on both sides of the bottom wall end, the first included angle formed by the bottom wall end and the first sidewall being an acute angle; and epitaxially fabricating a first epitaxial layer inside and outside the grooves.
[0007] This application provides a semiconductor structure and a method for fabricating the same. The semiconductor structure includes a beveled substrate with an upper and lower surface facing each other. A plurality of grooves are formed on the upper surface. Each groove includes a bottom wall end and a first sidewall and a second sidewall located on both sides of the bottom wall end and facing each other. The first included angle formed by the bottom wall end and the first sidewall is an acute angle. During epitaxial growth, a first epitaxial layer grows epitaxially from the bottom wall end. The first sidewall can terminate the extension of some dislocations and reduce the dislocation density of the semiconductor structure. Attached Figure Description
[0008] Figure 1 This is a schematic diagram of a semiconductor structure provided in one embodiment of this application;
[0009] Figure 2 for Figure 1 A schematic diagram of the oblique-angled substrate structure;
[0010] Figure 3 This is a schematic diagram of another beveled substrate provided in an embodiment of this application;
[0011] Figure 4 An enlarged schematic diagram of the structure of a beveled substrate surface provided in an embodiment of this application;
[0012] Figure 5 This is a schematic diagram of another semiconductor structure provided in an embodiment of this application;
[0013] Figure 6 This is a schematic diagram of another semiconductor structure provided in an embodiment of this application;
[0014] Figure 7 This is a schematic diagram of another semiconductor structure provided in an embodiment of this application;
[0015] Figure 8 A three-dimensional structural schematic diagram of a beveled substrate provided in an embodiment of this application;
[0016] Figure 9 A three-dimensional structural schematic diagram of a beveled substrate provided in an embodiment of this application;
[0017] Figures 10 to 13 This is a schematic diagram of an intermediate structure for fabricating a semiconductor structure according to an embodiment of this application. Detailed Implementation
[0018] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.
[0019] To reduce the dislocation density of semiconductor structures, this application provides the following technical solution:
[0020] Figure 1 This is a schematic diagram of a semiconductor structure provided in one embodiment of this application. Figure 2 for Figure 1 A schematic diagram of the beveled substrate structure is shown in the figure. Figure 1 and Figure 2 As shown, the semiconductor structure includes: a beveled substrate 10, which includes an upper surface 201 and a lower surface 202 facing each other, and a plurality of grooves 20 formed from the upper surface 201; a first epitaxial layer 31 located in the grooves 20; wherein the grooves 20 include a bottom wall end 23, and a first sidewall 21 and a second sidewall 22 located on both sides of the bottom wall end 23 and facing each other, and the first included angle β1 formed by the bottom wall end 23 and the first sidewall 21 is an acute angle.
[0021] Specifically, such as Figure 1 and Figure 2 As shown, the first included angle β1 formed by the bottom wall end 23 and the first sidewall 21 is an acute angle. In other words, in the projection direction perpendicular to the bottom wall end 23, at least part of the orthographic projection of the first sidewall 21 will fall within the bottom wall end 23. Since the extension direction of the dislocation is perpendicular to the plane where the bottom wall end 23 is located and is the same as the epitaxial growth direction of the first epitaxial layer 31, when the first epitaxial layer 31 is grown at the bottom wall end 23 of the groove 20, the first sidewall 21 can terminate the extension of part of the dislocation (e.g., dislocation A), thereby reducing the dislocation density of the semiconductor structure.
[0022] In one embodiment, such as Figure 2 As shown, the plane where the bottom wall end 23 is located is not parallel to the upper surface 201 of the beveled substrate 10. Optionally, the upper surface of the beveled substrate 10 is a (111) crystal plane with a bevel. When forming the groove 20, the bottom wall end 23 is etched to form a (111) crystal plane without a bevel. Therefore, the plane where the bottom wall end 23 is located is not parallel to the plane where the surface of the beveled substrate 10 near the second epitaxial layer 32 is located.
[0023] Optionally, such as Figure 2 As shown, the plane containing the bottom wall end 23 extends towards the upper surface 201 in the direction M, which is on a different side of the vertical axis Z from the extension direction N1 of the groove 20 towards the upper surface 201. The vertical axis Z is perpendicular to the plane containing the beveled substrate 10. Specifically, as shown... Figure 2 As shown, in a groove 20, the vertical axis Z extends vertically upward, the extension direction M is located to the left of the vertical axis Z and extends obliquely upward, and the extension direction N1 is located to the right of the vertical axis Z and extends obliquely upward. At this time, the extension direction M and the extension direction N1 form a second included angle β2.
[0024] Optionally, Figure 3This is a schematic diagram of another beveled substrate provided in an embodiment of this application, as shown below. Figure 3 As shown, the plane containing the bottom wall end 23 extends towards the upper surface 201 in the direction M, and the groove 20 extends towards the upper surface 201 in the direction N2, which is located on the same side of the vertical axis Z. The vertical axis Z is perpendicular to the plane containing the beveled substrate 10. Specifically, as shown... Figure 3 As shown, in a groove 20, the vertical axis Z extends vertically upward, and the extension direction M and the extension direction N2 are both located to the left of the vertical axis Z and extend obliquely upward. At this time, the extension direction M and the extension direction N2 form the first included angle β1.
[0025] Combination Figure 2 and Figure 3 The plane containing the bottom wall end 23 of the two beveled substrates extends in the same direction M toward the upper surface 201, controlling the etching direction of the groove 20. In the first case, the etching direction is along the extension direction N1, which is located on a different side of the vertical axis Z from the extension direction M, to obtain... Figure 2 The first type is a beveled substrate; the second type involves etching along an extension direction N2 that is on the same side of the vertical axis Z as the extension direction M, to obtain... Figure 3 The obliquely cut substrate is shown.
[0026] It should be noted that, taking the upper surface of the beveled substrate 10 as an example, which has a (111) crystal plane with a beveled angle, as... Figure 2 As shown, <111> The crystal orientation extends along a direction perpendicular to the plane where the bottom wall end 23 is located, and the depth direction of the groove 20 within the beveled substrate 10 is opposite to the extension direction N1. <111> The crystal orientation and the depth direction of groove 20 are not collinear. Similarly, as Figure 3 As shown, <111> The crystal orientation and the depth direction of the groove 20 are not collinear.
[0027] It should be noted that the first angle β1 formed by the extension directions M and N2 is smaller than the second angle β2 formed by the extension directions M and N1. Figure 3 The obliquely cut substrate shown is more conducive to reducing the dislocation density of semiconductor structures.
[0028] Optionally, Figure 4 This is an enlarged schematic diagram of the structure of a beveled substrate surface provided in an embodiment of this application, as shown below. Figure 4 As shown, the upper surface 201 of the beveled substrate 10 has many microsteps. When the second epitaxial layer 32 is epitaxially grown, the microsteps will merge, resulting in dislocations B( Figure 1 The dislocations (as shown in the image) are deflected, preventing them from extending to the surface, thereby further reducing the dislocation density.
[0029] In one embodiment, such as Figure 1As shown, the semiconductor structure also includes a second epitaxial layer 32, which is located on the upper surface 201 of the beveled substrate 10 and is healed with the first epitaxial layer 31. Specifically, the second epitaxial layer 32 can be epitaxially grown from the upper surface 201 of the beveled substrate 10 and the first epitaxial layer 31.
[0030] In one embodiment, Figure 5 This is a schematic diagram of another semiconductor structure provided in an embodiment of this application, as shown below. Figure 5 As shown, from the lower surface 202 of the beveled substrate 10 to the upper surface 201, the second epitaxial layer 32 includes an N-type semiconductor layer 302, an active layer 303, and a P-type semiconductor layer 304 stacked sequentially. The N-type semiconductor layer 302, the active layer 303, and the P-type semiconductor layer 304 fabricated on the beveled substrate 10 have a low dislocation density, which improves the crystal quality of the semiconductor structure and thus improves the luminous efficiency of the final fabricated light-emitting device.
[0031] Optionally, taking the second epitaxial layer 32 as an example where the material is GaN-based, the N-type semiconductor layer 302 is N-type GaN, the active layer 303 is a multi-quantum-well layer composed of GaN and GaN-based ternary or quaternary compounds, and the P-type semiconductor layer 304 is P-type GaN. Optionally, such as... Figure 5 As shown, the semiconductor structure also includes a buffer layer 301 located between the beveled substrate 10 and the N-type semiconductor layer 302. The buffer layer 301 is used to heal the epitaxial layer into a flat surface, which facilitates the subsequent fabrication of a flat semiconductor film. Optionally, the first epitaxial layer 31 includes a nucleation layer and a buffer layer. Optionally, Figure 5 The electrode structure is not shown, so the semiconductor structure can be an intermediate structure for fabricating light-emitting devices.
[0032] In one embodiment, Figure 6 This is a schematic diagram of another semiconductor structure provided in an embodiment of this application, as shown below. Figure 6 As shown, from the lower surface 202 of the beveled substrate 10 to the upper surface 201, the second epitaxial layer 32 includes a channel layer 306 and a barrier layer 307 stacked sequentially. The channel layer 306 and barrier layer 307 fabricated on the beveled substrate 10 have a low dislocation density, which improves the crystal quality of the semiconductor structure and improves the power characteristics of the final fabricated power device.
[0033] Optionally, taking the second epitaxial layer 32 as an example where the second epitaxial layer 32 is a GaN-based material, the channel layer 306 is GaN, and the barrier layer 307 is AlGaN. Optionally, such as... Figure 6 As shown, the semiconductor structure also includes a buffer layer 305 located between the beveled substrate 10 and the channel layer 306. The buffer layer 305 is used to heal the epitaxial layer into a flat surface, which facilitates the subsequent fabrication of a flat semiconductor film. Optionally, the first epitaxial layer 31 includes a nucleation layer and a buffer layer.
[0034] Optionally, Figure 4 yes Figure 2 and Figure 3 The microscopic structure of the upper surface 201. It should be noted that in subsequent embodiments, the beveled substrate of the semiconductor structure... Figure 2 The diagram shows the structure.
[0035] In one embodiment, the beveled substrate 10 is any one of single-crystal silicon, single-crystal germanium, single-crystal silicon germanium, single-crystal silicon carbide, and sapphire; and / or, the material of the first epitaxial layer 31 includes any one or a combination of GaN-based materials, GaAs-based materials, and InP-based materials.
[0036] Specifically, single-crystal silicon, single-crystal germanium, single-crystal silicon-germanium, single-crystal silicon carbide, and sapphire can all be used as growth substrates for III-V semiconductor films. For example, single-crystal silicon can be used as a growth substrate for GaN-based materials. Since silicon and GaN have similar lattice constants and coefficients of thermal expansion, the probability of dislocations during the epitaxial growth of GaN-based materials can be reduced. Similarly, single-crystal germanium can be used as a growth substrate for GaAs-based materials.
[0037] Optionally, such as Figure 2 As shown, when the beveled substrate is single-crystal silicon, single-crystal germanium, or single-crystal silicon-germanium, the crystal plane of the beveled substrate 10 is the (111) crystal plane, and the bevel angle ranges from 0.1° to 20°. The (111) crystal plane is more conducive to the subsequent epitaxial growth of the second epitaxial layer 32. Specifically, the beveled angle is obtained by mechanical bevel cutting.
[0038] Optionally, such as Figure 2 As shown, the crystal plane of the bottom wall end 23 is a (111) crystal plane, which is more conducive to the subsequent epitaxial growth of the first epitaxial layer 31. Specifically, the (111) crystal plane of single crystal silicon can be formed by alkaline etching.
[0039] Optionally, such as Figure 2 As shown, when the beveled substrate is a single crystal silicon carbide or sapphire, the crystal plane of the beveled substrate 10 is the (0001) crystal plane, and the bevel angle ranges from 0.1° to 20°. The (0001) crystal plane is more conducive to the subsequent epitaxial growth of the second epitaxial layer 32.
[0040] Specifically, appropriately increasing the bevel angle α can increase the likelihood of dislocations terminating at the sidewall of the via, thereby further reducing the dislocation density of the semiconductor structure; however, when the bevel angle is greater than 30°, the crystal plane of surface 11 will change, resulting in a decrease in the epitaxial rate.
[0041] Optionally, the bevel angle α ranges from 0.2° to 8°. Specifically, due to the physical properties of the substrate and semiconductor material, a small bevel angle α can further improve the dislocation density. Optionally, the bevel angle α can be 0.2°, 0.8°, 1°, 2°, 4°, or 8°, and those skilled in the art can select a suitable bevel angle value according to actual needs. For example, when the beveled substrate is sapphire, the bevel angle is 0.2°; when the beveled substrate is GaN or SiC, the bevel angle is 4°.
[0042] In one embodiment, such as Figure 2 As shown, the second included angle β2 formed by the bottom wall end 23 and the second sidewall 22 is an obtuse angle. Optionally, the first sidewall 21 is parallel to the second sidewall 22. Specifically, the groove 20 is formed by dry etching, forming the first sidewall 21 and the second sidewall 22 that are parallel to each other, and by controlling the etching direction, the second included angle β2 formed by the bottom wall end 23 and the second sidewall 22 is an obtuse angle.
[0043] Optionally, the sum of the first included angle β1 formed by the bottom wall end 23 and the first side wall 21 and the second included angle β2 formed by the bottom wall end 23 and the second side wall 22 is equal to 180°.
[0044] Optionally, the orthographic projection of the first sidewall 21 onto the bottom wall end 23 completely covers the bottom wall end 23. When the first epitaxial layer 31 grows epitaxially inside and outside the groove 20, most of the dislocations perpendicular to the bottom wall end 23 terminate on the first sidewall 21, which can further reduce the dislocation density.
[0045] In one embodiment, Figure 7 This is a schematic diagram of another semiconductor structure provided in an embodiment of this application, as shown below. Figure 7 As shown, along the direction from the lower surface 202 of the beveled substrate 10 to the upper surface 201, the cross-sectional area of the groove 20 gradually decreases in the plane parallel to the beveled substrate 10. Specifically, along the direction from the lower surface 202 of the beveled substrate 10 to the upper surface 201, the groove 20 has inwardly tapering sidewalls that terminate at least some of the dislocations C and D in the first epitaxial layer 31, preventing them from extending into the first epitaxial layer 31 to the minimum cross-sectional area of the groove 20, thereby reducing the dislocation density.
[0046] Optionally, such as Figure 7As shown, the third included angle β3 formed by the bottom wall end 23 and the second sidewall 22 is an acute angle. Specifically, in the direction perpendicular to the plane where the beveled substrate 10 is located, the cross-sectional shape of the groove 20 is similar to a trapezoid, and at least some dislocations are terminated by the first sidewall 21 and the second sidewall 22. For example, dislocation C is terminated by the first sidewall 21, and dislocation D is terminated by the second sidewall 22. Therefore, the higher the proportion of the orthographic projection of the first sidewall 21 and the second sidewall 22 covering the bottom wall end 23, the better the effect of improving the dislocation problem. Optionally, the first included angle β1 formed by the bottom wall end 23 and the first sidewall 21 is equal to the third included angle β3 formed by the bottom wall end 23 and the second sidewall 22. Optionally, the first included angle β1 formed by the bottom wall end 23 and the first sidewall 21 is not equal to the third included angle β3 formed by the bottom wall end 23 and the second sidewall 22.
[0047] Optionally, Figure 8 This is a three-dimensional structural diagram of a beveled substrate provided in an embodiment of this application, as shown below. Figure 8 As shown, the grooves 20 within the beveled substrate 10 are strip-shaped and spaced apart. Optionally, Figure 9 This is a three-dimensional structural diagram of a beveled substrate provided in an embodiment of this application, as shown below. Figure 9 As shown, the grooves 20 in the beveled substrate 10 are inclined cylindrical and arranged at intervals; alternatively, the grooves 20 are inclined hexagonal prisms or other cylindrical shapes.
[0048] One embodiment of this application also provides a method for fabricating a semiconductor structure. Figures 10 to 13 This is a schematic diagram of an intermediate structure for fabricating a semiconductor structure according to an embodiment of this application, such as... Figures 10 to 13 As shown, the manufacturing method includes:
[0049] Step S1, as follows Figure 10 As shown, a beveled substrate 10 is provided, which includes an upper surface 201 and a lower surface 202 opposite to each other.
[0050] Specifically, the beveled substrate 10 can be commercially available, or it can be a substrate with a specific crystal plane that is then beveled to obtain the beveled angle α, with the beveled angle α ranging from 0.1° to 20°. Further, the beveled angle α ranges from 0.2° to 8°.
[0051] Step S2, as follows Figure 2 As shown, a plurality of grooves 20 are etched from the upper surface 201. The grooves 20 include a bottom wall end 23, and a first side wall 21 and a second side wall 22 located on both sides of the bottom wall end 23 and opposite to each other. The first included angle β1 formed by the bottom wall end 23 and the first side wall 21 is an acute angle, which allows at least part of the projection of the first side wall 21 in the plane where the bottom wall end 23 is located to fall within the bottom wall end 23.
[0052] Optionally, in step S2, a plurality of grooves 20 are etched from the upper surface 201, including:
[0053] Step S21, as follows Figure 11 As shown, a patterned mask layer 12 is formed on one side of the beveled substrate 10. The mask layer 12 includes a plurality of openings 121 that expose the beveled substrate 10. Optionally, the mask layer 12 is made of silicon oxide, and the openings 121 are formed by photolithography.
[0054] Step S22, as follows Figure 12 As shown, a groove 20 is formed by etching the beveled substrate 10 in the opening 121, and the opening 121 of the mask layer is connected to the groove 20.
[0055] Specifically, such as Figure 13 As shown, by controlling the dry etching angle, the bottom included angle of the groove 20 is first made acute; then, through other processes, the bottom included angle of the groove 20 is made into a first included angle β1. Optionally, when the beveled substrate 10 is single-crystal silicon, single-crystal germanium, or single-crystal silicon-germanium, after obtaining the following... Figure 12 Following the groove 20 shown, the process further includes: treating the groove 20 with an alkaline solution to obtain, as shown... Figure 13 The intermediate structure of the semiconductor structure shown makes the crystal plane of the bottom wall end 23 a (111) crystal plane, which is more conducive to the epitaxial growth of the subsequent epitaxial layer.
[0056] Optionally, step S23, as Figure 2 As shown, the mask layer 12 is removed to obtain the beveled substrate 10 with grooves 20.
[0057] Step S3, as follows Figure 1 As shown, a first epitaxial layer 31 is epitaxially fabricated inside and outside the groove 20. Specifically, the first included angle β1 formed by the bottom wall end 23 and the first sidewall 21 is an acute angle. In other words, in the projection direction perpendicular to the bottom wall end 23, at least part of the orthographic projection of the first sidewall 21 will fall inside the bottom wall end 23. Since the extension direction of the dislocation is perpendicular to the plane where the bottom wall end 23 is located and is the same as the epitaxial growth direction of the first epitaxial layer 31, when the first epitaxial layer 31 is grown at the bottom wall end 23 of the groove 20, the first sidewall 21 can terminate the extension of part of the dislocation (e.g., dislocation A), thereby reducing the dislocation density of the semiconductor structure.
[0058] This application provides a semiconductor structure and a method for fabricating the same. The semiconductor structure includes a beveled substrate with an upper and lower surface facing each other. A plurality of grooves are formed on the upper surface. Each groove includes a bottom wall end and a first sidewall and a second sidewall located on both sides of the bottom wall end and facing each other. The first included angle formed by the bottom wall end and the first sidewall is an acute angle. During epitaxial growth, a first epitaxial layer grows epitaxially from the bottom wall end. The first sidewall can terminate the extension of some dislocations and reduce the dislocation density of the semiconductor structure.
[0059] It should be understood that the term "comprising" and its variations as used in this application are open-ended, meaning "including but not limited to". The term "one embodiment" means "at least one embodiment". Specific features, structures, materials, or characteristics described in this specification may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.
Claims
1. A semiconductor structure, characterized in that, include: A beveled substrate, the beveled substrate including opposing upper and lower surfaces, with a plurality of grooves formed from the upper surface; A first epitaxial layer is located within the groove; The groove includes a bottom wall end, and a first side wall and a second side wall located on both sides of the bottom wall end and opposite to each other. The first included angle formed by the bottom wall end and the first side wall is an acute angle.
2. The semiconductor structure according to claim 1, characterized in that, The second included angle formed by the bottom wall end and the second side wall is an obtuse angle.
3. The semiconductor structure according to claim 2, characterized in that, The first sidewall is parallel to the second sidewall.
4. The semiconductor structure according to claim 1, characterized in that, Along the direction from the lower surface of the beveled substrate to the upper surface, the cross-sectional area of the groove gradually decreases in the plane parallel to the beveled substrate.
5. The semiconductor structure according to claim 4, characterized in that, The third included angle formed by the bottom wall end and the second side wall is an acute angle.
6. The semiconductor structure according to claim 1, characterized in that, The plane containing the bottom wall end is not parallel to the upper surface of the beveled substrate.
7. The semiconductor structure according to claim 6, characterized in that, The plane at the bottom wall end extends toward the upper surface in a direction that is on a different side of the vertical axis from the direction in which the groove extends toward the upper surface. The vertical axis is perpendicular to the plane at the beveled substrate.
8. The semiconductor structure according to claim 6, characterized in that, The plane at the bottom wall end extends toward the upper surface in the same direction as the groove extending toward the upper surface on the same side of the vertical axis, which is perpendicular to the plane of the beveled substrate.
9. The semiconductor structure according to claim 1, characterized in that, The beveled substrate is any one of single-crystal silicon, single-crystal germanium, single-crystal silicon-germanium, single-crystal silicon carbide, and sapphire; and / or, The material of the first epitaxial layer includes any one or a combination of GaN-based materials, GaAs-based materials, and InP-based materials.
10. The semiconductor structure according to claim 9, characterized in that, When the beveled substrate is a single-crystal silicon, single-crystal germanium, or single-crystal silicon-germanium, the crystal plane of the beveled substrate is the (111) crystal plane, and the beveled angle of the beveled substrate is in the range of 0.1° to 20°.
11. The semiconductor structure according to claim 10, characterized in that, The crystal plane at the bottom wall end is the (111) crystal plane.
12. The semiconductor structure according to claim 9, characterized in that, When the beveled substrate is a single-crystal silicon carbide or sapphire, the crystal plane of the beveled substrate is the (0001) crystal plane, and the beveled angle of the beveled substrate is in the range of 0.1° to 20°.
13. The semiconductor structure according to claim 1, characterized in that, Also includes: The second epitaxial layer is located on the upper surface of the beveled substrate and is fused with the first epitaxial layer.
14. The semiconductor structure according to claim 13, characterized in that, The second epitaxial layer, in the direction from the lower surface of the beveled substrate to the upper surface, comprises: an N-type semiconductor layer, an active layer, and a P-type semiconductor layer stacked sequentially.
15. The semiconductor structure according to claim 13, characterized in that, The second epitaxial layer comprises, in the direction from the lower surface of the beveled substrate to the upper surface, a channel layer and a barrier layer stacked sequentially.
16. A method for fabricating a semiconductor structure, characterized in that, include: A beveled substrate is provided, the beveled substrate including opposing upper and lower surfaces; Multiple grooves are etched from the upper surface. Each groove includes a bottom wall end and a first side wall and a second side wall located on both sides of the bottom wall end and opposite to each other. The first included angle formed by the bottom wall end and the first side wall is an acute angle. A first epitaxial layer is formed inside and outside the groove.
17. The manufacturing method according to claim 16, characterized in that, The etching of multiple grooves from the upper surface includes: A patterned mask layer is formed on one side of the beveled substrate, the mask layer including a plurality of openings exposing the beveled substrate; The groove is formed by etching the beveled substrate through the opening, and the opening of the mask layer communicates with the groove.
18. The manufacturing method according to claim 17, characterized in that, When the beveled substrate is monocrystalline silicon, monocrystalline germanium, or monocrystalline silicon-germanium, after the groove is formed by etching the opening, the method further includes: The groove is treated with an alkaline solution so that the crystal plane at the bottom wall end is (111) crystal plane.