Embedded power chip packaging structure and preparation method thereof

Abstract

The application provides an embedded power chip packaging structure and a preparation method thereof, which comprises a metal layer provided with a groove; a through hole is arranged at the bottom of the groove; a chip is arranged in the groove; a first sintered metal layer is arranged to connect a lower electrode of the chip and the groove; a resin layer is filled in the groove; an upper electrode copper insert is connected with an upper electrode of the chip; an insulating heat-conducting layer is arranged in the through hole; a second sintered metal layer is arranged between the bottom surface of the chip and the insulating heat-conducting layer; a heat sink is arranged at the bottom of the metal layer; a third sintered metal layer is arranged between the metal layer and the heat sink and is provided with a micro flow channel. The packaging structure replaces the DBC / AMB ceramic substrate with the metal layer, the chip is embedded in the groove of the metal layer and is connected with the groove through the sintered metal layer, the number of intermediate interfaces such as ceramic-soldering / brazing material-metal is reduced, the heat-conducting path is shortened and the junction thermal resistance is reduced; the micro flow channel matched with the heat sink is arranged at the back side of the chip, the junction-to-heat sink thermal resistance is reduced under the high heat flux condition, and the temperature uniformity is improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power chip packaging, and particularly relates to an embedded power chip packaging structure and a preparation method thereof. BACKGROUND

[0002] DBC or AMB ceramic substrates are widely used in traditional power modules. The upper and lower copper layers are convenient for large-current wiring and provide a good heat dissipation path. AMB has an advantage in thermal cycle life compared to some DBC solutions because the interface metal-ceramic "reaction layer / soldering layer" can better buffer thermal stress. In the SiC high dv / dt and high di / dt working condition, the package also needs to reduce the loop inductance and the gate common inductance as much as possible; therefore, low inductance design routes such as laminated busbars, planar interconnections, and leadless packaging have emerged. In recent years, the technology of embedding power chips in PCB and integrating them with laminated copper foils to build current loops and heat dissipation channels has attracted attention. Embedding power semiconductors directly into the PCB cavity can obtain a more compact structure, lower parasitic, and higher integration.

[0003] Despite the above progress, the existing technology still has the following bottlenecks around high-power and high-heat flux density SiC applications, which directly restricts the further improvement of power density and reliability: 1. Thermal conduction bottleneck of resin / glass fiber medium. The chip will generate heat when working, and these heat needs to be conducted away through a certain path. In the conduction process, heat needs to pass through different medium layers or rely on dense thermal holes for conduction, while the base material layer of the PCB usually adopts glass fiber reinforced epoxy resin (such as FR-4), but the thickness direction thermal conductivity of typical FR-4 or high Tg epoxy prepreg is usually in the order of , which is much lower than Ceramics have poor thermal conductivity, and when the heat of the chip needs to pass through the medium layer or rely on dense heat holes for conduction, the junction-shell thermal resistance and hot spots are difficult to further reduce, and the uniformity and processing complexity problems caused by the heat hole-copper foil interface and filler wear. 2. High reliability interconnection and material system compatibility. SiC chips are often used with sintered silver / copper and other high-thermal-conductivity, high-temperature-resistant interconnections to improve power cycle life; but there is compatibility and interface delamination risk between the temperature resistance / hygroscopic expansion of the resin body in the embedded PCB and the sintering process temperature (often ≥200℃), and the deformation mismatch under long-term thermal cycling may also induce failure. 3. Limitations of metal embedded / local heat dissipation structure. There are PCB processes in the industry for copper Coin / metal Inlay and other local heat dissipation paths to more directly guide heat from the chip area to the back heat dissipation member; but this approach is mostly based on metal blocks close to or penetrating the medium, which is still subject to problems such as medium electrical isolation, sidewall insulation treatment, flatness, and stress concentration, making it difficult to balance low thermal resistance, low parasitic, and high voltage resistance / high reliability in high-power SiC scenarios. 4. Coupling conflict between low inductance and high heat dissipation path. Reducing circuit inductance requires the current supply / circuit to be close to the planarization, while improving heat dissipation often requires thick copper / large cross-section / vertical heat conduction channels. In the existing embedded PCB structure, the electrical-thermal path is often separated by a resin medium layer, making it difficult to achieve both extremely low inductance and extremely low thermal resistance, especially in designs where double-sided cooling or high-voltage creepage distance is limited. SUMMARY

[0004] The technical problem solved by the present application is to provide an embedded power chip packaging structure and a preparation method thereof, which uses a metal layer with high thermal conductivity to replace a DBC / AMB ceramic substrate, embeds a chip in a groove of the metal layer, connects the back surface of the chip with the bottom surface of the groove through a sintered metal layer, reduces the number of intermediate interfaces such as ceramic-solder / brazing filler-metal, forms a continuous metal heat conduction chain, shortens the heat conduction path, and significantly reduces the junction thermal resistance; and sets a micro-channel heat dissipation interconnection on the back side of the chip, which can be matched with a heat sink, to reduce the junction-to-ambient thermal resistance and improve temperature uniformity under high heat flux conditions.

[0005] To solve the above problems, one aspect of the present application provides an embedded power chip packaging structure, comprising:

[0006] A metal layer is provided with a groove; the bottom of the groove is provided with a through hole;

[0007] A chip is arranged in the groove of the metal layer and located above the through hole;

[0008] A first sintered metal layer is arranged between the bottom surface of the groove and the back surface of the chip; the lower electrode of the chip is electrically connected with the bottom surface of the groove through the first sintered metal layer;

[0009] A resin layer is filled in the groove;

[0010] an upper electrode copper insert, a bottom of the upper electrode copper insert being electrically connected to an upper electrode of the chip; a top of the upper electrode copper insert being exposed outside the resin layer;

[0011] an insulating and heat-conducting layer, arranged in the through hole;

[0012] a second sintered metal layer, arranged between a bottom surface of the chip and the insulating and heat-conducting layer;

[0013] a heat sink, arranged at a bottom of the metal layer, the heat sink being provided with a plurality of first micro-channels;

[0014] a third sintered metal layer, arranged between the metal layer and the heat sink, the third sintered metal layer being provided with a second micro-channel at a position below the through hole, the second micro-channel being in communication with the first micro-channel at a corresponding position on the heat sink.

[0015] Preferably, the upper electrode copper insert comprises:

[0016] a gate electrode copper insert, a longitudinal section of the gate electrode copper insert being L-shaped; a bottom surface of the L-shaped gate electrode copper insert being electrically connected to a gate electrode of the chip;

[0017] a source electrode copper insert, a longitudinal section of the source electrode copper insert being inverted T-shaped; a bottom surface of the inverted T-shaped source electrode copper insert being electrically connected to a source electrode of the chip.

[0018] Preferably, one side of the recess is provided with a side wall, and the other side is not provided with a side wall; the side wall of the recess is adapted to be connected to an external conductor or busbar.

[0019] Preferably, an electrically insulating layer is arranged between the inner side of the side wall of the recess and the resin layer.

[0020] Preferably, the metal layer is made of copper or copper alloy;

[0021] the first sintered metal layer is made of one of silver, copper and silver-copper composite material;

[0022] the resin layer is made of epoxy resin;

[0023] the heat sink is made of copper, copper alloy or aluminum alloy;

[0024] the insulating and heat-conducting layer is made of one of ceramic and diamond;

[0025] the third sintered metal layer is made of one of silver, copper and silver-copper composite material;

[0026] the electrically insulating layer is one of polyimide film, aluminum oxide thin layer, silicon nitride thin layer and glass fiber reinforced epoxy resin tape.

[0027] Preferably, the thickness of the chip is 150-300 μm;

[0028] The thickness of the first sintered metal layer is 50-100 μm;

[0029] The thickness of the electrically insulating layer is 10-100 μm;

[0030] The thickness of the third sintered metal layer is 100-500 μm;

[0031] The thickness of the bottom surface of the L-shaped gate copper insert is 50-150 μm;

[0032] The thickness of the bottom surface of the inverted T-shaped source copper insert is 100-300 μm;

[0033] The width of the second micro-channel is 100-600 μm; the depth is 100-500 μm; and the pitch is 100-800 μm.

[0034] Another aspect of the present application provides a preparation method of the embedded power chip packaging structure described above, comprising the following steps:

[0035] S1. Machining a groove on a metal block, and machining a through hole at the bottom of the groove;

[0036] S2. Setting a first sintered slurry layer around the through hole on the bottom surface of the groove, then setting a chip on the first sintered slurry layer, and sintering to electrically connect the bottom surface of the groove with the lower electrode of the chip;

[0037] S3. Setting an upper electrode copper insert on the chip, and electrically connecting the bottom of the upper electrode copper insert with the upper electrode of the chip;

[0038] S4. Filling the groove with resin and curing, then performing windowing to expose the surface of the upper electrode copper insert;

[0039] S5. Placing an insulating and heat-conducting layer in the through hole, and sintering and connecting with the bottom surface of the chip through a second sintered slurry layer;

[0040] S6. Setting a third sintered slurry layer on the bottom of the metal block, and setting a second micro-channel on the third sintered slurry layer, the position of the second micro-channel corresponding to the position of the first micro-channel on the heat sink;

[0041] S7. Setting a heat sink on the bottom of the third sintered slurry layer, sintering to form a third sintered metal layer to connect the bottom of the metal block with the heat sink, and obtaining the embedded power chip packaging structure.

[0042] Preferably, an electrically insulating layer is arranged inside the sidewall of the groove before the groove is filled with resin.

[0043] Preferably, in step S2, when the first sintering paste layer is silver, the sintering condition is that the temperature is 220-260 DEG C and the pressure is 5-30 MPa; when the first sintering paste layer is copper, the sintering condition is that the temperature is 230-270 DEG C and the sintering atmosphere is inert atmosphere or reducing atmosphere.

[0044] In step S7, when the third sintering paste layer is silver, the sintering condition is that the temperature is 220-260 DEG C and the pressure is 5-30 MPa; when the third sintering paste layer is copper, the sintering condition is that the temperature is 230-270 DEG C and the sintering atmosphere is inert atmosphere or reducing atmosphere.

[0045] Preferably, before the first sintering paste layer is arranged around the through hole on the bottom surface of the groove, roughening treatment is performed on the bottom surface of the groove around the through hole.

[0046] Compared with the prior art, the application has the following beneficial effects:

[0047] The embedded power chip packaging structure of the application replaces the DBC or AMB ceramic substrate with poor heat conduction performance with a metal layer with higher heat conduction performance, embeds the chip in the groove of the metal layer, and connects the back of the chip with the bottom of the groove through the sintered metal layer. The metal groove directly bears the chip and is connected with the sintered layer. Compared with the DBC or AMB ceramic substrate structure, the number of intermediate interfaces such as "ceramic-soldering / brazing filler-metal" is reduced, a continuous metal heat conduction chain is formed, the heat conduction path is shortened, and the junction thermal resistance is significantly reduced. A micro-channel heat dissipation interconnection that can match the heat sink is arranged on the back of the chip, which not only provides a high-thermal-conductivity metal framework to reduce the interface thermal resistance, but also forms a controlled cooling liquid channel to reduce the junction-to-bottom thermal resistance and improve the temperature uniformity under high heat flux conditions. An insulating heat conduction layer is arranged in the through hole below the groove bottom of the metal layer and below the chip, which establishes a low-thermal-resistance "insulating thermal via / thermal column" channel from the back of the chip to the heat sink / micro-channel on the premise of maintaining electrical insulation: the second sintered metal layer and the third sintered metal layer sequentially form a continuous metal-ceramic (or diamond)-metal heat conduction chain, which significantly shortens the heat path, reduces the junction-to-bottom thermal resistance, and uniformly diffuses the heat points; at the same time, the insulating heat conduction layer blocks the leakage and electrochemical path of the back electrode of the chip to the heat sink / cooling liquid, and provides high voltage resistance and creepage safety.

[0048] The embedded power chip packaging structure of the present application, the upper interconnection adopts copper inserts, without laser drilling and copper plating, reducing the defect sources of hole wall insulation, plating cavity, stress concentration and the like related to drilling and plating, being conducive to size consistency and batch manufacturing stability. The back electrode of the chip forms a metallurgical or quasi-metallurgical connection with the groove bottom surface through the sintering layer, without the need to punch the chip. The external lead-out of the back electrode directly utilizes the groove sidewall metal of the metal layer to abut against the external conductor or busbar, with a short path and few interfaces, reducing additional process steps and potential failure points, while facilitating better current diffusion and mechanical support.

[0049] The embedded power chip packaging structure of the present application, the size of the groove, the geometric size of the micro-channel, the thickness of the upper electrode copper insert and the like parameters can be reused and enlarged according to the chip size and current level; the back side heat dissipation interface can be adapted to water cooling or cold plate and the like standard components, facilitating the coplanar integration with the driving and sensing circuit and the system miniaturization design. BRIEF DESCRIPTION OF DRAWINGS

[0050] Figure 1 is a structural schematic diagram of the embedded power chip packaging structure of embodiment 1 of the present application;

[0051] Figure 2 is a schematic diagram of step 1 in the preparation method of the embedded power chip packaging structure of embodiment 2 of the present application;

[0052] Figure 3 is a schematic diagram of step 2 in the preparation method of the embedded power chip packaging structure of embodiment 2 of the present application;

[0053] Figure 4 is a schematic diagram of step 3 in the preparation method of the embedded power chip packaging structure of embodiment 2 of the present application;

[0054] Figure 5 is a schematic diagram of step 4 in the preparation method of the embedded power chip packaging structure of embodiment 2 of the present application;

[0055] Figure 6 is a schematic diagram of step 5 in the preparation method of the embedded power chip packaging structure of embodiment 2 of the present application;

[0056] Figure 7 is a schematic diagram of step 5 in the preparation method of the embedded power chip packaging structure of embodiment 2 of the present application;

[0057] Figure 8 is a schematic diagram of step 6 in the preparation method of the embedded power chip packaging structure of embodiment 2 of the present application;

[0058] Figure 9This is a schematic diagram of step 7 in the method for preparing the embedded power chip packaging structure according to Embodiment 2 of the present invention;

[0059] Figure 10 This is a schematic diagram of step 8 in the method for preparing the embedded power chip packaging structure according to Embodiment 2 of the present invention.

[0060] Wherein: 1-Metal layer; 2-Groove; 21-Sidewall; 3-Through hole; 4-Chip; 5-First sintered metal layer; 6-Copper pillar; 7-Resin layer; 8-Upper electrode copper insert; 81-Gate electrode copper insert; 82-Source electrode copper insert; 9-Insulating and thermally conductive layer; 10-Second sintered metal layer; 11-Heat sink; 12-First microchannel; 13-Third sintered metal layer; 14-Second microchannel; 15-Electrically insulating layer. Detailed Implementation

[0061] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0062] Example 1

[0063] like Figure 1 As shown in the figure, the embedded power chip packaging structure described in this embodiment includes:

[0064] Metal layer 1, with groove 2 on metal layer 1; through hole 3 at the bottom of groove 2;

[0065] Chip 4 is disposed in the groove 2 of metal layer 1 and located above the through hole 3;

[0066] The first sintered metal layer 5 is disposed between the bottom surface of the groove 2 and the back surface of the chip 4; the lower electrode of the chip 4 is electrically connected to the bottom surface of the groove 2 through the first sintered metal layer 5.

[0067] Resin layer 7 fills the groove 2;

[0068] The upper electrode copper insert 8 has its bottom electrically connected to the upper electrode of the chip 4; the top of the upper electrode copper insert 8 is exposed outside the resin layer 7.

[0069] An insulating and thermally conductive layer 9 is disposed in the through hole 3;

[0070] The second sintered metal layer 10 is disposed between the bottom surface of the chip 4 and the insulating and heat-conducting layer 9;

[0071] The heat sink 11 is located at the bottom of the metal layer 1, and the heat sink 11 is provided with a plurality of first microchannels 12;

[0072] A third sintered metal layer 13 is arranged between the metal layer 1 and the heat sink 11, and a second micro-channel 14 is arranged on the third sintered metal layer 13 at a position below the through hole 3. The second micro-channel 14 is in communication with the first micro-channel 12 at a corresponding position on the heat sink 11.

[0073] The embedded power chip packaging structure of the embodiment uses a metal layer with higher thermal conductivity to replace a DBC or AMB ceramic substrate with poor thermal conductivity. The chip is embedded in a groove in the metal layer, and the back of the chip is connected to the bottom surface of the groove through a sintered metal layer. The metal groove directly bears the chip and is connected to the sintered layer. Compared with the DBC or AMB ceramic substrate structure, the number of intermediate interfaces such as "ceramic - solder / brazing material - metal" is reduced, a continuous metal heat conduction chain is formed, the heat conduction path is shortened, and the junction thermal resistance is significantly reduced. Micro-channel heat dissipation interconnections that can match the heat sink are arranged on the back side of the chip, which not only provides a high-thermal-conductivity metal skeleton to reduce the interface thermal resistance, but also forms a controlled cooling liquid channel, which can reduce the junction-to-ambient thermal resistance and improve temperature uniformity under high heat flux conditions. An insulating and heat-conducting layer is arranged in the through hole below the groove bottom and the chip, which can establish a low-thermal-resistance and controllable-dielectric vertical heat conduction channel under the premise of ensuring electrical insulation and voltage isolation between the back electrode of the chip and the heat sink / cooling liquid. The layer and the sintered metal layers arranged above and below it jointly form a continuous heat conduction chain of "chip back - second sintered metal layer - insulating and heat-conducting layer - third sintered metal layer - heat sink micro-channel", so that the heat flow is directly coupled from the back of the chip to the micro-channel, the heat path is shortened, and the junction-to-ambient thermal resistance is significantly reduced, and the local hot spot is diffused downward to improve temperature uniformity. At the same time, the insulating and heat-conducting layer blocks the conduction and electrochemical path from the back electrode to the heat sink, improving the system's voltage resistance and creepage safety; its dielectric constant and thickness can be selected and designed as required to suppress the parasitic capacitance and common-mode current to the heat sink and reduce EMI under high d𝑣 / d𝑡 conditions. As a "plug body" of the through hole, the layer can also seal and buffer thermal stress, improving the long-term reliability of the micro-channel cold plate and the package in the cold and hot / power cycle process.

[0074] The embedded power chip packaging structure of the embodiment uses a copper insert for the upper interconnection, eliminating the need for laser drilling and copper plating, reducing defect sources such as hole wall insulation, plating layer cavities, and stress concentration related to drilling and plating, and being conducive to size consistency and batch manufacturing stability. The back electrode of the chip is connected to the bottom surface of the groove through a sintered layer, eliminating the need for drilling the chip. The external lead-out of the back electrode directly uses the groove sidewall metal of the metal layer to butt joint with an external conductor or busbar, with a short path and few interfaces, reducing additional process steps and potential failure points, while facilitating better current diffusion and mechanical support.

[0075] The embedded power chip packaging structure of the embodiment can reuse and amplify parameters such as the size of the groove, the geometric size of the micro-channel, and the thickness of the upper electrode copper insert according to the chip size and current level; the back side heat dissipation interface can be adapted to standard components such as water cooling or cold plate, facilitating the coplanar integration of the driving and sensing circuits and the miniaturization design of the system.

[0076] In some embodiments, the material of the metal layer 1 is copper or copper alloy, which serves as a direct channel for chip bearing and heat diffusion. The copper alloy can be copper-molybdenum alloy or copper-tungsten alloy.

[0077] In some embodiments, the thickness of the chip is 150-300 μm. The back metal of the chip can be Ti / Ni / Ag or Ti / Ni / Au barrier layer to inhibit interdiffusion.

[0078] In some embodiments, the upper electrode copper insert 8 includes:

[0079] The gate electrode copper insert 81 has an L-shaped longitudinal section; the bottom surface of the L-shaped gate electrode copper insert 81 is electrically connected to the gate electrode of the chip 4.

[0080] The source electrode copper insert 82 has an inverted T-shaped longitudinal section; the bottom surface of the inverted T-shaped source electrode copper insert 82 is electrically connected to the source electrode of the chip 4.

[0081] The embedded power chip packaging structure of the embodiment uses planarized low-inductance metal inserts on the front surface of the chip for lead-out. The gate electrode is arranged in an L-shaped short path with small cross-section and small loop area to suppress common inductance; the source electrode uses a widened and thickened planarized conductor to bear large current, and a T-shaped reinforcing section is formed in the transition area to increase the bonding area, disperse stress, and improve the shear bearing capacity; the back electrode is directly led out from the groove edge. Compared with traditional wire bonding, the above-mentioned planarized supply or return circuit can significantly reduce the loop area in geometry, which can reduce the loop parasitic inductance by several times and suppress switch overshoot and ringing. Through the above arrangement, efficient heat conduction, low parasitic inductance interconnection, and electrical isolation are realized on the same platform.

[0082] The embedded power chip packaging structure of the embodiment provides a high-rigidity bearing surface through sintered metal layers and metal grooves, and the T-shaped reinforcing section increases the bonding area and disperses stress; the planarized interconnection avoids the necking and fracture failure mode of gold wires or aluminum wires, and the risk of interface peeling in thermal and power cycles is reduced.

[0083] In some embodiments, the bottom surface thickness of the L-shaped gate electrode copper insert is 50-150 μm. The thickness of the bottom surface of the inverted T-shaped source electrode copper insert is 100-300 μm. If necessary, a copper column or other metal column can be provided at the outer end to facilitate the connection with external terminals.

[0084] In some embodiments, the bottom surface of the gate copper insert 81 and the source copper insert 82 is connected to the gate and source of the chip by sintering or brazing.

[0085] In some embodiments, the material of the first sintered metal layer 5 is silver, copper or silver-copper composite material; the thickness of the first sintered metal layer is 50-100 μm.

[0086] In some embodiments, the material of the second sintered metal layer 10 is silver, copper or silver-copper composite material; the thickness of the second sintered metal layer is 50-100 μm.

[0087] In some embodiments, the material of the third sintered metal layer 13 is silver, copper or silver-copper composite material; the thickness of the third sintered metal layer is 100-500 μm. The layer is used for heat conduction and as a sealing connection surface with the heat sink.

[0088] In some embodiments, the width of the second micro-channel in the third sintered metal layer is 100-600 μm; the depth is 100-500 μm; and the pitch is 100-800 μm.

[0089] In some embodiments, the insulating and heat-conducting layer is one of ceramic and diamond.

[0090] In some embodiments, the material of the resin layer is epoxy resin.

[0091] In some embodiments, the material of the heat sink is copper, copper alloy or aluminum alloy. It can be plated with Ni / Au, Ni / Pd / Au or Ti / Ni / Ag to take into account corrosion resistance and connection reliability.

[0092] In some embodiments, an electrically insulating layer 15 is provided between the inner side of the side wall 21 of the groove 2 and the resin layer 7. The electrically insulating layer can be one of polyimide film, aluminum oxide thin layer, silicon nitride thin layer and glass fiber reinforced epoxy resin tape to meet the creepage distance and withstand voltage requirements and reduce thermal stress concentration through structural matching and interface treatment. Preferably, the thickness of the electrically insulating layer is 10-100 μm. The electrically insulating layer can also extend from the groove side wall to the groove bottom wall by about 1 μm.

[0093] In some embodiments, one side of the groove 2 is provided with a side wall 21 and the other side is not provided with a side wall; the side wall 21 of the groove 2 is adapted to be connected to an external conductor or busbar. The back electrode of the chip is electrically connected to the external conductor or busbar by using a side wall on one side, and the other side is not provided with a side wall, which can make printing more convenient.

[0094] Example 2

[0095] This embodiment is a preparation method of the embedded power chip packaging structure of the above-mentioned example 1, which comprises the following steps:

[0096] 1. On the metal block (copper or copper-molybdenum alloy, copper-tungsten alloy), a groove is machined to form a groove with a side wall on one side and no side wall on the other side, and a through hole is machined at the bottom of the groove (the through hole can be machined by CNC, etched or surrounded by four long strip metals sintered into the shape of a through hole); wherein the method of machining the groove can be mechanical machining, etching or die casting. As shown in Figure 2 .

[0097] 2. The bottom of the groove is sandblasted or chemically roughened to enhance the adhesion of the subsequent sintered layer. An electrically insulating layer (such as PI film, aluminum oxide coating, silicon nitride coating or glass fiber reinforced epoxy tape) is provided on the side wall of the groove, preferably 10-100 μm thick, to meet the target creepage distance and withstand voltage requirements. As shown in Figure 3 .

[0098] 3. A sintered metal paste (silver, copper or silver-copper composite) is printed or dispensed on the bottom surface of the groove around the through hole to form a first sintered paste layer, preferably 50-100 μm thick, and then a SiC chip (thickness 150-300 μm) is placed in the groove, with the back electrode of the chip back surface metallurgically or quasi-metallurgically connected to the bottom surface of the groove. When the first sintered paste layer is silver, it is sintered at 220-260℃ and 5-30 MPa, and when the first sintered paste layer is copper, it is sintered at 230-270℃ in an inert or reducing atmosphere. The chip back metal can be Ti / Ni / Ag or Ti / Ni / Au barrier layer to suppress interdiffusion. As shown in Figure 4 .

[0099] 4. Pre-formed upper electrode copper inserts are placed on the front surface of the chip, the gate electrode uses an L-shaped short path structure with a small cross section (preferably 50-150 μm thick), the source electrode uses a widened and thickened planar lead-out (preferably 100-300 μm thick), and a T-shaped reinforcing section is made in the transition area to increase the bonding area and shear bearing capacity. The upper electrode copper inserts are connected to the top gate and source metal of the chip through low-temperature brazing or secondary sintering. If necessary, copper columns 6 or other metal columns are provided at the outer ends to facilitate connection with external terminals. As shown in Figure 5 .

[0100] 5. The gap between the grooves is backfilled or encapsulated with epoxy resin or other equivalent insulating material, and cured at a temperature of 150-180℃ to make the upper surface of the package level, followed by surface leveling and selective windowing to expose the metal surface of the upper electrode copper insert for electrical connection or Ni / Pd / Au plating protection. As shown in Figure 6 , 7 .

[0101] 6. An insulating and heat-conducting layer is placed in the through hole and sintered to the bottom surface of the chip through a second sintered paste layer. As shown in Figure 8 .

[0102] 7. A third sintering paste layer is set on the bottom of the metal block to form a thick layer of sintered metal, and a second micro-channel (with a width of 100-600 μm, a depth of 100-500 μm, and a pitch of 100-800 μm) is obtained by sacrificial template forming-burning-sintering or selective sintering, and the position of the second micro-channel corresponds to the position of the first micro-channel on the heat sink; the thickness of the third sintering paste layer is preferably 100-500 μm. The layer is used for heat conduction and as a sealing connection surface with the heat sink. As shown in Figure 9 .

[0103] 8. A heat sink is set on the bottom of the third sintering paste layer, and sintering is performed to form a third sintered metal layer to connect the bottom of the metal block with the heat sink, and the heat sink is perimetrically sealed with the third sintered metal layer on the back side in a sintering, metal-ceramic composite sealing, or elastic sealing ring manner to form a pressure-bearing cooling liquid channel, wherein the third sintering paste layer is sintered at 220-260 °C and 5-30 MPa when the third sintering paste layer is silver, and the third sintering paste layer is sintered at 230-270 °C in an inert atmosphere or a reducing atmosphere when the third sintering paste layer is copper; the heat sink material can be copper, copper alloy, or aluminum alloy and can be plated with Ni / Au, Ni / Pd / Au, or Ti / Ni / Ag to take into account corrosion resistance and connection reliability. As shown in Figure 10 .

[0104] 9. The back electrode is directly connected with the external copper layer or busbar through the groove sidewall metal, without the need for punching on the chip; the gate and source are respectively connected to the external terminals through their planarized metal inserts or copper pillars. After necessary appearance treatment, cleaning, and electrical / thermal / pressure tests, the finished product is obtained.

[0105] The preparation method of the embedded power chip packaging structure of the embodiment does not use the laser drilling-copper deposition-electroplating process on the top of the chip, but directly connects the pre-formed copper insert with the top layer metal of the chip through sintering or brazing, and then connects with the PCB surface copper or external terminals. This scheme avoids the risk of hole wall insulation and electroplating defects, reduces the thermal or mechanical impact on the chip and resin system, and has a more concise process and is beneficial to size consistency and long-term reliability.

[0106] Obviously, the above embodiments are merely examples for clear illustration, and are not limitations on the embodiments. Based on the above description, other different forms of changes or variations can be made by those of ordinary skill in the art. All embodiments do not need to be exhausted, and obvious changes or variations derived therefrom are still within the protection scope of the present application.

Claims

1. An embedded power chip package structure, characterized by, It comprises: a metal layer, which is provided with a groove; the bottom of the groove is provided with a through hole; a chip, which is arranged in the groove of the metal layer and above the through hole; a first sintered metal layer, which is arranged between the bottom surface of the groove and the back surface of the chip; the lower electrode of the chip is electrically connected to the bottom surface of the groove through the first sintered metal layer; a resin layer, which is filled in the groove; an upper electrode copper insert, the bottom of which is electrically connected to the upper electrode of the chip; the top of the upper electrode copper insert is exposed outside the resin layer; an insulating and heat-conducting layer, which is arranged in the through hole; a second sintered metal layer, which is arranged between the bottom surface of the chip and the insulating and heat-conducting layer; a heat sink, which is arranged at the bottom of the metal layer and is provided with a plurality of first micro-channels; a third sintered metal layer, which is arranged between the metal layer and the heat sink, and is provided with a second micro-channel at a position below the through hole; the second micro-channel is in communication with the first micro-channel at the opposite position on the heat sink.

2. The embedded power chip package structure of claim 1, wherein, The upper electrode copper insert comprises: a gate copper insert, the longitudinal section of which is L-shaped; the bottom surface of the L-shaped gate copper insert is electrically connected to the gate of the chip; a source copper insert, the longitudinal section of which is inverted T-shaped; the bottom surface of the inverted T-shaped source copper insert is electrically connected to the source of the chip.

3. The embedded power chip packaging structure according to claim 1, characterized in that: one side of the groove is provided with a side wall, and the other side is not provided with a side wall; the side wall of the groove is adapted to be connected to an external conductor or busbar.

4. The embedded power chip packaging structure according to claim 2, characterized in that: an electrically insulating layer is arranged between the inner side of the side wall of the groove and the resin layer.

5. The embedded power chip packaging structure according to claim 4, characterized in that: the material of the metal layer is copper or copper alloy; the material of the first sintered metal layer is one of silver, copper and silver-copper composite material; the material of the resin layer is epoxy resin; the material of the heat sink is copper, copper alloy or aluminum alloy; the material of the insulating and heat-conducting layer is one of ceramic and diamond; the material of the third sintered metal layer is one of silver, copper and silver-copper composite material; the electrically insulating layer is one of polyimide film, aluminum oxide thin layer, silicon nitride thin layer and glass fiber reinforced epoxy resin tape.

6. The embedded power chip packaging structure according to claim 4, characterized in that: the thickness of the chip is 150-300 μm; the thickness of the first sintered metal layer is 50-100 μm; the thickness of the electrically insulating layer is 10-100 μm; the thickness of the third sintered metal layer is 100-500 μm; the thickness of the bottom surface of the L-shaped gate copper insert is 50-150 μm; the thickness of the bottom surface of the inverted T-shaped source copper insert is 100-300 μm; the width of the second micro-channel is 100-600 μm; the depth is 100-500 μm; the pitch is 100-800 μm.

7. A method of manufacturing the embedded power chip package structure according to any one of claims 1-6, characterized in that, It comprises the following steps: S1. Machining a groove on a metal block, and machining a through hole at the bottom of the groove; S2. Setting a first sintering slurry layer around the through hole on the bottom surface of the groove, then setting a chip on the first sintering slurry layer, and sintering to make the bottom surface of the groove electrically connected with the lower electrode of the chip; S3. Setting an upper electrode copper insert on the chip, and electrically connecting the bottom of the upper electrode copper insert with the upper electrode of the chip; S4. Filling the groove with resin, and curing, then windowing to expose the surface of the upper electrode copper insert; S5. Placing an insulating and heat-conducting layer in the through hole, and sintering and connecting with the bottom surface of the chip through a second sintering slurry layer; S6. Setting a third sintering slurry layer on the bottom of the metal block, and setting a second micro flow channel on the third sintering slurry layer, the position of the second micro flow channel corresponding to the position of the first micro flow channel on the heat sink; S7. Setting a heat sink at the bottom of the third sintering slurry layer, sintering to form a third sintering metal layer to connect the bottom of the metal block with the heat sink, and obtaining the embedded power chip packaging structure.

8. The preparation method according to claim 7, further comprising, before filling the groove with resin, setting an electrically insulating layer inside the sidewall of the groove.

9. The preparation method according to claim 7, wherein in step S2, when the first sintering slurry layer is silver, the sintering conditions are a temperature of 220-260℃ and a pressure of 5-30MPa; when the first sintering slurry layer is copper, the sintering conditions are a temperature of 230-270℃ and a sintering atmosphere of inert gas or reducing gas; In step S7, when the third sintering slurry layer is silver, the sintering conditions are a temperature of 220-260℃ and a pressure of 5-30MPa; when the third sintering slurry layer is copper, the sintering conditions are a temperature of 230-270℃ and a sintering atmosphere of inert gas or reducing gas.

10. The preparation method according to claim 7, further comprising, before setting the first sintering slurry layer around the through hole on the bottom surface of the groove, roughening the bottom surface of the groove around the through hole. ​ ​ ​

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