Semiconductor laser

Abstract

The present disclosure provides a semiconductor laser including: a semiconductor substrate; a semiconductor laminated part laminated on the surface of the semiconductor substrate; and a first electrode and a second electrode. The semiconductor laminated portion has: an active layer; a first cladding layer located on the semiconductor substrate side with respect to the active layer; and a second cladding layer located on the opposite side from the semiconductor substrate with respect to the active layer, the first cladding layer and the second cladding layer each include an n-type cladding layer, and one of the first cladding layer and the second cladding layer further includes a p-type cladding layer located between the n-type cladding layer and the active layer.

Description

Technical Field

[0001] This disclosure relates to semiconductor lasers. Background Technology

[0002] Japanese Patent Application Publication No. 2007-123837 discloses a semiconductor laser device comprising an active layer having a photoconductive layer, and an n-type cladding layer and a p-type cladding layer disposed therebetween the active layer. The p-type cladding layer has a thickness of approximately 1.5 μm. Summary of the Invention

[0003] In the aforementioned semiconductor lasers, light absorption in the p-type cladding layer becomes a problem. In particular, light absorption in the human eye-safe wavelength range, including wavelengths above 1.4 μm, is problematic. To address this, light absorption in the p-type cladding layer can be suppressed by reducing its thickness; however, as the p-type cladding layer becomes thinner, optical confinement between the n-type and p-type cladding layers may become difficult.

[0004] Therefore, the purpose of this disclosure is to provide a semiconductor laser that can achieve light confinement and suppress light absorption.

[0005] One aspect of the semiconductor laser disclosed herein is, [1] "a semiconductor laser comprising: a semiconductor substrate; a semiconductor stacked on the surface of the semiconductor substrate; and a first electrode and a second electrode, the semiconductor stack having: an active layer; a first cladding layer located on the semiconductor substrate side relative to the active layer; and a second cladding layer located on the opposite side of the semiconductor substrate relative to the active layer, the first cladding layer and the second cladding layer each comprising an n-type cladding layer, one of the first cladding layer and the second cladding layer further comprising a p-type cladding layer located between the n-type cladding layer and the active layer, the first electrode and the second electrode being electrically connected via the other cladding layer of the first cladding layer and the second cladding layer, the active layer and the p-type cladding layer, the thickness of the p-type cladding layer being less than the thickness of the n-type cladding layer in the one cladding layer."

[0006] In this semiconductor laser, the thickness of the p-type cladding layer in one of the first and second cladding layers is less than the thickness of the n-type cladding layer in that cladding layer. Therefore, for example, compared to the case where the entire cladding layer is a p-type cladding layer, the thickness of the p-type cladding layer can be suppressed, and light absorption in the p-type cladding layer can be suppressed. Furthermore, this cladding layer includes an n-type cladding layer in addition to the p-type cladding layer. Therefore, the overall thickness of the cladding layer can be ensured. This achieves good light confinement between the first and second cladding layers. Thus, according to this semiconductor laser, light confinement and light absorption suppression can be achieved.

[0007] One aspect of this disclosure is a semiconductor laser that, [2] "according to the semiconductor laser described in [1] above, further comprises a p-type buried layer that contacts the p-type cladding layer in a direction intersecting the stacking direction of the semiconductor stack, and the first electrode is disposed on the surface of the p-type buried layer opposite to the semiconductor substrate." In this case, the p-type buried layer contacts the p-type cladding layer, and therefore the heat generated by the active layer is dissipated through the p-type buried layer. Thus, the heat dissipation performance can be improved according to this semiconductor laser.

[0008] One aspect of the semiconductor laser disclosed herein can be, [3] "the semiconductor laser according to [2] above, wherein a groove recessed into the active layer is formed on the surface of the second cladding layer opposite to the active layer." For example, when the p-type buried layer is formed in such a manner that it extends across the surface of the second cladding layer, forming a groove on the surface of the second cladding layer in this way can reduce the contact area between the p-type buried layer and the second cladding layer. In this case, leakage current can be suppressed by reducing the current path from the p-type buried layer in the second cladding layer.

[0009] One aspect of this disclosure is a semiconductor laser that can be, [4] "a semiconductor laser according to [1] above, wherein the surface of the p-type cladding layer opposite to the semiconductor substrate includes an exposed area exposed from the semiconductor stack, and the first electrode is disposed in the exposed area." In this case, compared to forming a p-type buried layer and disposing the first electrode in the p-type buried layer, the structure of the semiconductor laser can be simplified and the semiconductor laser can be manufactured more easily.

[0010] One aspect of the semiconductor laser disclosed herein is that it is, [5] "a semiconductor laser according to any one of [1] to [4] above, wherein the semiconductor substrate is made of an n-type semiconductor." In this case, light absorption can be suppressed compared to the case where the semiconductor substrate is made of a p-type semiconductor. Furthermore, in this case, contact can be formed between the semiconductor substrate and the n-type cladding layer.

[0011] One aspect of this disclosure is a semiconductor laser, [6] "a semiconductor laser according to any one of [1] to [5] above, wherein it further comprises a third electrode electrically connected to the first electrode via the n-type cladding layer and the p-type cladding layer in the cladding layer." In this case, a reverse bias voltage is applied to the pn junction formed between the n-type cladding layer and the p-type cladding layer in the cladding layer via the first electrode and the third electrode, thereby increasing the built-in potential in the pn junction. This reliably suppresses carrier leakage from the active layer.

[0012] One aspect of the semiconductor laser disclosed herein may be, [7] "a semiconductor laser according to any one of [1] to [6] above, wherein a pn junction is formed between the n-type cladding layer and the p-type cladding layer in the cladding layer, the thickness of the p-type cladding layer being greater than the thickness of the portion of the depletion layer formed by the pn junction that is formed inside the p-type cladding layer." In this case, it is possible to reliably ensure that no depletion layer is formed in the region of the p-type cladding layer.

[0013] One aspect of the semiconductor laser disclosed herein is that it is, [8] "a semiconductor laser according to any one of [1] to [7] above, wherein the thickness of the p-type cladding layer is less than 1 / 2 of the thickness of the n-type cladding layer in the cladding layer." In this case, light absorption can be reliably suppressed.

[0014] One aspect of the semiconductor laser disclosed herein can be, [9] "a semiconductor laser according to any one of [1] to [8] above, wherein the one coating layer is a first coating layer." In this case, the above-mentioned effects can be well achieved.

[0015] One aspect of the semiconductor laser disclosed herein can be,

[10] "a semiconductor laser according to any one of [1] to [8] above, wherein the one coating layer is a second coating layer." In this case, the above-mentioned effects can be well achieved.

[0016] According to one aspect of this disclosure, a semiconductor laser can be provided that can suppress light absorption while achieving light confinement. Attached Figure Description

[0017] Figure 1 This is a cross-sectional view of the semiconductor laser according to the first embodiment.

[0018] Figure 2 It is a graph showing the relationship between the thickness of the depletion layer and the carrier concentration of the n-type coating layer.

[0019] Figure 3This is a graph showing the relationship between the thickness of the depletion layer and the carrier concentration of the p-type coating layer.

[0020] Figure 4 This is a diagram illustrating carrier block caused by the built-in potential.

[0021] Figure 5 This is a cross-sectional view of the semiconductor laser according to the second embodiment.

[0022] Figure 6 This is a cross-sectional view of the semiconductor laser according to the third embodiment.

[0023] Figure 7 This is a cross-sectional view of the semiconductor laser according to the fourth embodiment.

[0024] Figure 8 This is a cross-sectional view of the semiconductor laser in the first modified example.

[0025] Figure 9 This is a cross-sectional view of the semiconductor laser in the second variation. Detailed Implementation

[0026] Hereinafter, one embodiment of the semiconductor integrated device according to this disclosure will be described in detail with reference to the accompanying drawings. Furthermore, in the description of the drawings, the same reference numerals will be used to label the same elements, and repeated descriptions will be omitted. Hereinafter, a semiconductor having an n-type conductivity type may be referred to as an "n-type semiconductor," and a semiconductor having a p-type conductivity type may be referred to as a "p-type semiconductor."

[0027] [First Implementation Method]

[0028] Figure 1 This is a cross-sectional view of the semiconductor laser according to the first embodiment. As an example, Figure 1 The semiconductor laser 1 shown is excited by a laser with a wavelength of approximately 1550 nm. For example... Figure 1 As shown, the semiconductor laser 1 includes a semiconductor substrate 2, a semiconductor stack 3, a p-type buried layer 4, a first electrode 5, a second electrode 6, and a third electrode 7.

[0029] The semiconductor substrate 2 has a surface 2a and a back surface 2b opposite to the surface 2a. Hereinafter, the direction intersecting the surface 2a and the back surface 2b is defined as the Z direction. In addition, the directions along the surface 2a and the back surface 2b that intersect (orthogonal) each other are defined as the X direction and the Y direction.

[0030] Semiconductor substrate 2 is made of n-type semiconductor. Semiconductor substrate 2 is formed, for example, of a material containing InP. As an example, semiconductor substrate 2 is made of InP. The carrier concentration of semiconductor substrate 2 is, for example, about 3.0 × 10¹⁸ (cm⁻³). The thickness of semiconductor substrate 2 is, for example, about 3500 nm.

[0031] A semiconductor stack 3 is stacked on the surface 2a of a semiconductor substrate 2. The semiconductor stack 3 includes a base 31 and a mesa 32. The base 31 is formed on the surface 2a of the semiconductor substrate 2. The mesa 32 is disposed on a portion of the base 31. The mesa 32 includes a top surface 32a opposite to the semiconductor substrate 2 and the base 31, and a side surface 32b extending from the top surface 32a to the base 31. The top surface 32a intersects (orthogonally) the stacking direction (Z direction) of the semiconductor stack 3. The side surface 32b is curved such that the width of the mesa 32 in the X direction gradually increases as it approaches the base 31 from the top surface 32a along the stacking direction.

[0032] The semiconductor stack 3 has a first cladding layer 41, a guiding layer 42, an active layer 43, a guiding layer 44, a second cladding layer 45, and a contact layer 46 sequentially stacked on the surface 2a of the semiconductor substrate 2. Therefore, the first cladding layer 41 is located on the semiconductor substrate 2 side relative to the active layer 43. Furthermore, the second cladding layer 45 is located on the opposite side of the semiconductor substrate 2 relative to the active layer 43. The first cladding layer 41 and the second cladding layer 45 are cladding layers designed to confine light emitted from the active layer 43 within the guiding layer 42, the active layer 43, and the guiding layer 44 located between the first cladding layer 41 and the second cladding layer 45.

[0033] Here, the base 31 is formed from a portion of the semiconductor substrate 2 side in the first cladding layer 41. The mesa 32 is formed from a portion of the semiconductor substrate 2 opposite to the first cladding layer 41, a guide layer 42, an active layer 43, a guide layer 44, a second cladding layer 45, and a contact layer 46. That is, the first cladding layer 41 is formed from the base 31 to the mesa 32.

[0034] One of the first cladding layer 41 and the second cladding layer 45 includes a p-type cladding layer, while the other cladding layer does not include a p-type cladding layer (here, a p-type semiconductor layer). In this embodiment, the first cladding layer 41 is a cladding layer that includes a p-type cladding layer 52. That is, the first cladding layer 41 includes an n-type cladding layer 51 and a p-type cladding layer 52 sequentially stacked on the surface 2a of the semiconductor substrate 2. The n-type cladding layer 51 has an n-type conductivity. The n-type cladding layer 51 is bonded to the semiconductor substrate 2 and the p-type cladding layer 52. The n-type cladding layer 51 is formed, for example, from a material containing InP. As an example, the n-type cladding layer 51 is made of InP. The carrier concentration of the n-type cladding layer 51 is, for example, about 1.0 × 10¹⁷ (cm⁻³). The thickness of the n-type cladding layer 51 is, for example, about 1500 nm. Although the n-type cladding layer 51 has a different conductivity type than the p-type cladding layer 52 described later, it is formed of a material with the same refractive index as the p-type cladding layer 52.

[0035] The p-type cladding layer 52 has p-type conductivity. The p-type cladding layer 52 is bonded to the n-type cladding layer 51 and the guiding layer 42. The p-type cladding layer 52 is formed, for example, from a material containing InP. As an example, the p-type cladding layer 52 is composed of InP. The carrier concentration of the p-type cladding layer 52 is, for example, about 1.0 × 10¹⁸ (cm⁻³). The thickness of the p-type cladding layer 52 is, for example, about 100 nm. That is, the thickness of the p-type cladding layer 52 is less than the thickness of the n-type cladding layer 51. As an example, the thickness of the p-type cladding layer 52 is less than half the thickness of the n-type cladding layer 51, and further less than one-tenth of the thickness of the n-type cladding layer 51.

[0036] As described above, in this embodiment, the n-type coating layer 51 and the p-type coating layer 52 are bonded together. Thus, a pn junction is formed between the n-type coating layer 51 and the p-type coating layer 52. Furthermore, a depletion layer formed by this pn junction is formed between the n-type coating layer 51 and the p-type coating layer 52. Here, "between the n-type coating layer 51 and the p-type coating layer 52" refers to the region from the side of the n-type coating layer 51 opposite to the p-type coating layer 52 to the side of the p-type coating layer 52 opposite to the n-type coating layer 51. Therefore, although the depletion layer may form inside both the n-type coating layer 51 and the p-type coating layer 52, it is considered here that the depletion layer is formed between the n-type coating layer 51 and the p-type coating layer 52. As described below, in the absence of applied voltage, when the carrier concentration of the n-type coating layer 51 is below 1.0 × 10¹⁸ (cm⁻³) and the carrier concentration of the p-type coating layer 52 is approximately 1.0 × 10¹⁸ (cm⁻³), the maximum thickness of the depletion layer formed inside the p-type coating layer 52 is approximately 30 nm. Therefore, in the absence of applied voltage, the thickness of the p-type coating layer 52 is greater than the thickness of the portion of the depletion layer formed inside the p-type coating layer 52.

[0037] The guide layer 42 is an undoped layer. The guide layer 42 can also have an n-type conductivity. The guide layer 42 is bonded to the p-type cladding layer 52 and the active layer 43. The guide layer 42 is formed, for example, from a material containing InAlGaAs. As an example, the guide layer 42 is made of InAlGaAs. The carrier concentration of the guide layer 42 is, for example, about 5.0 × 10¹⁶ (cm⁻³). The thickness of the guide layer 42 is about 50 nm.

[0038] Active layer 43 is an undoped layer. Active layer 43 can also have n-type conductivity. Active layer 43 is bonded to guide layers 42 and 44. Active layer 43 can, for example, be a multiple quantum well structure consisting of a well layer and a barrier layer. The well layer of active layer 43 may contain, for example, In. x1 Al y1 Ga 1-x1-y1 As (where x1>0, y1≥0, x1+y1<1). As an example, the well layer is composed of InGaAs or InAlGaAs. The barrier layer of the active layer 43 contains, for example, In... x2 Al y2 Ga 1-x2-y2 As (where x2>0, y2>0, x2+y2≤1). As an example, the barrier layer is composed of InAlAs or InAlGaAs. The carrier concentration of the active layer 43 is, for example, about 5.0×1016 (cm-3). The thickness of the active layer 43 is about 100 nm.

[0039] The guiding layer 44 is an undoped layer. The guiding layer 44 may also have an n-type conductivity. The guiding layer 44 is bonded to the active layer 43 and the second coating layer 45. The guiding layer 44 is formed, for example, from a material containing InAlGaAs. As an example, the guiding layer 44 is made of InAlGaAs. The carrier concentration of the guiding layer 44 is, for example, about 5.0 × 10¹⁶ ( / cm⁻³). The thickness of the guiding layer 44 is about 50 nm.

[0040] The second cladding layer 45 has a surface 45a opposite to the semiconductor substrate 2. Surface 45a includes a portion of the top surface 32a and a portion of the side surface 32b along the semiconductor stack 3. The second cladding layer 45 includes an n-type cladding layer 61. That is, the first cladding layer 41 and the second cladding layer 45 each include an n-type cladding layer. In this embodiment, the second cladding layer 45 does not include a p-type cladding layer, but only an n-type cladding layer 61. The n-type cladding layer 61 has an n-type conductivity. The n-type cladding layer 61 (i.e., the second cladding layer 45) is bonded to the guiding layer 44 and the contact layer 46. The n-type cladding layer 61 is formed, for example, of a material containing InP. As an example, the n-type cladding layer 61 is made of InP. The carrier concentration of the n-type cladding layer 61 is, for example, about 1.0 × 10¹⁸ (cm⁻³). The thickness of the n-type cladding layer 61 is, for example, about 1500 nm.

[0041] Contact layer 46 has an n-type conductivity. Contact layer 46 is formed, for example, of a material containing InGaAs. As an example, contact layer 46 is made of InGaAs. The carrier concentration of contact layer 46 is, for example, greater than 5.0 × 10¹⁸ (cm⁻³). The thickness of contact layer 46 is, for example, about 150 nm. Contact layer 46 is bonded to the second cladding layer 45 on one side in the Z direction and exposed to the outside on the other side in the Z direction. Therefore, contact layer 46 has a surface 46a opposite to the semiconductor substrate 2. Surface 46a of contact layer 46 is the top surface 32a of the mesa 32 in the semiconductor stack 3.

[0042] The p-type buried layer 4 is formed on the side surface 32b of the mesa 32 in a manner that it is buried within the mesa 32. The p-type buried layer 4 is in contact with the side surface 32b. The p-type buried layer 4 has a surface 4a that is in contact with the side surface 32b and a surface 4b that is opposite to the surface 4a. The surface 4b is the surface opposite to the semiconductor substrate 2. The p-type buried layer 4 is formed from the n-type cladding layer 51 of the first cladding layer 41 to the contact layer 46. Therefore, the p-type buried layer 4 is in contact with the n-type cladding layer 51, the p-type cladding layer 52, the guiding layer 42, the active layer 43, the guiding layer 44, the n-type cladding layer 61 (i.e., the second cladding layer 45), and the contact layer 46 on the surface 4a. In other words, the p-type buried layer 4 is in contact with the p-type cladding layer 52 in a direction that intersects with the stacking direction in the semiconductor stack 3. The surface 4b is formed along the side surface 32b of the semiconductor stack 3.

[0043] The p-type buried layer 4 has p-type conductivity. The p-type buried layer 4 has a first buried layer 81 and a second buried layer 82 sequentially formed on the side surface 32b of the semiconductor stack 3. The first buried layer 81 includes a surface 4a. The first buried layer 81 is formed, for example, of a material containing InP. As an example, the first buried layer 81 is made of InP. The carrier concentration of the first buried layer 81 is, for example, about 1.0 × 10¹⁸ (cm⁻³). The thickness of the first buried layer 81 is, for example, about 1500 nm. The second buried layer 82 includes the surface 4b of the p-type buried layer 4. The second buried layer 82 is formed, for example, of a material containing InGaAs. As an example, the second buried layer 82 is made of InGaAs. The carrier concentration of the second buried layer 82 is, for example, greater than 5.0 × 10¹⁸ (cm⁻³). The thickness of the second buried layer 82 is, for example, about 150 nm. The thickness of the p-type buried layer 4 is greater than the thickness of the p-type cladding layer 52. Therefore, the formation of the first electrode 5 and the wire connection can be stably performed on the p-type embedded layer 4. Furthermore, the aforementioned thicknesses of the p-type embedded layer 4, the first embedded layer 81, and the second embedded layer 82 refer to the thickness in the stacking direction at a position away from the top surface 32a and at a position where the surface 4b of the p-type embedded layer 4 is parallel (flat) to a surface orthogonal to the stacking direction.

[0044] As described above, when the p-type buried layer 4 is composed of a first buried layer 81 and a second buried layer 82, heat dissipation can be improved while suppressing the increase in resistance. Specifically, by forming the first buried layer 81 and the second buried layer 82 with materials containing InP and InGaAs, which have relatively high thermal conductivity, heat dissipation is improved. Furthermore, by forming the second buried layer 82 with InGaAs, which is less prone to diffusion than the material of the first electrode 5 (described later), the increase in resistance between the first electrode 5 and the second buried layer 82 can be suppressed. Therefore, the p-type buried layer 4 can improve heat dissipation while suppressing the increase in resistance.

[0045] When fabricating ohmic electrodes on a p-type semiconductor composed of InP, electrodes containing AuZn are typically used. However, depending on the formation conditions, the AuZn in this electrode may diffuse within the p-type semiconductor. As a result, the electrode may become a Schottky electrode, potentially affecting lasing characteristics. On the other hand, for p-type semiconductors containing InGaAs, electrodes containing materials such as Ti or Au, which are less prone to diffusion, can be used.

[0046] The first electrode 5 is disposed on the surface 4b of the second buried layer 82 of the p-type buried layer 4. That is, the first electrode 5 is disposed on the surface 4b of the p-type buried layer 4 opposite to the semiconductor substrate 2. The first electrode 5 is formed, for example, of a material containing Ti and Au. The first electrode 5 is formed, for example, of a double-layer structure of Ti layer and Au layer. In addition, the second electrode 6 is disposed on the surface 46a of the contact layer 46. The second electrode 6 is formed, for example, of a material containing Ti and Au. The second electrode 6 is formed, for example, of a double-layer structure of Ti layer and Au layer. The first electrode 5 and the second electrode 6 are electrically connected via the second cladding layer 45, the active layer 43 and the p-type cladding layer 52. Specifically, the first electrode 5 and the second electrode 6 are electrically connected via the p-type buried layer 4, the p-type cladding layer 52, the guiding layer 42, the active layer 43, the guiding layer 44, the n-type cladding layer 61 and the contact layer 46. Thus, a voltage can be applied to the mesa 32 via the first electrode 5 and the second electrode 6.

[0047] The third electrode 7 is disposed on the back side 2b of the semiconductor substrate 2. The third electrode 7 is formed, for example, of a material containing AuGe and Au. The third electrode 7 is formed, for example, of a double-layer structure consisting of an AuGe layer and an Au layer. The third electrode 7 is electrically connected to the first electrode 5 via an n-type cladding layer 51 and a p-type cladding layer 52 in the first cladding layer 41. The third electrode 7 is used to apply a reverse bias voltage to the pn junction formed between the n-type cladding layer 51 and the p-type cladding layer 52 through the first electrode 5 and the third electrode 7. This increases the built-in potential in the pn junction and reliably suppresses carrier leakage from the active layer.

[0048] When the semiconductor laser 1 is operated, a forward bias voltage is applied between the n-type cladding layer 61 and the p-type cladding layer 52 of the semiconductor stack 3 through the first electrode 5 and the second electrode 6, and a reverse bias voltage is applied between the n-type cladding layer 51 and the p-type cladding layer 52 through the first electrode 5 and the third electrode 7. Specifically, voltages are applied to the first electrode 5 and the third electrode 7 in a manner that the voltage applied to the n-type cladding layer 61, the voltage applied to the p-type cladding layer 52, and the voltage applied to the n-type cladding layer 51 increase sequentially. That is, voltages are applied to the first electrode 5 and the third electrode 7 such that the voltage applied to the p-type cladding layer 52 is greater than the voltage applied to the n-type cladding layer 61, and the voltage applied to the n-type cladding layer 51 is greater than the voltage applied to the p-type cladding layer 52.

[0049] As described above, a depletion layer formed by a pn junction is formed between the n-type cladding layer 51 and the p-type cladding layer 52. The verification results of the thickness of the portion of the depletion layer formed inside the p-type cladding layer 52 will be described below. Furthermore, in the following text, the thickness of the portion of the depletion layer formed inside the p-type cladding layer 52 will sometimes be referred to as the "depletion layer thickness of the p-type cladding layer 52".

[0050] Figure 2 This is a graph showing the relationship between the carrier concentration (horizontal axis) of the n-type cladding layer 51 and the thickness (vertical axis) of the depletion layer of the p-type cladding layer 52. Figure 2 The results are shown when the carrier concentration of the p-type coating layer 52 is fixed at 1.0 × 10¹⁸ (cm⁻³) and the carrier concentration of the n-type coating layer 51 is varied. Figure 2 It can be seen that as the carrier concentration of the n-type coating layer 51 increases, the thickness of the depletion layer of the p-type coating layer 52 also increases. Therefore, it can be seen that when the carrier concentration of the n-type coating layer 51 is below 1.0 × 10¹⁸ (cm⁻³), the maximum thickness of the depletion layer is approximately 30 nm. Therefore, in this embodiment, since the carrier concentration of the n-type coating layer 51 is below 1.0 × 10¹⁸ (cm⁻³) and the carrier concentration of the p-type coating layer 52 is approximately 1.0 × 10¹⁸ (cm⁻³), the maximum thickness of the depletion layer of the p-type coating layer 52 is approximately 30 nm. Thus, in order to make the thickness of the p-type coating layer 52 greater than the thickness of the depletion layer, it can be seen that the thickness of the p-type coating layer 52 only needs to be greater than 30 nm.

[0051] Figure 3 This is a graph showing the relationship between the carrier concentration (horizontal axis) of the p-type coating layer 52 and the thickness (vertical axis) of the depletion layer of the p-type coating layer 52. Figure 3 The results are shown when the carrier concentration of the n-type coating layer 51 is fixed at 1.0 × 10¹⁸ (cm⁻³) and the carrier concentration of the p-type coating layer 52 is varied. From... Figure 3It can be seen that as the carrier concentration of the p-type coating layer 52 decreases, the thickness of the portion formed inside the p-type coating layer 52 increases. Furthermore, Figure 3 The dashed line indicates the minimum carrier concentration (5.0 × 10¹⁶ (cm⁻³)) when the p-type cladding layer 52 is used as the contact layer. When the carrier concentration of the p-type cladding layer 52 is at this minimum value, the maximum thickness of the depletion layer of the p-type cladding layer 52 is only about 400 nm. Therefore, as long as the carrier concentration of the p-type cladding layer 52 is above this minimum value, the maximum thickness of the depletion layer of the p-type cladding layer 52 is considered to be only about 400 nm. Furthermore, as... Figure 2 As explained in the text, in this embodiment, since the carrier concentration of the p-type coating layer 52 is 1.0 × 10¹⁸ (cm⁻³), the maximum thickness of the depletion layer of the p-type coating layer 52 is only about 30 nm.

[0052] Figure 4 This is an energy band diagram used to illustrate the built-in potential of a pn structure. The horizontal axis represents the Z-direction position (thickness) in the semiconductor stack 3, and the vertical axis represents energy. For example... Figure 4 As shown, a built-in potential P is generated through the depletion layer formed by the pn junction. This built-in potential P can be used to suppress the leakage of charge carriers from the active layer 43.

[0053] As explained above, in the semiconductor laser 1 of this embodiment, the thickness of the p-type cladding layer 52 in the first cladding layer 41 is less than the thickness of the n-type cladding layer 51 in the first cladding layer 41. That is, in the semiconductor laser 1, the thickness of the p-type cladding layer 52 in one of the cladding layers (the first cladding layer 41 in this embodiment) of the first cladding layer 41 and the second cladding layer 45 is less than the thickness of the n-type cladding layer 51 in that cladding layer. Therefore, for example, compared to the case in this embodiment where the first cladding layer 41 is entirely a p-type cladding layer 52, the thickness of the p-type cladding layer 52 can be suppressed, and the light absorption of the p-type cladding layer 52 can be suppressed. Furthermore, in this embodiment, the first cladding layer 41 includes an n-type cladding layer 51 in addition to the p-type cladding layer 52. Therefore, the overall thickness of the first cladding layer 41 can be ensured. Thus, good light confinement between the first cladding layer 41 and the second cladding layer 45 can be achieved. Therefore, according to this semiconductor laser 1, light absorption can be suppressed while achieving light confinement.

[0054] Here, although the n-type cladding layer 51 in the first cladding layer 41 has a different conductivity type than the p-type cladding layer 52, it is formed of a material with the same refractive index as the p-type cladding layer 52. Therefore, the n-type cladding layer 51 also functions as a cladding layer, and even if the p-type cladding layer 52 is relatively thin, good light confinement can be achieved between the first cladding layer 41 and the second cladding layer 45.

[0055] Furthermore, in the semiconductor laser 1 of this embodiment, a pn junction is formed at the position between the n-type cladding layer 51 and the p-type cladding layer 52 in the first cladding layer 41, and a built-in potential P is generated along with the pn junction. This can suppress the leakage of charge carriers from the active layer 43.

[0056] Furthermore, in the semiconductor laser 1 of this embodiment, the p-type buried layer 4 is in contact with the p-type cladding layer 52. In this structure, because the p-type buried layer 4 is in contact with the p-type cladding layer 52, the heat generated in the active layer 43 is dissipated via the p-type buried layer 4. Therefore, the heat dissipation performance of the semiconductor laser 1 can be improved. Furthermore, the p-type buried layer 4 is in contact with the active layer 43. Therefore, the heat generated in the active layer 43 can be dissipated more effectively via the p-type buried layer 4. In addition, the thickness of the p-type buried layer 4 is greater than the thickness of the p-type cladding layer 52. Therefore, the first electrode 5 or wire connection can be stably formed on the p-type cladding layer 52.

[0057] Furthermore, in the semiconductor laser 1 of this embodiment, the semiconductor substrate 2 is made of an n-type semiconductor. Compared to the case where the semiconductor substrate 2 is made of a p-type semiconductor substrate, light absorption can be suppressed. That is, when the semiconductor substrate 2 is made of a p-type semiconductor, light absorption generated by the semiconductor substrate 2 may occur in either a surface-emitting semiconductor laser or a front-emitting semiconductor laser. On the other hand, in this embodiment, the semiconductor wafer 2 is made of an n-type semiconductor, thus light absorption generated by the semiconductor substrate 2 can be suppressed. Moreover, contact with the n-type cladding layer 51 can be obtained through the semiconductor substrate 2.

[0058] Furthermore, the semiconductor laser 1 of this embodiment also includes a third electrode 7 electrically connected to the first electrode 5 via an n-type cladding layer 51 and a p-type cladding layer 52 in the first cladding layer 41. Therefore, by applying a reverse bias voltage to the pn junction formed between the n-type cladding layer 51 and the p-type cladding layer 52 in the first cladding layer 41 via the first electrode 5 and the third electrode 7, the built-in potential in the pn junction can be increased. This reliably suppresses carrier leakage from the active layer 43.

[0059] Here, as structures for suppressing carrier leakage from the active layer 43, structures with a carrier blocking layer and structures with a multiple quantum barrier (MQB) are known. In the structure with a carrier blocking layer, the height of the barrier formed by the carrier blocking layer may be insufficient. Furthermore, regarding the structure with a multiple quantum barrier, the increased number of crystal interfaces can lead to increased losses when the crystallinity is poor. However, in the semiconductor laser 1 of this embodiment, by applying a reverse bias voltage using the first electrode 5 and the third electrode 7 as described above, the built-in potential of the pn junction can be increased, thus reliably suppressing carrier leakage from the active layer 43 without causing increased losses due to the increased number of crystal interfaces.

[0060] Furthermore, in the semiconductor laser 1 of this embodiment, the thickness of the p-type cladding layer 52 is greater than the thickness of the portion of the depletion layer formed inside the p-type cladding layer 52 in the pn junction formed between the n-type cladding layer 51 and the p-type cladding layer 52 in the first cladding layer 41. Therefore, it is possible to ensure that there is a region in the p-type cladding layer 52 that does not become a depletion layer. Here, the carrier concentration in the p-type cladding layer 52 is made higher than the carrier concentration in the n-type cladding layer 51. Since the depletion layer has the characteristic of easily extending to a layer with a low carrier concentration, it is assumed that even if a reverse bias voltage is applied, the thickness of the portion of the depletion layer formed inside the p-type cladding layer 52 will not increase significantly.

[0061] Furthermore, in the semiconductor laser 1 of this embodiment, the thickness of the p-type cladding layer 52 is less than half the thickness of the n-type cladding layer in a single cladding layer. Therefore, light absorption can be reliably suppressed.

[0062] Furthermore, in the semiconductor laser 1 of this embodiment, the first cladding layer 41 is "a single cladding layer" in both the first cladding layer 41 and the second cladding layer 45. Therefore, the aforementioned effects can be effectively achieved.

[0063] [Second Implementation]

[0064] Figure 5 This diagram illustrates a semiconductor laser 1A according to a second embodiment. Compared to the semiconductor laser 1 of the first embodiment, the semiconductor laser 1A differs from the semiconductor laser 1 in that the first cladding layer 41 does not have a p-type cladding layer 52, while the second cladding layer 45 does have a p-type cladding layer 52. That is, in the semiconductor laser 1A, of the first cladding layer 41 and the second cladding layer 45, the second cladding layer 45 is "one cladding layer" containing the p-type cladding layer 52, while the first cladding layer 41 is "another cladding layer" that does not contain the p-type cladding layer.

[0065] The first cladding layer 41 comprises only an n-type cladding layer 51. The n-type cladding layer 51 (i.e., the first cladding layer 41) is bonded to the semiconductor substrate 2 and the guiding layer 42. The guiding layer 42 is bonded to the n-type cladding layer 51 and the active layer 43. The second cladding layer 45 comprises a p-type cladding layer 52 and an n-type cladding layer 61 sequentially stacked on top of the guiding layer 44. The p-type cladding layer 52 is bonded to the guiding layer 44 and the n-type cladding layer 61.

[0066] In this configuration, the base 31 of the semiconductor stack 3 is formed by an n-type cladding layer 51, a guiding layer 42, an active layer 43, a guiding layer 44, and a p-type cladding layer 52, while the mesa 32 is formed by an n-type cladding layer 61 and a contact layer 46. Furthermore, the n-type cladding layer 51, guiding layer 42, active layer 43, guiding layer 44, and p-type cladding layer 52 do not include the side surface 32b of the mesa 32, while the n-type cladding layer 61 does include the side surface 32b. The p-type buried layer 4 contacts the p-type cladding layer 52 in a direction intersecting the stacking direction of the semiconductor stack 3.

[0067] The first electrode 5 is disposed on the surface 4b of the second buried layer 82 of the p-type buried layer 4. That is, the first electrode 5 is disposed on the surface 4b of the p-type buried layer 4 opposite to the semiconductor substrate 2. The second electrode 6 is disposed on the back surface 2b of the semiconductor substrate 2. The third electrode 7 is disposed on the surface 46a of the contact layer 46.

[0068] The semiconductor laser 1A of the second embodiment described above can also suppress light absorption while achieving light confinement, just like the semiconductor laser 1 of the first embodiment.

[0069] [Third Implementation Method]

[0070] Figure 6 This is a diagram showing a semiconductor laser 1B according to a third embodiment. Compared with the semiconductor laser 1 of the first embodiment, the semiconductor laser 1B differs from the semiconductor laser 1 in that the surface 52c opposite to the semiconductor substrate 2, which does not have a base 31 and a mesa 32, does not have a p-type buried layer 4, and a p-type cladding layer 52, includes an exposed area R that is exposed from the semiconductor stack 3.

[0071] More specifically, in the semiconductor laser 1B, the semiconductor stack 3 includes a first stack 3A and a second stack 3B. The first stack 3A includes a first cladding layer 41 (here composed of the first cladding layer 41) stacked on the surface 2a of the semiconductor substrate 2. The first cladding layer 41 includes a p-type cladding layer 52. The second stack 3B is formed on a portion of the first stack 3A. The second stack 3B includes a guiding layer 42, an active layer 43, a guiding layer 44, a second cladding layer 45, and a contact layer 46 sequentially stacked on the first cladding layer 41.

[0072] The second cladding layer 45 does not contain a p-type cladding layer. That is, in the semiconductor laser 1B, in the first cladding layer 41 and the second cladding layer 45, the first cladding layer 41 is "one cladding layer" that contains a p-type cladding layer 52, and the second cladding layer 45 is "another cladding layer" that does not contain a p-type cladding layer.

[0073] The area of ​​the first stacked portion 3A other than the area where the second stacked portion 3B is disposed is exposed from the semiconductor stacked portion 3. As a result, in the semiconductor laser 1B, the surface 52c of the p-type cladding layer 52 opposite to the semiconductor substrate 2 includes an exposed area R that is exposed from the semiconductor stacked portion 3. The first electrode 5 is disposed in this exposed area R and is in contact with the p-type cladding layer 52.

[0074] The semiconductor laser 1B according to the third embodiment described above can also suppress light absorption while achieving light confinement, similar to the semiconductor laser 1 of the first embodiment. Furthermore, compared to the semiconductor lasers 1 and 1A of the first and second embodiments, which form a p-type buried layer 4 and place the first electrode 5 in the p-type buried layer 4, the semiconductor laser 1B of the third embodiment has a simpler structure and can be formed more easily.

[0075] [Fourth Implementation Method]

[0076] Figure 7 This is a diagram illustrating a semiconductor laser 1C according to a fourth embodiment. Compared to the semiconductor laser 1B of the third embodiment, the semiconductor laser 1C differs from the semiconductor laser 1B in that the first cladding layer 41 does not contain a p-type cladding layer 52, while the second cladding layer 45 does contain a p-type cladding layer 52. That is, in the semiconductor laser 1C, of ​​the first cladding layer 41 and the second cladding layer 45, the second cladding layer 45 is "one cladding layer" containing the p-type cladding layer 52, and the first cladding layer 41 is "another cladding layer" that does not contain a p-type cladding layer.

[0077] The first cladding layer 41 comprises only an n-type cladding layer 51. The n-type cladding layer 51 (i.e., the first cladding layer 41) is bonded to the semiconductor substrate 2 and the guiding layer 42. The guiding layer 42 is bonded to the n-type cladding layer 51 and the active layer 43. The second cladding layer 45 comprises a p-type cladding layer 52 and an n-type cladding layer 61 sequentially stacked on the guiding layer 44. The p-type cladding layer 52 is bonded to the guiding layer 44 and the n-type cladding layer 61.

[0078] In this case, the first stacked portion 3A of the semiconductor stacked portion 3 includes an n-type cladding layer 51, a guiding layer 42, an active layer 43, a guiding layer 44, and a p-type cladding layer 52 sequentially stacked on the surface 2a of the semiconductor substrate 2. The second stacked portion 3B includes an n-type cladding layer 61 and a contact layer 46 sequentially stacked on the p-type cladding layer 52.

[0079] The area of ​​the first stacked portion 3A, excluding the area where the second stacked portion 3B is located, is exposed from the semiconductor stacked portion 3. As a result, in the semiconductor laser 1B, the surface 52c of the p-type cladding layer 52 opposite to the semiconductor substrate 2 includes an exposed area R that is exposed from the semiconductor stacked portion 3. A first electrode 5 is disposed in this exposed area R and contacts the p-type cladding layer 52. A second electrode 6 is disposed on the back surface 2b of the semiconductor substrate 2. A third electrode 7 is disposed on the surface 46a of the contact layer 46.

[0080] The semiconductor laser 1C according to the fourth embodiment described above can also suppress light absorption while achieving light confinement, similar to the semiconductor laser 1 of the first embodiment. Furthermore, compared to the semiconductor lasers 1 and 1A of the first and second embodiments, which form a p-type buried layer 4 and place the first electrode 5 in the p-type buried layer 4, the semiconductor laser 1C of the fourth embodiment has a simpler structure and can be formed more easily.

[0081] [Fifth Implementation]

[0082] Figure 8 This is a diagram showing a semiconductor laser 1D according to a fifth embodiment. Compared with the semiconductor laser 1 of the first embodiment, the semiconductor laser 1D differs from the semiconductor laser 1 in that a groove 45c is formed in the second cladding layer 45.

[0083] A groove 45c is formed on the surface 45a of the second cladding layer 45 opposite to the active layer 43 and on the surface 4a of the p-type buried layer 4. The groove 45c is recessed into the active layer 43. In the illustrated example, the groove 45c is configured to reach the guide layer 44, but it may not reach the guide layer 44 (i.e., the n-type cladding layer 61 may remain). The groove 45c can be formed, for example, by etching. The semiconductor laser 1D can be formed, for example, by forming the groove 45c in the semiconductor laser 1 of the first embodiment at a location including the surface of the surface 45a of the second cladding layer 45 that contacts the p-type buried layer 4.

[0084] The semiconductor laser 1D according to the fifth embodiment described above can, like the semiconductor laser 1 of the first embodiment, suppress light absorption while achieving light confinement. Furthermore, according to the semiconductor laser 1D, compared to the case where the p-type buried layer 4 is formed throughout the surface 45a of the second cladding layer 45 as in the semiconductor laser 1 of the first embodiment, the contact area between the p-type buried layer 4 and the second cladding layer 45 can be reduced. Therefore, leakage current can be suppressed by reducing the current path from the p-type buried layer 4 in the second cladding layer 45.

[0085] [Sixth Implementation Method]

[0086] Figure 9 This is a diagram showing a semiconductor laser 1E according to a sixth embodiment. Compared to the semiconductor laser 1A of the second embodiment, the semiconductor laser 1E differs from the semiconductor laser 1A in that a groove 45c is formed in the second cladding layer 45.

[0087] A groove 45c is formed on the surface 45a of the second cladding layer 45 opposite to the active layer 43 and on the surface 4a of the p-type buried layer 4. The groove 45c is recessed into the active layer 43. In the illustrated example, the groove 45c is configured to reach the p-type cladding layer 52, but it may not reach the p-type cladding layer 52 (i.e., an n-type cladding layer 61 may be left). The groove 45c can be formed, for example, by etching. The semiconductor laser 1E can be formed, for example, by forming the groove 45c in the semiconductor laser 1A of the second embodiment at a location including the surface of the surface 45a of the second cladding layer 45 that contacts the p-type buried layer 4.

[0088] The semiconductor laser 1E of the sixth embodiment can also suppress light absorption while achieving light confinement, similar to the semiconductor laser 1A of the second embodiment. Furthermore, according to the semiconductor laser 1E, compared to the case where the p-type buried layer 4 is formed throughout the surface 45a of the second cladding layer 45 as in the semiconductor laser 1A of the second embodiment, the contact area between the p-type buried layer 4 and the second cladding layer 45 can be reduced. Therefore, leakage current can be suppressed by reducing the current path from the p-type buried layer 4 in the second cladding layer 45.

[0089] [Variation Example]

[0090] This disclosure is not limited to the embodiments and modifications described above. For example, the materials and shapes of each structure are not limited to those described above, and various materials and shapes can be used. For example, the semiconductor substrate 2 may not be an n-type semiconductor, but may be a p-type semiconductor or a semi-insulating semiconductor. The semiconductor lasers 1, 1A to 1D may not have a third electrode 7. The thickness of the p-type cladding layer 52 may not be less than half the thickness of the n-type cladding layer 51 in the first cladding layer 41.

[0091] Between the first cladding layer 41 and the guiding layer 42, a carrier blocking layer may be provided, which is formed of a material having the potential energy to form a high-energy band offset between itself and the guiding layer 42. Furthermore, between the second cladding layer 45 and the guiding layer 44, a carrier blocking layer may be provided, which is formed of a material having the potential energy to form a high-energy band offset between itself and the guiding layer 44.

[0092] Between the n-type cladding layer and the p-type cladding layer 52 in one of the first cladding layer 41 and the second cladding layer 45 (for example, between the n-type cladding layer 51 and the p-type cladding layer 52 in the first embodiment), an undoped semiconductor layer may be formed. At this time, the pn junction formed between the n-type cladding layer and the p-type cladding layer 52 may be formed by laminating the n-type cladding layer and the p-type cladding layer 52 via the undoped semiconductor layer. In addition, an n-type semiconductor that does not function as a cladding layer may be formed between the n-type cladding layer and the p-type cladding layer 52 in one of the cladding layers. At this time, by forming a pn junction between the p-type cladding layer 52 and the n-type semiconductor, a pn junction is formed between the p-type cladding layer 52 and the n-type cladding layer in one of the cladding layers. In this case, the thickness of the p-type cladding layer 52 is also greater than the thickness of the portion formed inside the p-type cladding layer in the depletion layer formed by the pn junction. In addition, a p-type semiconductor that does not function as a cladding layer may be formed between the n-type cladding layer and the p-type cladding layer 52 in one of the cladding layers. At this time, by forming a pn junction between the n-type cladding layer and the p-type semiconductor, a pn junction is formed between the n-type cladding layer and the p-type cladding layer 52 in one of the cladding layers. In this case, the thickness of the p-type cladding layer 52 is also greater than the thickness of the portion formed inside the p-type cladding layer in the depletion layer formed by the pn junction.

[0093] The well layer of the active layer 43 may contain, for example, In 1-x3 Ga x3 As y3 P 1-y3 (where 0 < x3 < 1, 0 < y3 ≤ 1). As an example, the well layer of the active layer 43 may be composed of InGaAs and InGaAsP. The barrier layer of the active layer 43 may contain, for example, InGaAsP. At this time, the guiding layer 42 and the guiding layer 44 may be formed of a material containing InGaAsP, for example.

[0094] The p-type buried layer 4 may not have the second buried layer 82 and may be composed only of the first buried layer 81. In this case, the heat dissipation performance can be improved in the same manner as when the second buried layer 82 is present. In addition, when the p-type buried layer 4 is composed only of the first buried layer 81, the first buried layer 81 may not contain InP or may contain InGaAs. At this time, compared with the case where the p-type buried layer 4 contains InP, the diffusion of the material of the first electrode 5 into the p-type buried layer 4 can be suppressed, thereby suppressing an increase in the current resistance value.

[0095] Semiconductor substrate 2 may contain GaAs. In this case, a semiconductor laser, for example, excites a laser with a wavelength of approximately 940 nm. Furthermore, when semiconductor substrate 2 contains GaAs, the n-type cladding layer 51, p-type cladding layer 52, guide layer 42 and guide layer 44, and n-type cladding layer 61 may, for example, contain AlGaAs. The well layer of active layer 43 may, for example, contain InGaAs. The barrier layer of active layer 43 may, for example, contain AlGaAs. The contact layer 46 may, for example, contain GaAs. The first buried layer 81 of p-type buried layer 4 may, for example, contain AlGaAs. The second buried layer 82 of p-type buried layer 4 may, for example, contain GaAs.

[0096] In the first and second embodiments, the side surface 32b of the mesa 32 of the semiconductor stack 3 may not be curved, or it may be formed along the stacking direction of the semiconductor stack 3. In this case, the surface 4b of the p-type buried layer 4 is the surface opposite to the semiconductor substrate 2, but it may not be the surface opposite to the surface 4a that contacts the side surface 32b. Furthermore, in this case, the groove 45c in the fifth and sixth embodiments may be formed in the portion of the surface 45a of the second covering layer 45 along the top surface 32a of the semiconductor stack 3.

Claims

1. A semiconductor laser, wherein, have: Semiconductor substrate; Semiconductor stacks layered on the surface of the semiconductor substrate; and First electrode and second electrode The semiconductor stack has: Active layer; The first cladding layer located on the semiconductor substrate side relative to the active layer; and The second cladding layer, located on the opposite side of the semiconductor substrate relative to the active layer, The first coating layer and the second coating layer each comprise an n-type coating layer. One of the first and second coating layers further comprises a p-type coating layer located between the n-type coating layer and the active layer. The first electrode and the second electrode are electrically connected via the first coating layer and another coating layer of the second coating layer, the active layer, and the p-type coating layer. The thickness of the p-type coating layer is less than the thickness of the n-type coating layer in the one coating layer.

2. The semiconductor laser according to claim 1, wherein, It also includes a p-type buried layer, which contacts the p-type overlay layer in a direction intersecting the stacking direction of the semiconductor stack. The first electrode is disposed on the side of the p-type buried layer opposite to the semiconductor substrate.

3. The semiconductor laser according to claim 2, wherein, On the surface of the second coating layer opposite to the active layer, a groove is formed that is recessed into the active layer.

4. The semiconductor laser according to claim 1, wherein, The p-type cladding layer, on the side opposite to the semiconductor substrate, includes an exposed area that protrudes from the semiconductor stack. The first electrode is disposed in the exposed area.

5. The semiconductor laser according to any one of claims 1 to 4, wherein, The semiconductor substrate is made of n-type semiconductor.

6. The semiconductor laser according to any one of claims 1 to 5, wherein, It also has a third electrode, which is electrically connected to the first electrode via the n-type coating layer and the p-type coating layer in the one coating layer.

7. The semiconductor laser according to any one of claims 1 to 6, wherein, A pn junction is formed between the n-type cladding layer and the p-type cladding layer in the one cladding layer, wherein the thickness of the p-type cladding layer is greater than the thickness of the portion formed inside the p-type cladding layer in the depletion layer formed by the pn junction.

8. The semiconductor laser according to any one of claims 1 to 7, wherein, The thickness of the p-type coating layer is less than 1 / 2 of the thickness of the n-type coating layer in the one coating layer.

9. The semiconductor laser according to any one of claims 1 to 8, wherein, The coating layer is the first coating layer.

10. The semiconductor laser according to any one of claims 1 to 8, wherein, The first coating layer is the second coating layer.

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