A circuit and method for implementing BMS adaptive load

Abstract

This invention relates to the field of Battery Management Systems (BMS) and provides a circuit and method for implementing BMS adaptive load control. The circuit includes an AFE (Automatic Front-End Controller), a discharge control switch circuit, and a level adjustment circuit. The power supply terminal of the AFE is connected to the positive terminal of the battery pack, and the negative terminal of the battery pack serves as a reference ground. The discharge control switch circuit uses an N-channel MOSFET Q1, with its source connected to the negative terminal of the battery pack, its drain connected to the negative terminal of the load, and the positive terminal of the load connected to the positive terminal of the battery pack. The input terminal of the level adjustment circuit is connected to the PWM output terminal of the MCU, and its output terminal is connected to the gate control node, with the reference ground connected to the negative terminal of the battery pack. When the MCU outputs a PWM signal, the level adjustment circuit modulates the constant high-level gate drive signal provided by the DSG terminal of the AFE, causing the gate of Q1 to obtain a waveform with the same frequency as the PWM, controlling Q1 to periodically turn on and off according to the duty cycle, thereby achieving adaptive load control by the BMS. This invention solves the problem of the AFE lacking PWM functionality, expands the functionality of the BMS with a low-cost circuit design, and is beneficial for full resource utilization and reduced operating costs.

Description

Technical Field

[0001] This invention relates to the technical fields of BMS protection boards and circuit design, and in particular to a circuit and method for realizing BMS adaptive load. Background Technology

[0002] Current BMS protection boards typically lack load matching functionality, and most mature AFE chips do not have built-in PWM functionality in their DSG output. For example, TI's BQ76930 chip (one of the most widely used AFE chips in the industry) cannot output a PWM waveform without new circuit design, thus failing to achieve load matching. Furthermore, it lacks DSG failure control methods for AFE chips. In summary, BMS protection board solutions without load matching functionality present several technical challenges: First, AFE chips lack PWM functionality; second, the validity of AFE chip DSG signals cannot be monitored, and there is a lack of corresponding control methods when AFE chip DSG signals fail; third, they cannot adaptively adapt to different loads, and fail to provide timely alarms when loads exceed their tolerance range.

[0003] Therefore, there is an urgent need in this field for a circuit that enables BMS to adapt to different loads, in order to: 1) add PWM function to AFE chips without PWM function; 2) monitor the validity of DSG signal of AFE chip; 3) add a method for DSG signal failure control of AFE chip; 4) adapt to different loads; 5) provide timely alarm when the load exceeds the adapted load range; 6) have a reasonable and simple circuit, fewer electronic components, convenient installation, low production cost and convenient operation and maintenance. Summary of the Invention

[0004] To address the shortcomings of the existing technologies, this invention provides a circuit and method for implementing adaptive load in a BMS, thereby solving the problem of the lack of PWM function in the front-end analog chip AFE of the current BMS protection board. This facilitates the full utilization of resources, provides secondary protection after chip failure, effectively reduces operating costs, and enhances the safety and reliability of the BMS. It achieves functional expansion and further enhances the safety of lithium battery applications with low-cost circuit design.

[0005] First invention: This invention provides a circuit for implementing BMS adaptive load, comprising:

[0006] The AFE chip has its power supply terminal BAT connected to the positive terminal B+ of the battery pack, and the negative terminal B- of the battery pack used as a reference ground.

[0007] The discharge control switch circuit includes an N-channel MOSFET Q1; the source of Q1 is connected to the negative terminal B- of the battery pack, the drain serves as the discharge path output terminal and is connected to the negative terminal of the load RL, and the positive terminal of the load RL is connected to the positive terminal of the battery pack; the discharge control switch circuit is provided with a gate control node, which is connected to the gate of Q1 through a resistor R8.

[0008] The level adjustment circuit has its signal input terminal connected to the PWM output terminal of the MCU, and its signal output terminal electrically connected to the gate control node. The reference ground is connected to the negative terminal B- of the battery pack. When receiving the PWM signal from the MCU, the level adjustment circuit outputs a periodically pulled-down level adjustment signal to the gate control node to modulate the constant high-level gate drive signal provided to the gate control node by the DSG terminal of the AFE chip. This modulates the effective drive level applied to the gate of Q1 to become a PWM waveform with the same frequency as the MCU through resistor R8, which is used to control Q1 to switch periodically between on and off according to the duty cycle of the PWM waveform.

[0009] Furthermore, the circuit for implementing BMS adaptive load also includes a level acquisition circuit. The level acquisition circuit is grounded with the negative terminal B- of the battery pack. Its sampling terminal is connected to the gate control node, and its output terminal is connected to the level sampling pin DSG DET of the MCU. The MCU also communicates with the AFE chip to obtain the DSG status information of the AFE chip, and compares the gate control node level obtained through the level acquisition circuit with the DSG status reported by the AFE chip to determine whether the DSG signal is valid.

[0010] Furthermore, the discharge control switch circuit also includes resistors R2 and R5; one end of resistor R2 is connected to the DSG terminal of the AFE chip, and the other end is electrically connected to the gate control node, so as to provide the constant high-level gate drive signal provided by the DSG terminal of the AFE chip to the gate control node; resistor R8 is connected in series between the gate control node and the gate of Q1; one end of resistor R5 is connected to the gate of Q1, and the other end is connected to the source of Q1.

[0011] Further, the level adjustment circuit includes a pull-down transistor Q3, a current-limiting resistor R3, and a bias resistor R4. One end of the current-limiting resistor R3 serves as the signal input end of the level adjustment circuit and is connected to the PWM output end of the MCU, and the other end is connected to the control electrode of Q3. The collector of Q3 serves as the signal output end of the level adjustment circuit and is connected to the gate control node, and the emitter is connected to the negative electrode B- of the battery pack. One end of the bias resistor R4 is connected to the control electrode of Q3, and the other end is connected to the negative electrode B- of the battery pack. When the PWM signal output by the MCU is at a low level, Q3 conducts and pulls the gate control node towards the negative electrode B- of the battery pack. When the PWM signal output by the MCU is at a high level, Q3 is cut off and does not affect the constant high-level gate drive signal provided by the DSG terminal of the AFE chip.

[0012] Further, the circuit for implementing BMS adaptive load further includes a current sampling circuit. The current sampling circuit includes a sampling resistor R1. The sampling resistor R1 is connected in series between the negative electrode B- of the battery pack and the source electrode of Q1, so that the discharge current returns to the negative electrode B- of the battery pack through the sampling resistor R1. The AFE chip is provided with differential current detection terminals RS1 and RS2. RS1 and RS2 are connected to both ends of the sampling resistor R1 by Kelvin leads. RS2 is electrically connected to one end of the sampling resistor R1 close to the source electrode of Q1, and RS2 is electrically connected to one end of the sampling resistor R1 close to the negative electrode B- of the battery pack, so as to measure the voltage drop across the sampling resistor R1 and obtain the discharge current signal accordingly.

[0013] Further, the MCU is configured to generate a PWM corresponding to the size of the load RL to achieve adaptive adaptation according to the average value Iavg of the discharge current obtained by the AFE chip through the sampling resistor R1 within a preset time window. When the average value Iavg ≤ the preset rated output current Irated, the MCU does not perform pull-down modulation on the gate control node, so that Q1 remains continuously conductive. When Iavg > Irated, the MCU outputs a PWM at a set frequency fPWM, and determines the duty cycle D according to D = Irated / Iavg, and applies the output PWM to the level adjustment circuit, so that Q1 periodically switches between conduction and cut-off according to the duty cycle, so as to adjust the average discharge current to not higher than Irated.

[0014] Further, the MCU presets a duty cycle lower limit parameter Dmin to limit the load range of adaptive adaptation. When the duty cycle D < Dmin, an alarm is triggered, and the MCU drives an alarm unit connected to its alarm control terminal BEEP to output an alarm signal. At the same time, the MCU limits the PWM duty cycle output to Dmin and enters power-limited operation. If the condition of D < Dmin is still satisfied within the duration Talarm, then Q1 is controlled to turn off to stop discharging.

[0015] Further, the level acquisition circuit includes a voltage division sampling circuit composed of a resistor R6 and a resistor R7. The first end of the resistor R6 serves as the sampling end of the level acquisition circuit and is connected to the gate control node. The second end of the resistor R6 is electrically connected to the first end of the resistor R7 to form a sampling node as the output end of the level acquisition circuit. The second end of the resistor R7 is connected to the negative electrode B- of the battery pack; the sampling node is connected to the level sampling pin DSG DET of the MCU so that the MCU can obtain the level of the gate control node.

[0016] Further, a communication interface for status reading is provided between the MCU and the AFE chip. The MCU is configured to: periodically obtain the DSG status information reported by the AFE chip through the communication interface, and read the sampling node voltage Vdet of the voltage division sampling circuit composed of the resistor R6 and the resistor R7 to obtain the level of the gate control node; when the DSG status reported by the AFE chip is off and Vdet≥the preset threshold Vth, it is determined that the DSG signal fails; when the DSG status reported by the AFE chip is on and Vdet<Vth, it is determined that the DSG signal is valid.

[0017] Further, when the MCU determines that the DSG signal fails, it enters the failure shutdown control. Specifically: switch the PWM output connected to the level adjustment circuit to a constant control level to continuously drive the pull-down transistor Q3 to conduct; drive and bias the Q3 through the current-limiting resistor R3 and the bias resistor R4, so that the gate control node is pulled towards the negative electrode B- of the battery pack through Q3, and the potential applied to the gate of Q1 through the resistor R8 is pulled down to be lower than the threshold voltage to forcibly turn off Q1; during the maintenance of the failure shutdown control, the MCU keeps monitoring Vdet and the DSG status reported by the AFE chip, and exits the failure shutdown control when Vdet<Vth and the DSG status is on.

[0018] Further, the constant control level is either a constant high level or a level equivalent to making the pull-down stage conduct.

[0019] In a second aspect, the present invention provides a method for implementing BMS adaptive load. The method for implementing BMS adaptive load uses the circuit for implementing BMS adaptive load described in any one of the above.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] This invention provides a circuit and method for implementing BMS adaptive load. The circuit includes: an AFE chip, whose power supply terminal BAT is connected to the positive terminal B+ of the battery pack, and the negative terminal B- of the battery pack serves as a reference ground; a discharge control switch circuit, including an N-channel MOSFET Q1; the source of Q1 is connected to the negative terminal B- of the battery pack, and the drain serves as the discharge path output terminal and is connected to the negative terminal of the load RL, the positive terminal of the load RL is connected to the positive terminal of the battery pack; the discharge control switch circuit has a gate control node, which is connected to the gate of Q1 via a resistor R8; and a level adjustment circuit, whose signal input terminal is connected to the PWM of the MCU. The output terminal is electrically connected to the gate control node, and the reference ground is connected to the negative terminal B- of the battery pack. When the level adjustment circuit receives the PWM signal from the MCU, it outputs a periodically pulled-down level adjustment signal to the gate control node to modulate the constant high-level gate drive signal provided by the DSG terminal of the AFE chip to the gate control node. This modulates the effective drive level applied to the gate of Q1 into a PWM waveform with the same frequency as the MCU through resistor R8, which is used to control Q1 to periodically switch between on and off according to the duty cycle of the PWM waveform, thereby realizing the BMS's adaptive adjustment to the load. This invention implements a circuit for BMS adaptive load, which can solve the problem that the current front-end analog chip AFE of the BMS protection board lacks PWM function. It is beneficial to make full use of resources, effectively reduce operating costs, and achieve functional expansion with low-cost circuit design. Attached Figure Description

[0022] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. Some specific embodiments of the invention will be described in detail below with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings designate the same or similar parts or components. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the drawings:

[0023] Figure 1 This is a schematic diagram of a circuit structure for implementing BMS adaptive load according to an embodiment of the present invention;

[0024] Figure 2 This is a schematic diagram of another circuit structure for implementing BMS adaptive load in an embodiment of the present invention.

[0025] Explanation of reference numerals in the attached figures:

[0026] DL10, Discharge control switch circuit;

[0027] DL20, Level Adjustment Circuit;

[0028] DL30, Level Acquisition Circuit;

[0029] DL40, current sampling circuit. Detailed Implementation

[0030] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0031] Example 1

[0032] See Figures 1-2 This embodiment provides a circuit and method for implementing BMS adaptive load, wherein the method for implementing BMS adaptive load uses the circuit for implementing BMS adaptive load. The circuit for implementing BMS adaptive load includes:

[0033] The AFE chip has its power supply terminal BAT connected to the positive terminal B+ of the battery pack, and the negative terminal B- of the battery pack used as a reference ground.

[0034] The discharge control switch circuit DL10 includes an N-channel MOSFET Q1; the source of Q1 is connected to the negative terminal B- of the battery pack, the drain serves as the discharge path output terminal and is connected to the negative terminal of the load RL, and the positive terminal of the load RL is connected to the positive terminal of the battery pack; the discharge control switch circuit is provided with a gate control node, which is connected to the gate of Q1 through a resistor R8.

[0035] The level adjustment circuit DL20 has its signal input terminal connected to the PWM output terminal of the MCU, and its signal output terminal electrically connected to the gate control node. The reference ground is connected to the negative terminal B- of the battery pack. When receiving the PWM signal from the MCU, the level adjustment circuit outputs a periodically pulled-down level adjustment signal to the gate control node to modulate the constant high-level gate drive signal provided to the gate control node by the DSG terminal of the AFE chip. This modulates the effective drive level applied to the gate of Q1 to become a PWM waveform with the same frequency as the MCU through resistor R8, which is used to control Q1 to switch periodically between on and off according to the duty cycle of the PWM waveform.

[0036] In this embodiment, the level adjustment circuit has its signal input terminal connected to the PWM output terminal of the MCU, and its signal output terminal electrically connected to the gate control node, with the reference ground connected to the negative terminal B- of the battery pack. When receiving the PWM signal from the MCU, the level adjustment circuit outputs a periodically pulled-down level adjustment signal to the gate control node to modulate the constant high-level gate drive signal provided by the DSG terminal of the AFE chip to the gate control node. This modulates the effective drive level applied to the gate of Q1 to become a PWM waveform with the same frequency as the MCU through resistor R8. This solves the problem of the AFE chip lacking PWM functionality, achieving the technical effect of adding PWM functionality to AFE chips without PWM functionality (such as TI BQ76930), thereby allowing the conduction and turn-off of the discharge switch Q1 to be controlled by the PWM waveform, providing a basis for load adaptation. The discharge control switch circuit includes an N-channel MOSFET Q1. The source of Q1 is connected to the negative terminal B- of the battery pack, and the drain serves as the discharge path output terminal and is connected to the negative terminal of the load RL. The positive terminal of the load RL is connected to the positive terminal of the battery pack. The gate control node is connected to the gate of Q1 via a resistor R8. Combined with PWM modulation of the level adjustment circuit, the periodic switching of Q1 can be controlled by the PWM duty cycle, thereby adjusting the average discharge current and initially achieving the technical effect of load adaptation, providing hardware support for adaptive control. In this embodiment, the entire circuit design includes a simple connection of the AFE chip, the discharge control switch circuit, and the level adjustment circuit. The circuit is reasonable and simple, with few electronic components, easy to install, low production cost, and convenient operation and maintenance. It achieves the technical effect of expanding functions with low-cost circuit design, which is conducive to the full utilization of resources and the effective reduction of operating costs.

[0037] Preferably, the discharge control switch circuit further includes resistors R2 and R5; one end of resistor R2 is connected to the DSG terminal of the AFE chip, and the other end is electrically connected to the gate control node, so as to provide the constant high-level gate drive signal provided by the DSG terminal of the AFE chip to the gate control node; resistor R8 is connected in series between the gate control node and the gate of Q1; one end of resistor R5 is connected to the gate of Q1, and the other end is connected to the source of Q1.

[0038] In this embodiment, one end of resistor R2 is connected to the DSG terminal of the AFE chip, and the other end is electrically connected to the gate control node. This provides the constant high-level gate drive signal provided by the DSG terminal of the AFE chip to the gate control node, solving the problem that the AFE chip lacks PWM functionality but requires its DSG signal as a basic drive. This reliably introduces the original DSG drive signal of the AFE chip into the PWM modulation node (gate control node), providing the necessary and stable high-level signal source for PWM modulation. Resistor R8 is connected in series between the gate control node and the gate of Q1. This allows the modulated PWM waveform to be transmitted to the gate of Q1 while simultaneously limiting the gate charging current, protecting the MOSFET, and ensuring the stable execution of the PWM control function. One end of resistor R5 is connected to the gate of Q1, and the other end is connected to the source of Q1. This solves the problem of false turn-on of the MOSFET gate due to induced voltage or other reasons when there is no driving signal. It provides a discharge path for the gate charge of Q1, ensuring that Q1 can be reliably turned off when there is no output from the DSG terminal of the AFE chip and the PWM terminal of the MCU, thus enhancing the anti-interference capability and reliability of the circuit. In this embodiment, the core control circuit is constructed using common and low-cost electronic components such as resistors R2, R5, and R8. The circuit is reasonable and simple, with few electronic components, easy to install, and low in production cost. It can achieve the technical effect of functional expansion and safety enhancement with low-cost circuit design, which is conducive to the effective reduction of operating costs.

[0039] Furthermore, the circuit for implementing BMS adaptive load also includes a level acquisition circuit DL30. The level acquisition circuit is grounded with the negative terminal B- of the battery pack. Its sampling terminal is connected to the gate control node, and its output terminal is connected to the level sampling pin DSG DET of the MCU. The MCU also communicates with the AFE chip to obtain the DSG status information of the AFE chip, and compares the gate control node level obtained by the level acquisition circuit with the DSG status reported by the AFE chip to determine whether the DSG signal is valid.

[0040] In this embodiment, the circuit for implementing BMS adaptive load also includes a level acquisition circuit. Its sampling terminal is connected to the gate control node, and its output terminal is connected to the MCU's level sampling pin DSG DET. This solves the problem of unmonitored DSG signal validity of the AFE chip, enabling real-time hardware acquisition of the DSG signal level at the gate control node. The MCU also communicates with the AFE chip to obtain its DSG status information and compares the gate control node level obtained through the level acquisition circuit with the DSG status reported by the AFE chip to determine whether the DSG signal is valid. This solves the problem of unmonitored DSG signal validity of the AFE chip. Furthermore, it allows for cross-validation of the AFE chip's instruction state (output DSG) with the actual circuit state (actual gate control node level) through the MCU's software logic, thereby intelligently determining whether the DSG signal path is faulty.

[0041] Preferably, the level adjustment circuit includes a pull-down transistor Q3, a current-limiting resistor R3, and a bias resistor R4; one end of the current-limiting resistor R3 serves as the signal input terminal of the level adjustment circuit, connected to the PWM output terminal of the MCU, and the other end is connected to the control terminal of Q3; the collector of Q3 serves as the signal output terminal of the level adjustment circuit, connected to the gate control node, and the emitter is connected to the negative terminal B- of the battery pack; one end of the bias resistor R4 is connected to the control terminal of Q3, and the other end is connected to the negative terminal B- of the battery pack; when the PWM signal output by the MCU is low, Q3 is turned on, pulling the gate control node towards the negative terminal B- of the battery pack; when the PWM signal output by the MCU is high, Q3 is turned off without affecting the constant high-level gate drive signal provided by the DSG terminal of the AFE chip.

[0042] In this embodiment, the level adjustment circuit includes a pull-down transistor Q3, a current-limiting resistor R3, and a bias resistor R4. When the PWM signal output by the MCU is low, Q3 is turned on, pulling the gate control node towards the negative terminal B- of the battery pack. When the PWM signal output by the MCU is high, Q3 is turned off without affecting the constant high-level gate drive signal provided by the DSG terminal of the AFE chip. This can solve the problem of the AFE chip lacking PWM functionality, and realize the effective PWM modulation of the constant high level output by the DSG terminal of the AFE chip using the PWM signal of the MCU and a simple transistor switching circuit, thereby adding PWM functionality to the AFE chip that lacks PWM functionality. One end of the current-limiting resistor R3 serves as the signal input terminal of the level adjustment circuit, connected to the PWM output terminal of the MCU. The other end is connected to the control terminal of Q3. One end of the bias resistor R4 is connected to the control terminal of Q3, and the other end is connected to the negative terminal B- of the battery pack. This design addresses circuit reliability and stability issues, limits the current flowing into the control terminal of Q3, protects the MCU's PWM output pin, provides a defined bias voltage to Q3, and ensures that Q3 reliably cuts off when the MCU's PWM signal is high, preventing malfunctions. This enhances the accuracy of the PWM modulation waveform and the overall safety and reliability of the circuit. The circuit composed of the pull-down transistor Q3, current-limiting resistor R3, and bias resistor R4 is reasonable and simple, with few electronic components, easy installation, and low production cost. It enables PWM modulation functionality with a low-cost circuit design, facilitating resource utilization and effective cost reduction.

[0043] Furthermore, the circuit for realizing BMS adaptive load also includes a current sampling circuit DL40, which includes a sampling resistor R1. The sampling resistor R1 is connected in series between the negative terminal B- of the battery pack and the source of Q1, so that the discharge current returns to the negative terminal B- of the battery pack through the sampling resistor R1. The AFE chip is provided with differential current detection terminals RS1 and RS2. RS1 and RS2 are connected to the two ends of the sampling resistor R1 by Kelvin leads. RS2 is electrically connected to the end of the sampling resistor R1 near the source of Q1 and the end of the sampling resistor R1 near the negative terminal B- of the battery pack, so as to measure the voltage drop across the sampling resistor R1 and obtain the discharge current signal accordingly.

[0044] In this embodiment, the current sampling circuit includes a sampling resistor R1. The sampling resistor R1 is connected in series between the negative terminal B- of the battery pack and the source terminal of Q1, allowing the discharge current to return to the negative terminal B- of the battery pack via the sampling resistor R1. This solves the problem of not being able to adaptively adapt to different loads and provides a current feedback signal for the entire adaptive load system. The AFE chip is equipped with differential current detection terminals RS1 and RS2. RS1 and RS2 are connected to the two ends of the sampling resistor R1 using Kelvin leads. This solves the measurement error problem caused by line resistance and contact resistance when measuring small voltage drops across a low-resistance sampling resistor, achieving high-precision and high-reliability current signal acquisition.

[0045] Furthermore, the MCU is configured to generate a PWM corresponding to the load RL based on the average value Iavg of the discharge current obtained by the AFE chip through the sampling resistor R1 within a preset time window to achieve adaptive adaptation. When the average value Iavg ≤ the preset rated output current Irated, the MCU does not pull down the gate control node to keep Q1 continuously on. When Iavg > Irated, the MCU outputs PWM at a set frequency fPWM and determines the duty cycle D according to D = Irated / Iavg. The output PWM is applied to the level adjustment circuit so that Q1 switches periodically between on and off according to the duty cycle to adjust the average discharge current to not exceed Irated.

[0046] In this embodiment, the MCU is configured to generate a PWM corresponding to the load RL based on the average value Iavg of the discharge current obtained by the AFE chip through the sampling resistor R1 within a preset time window, thereby achieving adaptive adaptation. This solves the problem of not being able to adaptively adapt to different loads, realizing a truly adaptive function that can intelligently identify load requirements and automatically adjust the output power. When Iavg > Irated, the MCU outputs PWM at a set frequency fPWM and determines the duty cycle D according to D = Irated / Iavg, causing Q1 to periodically switch between on and off according to the duty cycle, so as to adjust the average discharge current to not exceed Irated. This solves the problem that when a load exceeding the rated power is connected, the battery and system may be damaged due to overcurrent or trigger thermal shutdown, achieving constant current power limiting control. Without directly cutting off the power supply, the output current is effectively limited to a safe range, protecting the battery and circuit, and providing the possibility of continued operation for some short-term overloaded loads, enhancing the applicability of the circuit and the user experience. Meanwhile, this embodiment provides an effective supplement to the hardware protection of the AFE chip through this proactive, software algorithm-based protection method, thereby enhancing the security and reliability of the circuit.

[0047] Preferably, the MCU preset duty cycle lower limit parameter Dmin is used to limit the load range of adaptive adaptation. When the duty cycle D < Dmin, an alarm is triggered, and the MCU drives an alarm unit connected to its alarm control terminal BEEP to output an alarm signal. At the same time, the MCU limits the output PWM duty cycle to Dmin and enters power-limited operation. If the condition of D < Dmin is still met within the duration Talarm, then Q1 is controlled to turn off to stop discharging.

[0048] In this embodiment, the MCU preset duty cycle lower limit parameter Dmin is used to limit the load range of adaptive adaptation. When the duty cycle D < Dmin, an alarm is triggered and an alarm signal is output, which can solve the problem that an alarm cannot be given in time when the load range exceeds the adaptation range, realize the active early warning function of the circuit for extreme overload or fault states, provide a clear fault indication for users or the upper system, enable them to take intervention measures in time, avoid continuous operation in a potentially dangerous state, and enhance the safety and maintainability of the circuit. At the same time, the MCU limits the output PWM duty cycle to Dmin and enters power-limited operation. If the condition of D < Dmin is still met within the duration Talarm, then Q1 is controlled to turn off to stop discharging, which can solve the problems of the lack of corresponding control methods after the DSG signal of the AFE chip fails and the ultimate protection for extreme overload, and realize hierarchical and time-limited failure control and protection. First, the circuit does not turn off immediately but first enters the maximum power-limited mode and gives an alarm, which provides a buffer and recovery opportunity for overload or user misoperation and improves the user experience. Second, if the abnormal state persists, the circuit will perform the final protection action and completely turn off the discharge to achieve safe control from early warning, power limitation to final turn-off, provide a complete, reliable and software-based secondary protection scheme, effectively compensate for the deficiency of relying solely on the hardware protection of the AFE chip, and reduce the operation risk and maintenance cost.

[0049] Further, the level acquisition circuit includes a voltage division sampling circuit composed of a resistor R6 and a resistor R7. The first end of the resistor R6 is used as the sampling end of the level acquisition circuit and is connected to the gate control node. The second end of the resistor R6 is electrically connected to the first end of the resistor R7 to form a sampling node as the output end of the level acquisition circuit. The second end of the resistor R7 is connected to the negative pole B- of the battery pack; the sampling node is connected to the level sampling pin DSG DET of the MCU so that the MCU can obtain the level of the gate control node.

[0050] In this embodiment, the level acquisition circuit includes a voltage division sampling circuit composed of resistor R6 and resistor R7. The first end of resistor R6 serves as the sampling end of the level acquisition circuit and is connected to the gate control node. The second end of resistor R6 is electrically connected to the first end of resistor R7 to form a sampling node, which serves as the output end of the level acquisition circuit. The second end of resistor R7 is connected to the negative electrode B- of the battery pack, which can solve the hardware implementation problem of the inability to monitor the validity of the DSG signal of the AFE chip, and realize the safe conversion of the potential of the high-side gate control node to the low voltage range recognizable by the MCU with an extremely low cost and a simple and reliable circuit structure. The sampling node is connected to the level sampling pin DSG DET of the MCU so that the MCU can obtain the level of the gate control node, which can solve the problem of how to transmit the monitoring signal to the MCU, and realize the introduction of the key hardware state signal (the actual level of the gate control node) into the software logic of the MCU, providing indispensable input data for intelligent comparison and failure judgment. This design in this embodiment makes full use of the ADC resources built in the MCU, avoids using complex or expensive dedicated detection chips, has a reasonable and simple circuit, few electronic components, is convenient to install, and has a low production cost.

[0051] Furthermore, a communication interface for status reading is provided between the MCU and the AFE chip. The MCU is configured to: periodically obtain the DSG status information reported by the AFE chip through the communication interface, and read the sampling node voltage Vdet of the voltage division sampling circuit composed of resistor R6 and resistor R7 to obtain the level of the gate control node; when the DSG status reported by the AFE chip is off and Vdet ≥ the preset threshold Vth, it is determined that the DSG signal fails; when the DSG status reported by the AFE chip is on and Vdet < Vth, it is determined that the DSG signal is valid.

[0052] In this embodiment, the MCU is configured to: periodically obtain the DSG status information reported by the AFE chip through the communication interface, and read the sampling node voltage Vdet to obtain the level of the gate control node; when the DSG status reported by the AFE chip is off and Vdet ≥ the preset threshold Vth, it is determined that the DSG signal fails, which can solve the problem that the effectiveness of the DSG signal of the AFE chip cannot be monitored, and realize an intelligent cross-verification monitoring mechanism based on software logic. This determination logic of this embodiment can accurately capture a typical failure mode: that is, the internal logic of the AFE chip intends to turn off the DSG output (status is off), but due to damage to the internal driving stage of the chip (such as short circuit to BAT) or abnormal external circuit, the potential of the gate control node remains high (Vdet ≥ Vth), and the discharge tube Q1 cannot be turned off. When the DSG status reported by the AFE chip is on and Vdet < Vth, it is determined that the DSG signal is valid, which can realize the monitoring of another failure mode (DSG signal loss) and clarify the determination conditions for the normal working state. This two-way verification logic of this embodiment enables the determination conditions for the normal working state. This two-way verification logic of this embodiment enables the circuit to not only detect the low-but-not-high failure, but also identify the high-but-not-high abnormality, constituting a complete DSG signal effectiveness monitoring system and enhancing the safety and reliability of the circuit.

[0053] Furthermore, when the MCU determines that the DSG signal fails, it enters the failure shutdown control, specifically: switch the PWM output connected to the level adjustment circuit to a constant control level to continuously drive the pull-down transistor Q3 to conduct; drive and bias Q3 through the current-limiting resistor R3 and the bias resistor R4, so that the gate control node is pulled towards the negative pole B- of the battery pack through Q3, and the potential applied to the gate of Q1 through the resistor R8 is pulled down to be lower than the threshold voltage to forcibly turn off Q1; during the maintenance of the failure shutdown control, the MCU keeps monitoring Vdet and the DSG status reported by the AFE chip, and exits the failure shutdown control when Vdet < Vth and the DSG status is on.

[0054] In this embodiment, when the MCU determines that the DSG signal has failed, it enters a failure shutdown control. Specifically, it switches the PWM output connected to the level adjustment circuit to a constant control level to continuously drive the pull-down transistor Q3 to conduct; the gate control node is pulled towards the negative terminal B- of the battery pack via Q3, causing the potential applied to the gate of Q1 via resistor R8 to be pulled down below the threshold voltage, thus forcibly shutting down Q1. This solves the critical safety problem of lacking a corresponding control method after the AFE chip's DSG signal fails, achieving a reliable secondary protection shutdown led by the MCU after the first layer of protection of the AFE chip fails. The innovation of this embodiment lies in the fact that it does not add a new shutdown execution device, but reuses the level adjustment circuit designed for PWM function. When a failure occurs, the MCU transforms the originally dynamic PWM signal into a fixed shutdown command (constant control level), and uses the pull-down transistor Q3 to forcibly pull the gate control node to a low level, thereby bypassing the failed AFE chip DSG signal and directly forcibly shutting down the discharge MOS transistor Q1. The circuit is reasonable and simple, with few electronic components, achieving crucial safety redundancy at the lowest cost. During the failure shutdown control period, the MCU continuously monitors Vdet and the DSG status reported by the AFE chip. When Vdet < Vth and the DSG status is on, the MCU exits the failure shutdown control, ensuring recoverability of the failure control and providing an intelligent and flexible protection mechanism, rather than a simple lockout. Continuous monitoring of failure conditions ensures that once the AFE chip's DSG signal returns to normal (e.g., the AFE chip normally shut down the DSG due to other protection measures, and then normally turned on again after the danger subsides), the circuit automatically exits the forced shutdown state, returning control to the AFE chip, thus improving circuit maintainability and user experience.

[0055] Preferably, the constant control level is either a constant high level or an equivalent level that turns on the pull-down stage. In this embodiment, the constant control level being either a constant high level or an equivalent level that turns on the pull-down stage can achieve explicitness and standardization of the failure shutdown control command, ensuring that the pull-down transistor Q3 can be reliably and continuously driven to the saturation conduction state, thereby providing the most fundamental guarantee for the forced shutdown of Q1.

[0056] exist Figures 1-2 In this context, AFE refers to the analog front-end chip, BAT refers to the chip power supply pin, GND refers to the chip ground, RS1 and RS2 refer to the chip differential input pins, DSG refers to the discharge FET control pin, CHG refers to the charge FET control pin, SDA refers to the serial data pin, SCL refers to the serial clock pin, MCU refers to the microcontroller unit, PA1-PA3 refer to pins 1-3 of port A, BEEP refers to the buzzer signal, PWM refers to pulse width modulation, and DSG DET refers to the discharge FET control signal detection.

[0057] It should be noted that the above embodiments are merely preferred embodiments of the present invention, and the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention, and the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A circuit for implementing BMS adaptive load, characterized in that, The application relates to a battery discharge control circuit, which comprises the following parts: an AFE chip, the positive electrode B+ of which is connected with a battery pack, and the negative electrode B- of which is used as a reference ground; a discharge control switch circuit, which comprises an N-channel MOS tube Q1; the source electrode of the Q1 is connected with the negative electrode B- of the battery pack, the drain electrode of the Q1 is used as a discharge path output end and is connected with the negative electrode of a load RL, the positive electrode of the load RL is connected with the positive electrode of the battery pack; the discharge control switch circuit is provided with a gate control node, which is connected with the gate electrode of the Q1 through a resistor R8; a level adjustment circuit, the signal input end of which is connected with the PWM output end of an MCU, the signal output end of which is electrically connected with the gate control node, and the reference ground of which is connected with the negative electrode B- of the battery pack; when receiving the PWM signal of the MCU, the level adjustment circuit outputs a periodic pull-down level adjustment signal to the gate control node, so that the constant high-level gate drive signal provided by the DSG end of the AFE chip to the gate control node is modulated, the effective drive level on the gate electrode of the Q1 is changed into a PWM waveform with the same frequency as the MCU through the resistor R8, and the Q1 is periodically switched between the on and off states according to the duty ratio of the PWM waveform. The level adjustment circuit comprises a pull-down transistor Q3, a current-limiting resistor R3 and a bias resistor R4. One end of the current-limiting resistor R3 is connected with the PWM output end of the MCU as the signal input end of the level adjustment circuit, and the other end is connected with the control electrode of the Q3; the collector electrode of the Q3 is connected with the gate control node as the signal output end of the level adjustment circuit, and the emitter electrode of the Q3 is connected with the negative electrode B- of the battery pack; one end of the bias resistor R4 is connected with the control electrode of the Q3, and the other end is connected with the negative electrode B- of the battery pack; when the PWM signal output by the MCU is low, the Q3 is turned on to pull the gate control node to the negative electrode B- of the battery pack; when the PWM signal output by the MCU is high, the Q3 is turned off without affecting the constant high-level gate drive signal provided by the DSG end of the AFE chip.

2. The circuit of claim 1, wherein, The battery discharge control circuit further comprises a level acquisition circuit, which has the same reference ground as the negative electrode B- of the battery pack, the sampling end of which is connected with the gate control node, and the output end of which is connected with the level sampling pin DSG DET of the MCU; the MCU further communicates with the AFE chip to obtain the DSG state information of the AFE chip, and compares the gate control node level obtained through the level acquisition circuit with the DSG state reported by the AFE chip to determine whether the DSG signal is valid.

3. The circuit of claim 1, wherein, The discharge control switch circuit further comprises a resistor R2 and a resistor R5; one end of the resistor R2 is connected with the DSG end of the AFE chip, and the other end is electrically connected with the gate control node to provide the constant high-level gate drive signal provided by the DSG end of the AFE chip to the gate control node; the resistor R8 is connected in series between the gate control node and the gate electrode of the Q1; one end of the resistor R5 is connected with the gate electrode of the Q1, and the other end is connected with the source electrode of the Q1.

4. The circuit of claim 1, wherein, The current sampling circuit comprises a sampling resistor R1; the sampling resistor R1 is connected in series between the battery negative electrode B- and the source of the Q1, so that the discharge current returns to the battery negative electrode B- through the sampling resistor R1; the AFE chip is provided with differential current detection terminals RS1 and RS2, which are connected to both ends of the sampling resistor R1 in a Kelvin lead manner, and RS2 is electrically connected to one end of the sampling resistor R1 close to the source of the Q1 and to the other end of the sampling resistor R1 close to the battery negative electrode B-, so as to measure the voltage drop across the sampling resistor R1 and obtain the discharge current signal accordingly.

5. The circuit of claim 4, wherein, The MCU is configured to generate a PWM corresponding to the size of the load RL according to the average value Iavg of the discharge current obtained by the AFE chip through the sampling resistor R1 within a preset time window, so as to realize adaptive adaptation; when the average value Iavg is less than or equal to a preset rated output current Irated, the MCU does not pull down the gate control node for modulation, so that the Q1 remains continuously conductive; when Iavg> Irated, the MCU outputs a PWM at a set frequency fPWM and determines the duty cycle D as D=Irated / Iavg, and applies the output PWM to the level adjustment circuit, so that the Q1 is periodically switched between conduction and non-conduction according to the duty cycle, so as to adjust the average discharge current to be not higher than Irated.

6. The circuit of claim 5, wherein, The MCU presets a lower limit parameter Dmin of the duty cycle for limiting the load range of adaptive adaptation, and triggers an alarm when the duty cycle D is less than Dmin, and the MCU drives an alarm unit connected to the alarm control end BEEP to output an alarm signal; at the same time, the MCU limits the duty cycle of the output PWM to Dmin and enters a limited power operation, and if the condition of D<Dmin is still met within a continuous time Talarm, the Q1 is controlled to be turned off to stop discharging.

7. The circuit of claim 2, wherein, The level acquisition circuit comprises a voltage division sampling circuit composed of a resistor R6 and a resistor R7, a first end of the resistor R6 is connected to the gate control node as a sampling end of the level acquisition circuit, a second end of the resistor R6 and a first end of the resistor R7 are electrically connected to form a sampling node as an output end of the level acquisition circuit, and a second end of the resistor R7 is connected to the battery negative electrode B-; the sampling node is connected to a level sampling pin DSGDET of the MCU, so that the MCU obtains the level of the gate control node.

8. The circuit of claim 7, wherein, The MCU and the AFE chip are provided with a communication interface for state reading, and the MCU is configured to periodically obtain DSG state information reported by the AFE chip through the communication interface, and read the voltage Vdet of the sampling node of the voltage division sampling circuit composed of the resistor R6 and the resistor R7 to obtain the level of the gate control node; when the DSG state reported by the AFE chip is off and Vdet≥a preset threshold Vth, it is determined that the DSG signal is invalid; when the DSG state reported by the AFE chip is on and Vdet< Vth, it is determined that the DSG signal is valid.

9. A method of implementing BMS adaptive load, characterized in that, The method for implementing BMS adaptive load uses the circuit for implementing BMS adaptive load as claimed in any one of claims 1-8.

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